1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/bits.h> 11 #include <linux/types.h> 12 #include <linux/uuid.h> 13 14 /* NQN names in commands fields specified one size */ 15 #define NVMF_NQN_FIELD_LEN 256 16 17 /* However the max length of a qualified name is another size */ 18 #define NVMF_NQN_SIZE 223 19 20 #define NVMF_TRSVCID_SIZE 32 21 #define NVMF_TRADDR_SIZE 256 22 #define NVMF_TSAS_SIZE 256 23 24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 25 26 #define NVME_NSID_ALL 0xffffffff 27 28 /* Special NSSR value, 'NVMe' */ 29 #define NVME_SUBSYS_RESET 0x4E564D65 30 31 enum nvme_subsys_type { 32 /* Referral to another discovery type target subsystem */ 33 NVME_NQN_DISC = 1, 34 35 /* NVME type target subsystem */ 36 NVME_NQN_NVME = 2, 37 38 /* Current discovery type target subsystem */ 39 NVME_NQN_CURR = 3, 40 }; 41 42 enum nvme_ctrl_type { 43 NVME_CTRL_IO = 1, /* I/O controller */ 44 NVME_CTRL_DISC = 2, /* Discovery controller */ 45 NVME_CTRL_ADMIN = 3, /* Administrative controller */ 46 }; 47 48 enum nvme_dctype { 49 NVME_DCTYPE_NOT_REPORTED = 0, 50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */ 51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */ 52 }; 53 54 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 55 enum { 56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ 62 NVMF_ADDR_FAMILY_MAX, 63 }; 64 65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 66 enum { 67 NVMF_TRTYPE_PCI = 0, /* PCI */ 68 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 69 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 70 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 71 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 72 NVMF_TRTYPE_MAX, 73 }; 74 75 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 76 enum { 77 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 78 NVMF_TREQ_REQUIRED = 1, /* Required */ 79 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 80 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 81 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 82 83 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 84 }; 85 86 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 87 * RDMA_QPTYPE field 88 */ 89 enum { 90 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 91 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 92 NVMF_RDMA_QPTYPE_INVALID = 0xff, 93 }; 94 95 /* RDMA Provider Type codes for Discovery Log Page entry TSAS 96 * RDMA_PRTYPE field 97 */ 98 enum { 99 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 100 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 101 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 102 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 103 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 104 }; 105 106 /* RDMA Connection Management Service Type codes for Discovery Log Page 107 * entry TSAS RDMA_CMS field 108 */ 109 enum { 110 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 111 }; 112 113 /* TSAS SECTYPE for TCP transport */ 114 enum { 115 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */ 116 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 117 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 118 NVMF_TCP_SECTYPE_INVALID = 0xff, 119 }; 120 121 #define NVME_AQ_DEPTH 32 122 #define NVME_NR_AEN_COMMANDS 1 123 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 124 125 /* 126 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 127 * NVM-Express 1.2 specification, section 4.1.2. 128 */ 129 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 130 131 enum { 132 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 133 NVME_REG_VS = 0x0008, /* Version */ 134 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 135 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 136 NVME_REG_CC = 0x0014, /* Controller Configuration */ 137 NVME_REG_CSTS = 0x001c, /* Controller Status */ 138 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 139 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 140 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 141 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 142 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 143 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 144 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ 145 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ 146 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer 147 * Location 148 */ 149 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory 150 * Space Control 151 */ 152 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */ 153 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ 154 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ 155 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ 156 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity 157 * Buffer Size 158 */ 159 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained 160 * Write Throughput 161 */ 162 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 163 }; 164 165 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 166 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 167 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 168 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 169 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) 170 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 171 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 172 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) 173 174 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 175 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 176 177 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16) 178 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff) 179 180 enum { 181 NVME_CMBSZ_SQS = 1 << 0, 182 NVME_CMBSZ_CQS = 1 << 1, 183 NVME_CMBSZ_LISTS = 1 << 2, 184 NVME_CMBSZ_RDS = 1 << 3, 185 NVME_CMBSZ_WDS = 1 << 4, 186 187 NVME_CMBSZ_SZ_SHIFT = 12, 188 NVME_CMBSZ_SZ_MASK = 0xfffff, 189 190 NVME_CMBSZ_SZU_SHIFT = 8, 191 NVME_CMBSZ_SZU_MASK = 0xf, 192 }; 193 194 /* 195 * Submission and Completion Queue Entry Sizes for the NVM command set. 196 * (In bytes and specified as a power of two (2^n)). 197 */ 198 #define NVME_ADM_SQES 6 199 #define NVME_NVM_IOSQES 6 200 #define NVME_NVM_IOCQES 4 201 202 enum { 203 NVME_CC_ENABLE = 1 << 0, 204 NVME_CC_EN_SHIFT = 0, 205 NVME_CC_CSS_SHIFT = 4, 206 NVME_CC_MPS_SHIFT = 7, 207 NVME_CC_AMS_SHIFT = 11, 208 NVME_CC_SHN_SHIFT = 14, 209 NVME_CC_IOSQES_SHIFT = 16, 210 NVME_CC_IOCQES_SHIFT = 20, 211 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, 212 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, 213 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, 214 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 215 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 216 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 217 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 218 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 219 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 220 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 221 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 222 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 223 NVME_CC_CRIME = 1 << 24, 224 }; 225 226 enum { 227 NVME_CSTS_RDY = 1 << 0, 228 NVME_CSTS_CFS = 1 << 1, 229 NVME_CSTS_NSSRO = 1 << 4, 230 NVME_CSTS_PP = 1 << 5, 231 NVME_CSTS_SHST_NORMAL = 0 << 2, 232 NVME_CSTS_SHST_OCCUR = 1 << 2, 233 NVME_CSTS_SHST_CMPLT = 2 << 2, 234 NVME_CSTS_SHST_MASK = 3 << 2, 235 }; 236 237 enum { 238 NVME_CMBMSC_CRE = 1 << 0, 239 NVME_CMBMSC_CMSE = 1 << 1, 240 }; 241 242 enum { 243 NVME_CAP_CSS_NVM = 1 << 0, 244 NVME_CAP_CSS_CSI = 1 << 6, 245 }; 246 247 enum { 248 NVME_CAP_CRMS_CRWMS = 1ULL << 59, 249 NVME_CAP_CRMS_CRIMS = 1ULL << 60, 250 }; 251 252 struct nvme_id_power_state { 253 __le16 max_power; /* centiwatts */ 254 __u8 rsvd2; 255 __u8 flags; 256 __le32 entry_lat; /* microseconds */ 257 __le32 exit_lat; /* microseconds */ 258 __u8 read_tput; 259 __u8 read_lat; 260 __u8 write_tput; 261 __u8 write_lat; 262 __le16 idle_power; 263 __u8 idle_scale; 264 __u8 rsvd19; 265 __le16 active_power; 266 __u8 active_work_scale; 267 __u8 rsvd23[9]; 268 }; 269 270 enum { 271 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 272 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 273 }; 274 275 enum nvme_ctrl_attr { 276 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 277 NVME_CTRL_ATTR_TBKAS = (1 << 6), 278 NVME_CTRL_ATTR_ELBAS = (1 << 15), 279 NVME_CTRL_ATTR_RHII = (1 << 18), 280 }; 281 282 struct nvme_id_ctrl { 283 __le16 vid; 284 __le16 ssvid; 285 char sn[20]; 286 char mn[40]; 287 char fr[8]; 288 __u8 rab; 289 __u8 ieee[3]; 290 __u8 cmic; 291 __u8 mdts; 292 __le16 cntlid; 293 __le32 ver; 294 __le32 rtd3r; 295 __le32 rtd3e; 296 __le32 oaes; 297 __le32 ctratt; 298 __u8 rsvd100[11]; 299 __u8 cntrltype; 300 __u8 fguid[16]; 301 __le16 crdt1; 302 __le16 crdt2; 303 __le16 crdt3; 304 __u8 rsvd134[122]; 305 __le16 oacs; 306 __u8 acl; 307 __u8 aerl; 308 __u8 frmw; 309 __u8 lpa; 310 __u8 elpe; 311 __u8 npss; 312 __u8 avscc; 313 __u8 apsta; 314 __le16 wctemp; 315 __le16 cctemp; 316 __le16 mtfa; 317 __le32 hmpre; 318 __le32 hmmin; 319 __u8 tnvmcap[16]; 320 __u8 unvmcap[16]; 321 __le32 rpmbs; 322 __le16 edstt; 323 __u8 dsto; 324 __u8 fwug; 325 __le16 kas; 326 __le16 hctma; 327 __le16 mntmt; 328 __le16 mxtmt; 329 __le32 sanicap; 330 __le32 hmminds; 331 __le16 hmmaxd; 332 __le16 nvmsetidmax; 333 __le16 endgidmax; 334 __u8 anatt; 335 __u8 anacap; 336 __le32 anagrpmax; 337 __le32 nanagrpid; 338 __u8 rsvd352[160]; 339 __u8 sqes; 340 __u8 cqes; 341 __le16 maxcmd; 342 __le32 nn; 343 __le16 oncs; 344 __le16 fuses; 345 __u8 fna; 346 __u8 vwc; 347 __le16 awun; 348 __le16 awupf; 349 __u8 nvscc; 350 __u8 nwpc; 351 __le16 acwu; 352 __u8 rsvd534[2]; 353 __le32 sgls; 354 __le32 mnan; 355 __u8 rsvd544[224]; 356 char subnqn[256]; 357 __u8 rsvd1024[768]; 358 __le32 ioccsz; 359 __le32 iorcsz; 360 __le16 icdoff; 361 __u8 ctrattr; 362 __u8 msdbd; 363 __u8 rsvd1804[2]; 364 __u8 dctype; 365 __u8 rsvd1807[241]; 366 struct nvme_id_power_state psd[32]; 367 __u8 vs[1024]; 368 }; 369 370 enum { 371 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, 372 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, 373 NVME_CTRL_CMIC_ANA = 1 << 3, 374 NVME_CTRL_ONCS_COMPARE = 1 << 0, 375 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 376 NVME_CTRL_ONCS_DSM = 1 << 2, 377 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 378 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, 379 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 380 NVME_CTRL_VWC_PRESENT = 1 << 0, 381 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 382 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, 383 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 384 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 385 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 386 NVME_CTRL_CTRATT_128_ID = 1 << 0, 387 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, 388 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, 389 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, 390 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, 391 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, 392 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, 393 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, 394 NVME_CTRL_SGLS_BYTE_ALIGNED = 1, 395 NVME_CTRL_SGLS_DWORD_ALIGNED = 2, 396 NVME_CTRL_SGLS_KSDBDS = 1 << 2, 397 NVME_CTRL_SGLS_MSDS = 1 << 19, 398 NVME_CTRL_SGLS_SAOS = 1 << 20, 399 }; 400 401 struct nvme_lbaf { 402 __le16 ms; 403 __u8 ds; 404 __u8 rp; 405 }; 406 407 struct nvme_id_ns { 408 __le64 nsze; 409 __le64 ncap; 410 __le64 nuse; 411 __u8 nsfeat; 412 __u8 nlbaf; 413 __u8 flbas; 414 __u8 mc; 415 __u8 dpc; 416 __u8 dps; 417 __u8 nmic; 418 __u8 rescap; 419 __u8 fpi; 420 __u8 dlfeat; 421 __le16 nawun; 422 __le16 nawupf; 423 __le16 nacwu; 424 __le16 nabsn; 425 __le16 nabo; 426 __le16 nabspf; 427 __le16 noiob; 428 __u8 nvmcap[16]; 429 __le16 npwg; 430 __le16 npwa; 431 __le16 npdg; 432 __le16 npda; 433 __le16 nows; 434 __u8 rsvd74[18]; 435 __le32 anagrpid; 436 __u8 rsvd96[3]; 437 __u8 nsattr; 438 __le16 nvmsetid; 439 __le16 endgid; 440 __u8 nguid[16]; 441 __u8 eui64[8]; 442 struct nvme_lbaf lbaf[64]; 443 __u8 vs[3712]; 444 }; 445 446 /* I/O Command Set Independent Identify Namespace Data Structure */ 447 struct nvme_id_ns_cs_indep { 448 __u8 nsfeat; 449 __u8 nmic; 450 __u8 rescap; 451 __u8 fpi; 452 __le32 anagrpid; 453 __u8 nsattr; 454 __u8 rsvd9; 455 __le16 nvmsetid; 456 __le16 endgid; 457 __u8 nstat; 458 __u8 rsvd15[4081]; 459 }; 460 461 struct nvme_zns_lbafe { 462 __le64 zsze; 463 __u8 zdes; 464 __u8 rsvd9[7]; 465 }; 466 467 struct nvme_id_ns_zns { 468 __le16 zoc; 469 __le16 ozcs; 470 __le32 mar; 471 __le32 mor; 472 __le32 rrl; 473 __le32 frl; 474 __u8 rsvd20[2796]; 475 struct nvme_zns_lbafe lbafe[64]; 476 __u8 vs[256]; 477 }; 478 479 struct nvme_id_ctrl_zns { 480 __u8 zasl; 481 __u8 rsvd1[4095]; 482 }; 483 484 struct nvme_id_ns_nvm { 485 __le64 lbstm; 486 __u8 pic; 487 __u8 rsvd9[3]; 488 __le32 elbaf[64]; 489 __u8 rsvd268[3828]; 490 }; 491 492 enum { 493 NVME_ID_NS_NVM_STS_MASK = 0x7f, 494 NVME_ID_NS_NVM_GUARD_SHIFT = 7, 495 NVME_ID_NS_NVM_GUARD_MASK = 0x3, 496 NVME_ID_NS_NVM_QPIF_SHIFT = 9, 497 NVME_ID_NS_NVM_QPIF_MASK = 0xf, 498 NVME_ID_NS_NVM_QPIFS = 1 << 3, 499 }; 500 501 static inline __u8 nvme_elbaf_sts(__u32 elbaf) 502 { 503 return elbaf & NVME_ID_NS_NVM_STS_MASK; 504 } 505 506 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf) 507 { 508 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK; 509 } 510 511 static inline __u8 nvme_elbaf_qualified_guard_type(__u32 elbaf) 512 { 513 return (elbaf >> NVME_ID_NS_NVM_QPIF_SHIFT) & NVME_ID_NS_NVM_QPIF_MASK; 514 } 515 516 struct nvme_id_ctrl_nvm { 517 __u8 vsl; 518 __u8 wzsl; 519 __u8 wusl; 520 __u8 dmrl; 521 __le32 dmrsl; 522 __le64 dmsl; 523 __u8 rsvd16[4080]; 524 }; 525 526 enum { 527 NVME_ID_CNS_NS = 0x00, 528 NVME_ID_CNS_CTRL = 0x01, 529 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 530 NVME_ID_CNS_NS_DESC_LIST = 0x03, 531 NVME_ID_CNS_CS_NS = 0x05, 532 NVME_ID_CNS_CS_CTRL = 0x06, 533 NVME_ID_CNS_NS_ACTIVE_LIST_CS = 0x07, 534 NVME_ID_CNS_NS_CS_INDEP = 0x08, 535 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 536 NVME_ID_CNS_NS_PRESENT = 0x11, 537 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 538 NVME_ID_CNS_CTRL_LIST = 0x13, 539 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, 540 NVME_ID_CNS_NS_GRANULARITY = 0x16, 541 NVME_ID_CNS_UUID_LIST = 0x17, 542 NVME_ID_CNS_ENDGRP_LIST = 0x19, 543 }; 544 545 enum { 546 NVME_CSI_NVM = 0, 547 NVME_CSI_ZNS = 2, 548 }; 549 550 enum { 551 NVME_DIR_IDENTIFY = 0x00, 552 NVME_DIR_STREAMS = 0x01, 553 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 554 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 555 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 556 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 557 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 558 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 559 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 560 NVME_DIR_ENDIR = 0x01, 561 }; 562 563 enum { 564 NVME_NS_FEAT_THIN = 1 << 0, 565 NVME_NS_FEAT_ATOMICS = 1 << 1, 566 NVME_NS_FEAT_IO_OPT = 1 << 4, 567 NVME_NS_ATTR_RO = 1 << 0, 568 NVME_NS_FLBAS_LBA_MASK = 0xf, 569 NVME_NS_FLBAS_LBA_UMASK = 0x60, 570 NVME_NS_FLBAS_LBA_SHIFT = 1, 571 NVME_NS_FLBAS_META_EXT = 0x10, 572 NVME_NS_NMIC_SHARED = 1 << 0, 573 NVME_NS_ROTATIONAL = 1 << 4, 574 NVME_NS_VWC_NOT_PRESENT = 1 << 5, 575 NVME_LBAF_RP_BEST = 0, 576 NVME_LBAF_RP_BETTER = 1, 577 NVME_LBAF_RP_GOOD = 2, 578 NVME_LBAF_RP_DEGRADED = 3, 579 NVME_NS_DPC_PI_LAST = 1 << 4, 580 NVME_NS_DPC_PI_FIRST = 1 << 3, 581 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 582 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 583 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 584 NVME_NS_DPS_PI_FIRST = 1 << 3, 585 NVME_NS_DPS_PI_MASK = 0x7, 586 NVME_NS_DPS_PI_TYPE1 = 1, 587 NVME_NS_DPS_PI_TYPE2 = 2, 588 NVME_NS_DPS_PI_TYPE3 = 3, 589 }; 590 591 enum { 592 NVME_NSTAT_NRDY = 1 << 0, 593 }; 594 595 enum { 596 NVME_NVM_NS_16B_GUARD = 0, 597 NVME_NVM_NS_32B_GUARD = 1, 598 NVME_NVM_NS_64B_GUARD = 2, 599 NVME_NVM_NS_QTYPE_GUARD = 3, 600 }; 601 602 static inline __u8 nvme_lbaf_index(__u8 flbas) 603 { 604 return (flbas & NVME_NS_FLBAS_LBA_MASK) | 605 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT); 606 } 607 608 /* Identify Namespace Metadata Capabilities (MC): */ 609 enum { 610 NVME_MC_EXTENDED_LBA = (1 << 0), 611 NVME_MC_METADATA_PTR = (1 << 1), 612 }; 613 614 struct nvme_ns_id_desc { 615 __u8 nidt; 616 __u8 nidl; 617 __le16 reserved; 618 }; 619 620 #define NVME_NIDT_EUI64_LEN 8 621 #define NVME_NIDT_NGUID_LEN 16 622 #define NVME_NIDT_UUID_LEN 16 623 #define NVME_NIDT_CSI_LEN 1 624 625 enum { 626 NVME_NIDT_EUI64 = 0x01, 627 NVME_NIDT_NGUID = 0x02, 628 NVME_NIDT_UUID = 0x03, 629 NVME_NIDT_CSI = 0x04, 630 }; 631 632 struct nvme_endurance_group_log { 633 __u8 egcw; 634 __u8 egfeat; 635 __u8 rsvd2; 636 __u8 avsp; 637 __u8 avspt; 638 __u8 pused; 639 __le16 did; 640 __u8 rsvd8[24]; 641 __u8 ee[16]; 642 __u8 dur[16]; 643 __u8 duw[16]; 644 __u8 muw[16]; 645 __u8 hrc[16]; 646 __u8 hwc[16]; 647 __u8 mdie[16]; 648 __u8 neile[16]; 649 __u8 tegcap[16]; 650 __u8 uegcap[16]; 651 __u8 rsvd192[320]; 652 }; 653 654 struct nvme_rotational_media_log { 655 __le16 endgid; 656 __le16 numa; 657 __le16 nrs; 658 __u8 rsvd6[2]; 659 __le32 spinc; 660 __le32 fspinc; 661 __le32 ldc; 662 __le32 fldc; 663 __u8 rsvd24[488]; 664 }; 665 666 struct nvme_smart_log { 667 __u8 critical_warning; 668 __u8 temperature[2]; 669 __u8 avail_spare; 670 __u8 spare_thresh; 671 __u8 percent_used; 672 __u8 endu_grp_crit_warn_sumry; 673 __u8 rsvd7[25]; 674 __u8 data_units_read[16]; 675 __u8 data_units_written[16]; 676 __u8 host_reads[16]; 677 __u8 host_writes[16]; 678 __u8 ctrl_busy_time[16]; 679 __u8 power_cycles[16]; 680 __u8 power_on_hours[16]; 681 __u8 unsafe_shutdowns[16]; 682 __u8 media_errors[16]; 683 __u8 num_err_log_entries[16]; 684 __le32 warning_temp_time; 685 __le32 critical_comp_time; 686 __le16 temp_sensor[8]; 687 __le32 thm_temp1_trans_count; 688 __le32 thm_temp2_trans_count; 689 __le32 thm_temp1_total_time; 690 __le32 thm_temp2_total_time; 691 __u8 rsvd232[280]; 692 }; 693 694 struct nvme_fw_slot_info_log { 695 __u8 afi; 696 __u8 rsvd1[7]; 697 __le64 frs[7]; 698 __u8 rsvd64[448]; 699 }; 700 701 enum { 702 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 703 NVME_CMD_EFFECTS_LBCC = 1 << 1, 704 NVME_CMD_EFFECTS_NCC = 1 << 2, 705 NVME_CMD_EFFECTS_NIC = 1 << 3, 706 NVME_CMD_EFFECTS_CCC = 1 << 4, 707 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14), 708 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), 709 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, 710 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20), 711 }; 712 713 struct nvme_effects_log { 714 __le32 acs[256]; 715 __le32 iocs[256]; 716 __u8 resv[2048]; 717 }; 718 719 enum nvme_ana_state { 720 NVME_ANA_OPTIMIZED = 0x01, 721 NVME_ANA_NONOPTIMIZED = 0x02, 722 NVME_ANA_INACCESSIBLE = 0x03, 723 NVME_ANA_PERSISTENT_LOSS = 0x04, 724 NVME_ANA_CHANGE = 0x0f, 725 }; 726 727 struct nvme_ana_group_desc { 728 __le32 grpid; 729 __le32 nnsids; 730 __le64 chgcnt; 731 __u8 state; 732 __u8 rsvd17[15]; 733 __le32 nsids[]; 734 }; 735 736 /* flag for the log specific field of the ANA log */ 737 #define NVME_ANA_LOG_RGO (1 << 0) 738 739 struct nvme_ana_rsp_hdr { 740 __le64 chgcnt; 741 __le16 ngrps; 742 __le16 rsvd10[3]; 743 }; 744 745 struct nvme_zone_descriptor { 746 __u8 zt; 747 __u8 zs; 748 __u8 za; 749 __u8 rsvd3[5]; 750 __le64 zcap; 751 __le64 zslba; 752 __le64 wp; 753 __u8 rsvd32[32]; 754 }; 755 756 enum { 757 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, 758 }; 759 760 struct nvme_zone_report { 761 __le64 nr_zones; 762 __u8 resv8[56]; 763 struct nvme_zone_descriptor entries[]; 764 }; 765 766 enum { 767 NVME_SMART_CRIT_SPARE = 1 << 0, 768 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 769 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 770 NVME_SMART_CRIT_MEDIA = 1 << 3, 771 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 772 }; 773 774 enum { 775 NVME_AER_ERROR = 0, 776 NVME_AER_SMART = 1, 777 NVME_AER_NOTICE = 2, 778 NVME_AER_CSS = 6, 779 NVME_AER_VS = 7, 780 }; 781 782 enum { 783 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03, 784 }; 785 786 enum { 787 NVME_AER_NOTICE_NS_CHANGED = 0x00, 788 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 789 NVME_AER_NOTICE_ANA = 0x03, 790 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 791 }; 792 793 enum { 794 NVME_AEN_BIT_NS_ATTR = 8, 795 NVME_AEN_BIT_FW_ACT = 9, 796 NVME_AEN_BIT_ANA_CHANGE = 11, 797 NVME_AEN_BIT_DISC_CHANGE = 31, 798 }; 799 800 enum { 801 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 802 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 803 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 804 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 805 }; 806 807 struct nvme_lba_range_type { 808 __u8 type; 809 __u8 attributes; 810 __u8 rsvd2[14]; 811 __le64 slba; 812 __le64 nlb; 813 __u8 guid[16]; 814 __u8 rsvd48[16]; 815 }; 816 817 enum { 818 NVME_LBART_TYPE_FS = 0x01, 819 NVME_LBART_TYPE_RAID = 0x02, 820 NVME_LBART_TYPE_CACHE = 0x03, 821 NVME_LBART_TYPE_SWAP = 0x04, 822 823 NVME_LBART_ATTRIB_TEMP = 1 << 0, 824 NVME_LBART_ATTRIB_HIDE = 1 << 1, 825 }; 826 827 enum nvme_pr_type { 828 NVME_PR_WRITE_EXCLUSIVE = 1, 829 NVME_PR_EXCLUSIVE_ACCESS = 2, 830 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3, 831 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4, 832 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5, 833 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6, 834 }; 835 836 enum nvme_eds { 837 NVME_EXTENDED_DATA_STRUCT = 0x1, 838 }; 839 840 struct nvme_registered_ctrl { 841 __le16 cntlid; 842 __u8 rcsts; 843 __u8 rsvd3[5]; 844 __le64 hostid; 845 __le64 rkey; 846 }; 847 848 struct nvme_reservation_status { 849 __le32 gen; 850 __u8 rtype; 851 __u8 regctl[2]; 852 __u8 resv5[2]; 853 __u8 ptpls; 854 __u8 resv10[14]; 855 struct nvme_registered_ctrl regctl_ds[]; 856 }; 857 858 struct nvme_registered_ctrl_ext { 859 __le16 cntlid; 860 __u8 rcsts; 861 __u8 rsvd3[5]; 862 __le64 rkey; 863 __u8 hostid[16]; 864 __u8 rsvd32[32]; 865 }; 866 867 struct nvme_reservation_status_ext { 868 __le32 gen; 869 __u8 rtype; 870 __u8 regctl[2]; 871 __u8 resv5[2]; 872 __u8 ptpls; 873 __u8 resv10[14]; 874 __u8 rsvd24[40]; 875 struct nvme_registered_ctrl_ext regctl_eds[]; 876 }; 877 878 /* I/O commands */ 879 880 enum nvme_opcode { 881 nvme_cmd_flush = 0x00, 882 nvme_cmd_write = 0x01, 883 nvme_cmd_read = 0x02, 884 nvme_cmd_write_uncor = 0x04, 885 nvme_cmd_compare = 0x05, 886 nvme_cmd_write_zeroes = 0x08, 887 nvme_cmd_dsm = 0x09, 888 nvme_cmd_verify = 0x0c, 889 nvme_cmd_resv_register = 0x0d, 890 nvme_cmd_resv_report = 0x0e, 891 nvme_cmd_resv_acquire = 0x11, 892 nvme_cmd_resv_release = 0x15, 893 nvme_cmd_zone_mgmt_send = 0x79, 894 nvme_cmd_zone_mgmt_recv = 0x7a, 895 nvme_cmd_zone_append = 0x7d, 896 nvme_cmd_vendor_start = 0x80, 897 }; 898 899 #define nvme_opcode_name(opcode) { opcode, #opcode } 900 #define show_nvm_opcode_name(val) \ 901 __print_symbolic(val, \ 902 nvme_opcode_name(nvme_cmd_flush), \ 903 nvme_opcode_name(nvme_cmd_write), \ 904 nvme_opcode_name(nvme_cmd_read), \ 905 nvme_opcode_name(nvme_cmd_write_uncor), \ 906 nvme_opcode_name(nvme_cmd_compare), \ 907 nvme_opcode_name(nvme_cmd_write_zeroes), \ 908 nvme_opcode_name(nvme_cmd_dsm), \ 909 nvme_opcode_name(nvme_cmd_verify), \ 910 nvme_opcode_name(nvme_cmd_resv_register), \ 911 nvme_opcode_name(nvme_cmd_resv_report), \ 912 nvme_opcode_name(nvme_cmd_resv_acquire), \ 913 nvme_opcode_name(nvme_cmd_resv_release), \ 914 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ 915 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ 916 nvme_opcode_name(nvme_cmd_zone_append)) 917 918 919 920 /* 921 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 922 * 923 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 924 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 925 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 926 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 927 * request subtype 928 */ 929 enum { 930 NVME_SGL_FMT_ADDRESS = 0x00, 931 NVME_SGL_FMT_OFFSET = 0x01, 932 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 933 NVME_SGL_FMT_INVALIDATE = 0x0f, 934 }; 935 936 /* 937 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 938 * 939 * For struct nvme_sgl_desc: 940 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 941 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 942 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 943 * 944 * For struct nvme_keyed_sgl_desc: 945 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 946 * 947 * Transport-specific SGL types: 948 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 949 */ 950 enum { 951 NVME_SGL_FMT_DATA_DESC = 0x00, 952 NVME_SGL_FMT_SEG_DESC = 0x02, 953 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 954 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 955 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 956 }; 957 958 struct nvme_sgl_desc { 959 __le64 addr; 960 __le32 length; 961 __u8 rsvd[3]; 962 __u8 type; 963 }; 964 965 struct nvme_keyed_sgl_desc { 966 __le64 addr; 967 __u8 length[3]; 968 __u8 key[4]; 969 __u8 type; 970 }; 971 972 union nvme_data_ptr { 973 struct { 974 __le64 prp1; 975 __le64 prp2; 976 }; 977 struct nvme_sgl_desc sgl; 978 struct nvme_keyed_sgl_desc ksgl; 979 }; 980 981 /* 982 * Lowest two bits of our flags field (FUSE field in the spec): 983 * 984 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 985 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 986 * 987 * Highest two bits in our flags field (PSDT field in the spec): 988 * 989 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 990 * If used, MPTR contains addr of single physical buffer (byte aligned). 991 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 992 * If used, MPTR contains an address of an SGL segment containing 993 * exactly 1 SGL descriptor (qword aligned). 994 */ 995 enum { 996 NVME_CMD_FUSE_FIRST = (1 << 0), 997 NVME_CMD_FUSE_SECOND = (1 << 1), 998 999 NVME_CMD_SGL_METABUF = (1 << 6), 1000 NVME_CMD_SGL_METASEG = (1 << 7), 1001 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 1002 }; 1003 1004 struct nvme_common_command { 1005 __u8 opcode; 1006 __u8 flags; 1007 __u16 command_id; 1008 __le32 nsid; 1009 __le32 cdw2[2]; 1010 __le64 metadata; 1011 union nvme_data_ptr dptr; 1012 struct_group(cdws, 1013 __le32 cdw10; 1014 __le32 cdw11; 1015 __le32 cdw12; 1016 __le32 cdw13; 1017 __le32 cdw14; 1018 __le32 cdw15; 1019 ); 1020 }; 1021 1022 struct nvme_rw_command { 1023 __u8 opcode; 1024 __u8 flags; 1025 __u16 command_id; 1026 __le32 nsid; 1027 __le32 cdw2; 1028 __le32 cdw3; 1029 __le64 metadata; 1030 union nvme_data_ptr dptr; 1031 __le64 slba; 1032 __le16 length; 1033 __le16 control; 1034 __le32 dsmgmt; 1035 __le32 reftag; 1036 __le16 lbat; 1037 __le16 lbatm; 1038 }; 1039 1040 enum { 1041 NVME_RW_LR = 1 << 15, 1042 NVME_RW_FUA = 1 << 14, 1043 NVME_RW_APPEND_PIREMAP = 1 << 9, 1044 NVME_RW_DSM_FREQ_UNSPEC = 0, 1045 NVME_RW_DSM_FREQ_TYPICAL = 1, 1046 NVME_RW_DSM_FREQ_RARE = 2, 1047 NVME_RW_DSM_FREQ_READS = 3, 1048 NVME_RW_DSM_FREQ_WRITES = 4, 1049 NVME_RW_DSM_FREQ_RW = 5, 1050 NVME_RW_DSM_FREQ_ONCE = 6, 1051 NVME_RW_DSM_FREQ_PREFETCH = 7, 1052 NVME_RW_DSM_FREQ_TEMP = 8, 1053 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 1054 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 1055 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 1056 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 1057 NVME_RW_DSM_SEQ_REQ = 1 << 6, 1058 NVME_RW_DSM_COMPRESSED = 1 << 7, 1059 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 1060 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 1061 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 1062 NVME_RW_PRINFO_PRACT = 1 << 13, 1063 NVME_RW_DTYPE_STREAMS = 1 << 4, 1064 NVME_WZ_DEAC = 1 << 9, 1065 }; 1066 1067 struct nvme_dsm_cmd { 1068 __u8 opcode; 1069 __u8 flags; 1070 __u16 command_id; 1071 __le32 nsid; 1072 __u64 rsvd2[2]; 1073 union nvme_data_ptr dptr; 1074 __le32 nr; 1075 __le32 attributes; 1076 __u32 rsvd12[4]; 1077 }; 1078 1079 enum { 1080 NVME_DSMGMT_IDR = 1 << 0, 1081 NVME_DSMGMT_IDW = 1 << 1, 1082 NVME_DSMGMT_AD = 1 << 2, 1083 }; 1084 1085 #define NVME_DSM_MAX_RANGES 256 1086 1087 struct nvme_dsm_range { 1088 __le32 cattr; 1089 __le32 nlb; 1090 __le64 slba; 1091 }; 1092 1093 struct nvme_write_zeroes_cmd { 1094 __u8 opcode; 1095 __u8 flags; 1096 __u16 command_id; 1097 __le32 nsid; 1098 __u64 rsvd2; 1099 __le64 metadata; 1100 union nvme_data_ptr dptr; 1101 __le64 slba; 1102 __le16 length; 1103 __le16 control; 1104 __le32 dsmgmt; 1105 __le32 reftag; 1106 __le16 lbat; 1107 __le16 lbatm; 1108 }; 1109 1110 enum nvme_zone_mgmt_action { 1111 NVME_ZONE_CLOSE = 0x1, 1112 NVME_ZONE_FINISH = 0x2, 1113 NVME_ZONE_OPEN = 0x3, 1114 NVME_ZONE_RESET = 0x4, 1115 NVME_ZONE_OFFLINE = 0x5, 1116 NVME_ZONE_SET_DESC_EXT = 0x10, 1117 }; 1118 1119 struct nvme_zone_mgmt_send_cmd { 1120 __u8 opcode; 1121 __u8 flags; 1122 __u16 command_id; 1123 __le32 nsid; 1124 __le32 cdw2[2]; 1125 __le64 metadata; 1126 union nvme_data_ptr dptr; 1127 __le64 slba; 1128 __le32 cdw12; 1129 __u8 zsa; 1130 __u8 select_all; 1131 __u8 rsvd13[2]; 1132 __le32 cdw14[2]; 1133 }; 1134 1135 struct nvme_zone_mgmt_recv_cmd { 1136 __u8 opcode; 1137 __u8 flags; 1138 __u16 command_id; 1139 __le32 nsid; 1140 __le64 rsvd2[2]; 1141 union nvme_data_ptr dptr; 1142 __le64 slba; 1143 __le32 numd; 1144 __u8 zra; 1145 __u8 zrasf; 1146 __u8 pr; 1147 __u8 rsvd13; 1148 __le32 cdw14[2]; 1149 }; 1150 1151 enum { 1152 NVME_ZRA_ZONE_REPORT = 0, 1153 NVME_ZRASF_ZONE_REPORT_ALL = 0, 1154 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, 1155 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, 1156 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, 1157 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, 1158 NVME_ZRASF_ZONE_STATE_READONLY = 0x05, 1159 NVME_ZRASF_ZONE_STATE_FULL = 0x06, 1160 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, 1161 NVME_REPORT_ZONE_PARTIAL = 1, 1162 }; 1163 1164 /* Features */ 1165 1166 enum { 1167 NVME_TEMP_THRESH_MASK = 0xffff, 1168 NVME_TEMP_THRESH_SELECT_SHIFT = 16, 1169 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, 1170 }; 1171 1172 struct nvme_feat_auto_pst { 1173 __le64 entries[32]; 1174 }; 1175 1176 enum { 1177 NVME_HOST_MEM_ENABLE = (1 << 0), 1178 NVME_HOST_MEM_RETURN = (1 << 1), 1179 }; 1180 1181 struct nvme_feat_host_behavior { 1182 __u8 acre; 1183 __u8 etdas; 1184 __u8 lbafee; 1185 __u8 resv1[509]; 1186 }; 1187 1188 enum { 1189 NVME_ENABLE_ACRE = 1, 1190 NVME_ENABLE_LBAFEE = 1, 1191 }; 1192 1193 /* Admin commands */ 1194 1195 enum nvme_admin_opcode { 1196 nvme_admin_delete_sq = 0x00, 1197 nvme_admin_create_sq = 0x01, 1198 nvme_admin_get_log_page = 0x02, 1199 nvme_admin_delete_cq = 0x04, 1200 nvme_admin_create_cq = 0x05, 1201 nvme_admin_identify = 0x06, 1202 nvme_admin_abort_cmd = 0x08, 1203 nvme_admin_set_features = 0x09, 1204 nvme_admin_get_features = 0x0a, 1205 nvme_admin_async_event = 0x0c, 1206 nvme_admin_ns_mgmt = 0x0d, 1207 nvme_admin_activate_fw = 0x10, 1208 nvme_admin_download_fw = 0x11, 1209 nvme_admin_dev_self_test = 0x14, 1210 nvme_admin_ns_attach = 0x15, 1211 nvme_admin_keep_alive = 0x18, 1212 nvme_admin_directive_send = 0x19, 1213 nvme_admin_directive_recv = 0x1a, 1214 nvme_admin_virtual_mgmt = 0x1c, 1215 nvme_admin_nvme_mi_send = 0x1d, 1216 nvme_admin_nvme_mi_recv = 0x1e, 1217 nvme_admin_dbbuf = 0x7C, 1218 nvme_admin_format_nvm = 0x80, 1219 nvme_admin_security_send = 0x81, 1220 nvme_admin_security_recv = 0x82, 1221 nvme_admin_sanitize_nvm = 0x84, 1222 nvme_admin_get_lba_status = 0x86, 1223 nvme_admin_vendor_start = 0xC0, 1224 }; 1225 1226 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 1227 #define show_admin_opcode_name(val) \ 1228 __print_symbolic(val, \ 1229 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 1230 nvme_admin_opcode_name(nvme_admin_create_sq), \ 1231 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 1232 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 1233 nvme_admin_opcode_name(nvme_admin_create_cq), \ 1234 nvme_admin_opcode_name(nvme_admin_identify), \ 1235 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 1236 nvme_admin_opcode_name(nvme_admin_set_features), \ 1237 nvme_admin_opcode_name(nvme_admin_get_features), \ 1238 nvme_admin_opcode_name(nvme_admin_async_event), \ 1239 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 1240 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 1241 nvme_admin_opcode_name(nvme_admin_download_fw), \ 1242 nvme_admin_opcode_name(nvme_admin_dev_self_test), \ 1243 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 1244 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 1245 nvme_admin_opcode_name(nvme_admin_directive_send), \ 1246 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 1247 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \ 1248 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \ 1249 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \ 1250 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 1251 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 1252 nvme_admin_opcode_name(nvme_admin_security_send), \ 1253 nvme_admin_opcode_name(nvme_admin_security_recv), \ 1254 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 1255 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 1256 1257 enum { 1258 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 1259 NVME_CQ_IRQ_ENABLED = (1 << 1), 1260 NVME_SQ_PRIO_URGENT = (0 << 1), 1261 NVME_SQ_PRIO_HIGH = (1 << 1), 1262 NVME_SQ_PRIO_MEDIUM = (2 << 1), 1263 NVME_SQ_PRIO_LOW = (3 << 1), 1264 NVME_FEAT_ARBITRATION = 0x01, 1265 NVME_FEAT_POWER_MGMT = 0x02, 1266 NVME_FEAT_LBA_RANGE = 0x03, 1267 NVME_FEAT_TEMP_THRESH = 0x04, 1268 NVME_FEAT_ERR_RECOVERY = 0x05, 1269 NVME_FEAT_VOLATILE_WC = 0x06, 1270 NVME_FEAT_NUM_QUEUES = 0x07, 1271 NVME_FEAT_IRQ_COALESCE = 0x08, 1272 NVME_FEAT_IRQ_CONFIG = 0x09, 1273 NVME_FEAT_WRITE_ATOMIC = 0x0a, 1274 NVME_FEAT_ASYNC_EVENT = 0x0b, 1275 NVME_FEAT_AUTO_PST = 0x0c, 1276 NVME_FEAT_HOST_MEM_BUF = 0x0d, 1277 NVME_FEAT_TIMESTAMP = 0x0e, 1278 NVME_FEAT_KATO = 0x0f, 1279 NVME_FEAT_HCTM = 0x10, 1280 NVME_FEAT_NOPSC = 0x11, 1281 NVME_FEAT_RRL = 0x12, 1282 NVME_FEAT_PLM_CONFIG = 0x13, 1283 NVME_FEAT_PLM_WINDOW = 0x14, 1284 NVME_FEAT_HOST_BEHAVIOR = 0x16, 1285 NVME_FEAT_SANITIZE = 0x17, 1286 NVME_FEAT_SW_PROGRESS = 0x80, 1287 NVME_FEAT_HOST_ID = 0x81, 1288 NVME_FEAT_RESV_MASK = 0x82, 1289 NVME_FEAT_RESV_PERSIST = 0x83, 1290 NVME_FEAT_WRITE_PROTECT = 0x84, 1291 NVME_FEAT_VENDOR_START = 0xC0, 1292 NVME_FEAT_VENDOR_END = 0xFF, 1293 NVME_LOG_SUPPORTED = 0x00, 1294 NVME_LOG_ERROR = 0x01, 1295 NVME_LOG_SMART = 0x02, 1296 NVME_LOG_FW_SLOT = 0x03, 1297 NVME_LOG_CHANGED_NS = 0x04, 1298 NVME_LOG_CMD_EFFECTS = 0x05, 1299 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1300 NVME_LOG_TELEMETRY_HOST = 0x07, 1301 NVME_LOG_TELEMETRY_CTRL = 0x08, 1302 NVME_LOG_ENDURANCE_GROUP = 0x09, 1303 NVME_LOG_ANA = 0x0c, 1304 NVME_LOG_FEATURES = 0x12, 1305 NVME_LOG_RMI = 0x16, 1306 NVME_LOG_DISC = 0x70, 1307 NVME_LOG_RESERVATION = 0x80, 1308 NVME_FWACT_REPL = (0 << 3), 1309 NVME_FWACT_REPL_ACTV = (1 << 3), 1310 NVME_FWACT_ACTV = (2 << 3), 1311 }; 1312 1313 struct nvme_supported_log { 1314 __le32 lids[256]; 1315 }; 1316 1317 enum { 1318 NVME_LIDS_LSUPP = 1 << 0, 1319 }; 1320 1321 struct nvme_supported_features_log { 1322 __le32 fis[256]; 1323 }; 1324 1325 enum { 1326 NVME_FIS_FSUPP = 1 << 0, 1327 NVME_FIS_NSCPE = 1 << 20, 1328 NVME_FIS_CSCPE = 1 << 21, 1329 }; 1330 1331 /* NVMe Namespace Write Protect State */ 1332 enum { 1333 NVME_NS_NO_WRITE_PROTECT = 0, 1334 NVME_NS_WRITE_PROTECT, 1335 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 1336 NVME_NS_WRITE_PROTECT_PERMANENT, 1337 }; 1338 1339 #define NVME_MAX_CHANGED_NAMESPACES 1024 1340 1341 struct nvme_identify { 1342 __u8 opcode; 1343 __u8 flags; 1344 __u16 command_id; 1345 __le32 nsid; 1346 __u64 rsvd2[2]; 1347 union nvme_data_ptr dptr; 1348 __u8 cns; 1349 __u8 rsvd3; 1350 __le16 ctrlid; 1351 __le16 cnssid; 1352 __u8 rsvd11; 1353 __u8 csi; 1354 __u32 rsvd12[4]; 1355 }; 1356 1357 #define NVME_IDENTIFY_DATA_SIZE 4096 1358 1359 struct nvme_features { 1360 __u8 opcode; 1361 __u8 flags; 1362 __u16 command_id; 1363 __le32 nsid; 1364 __u64 rsvd2[2]; 1365 union nvme_data_ptr dptr; 1366 __le32 fid; 1367 __le32 dword11; 1368 __le32 dword12; 1369 __le32 dword13; 1370 __le32 dword14; 1371 __le32 dword15; 1372 }; 1373 1374 struct nvme_host_mem_buf_desc { 1375 __le64 addr; 1376 __le32 size; 1377 __u32 rsvd; 1378 }; 1379 1380 struct nvme_create_cq { 1381 __u8 opcode; 1382 __u8 flags; 1383 __u16 command_id; 1384 __u32 rsvd1[5]; 1385 __le64 prp1; 1386 __u64 rsvd8; 1387 __le16 cqid; 1388 __le16 qsize; 1389 __le16 cq_flags; 1390 __le16 irq_vector; 1391 __u32 rsvd12[4]; 1392 }; 1393 1394 struct nvme_create_sq { 1395 __u8 opcode; 1396 __u8 flags; 1397 __u16 command_id; 1398 __u32 rsvd1[5]; 1399 __le64 prp1; 1400 __u64 rsvd8; 1401 __le16 sqid; 1402 __le16 qsize; 1403 __le16 sq_flags; 1404 __le16 cqid; 1405 __u32 rsvd12[4]; 1406 }; 1407 1408 struct nvme_delete_queue { 1409 __u8 opcode; 1410 __u8 flags; 1411 __u16 command_id; 1412 __u32 rsvd1[9]; 1413 __le16 qid; 1414 __u16 rsvd10; 1415 __u32 rsvd11[5]; 1416 }; 1417 1418 struct nvme_abort_cmd { 1419 __u8 opcode; 1420 __u8 flags; 1421 __u16 command_id; 1422 __u32 rsvd1[9]; 1423 __le16 sqid; 1424 __u16 cid; 1425 __u32 rsvd11[5]; 1426 }; 1427 1428 struct nvme_download_firmware { 1429 __u8 opcode; 1430 __u8 flags; 1431 __u16 command_id; 1432 __u32 rsvd1[5]; 1433 union nvme_data_ptr dptr; 1434 __le32 numd; 1435 __le32 offset; 1436 __u32 rsvd12[4]; 1437 }; 1438 1439 struct nvme_format_cmd { 1440 __u8 opcode; 1441 __u8 flags; 1442 __u16 command_id; 1443 __le32 nsid; 1444 __u64 rsvd2[4]; 1445 __le32 cdw10; 1446 __u32 rsvd11[5]; 1447 }; 1448 1449 struct nvme_get_log_page_command { 1450 __u8 opcode; 1451 __u8 flags; 1452 __u16 command_id; 1453 __le32 nsid; 1454 __u64 rsvd2[2]; 1455 union nvme_data_ptr dptr; 1456 __u8 lid; 1457 __u8 lsp; /* upper 4 bits reserved */ 1458 __le16 numdl; 1459 __le16 numdu; 1460 __le16 lsi; 1461 union { 1462 struct { 1463 __le32 lpol; 1464 __le32 lpou; 1465 }; 1466 __le64 lpo; 1467 }; 1468 __u8 rsvd14[3]; 1469 __u8 csi; 1470 __u32 rsvd15; 1471 }; 1472 1473 struct nvme_directive_cmd { 1474 __u8 opcode; 1475 __u8 flags; 1476 __u16 command_id; 1477 __le32 nsid; 1478 __u64 rsvd2[2]; 1479 union nvme_data_ptr dptr; 1480 __le32 numd; 1481 __u8 doper; 1482 __u8 dtype; 1483 __le16 dspec; 1484 __u8 endir; 1485 __u8 tdtype; 1486 __u16 rsvd15; 1487 1488 __u32 rsvd16[3]; 1489 }; 1490 1491 /* 1492 * Fabrics subcommands. 1493 */ 1494 enum nvmf_fabrics_opcode { 1495 nvme_fabrics_command = 0x7f, 1496 }; 1497 1498 enum nvmf_capsule_command { 1499 nvme_fabrics_type_property_set = 0x00, 1500 nvme_fabrics_type_connect = 0x01, 1501 nvme_fabrics_type_property_get = 0x04, 1502 nvme_fabrics_type_auth_send = 0x05, 1503 nvme_fabrics_type_auth_receive = 0x06, 1504 }; 1505 1506 #define nvme_fabrics_type_name(type) { type, #type } 1507 #define show_fabrics_type_name(type) \ 1508 __print_symbolic(type, \ 1509 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1510 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1511 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \ 1512 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \ 1513 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive)) 1514 1515 /* 1516 * If not fabrics command, fctype will be ignored. 1517 */ 1518 #define show_opcode_name(qid, opcode, fctype) \ 1519 ((opcode) == nvme_fabrics_command ? \ 1520 show_fabrics_type_name(fctype) : \ 1521 ((qid) ? \ 1522 show_nvm_opcode_name(opcode) : \ 1523 show_admin_opcode_name(opcode))) 1524 1525 struct nvmf_common_command { 1526 __u8 opcode; 1527 __u8 resv1; 1528 __u16 command_id; 1529 __u8 fctype; 1530 __u8 resv2[35]; 1531 __u8 ts[24]; 1532 }; 1533 1534 /* 1535 * The legal cntlid range a NVMe Target will provide. 1536 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1537 * Devices based on earlier specs did not have the subsystem concept; 1538 * therefore, those devices had their cntlid value set to 0 as a result. 1539 */ 1540 #define NVME_CNTLID_MIN 1 1541 #define NVME_CNTLID_MAX 0xffef 1542 #define NVME_CNTLID_DYNAMIC 0xffff 1543 1544 #define MAX_DISC_LOGS 255 1545 1546 /* Discovery log page entry flags (EFLAGS): */ 1547 enum { 1548 NVME_DISC_EFLAGS_EPCSD = (1 << 1), 1549 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0), 1550 }; 1551 1552 /* Discovery log page entry */ 1553 struct nvmf_disc_rsp_page_entry { 1554 __u8 trtype; 1555 __u8 adrfam; 1556 __u8 subtype; 1557 __u8 treq; 1558 __le16 portid; 1559 __le16 cntlid; 1560 __le16 asqsz; 1561 __le16 eflags; 1562 __u8 resv10[20]; 1563 char trsvcid[NVMF_TRSVCID_SIZE]; 1564 __u8 resv64[192]; 1565 char subnqn[NVMF_NQN_FIELD_LEN]; 1566 char traddr[NVMF_TRADDR_SIZE]; 1567 union tsas { 1568 char common[NVMF_TSAS_SIZE]; 1569 struct rdma { 1570 __u8 qptype; 1571 __u8 prtype; 1572 __u8 cms; 1573 __u8 resv3[5]; 1574 __u16 pkey; 1575 __u8 resv10[246]; 1576 } rdma; 1577 struct tcp { 1578 __u8 sectype; 1579 } tcp; 1580 } tsas; 1581 }; 1582 1583 /* Discovery log page header */ 1584 struct nvmf_disc_rsp_page_hdr { 1585 __le64 genctr; 1586 __le64 numrec; 1587 __le16 recfmt; 1588 __u8 resv14[1006]; 1589 struct nvmf_disc_rsp_page_entry entries[]; 1590 }; 1591 1592 enum { 1593 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1594 }; 1595 1596 struct nvmf_connect_command { 1597 __u8 opcode; 1598 __u8 resv1; 1599 __u16 command_id; 1600 __u8 fctype; 1601 __u8 resv2[19]; 1602 union nvme_data_ptr dptr; 1603 __le16 recfmt; 1604 __le16 qid; 1605 __le16 sqsize; 1606 __u8 cattr; 1607 __u8 resv3; 1608 __le32 kato; 1609 __u8 resv4[12]; 1610 }; 1611 1612 enum { 1613 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18), 1614 NVME_CONNECT_AUTHREQ_ATR = (1U << 17), 1615 }; 1616 1617 struct nvmf_connect_data { 1618 uuid_t hostid; 1619 __le16 cntlid; 1620 char resv4[238]; 1621 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1622 char hostnqn[NVMF_NQN_FIELD_LEN]; 1623 char resv5[256]; 1624 }; 1625 1626 struct nvmf_property_set_command { 1627 __u8 opcode; 1628 __u8 resv1; 1629 __u16 command_id; 1630 __u8 fctype; 1631 __u8 resv2[35]; 1632 __u8 attrib; 1633 __u8 resv3[3]; 1634 __le32 offset; 1635 __le64 value; 1636 __u8 resv4[8]; 1637 }; 1638 1639 struct nvmf_property_get_command { 1640 __u8 opcode; 1641 __u8 resv1; 1642 __u16 command_id; 1643 __u8 fctype; 1644 __u8 resv2[35]; 1645 __u8 attrib; 1646 __u8 resv3[3]; 1647 __le32 offset; 1648 __u8 resv4[16]; 1649 }; 1650 1651 struct nvmf_auth_common_command { 1652 __u8 opcode; 1653 __u8 resv1; 1654 __u16 command_id; 1655 __u8 fctype; 1656 __u8 resv2[19]; 1657 union nvme_data_ptr dptr; 1658 __u8 resv3; 1659 __u8 spsp0; 1660 __u8 spsp1; 1661 __u8 secp; 1662 __le32 al_tl; 1663 __u8 resv4[16]; 1664 }; 1665 1666 struct nvmf_auth_send_command { 1667 __u8 opcode; 1668 __u8 resv1; 1669 __u16 command_id; 1670 __u8 fctype; 1671 __u8 resv2[19]; 1672 union nvme_data_ptr dptr; 1673 __u8 resv3; 1674 __u8 spsp0; 1675 __u8 spsp1; 1676 __u8 secp; 1677 __le32 tl; 1678 __u8 resv4[16]; 1679 }; 1680 1681 struct nvmf_auth_receive_command { 1682 __u8 opcode; 1683 __u8 resv1; 1684 __u16 command_id; 1685 __u8 fctype; 1686 __u8 resv2[19]; 1687 union nvme_data_ptr dptr; 1688 __u8 resv3; 1689 __u8 spsp0; 1690 __u8 spsp1; 1691 __u8 secp; 1692 __le32 al; 1693 __u8 resv4[16]; 1694 }; 1695 1696 /* Value for secp */ 1697 enum { 1698 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9, 1699 }; 1700 1701 /* Defined value for auth_type */ 1702 enum { 1703 NVME_AUTH_COMMON_MESSAGES = 0x00, 1704 NVME_AUTH_DHCHAP_MESSAGES = 0x01, 1705 }; 1706 1707 /* Defined messages for auth_id */ 1708 enum { 1709 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00, 1710 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01, 1711 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02, 1712 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03, 1713 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04, 1714 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0, 1715 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1, 1716 }; 1717 1718 struct nvmf_auth_dhchap_protocol_descriptor { 1719 __u8 authid; 1720 __u8 rsvd; 1721 __u8 halen; 1722 __u8 dhlen; 1723 __u8 idlist[60]; 1724 }; 1725 1726 enum { 1727 NVME_AUTH_DHCHAP_AUTH_ID = 0x01, 1728 }; 1729 1730 /* Defined hash functions for DH-HMAC-CHAP authentication */ 1731 enum { 1732 NVME_AUTH_HASH_SHA256 = 0x01, 1733 NVME_AUTH_HASH_SHA384 = 0x02, 1734 NVME_AUTH_HASH_SHA512 = 0x03, 1735 NVME_AUTH_HASH_INVALID = 0xff, 1736 }; 1737 1738 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */ 1739 enum { 1740 NVME_AUTH_DHGROUP_NULL = 0x00, 1741 NVME_AUTH_DHGROUP_2048 = 0x01, 1742 NVME_AUTH_DHGROUP_3072 = 0x02, 1743 NVME_AUTH_DHGROUP_4096 = 0x03, 1744 NVME_AUTH_DHGROUP_6144 = 0x04, 1745 NVME_AUTH_DHGROUP_8192 = 0x05, 1746 NVME_AUTH_DHGROUP_INVALID = 0xff, 1747 }; 1748 1749 union nvmf_auth_protocol { 1750 struct nvmf_auth_dhchap_protocol_descriptor dhchap; 1751 }; 1752 1753 struct nvmf_auth_dhchap_negotiate_data { 1754 __u8 auth_type; 1755 __u8 auth_id; 1756 __le16 rsvd; 1757 __le16 t_id; 1758 __u8 sc_c; 1759 __u8 napd; 1760 union nvmf_auth_protocol auth_protocol[]; 1761 }; 1762 1763 struct nvmf_auth_dhchap_challenge_data { 1764 __u8 auth_type; 1765 __u8 auth_id; 1766 __u16 rsvd1; 1767 __le16 t_id; 1768 __u8 hl; 1769 __u8 rsvd2; 1770 __u8 hashid; 1771 __u8 dhgid; 1772 __le16 dhvlen; 1773 __le32 seqnum; 1774 /* 'hl' bytes of challenge value */ 1775 __u8 cval[]; 1776 /* followed by 'dhvlen' bytes of DH value */ 1777 }; 1778 1779 struct nvmf_auth_dhchap_reply_data { 1780 __u8 auth_type; 1781 __u8 auth_id; 1782 __le16 rsvd1; 1783 __le16 t_id; 1784 __u8 hl; 1785 __u8 rsvd2; 1786 __u8 cvalid; 1787 __u8 rsvd3; 1788 __le16 dhvlen; 1789 __le32 seqnum; 1790 /* 'hl' bytes of response data */ 1791 __u8 rval[]; 1792 /* followed by 'hl' bytes of Challenge value */ 1793 /* followed by 'dhvlen' bytes of DH value */ 1794 }; 1795 1796 enum { 1797 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0), 1798 }; 1799 1800 struct nvmf_auth_dhchap_success1_data { 1801 __u8 auth_type; 1802 __u8 auth_id; 1803 __le16 rsvd1; 1804 __le16 t_id; 1805 __u8 hl; 1806 __u8 rsvd2; 1807 __u8 rvalid; 1808 __u8 rsvd3[7]; 1809 /* 'hl' bytes of response value */ 1810 __u8 rval[]; 1811 }; 1812 1813 struct nvmf_auth_dhchap_success2_data { 1814 __u8 auth_type; 1815 __u8 auth_id; 1816 __le16 rsvd1; 1817 __le16 t_id; 1818 __u8 rsvd2[10]; 1819 }; 1820 1821 struct nvmf_auth_dhchap_failure_data { 1822 __u8 auth_type; 1823 __u8 auth_id; 1824 __le16 rsvd1; 1825 __le16 t_id; 1826 __u8 rescode; 1827 __u8 rescode_exp; 1828 }; 1829 1830 enum { 1831 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01, 1832 }; 1833 1834 enum { 1835 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01, 1836 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02, 1837 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03, 1838 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04, 1839 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05, 1840 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06, 1841 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07, 1842 }; 1843 1844 1845 struct nvme_dbbuf { 1846 __u8 opcode; 1847 __u8 flags; 1848 __u16 command_id; 1849 __u32 rsvd1[5]; 1850 __le64 prp1; 1851 __le64 prp2; 1852 __u32 rsvd12[6]; 1853 }; 1854 1855 struct streams_directive_params { 1856 __le16 msl; 1857 __le16 nssa; 1858 __le16 nsso; 1859 __u8 rsvd[10]; 1860 __le32 sws; 1861 __le16 sgs; 1862 __le16 nsa; 1863 __le16 nso; 1864 __u8 rsvd2[6]; 1865 }; 1866 1867 struct nvme_command { 1868 union { 1869 struct nvme_common_command common; 1870 struct nvme_rw_command rw; 1871 struct nvme_identify identify; 1872 struct nvme_features features; 1873 struct nvme_create_cq create_cq; 1874 struct nvme_create_sq create_sq; 1875 struct nvme_delete_queue delete_queue; 1876 struct nvme_download_firmware dlfw; 1877 struct nvme_format_cmd format; 1878 struct nvme_dsm_cmd dsm; 1879 struct nvme_write_zeroes_cmd write_zeroes; 1880 struct nvme_zone_mgmt_send_cmd zms; 1881 struct nvme_zone_mgmt_recv_cmd zmr; 1882 struct nvme_abort_cmd abort; 1883 struct nvme_get_log_page_command get_log_page; 1884 struct nvmf_common_command fabrics; 1885 struct nvmf_connect_command connect; 1886 struct nvmf_property_set_command prop_set; 1887 struct nvmf_property_get_command prop_get; 1888 struct nvmf_auth_common_command auth_common; 1889 struct nvmf_auth_send_command auth_send; 1890 struct nvmf_auth_receive_command auth_receive; 1891 struct nvme_dbbuf dbbuf; 1892 struct nvme_directive_cmd directive; 1893 }; 1894 }; 1895 1896 static inline bool nvme_is_fabrics(const struct nvme_command *cmd) 1897 { 1898 return cmd->common.opcode == nvme_fabrics_command; 1899 } 1900 1901 #ifdef CONFIG_NVME_VERBOSE_ERRORS 1902 const char *nvme_get_error_status_str(u16 status); 1903 const char *nvme_get_opcode_str(u8 opcode); 1904 const char *nvme_get_admin_opcode_str(u8 opcode); 1905 const char *nvme_get_fabrics_opcode_str(u8 opcode); 1906 #else /* CONFIG_NVME_VERBOSE_ERRORS */ 1907 static inline const char *nvme_get_error_status_str(u16 status) 1908 { 1909 return "I/O Error"; 1910 } 1911 static inline const char *nvme_get_opcode_str(u8 opcode) 1912 { 1913 return "I/O Cmd"; 1914 } 1915 static inline const char *nvme_get_admin_opcode_str(u8 opcode) 1916 { 1917 return "Admin Cmd"; 1918 } 1919 1920 static inline const char *nvme_get_fabrics_opcode_str(u8 opcode) 1921 { 1922 return "Fabrics Cmd"; 1923 } 1924 #endif /* CONFIG_NVME_VERBOSE_ERRORS */ 1925 1926 static inline const char *nvme_opcode_str(int qid, u8 opcode) 1927 { 1928 return qid ? nvme_get_opcode_str(opcode) : 1929 nvme_get_admin_opcode_str(opcode); 1930 } 1931 1932 static inline const char *nvme_fabrics_opcode_str( 1933 int qid, const struct nvme_command *cmd) 1934 { 1935 if (nvme_is_fabrics(cmd)) 1936 return nvme_get_fabrics_opcode_str(cmd->fabrics.fctype); 1937 1938 return nvme_opcode_str(qid, cmd->common.opcode); 1939 } 1940 1941 struct nvme_error_slot { 1942 __le64 error_count; 1943 __le16 sqid; 1944 __le16 cmdid; 1945 __le16 status_field; 1946 __le16 param_error_location; 1947 __le64 lba; 1948 __le32 nsid; 1949 __u8 vs; 1950 __u8 resv[3]; 1951 __le64 cs; 1952 __u8 resv2[24]; 1953 }; 1954 1955 static inline bool nvme_is_write(const struct nvme_command *cmd) 1956 { 1957 /* 1958 * What a mess... 1959 * 1960 * Why can't we simply have a Fabrics In and Fabrics out command? 1961 */ 1962 if (unlikely(nvme_is_fabrics(cmd))) 1963 return cmd->fabrics.fctype & 1; 1964 return cmd->common.opcode & 1; 1965 } 1966 1967 enum { 1968 /* 1969 * Generic Command Status: 1970 */ 1971 NVME_SCT_GENERIC = 0x0, 1972 NVME_SC_SUCCESS = 0x0, 1973 NVME_SC_INVALID_OPCODE = 0x1, 1974 NVME_SC_INVALID_FIELD = 0x2, 1975 NVME_SC_CMDID_CONFLICT = 0x3, 1976 NVME_SC_DATA_XFER_ERROR = 0x4, 1977 NVME_SC_POWER_LOSS = 0x5, 1978 NVME_SC_INTERNAL = 0x6, 1979 NVME_SC_ABORT_REQ = 0x7, 1980 NVME_SC_ABORT_QUEUE = 0x8, 1981 NVME_SC_FUSED_FAIL = 0x9, 1982 NVME_SC_FUSED_MISSING = 0xa, 1983 NVME_SC_INVALID_NS = 0xb, 1984 NVME_SC_CMD_SEQ_ERROR = 0xc, 1985 NVME_SC_SGL_INVALID_LAST = 0xd, 1986 NVME_SC_SGL_INVALID_COUNT = 0xe, 1987 NVME_SC_SGL_INVALID_DATA = 0xf, 1988 NVME_SC_SGL_INVALID_METADATA = 0x10, 1989 NVME_SC_SGL_INVALID_TYPE = 0x11, 1990 NVME_SC_CMB_INVALID_USE = 0x12, 1991 NVME_SC_PRP_INVALID_OFFSET = 0x13, 1992 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, 1993 NVME_SC_OP_DENIED = 0x15, 1994 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1995 NVME_SC_RESERVED = 0x17, 1996 NVME_SC_HOST_ID_INCONSIST = 0x18, 1997 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, 1998 NVME_SC_KA_TIMEOUT_INVALID = 0x1A, 1999 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, 2000 NVME_SC_SANITIZE_FAILED = 0x1C, 2001 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, 2002 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, 2003 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, 2004 NVME_SC_NS_WRITE_PROTECTED = 0x20, 2005 NVME_SC_CMD_INTERRUPTED = 0x21, 2006 NVME_SC_TRANSIENT_TR_ERR = 0x22, 2007 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24, 2008 NVME_SC_INVALID_IO_CMD_SET = 0x2C, 2009 2010 NVME_SC_LBA_RANGE = 0x80, 2011 NVME_SC_CAP_EXCEEDED = 0x81, 2012 NVME_SC_NS_NOT_READY = 0x82, 2013 NVME_SC_RESERVATION_CONFLICT = 0x83, 2014 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 2015 2016 /* 2017 * Command Specific Status: 2018 */ 2019 NVME_SCT_COMMAND_SPECIFIC = 0x100, 2020 NVME_SC_CQ_INVALID = 0x100, 2021 NVME_SC_QID_INVALID = 0x101, 2022 NVME_SC_QUEUE_SIZE = 0x102, 2023 NVME_SC_ABORT_LIMIT = 0x103, 2024 NVME_SC_ABORT_MISSING = 0x104, 2025 NVME_SC_ASYNC_LIMIT = 0x105, 2026 NVME_SC_FIRMWARE_SLOT = 0x106, 2027 NVME_SC_FIRMWARE_IMAGE = 0x107, 2028 NVME_SC_INVALID_VECTOR = 0x108, 2029 NVME_SC_INVALID_LOG_PAGE = 0x109, 2030 NVME_SC_INVALID_FORMAT = 0x10a, 2031 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 2032 NVME_SC_INVALID_QUEUE = 0x10c, 2033 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 2034 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 2035 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 2036 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 2037 NVME_SC_FW_NEEDS_RESET = 0x111, 2038 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 2039 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 2040 NVME_SC_OVERLAPPING_RANGE = 0x114, 2041 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 2042 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 2043 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 2044 NVME_SC_NS_IS_PRIVATE = 0x119, 2045 NVME_SC_NS_NOT_ATTACHED = 0x11a, 2046 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 2047 NVME_SC_CTRL_LIST_INVALID = 0x11c, 2048 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, 2049 NVME_SC_BP_WRITE_PROHIBITED = 0x11e, 2050 NVME_SC_CTRL_ID_INVALID = 0x11f, 2051 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, 2052 NVME_SC_CTRL_RES_NUM_INVALID = 0x121, 2053 NVME_SC_RES_ID_INVALID = 0x122, 2054 NVME_SC_PMR_SAN_PROHIBITED = 0x123, 2055 NVME_SC_ANA_GROUP_ID_INVALID = 0x124, 2056 NVME_SC_ANA_ATTACH_FAILED = 0x125, 2057 2058 /* 2059 * I/O Command Set Specific - NVM commands: 2060 */ 2061 NVME_SC_BAD_ATTRIBUTES = 0x180, 2062 NVME_SC_INVALID_PI = 0x181, 2063 NVME_SC_READ_ONLY = 0x182, 2064 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 2065 2066 /* 2067 * I/O Command Set Specific - Fabrics commands: 2068 */ 2069 NVME_SC_CONNECT_FORMAT = 0x180, 2070 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 2071 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 2072 NVME_SC_CONNECT_RESTART_DISC = 0x183, 2073 NVME_SC_CONNECT_INVALID_HOST = 0x184, 2074 2075 NVME_SC_DISCOVERY_RESTART = 0x190, 2076 NVME_SC_AUTH_REQUIRED = 0x191, 2077 2078 /* 2079 * I/O Command Set Specific - Zoned commands: 2080 */ 2081 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, 2082 NVME_SC_ZONE_FULL = 0x1b9, 2083 NVME_SC_ZONE_READ_ONLY = 0x1ba, 2084 NVME_SC_ZONE_OFFLINE = 0x1bb, 2085 NVME_SC_ZONE_INVALID_WRITE = 0x1bc, 2086 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, 2087 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, 2088 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, 2089 2090 /* 2091 * Media and Data Integrity Errors: 2092 */ 2093 NVME_SCT_MEDIA_ERROR = 0x200, 2094 NVME_SC_WRITE_FAULT = 0x280, 2095 NVME_SC_READ_ERROR = 0x281, 2096 NVME_SC_GUARD_CHECK = 0x282, 2097 NVME_SC_APPTAG_CHECK = 0x283, 2098 NVME_SC_REFTAG_CHECK = 0x284, 2099 NVME_SC_COMPARE_FAILED = 0x285, 2100 NVME_SC_ACCESS_DENIED = 0x286, 2101 NVME_SC_UNWRITTEN_BLOCK = 0x287, 2102 2103 /* 2104 * Path-related Errors: 2105 */ 2106 NVME_SCT_PATH = 0x300, 2107 NVME_SC_INTERNAL_PATH_ERROR = 0x300, 2108 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 2109 NVME_SC_ANA_INACCESSIBLE = 0x302, 2110 NVME_SC_ANA_TRANSITION = 0x303, 2111 NVME_SC_CTRL_PATH_ERROR = 0x360, 2112 NVME_SC_HOST_PATH_ERROR = 0x370, 2113 NVME_SC_HOST_ABORTED_CMD = 0x371, 2114 2115 NVME_SC_MASK = 0x00ff, /* Status Code */ 2116 NVME_SCT_MASK = 0x0700, /* Status Code Type */ 2117 NVME_SCT_SC_MASK = NVME_SCT_MASK | NVME_SC_MASK, 2118 2119 NVME_STATUS_CRD = 0x1800, /* Command Retry Delayed */ 2120 NVME_STATUS_MORE = 0x2000, 2121 NVME_STATUS_DNR = 0x4000, /* Do Not Retry */ 2122 }; 2123 2124 #define NVME_SCT(status) ((status) >> 8 & 7) 2125 2126 struct nvme_completion { 2127 /* 2128 * Used by Admin and Fabrics commands to return data: 2129 */ 2130 union nvme_result { 2131 __le16 u16; 2132 __le32 u32; 2133 __le64 u64; 2134 } result; 2135 __le16 sq_head; /* how much of this queue may be reclaimed */ 2136 __le16 sq_id; /* submission queue that generated this entry */ 2137 __u16 command_id; /* of the command which completed */ 2138 __le16 status; /* did the command fail, and if so, why? */ 2139 }; 2140 2141 #define NVME_VS(major, minor, tertiary) \ 2142 (((major) << 16) | ((minor) << 8) | (tertiary)) 2143 2144 #define NVME_MAJOR(ver) ((ver) >> 16) 2145 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 2146 #define NVME_TERTIARY(ver) ((ver) & 0xff) 2147 2148 enum { 2149 NVME_AEN_RESV_LOG_PAGE_AVALIABLE = 0x00, 2150 }; 2151 2152 enum { 2153 NVME_PR_LOG_EMPTY_LOG_PAGE = 0x00, 2154 NVME_PR_LOG_REGISTRATION_PREEMPTED = 0x01, 2155 NVME_PR_LOG_RESERVATION_RELEASED = 0x02, 2156 NVME_PR_LOG_RESERVATOIN_PREEMPTED = 0x03, 2157 }; 2158 2159 enum { 2160 NVME_PR_NOTIFY_BIT_REG_PREEMPTED = 1, 2161 NVME_PR_NOTIFY_BIT_RESV_RELEASED = 2, 2162 NVME_PR_NOTIFY_BIT_RESV_PREEMPTED = 3, 2163 }; 2164 2165 struct nvme_pr_log { 2166 __le64 count; 2167 __u8 type; 2168 __u8 nr_pages; 2169 __u8 rsvd1[2]; 2170 __le32 nsid; 2171 __u8 rsvd2[48]; 2172 }; 2173 2174 struct nvmet_pr_register_data { 2175 __le64 crkey; 2176 __le64 nrkey; 2177 }; 2178 2179 struct nvmet_pr_acquire_data { 2180 __le64 crkey; 2181 __le64 prkey; 2182 }; 2183 2184 struct nvmet_pr_release_data { 2185 __le64 crkey; 2186 }; 2187 2188 enum nvme_pr_capabilities { 2189 NVME_PR_SUPPORT_PTPL = 1, 2190 NVME_PR_SUPPORT_WRITE_EXCLUSIVE = 1 << 1, 2191 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS = 1 << 2, 2192 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY = 1 << 3, 2193 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY = 1 << 4, 2194 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS = 1 << 5, 2195 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS = 1 << 6, 2196 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF = 1 << 7, 2197 }; 2198 2199 enum nvme_pr_register_action { 2200 NVME_PR_REGISTER_ACT_REG = 0, 2201 NVME_PR_REGISTER_ACT_UNREG = 1, 2202 NVME_PR_REGISTER_ACT_REPLACE = 1 << 1, 2203 }; 2204 2205 enum nvme_pr_acquire_action { 2206 NVME_PR_ACQUIRE_ACT_ACQUIRE = 0, 2207 NVME_PR_ACQUIRE_ACT_PREEMPT = 1, 2208 NVME_PR_ACQUIRE_ACT_PREEMPT_AND_ABORT = 1 << 1, 2209 }; 2210 2211 enum nvme_pr_release_action { 2212 NVME_PR_RELEASE_ACT_RELEASE = 0, 2213 NVME_PR_RELEASE_ACT_CLEAR = 1, 2214 }; 2215 2216 enum nvme_pr_change_ptpl { 2217 NVME_PR_CPTPL_NO_CHANGE = 0, 2218 NVME_PR_CPTPL_RESV = 1 << 30, 2219 NVME_PR_CPTPL_CLEARED = 2 << 30, 2220 NVME_PR_CPTPL_PERSIST = 3 << 30, 2221 }; 2222 2223 #define NVME_PR_IGNORE_KEY (1 << 3) 2224 2225 #endif /* _LINUX_NVME_H */ 2226