1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/bits.h> 11 #include <linux/types.h> 12 #include <linux/uuid.h> 13 14 /* NQN names in commands fields specified one size */ 15 #define NVMF_NQN_FIELD_LEN 256 16 17 /* However the max length of a qualified name is another size */ 18 #define NVMF_NQN_SIZE 223 19 20 #define NVMF_TRSVCID_SIZE 32 21 #define NVMF_TRADDR_SIZE 256 22 #define NVMF_TSAS_SIZE 256 23 24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 25 26 #define NVME_RDMA_IP_PORT 4420 27 28 #define NVME_NSID_ALL 0xffffffff 29 30 enum nvme_subsys_type { 31 /* Referral to another discovery type target subsystem */ 32 NVME_NQN_DISC = 1, 33 34 /* NVME type target subsystem */ 35 NVME_NQN_NVME = 2, 36 37 /* Current discovery type target subsystem */ 38 NVME_NQN_CURR = 3, 39 }; 40 41 enum nvme_ctrl_type { 42 NVME_CTRL_IO = 1, /* I/O controller */ 43 NVME_CTRL_DISC = 2, /* Discovery controller */ 44 NVME_CTRL_ADMIN = 3, /* Administrative controller */ 45 }; 46 47 enum nvme_dctype { 48 NVME_DCTYPE_NOT_REPORTED = 0, 49 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */ 50 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */ 51 }; 52 53 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 54 enum { 55 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 56 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 57 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 58 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 59 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 60 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ 61 NVMF_ADDR_FAMILY_MAX, 62 }; 63 64 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 65 enum { 66 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 67 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 68 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 69 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 70 NVMF_TRTYPE_MAX, 71 }; 72 73 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 74 enum { 75 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 76 NVMF_TREQ_REQUIRED = 1, /* Required */ 77 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 78 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 79 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 80 81 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 82 }; 83 84 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 85 * RDMA_QPTYPE field 86 */ 87 enum { 88 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 89 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 90 }; 91 92 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 93 * RDMA_QPTYPE field 94 */ 95 enum { 96 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 97 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 98 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 99 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 100 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 101 }; 102 103 /* RDMA Connection Management Service Type codes for Discovery Log Page 104 * entry TSAS RDMA_CMS field 105 */ 106 enum { 107 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 108 }; 109 110 /* TSAS SECTYPE for TCP transport */ 111 enum { 112 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */ 113 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 114 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 115 }; 116 117 #define NVME_AQ_DEPTH 32 118 #define NVME_NR_AEN_COMMANDS 1 119 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 120 121 /* 122 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 123 * NVM-Express 1.2 specification, section 4.1.2. 124 */ 125 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 126 127 enum { 128 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 129 NVME_REG_VS = 0x0008, /* Version */ 130 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 131 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 132 NVME_REG_CC = 0x0014, /* Controller Configuration */ 133 NVME_REG_CSTS = 0x001c, /* Controller Status */ 134 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 135 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 136 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 137 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 138 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 139 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 140 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ 141 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ 142 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer 143 * Location 144 */ 145 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory 146 * Space Control 147 */ 148 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */ 149 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ 150 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ 151 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ 152 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity 153 * Buffer Size 154 */ 155 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained 156 * Write Throughput 157 */ 158 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 159 }; 160 161 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 162 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 163 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 164 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 165 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) 166 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 167 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 168 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) 169 170 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 171 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 172 173 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16) 174 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff) 175 176 enum { 177 NVME_CMBSZ_SQS = 1 << 0, 178 NVME_CMBSZ_CQS = 1 << 1, 179 NVME_CMBSZ_LISTS = 1 << 2, 180 NVME_CMBSZ_RDS = 1 << 3, 181 NVME_CMBSZ_WDS = 1 << 4, 182 183 NVME_CMBSZ_SZ_SHIFT = 12, 184 NVME_CMBSZ_SZ_MASK = 0xfffff, 185 186 NVME_CMBSZ_SZU_SHIFT = 8, 187 NVME_CMBSZ_SZU_MASK = 0xf, 188 }; 189 190 /* 191 * Submission and Completion Queue Entry Sizes for the NVM command set. 192 * (In bytes and specified as a power of two (2^n)). 193 */ 194 #define NVME_ADM_SQES 6 195 #define NVME_NVM_IOSQES 6 196 #define NVME_NVM_IOCQES 4 197 198 enum { 199 NVME_CC_ENABLE = 1 << 0, 200 NVME_CC_EN_SHIFT = 0, 201 NVME_CC_CSS_SHIFT = 4, 202 NVME_CC_MPS_SHIFT = 7, 203 NVME_CC_AMS_SHIFT = 11, 204 NVME_CC_SHN_SHIFT = 14, 205 NVME_CC_IOSQES_SHIFT = 16, 206 NVME_CC_IOCQES_SHIFT = 20, 207 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, 208 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, 209 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, 210 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 211 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 212 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 213 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 214 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 215 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 216 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 217 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 218 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 219 NVME_CC_CRIME = 1 << 24, 220 }; 221 222 enum { 223 NVME_CSTS_RDY = 1 << 0, 224 NVME_CSTS_CFS = 1 << 1, 225 NVME_CSTS_NSSRO = 1 << 4, 226 NVME_CSTS_PP = 1 << 5, 227 NVME_CSTS_SHST_NORMAL = 0 << 2, 228 NVME_CSTS_SHST_OCCUR = 1 << 2, 229 NVME_CSTS_SHST_CMPLT = 2 << 2, 230 NVME_CSTS_SHST_MASK = 3 << 2, 231 }; 232 233 enum { 234 NVME_CMBMSC_CRE = 1 << 0, 235 NVME_CMBMSC_CMSE = 1 << 1, 236 }; 237 238 enum { 239 NVME_CAP_CSS_NVM = 1 << 0, 240 NVME_CAP_CSS_CSI = 1 << 6, 241 }; 242 243 enum { 244 NVME_CAP_CRMS_CRWMS = 1ULL << 59, 245 NVME_CAP_CRMS_CRIMS = 1ULL << 60, 246 }; 247 248 struct nvme_id_power_state { 249 __le16 max_power; /* centiwatts */ 250 __u8 rsvd2; 251 __u8 flags; 252 __le32 entry_lat; /* microseconds */ 253 __le32 exit_lat; /* microseconds */ 254 __u8 read_tput; 255 __u8 read_lat; 256 __u8 write_tput; 257 __u8 write_lat; 258 __le16 idle_power; 259 __u8 idle_scale; 260 __u8 rsvd19; 261 __le16 active_power; 262 __u8 active_work_scale; 263 __u8 rsvd23[9]; 264 }; 265 266 enum { 267 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 268 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 269 }; 270 271 enum nvme_ctrl_attr { 272 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 273 NVME_CTRL_ATTR_TBKAS = (1 << 6), 274 NVME_CTRL_ATTR_ELBAS = (1 << 15), 275 }; 276 277 struct nvme_id_ctrl { 278 __le16 vid; 279 __le16 ssvid; 280 char sn[20]; 281 char mn[40]; 282 char fr[8]; 283 __u8 rab; 284 __u8 ieee[3]; 285 __u8 cmic; 286 __u8 mdts; 287 __le16 cntlid; 288 __le32 ver; 289 __le32 rtd3r; 290 __le32 rtd3e; 291 __le32 oaes; 292 __le32 ctratt; 293 __u8 rsvd100[11]; 294 __u8 cntrltype; 295 __u8 fguid[16]; 296 __le16 crdt1; 297 __le16 crdt2; 298 __le16 crdt3; 299 __u8 rsvd134[122]; 300 __le16 oacs; 301 __u8 acl; 302 __u8 aerl; 303 __u8 frmw; 304 __u8 lpa; 305 __u8 elpe; 306 __u8 npss; 307 __u8 avscc; 308 __u8 apsta; 309 __le16 wctemp; 310 __le16 cctemp; 311 __le16 mtfa; 312 __le32 hmpre; 313 __le32 hmmin; 314 __u8 tnvmcap[16]; 315 __u8 unvmcap[16]; 316 __le32 rpmbs; 317 __le16 edstt; 318 __u8 dsto; 319 __u8 fwug; 320 __le16 kas; 321 __le16 hctma; 322 __le16 mntmt; 323 __le16 mxtmt; 324 __le32 sanicap; 325 __le32 hmminds; 326 __le16 hmmaxd; 327 __u8 rsvd338[4]; 328 __u8 anatt; 329 __u8 anacap; 330 __le32 anagrpmax; 331 __le32 nanagrpid; 332 __u8 rsvd352[160]; 333 __u8 sqes; 334 __u8 cqes; 335 __le16 maxcmd; 336 __le32 nn; 337 __le16 oncs; 338 __le16 fuses; 339 __u8 fna; 340 __u8 vwc; 341 __le16 awun; 342 __le16 awupf; 343 __u8 nvscc; 344 __u8 nwpc; 345 __le16 acwu; 346 __u8 rsvd534[2]; 347 __le32 sgls; 348 __le32 mnan; 349 __u8 rsvd544[224]; 350 char subnqn[256]; 351 __u8 rsvd1024[768]; 352 __le32 ioccsz; 353 __le32 iorcsz; 354 __le16 icdoff; 355 __u8 ctrattr; 356 __u8 msdbd; 357 __u8 rsvd1804[2]; 358 __u8 dctype; 359 __u8 rsvd1807[241]; 360 struct nvme_id_power_state psd[32]; 361 __u8 vs[1024]; 362 }; 363 364 enum { 365 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, 366 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, 367 NVME_CTRL_CMIC_ANA = 1 << 3, 368 NVME_CTRL_ONCS_COMPARE = 1 << 0, 369 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 370 NVME_CTRL_ONCS_DSM = 1 << 2, 371 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 372 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, 373 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 374 NVME_CTRL_VWC_PRESENT = 1 << 0, 375 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 376 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, 377 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 378 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 379 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 380 NVME_CTRL_CTRATT_128_ID = 1 << 0, 381 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, 382 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, 383 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, 384 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, 385 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, 386 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, 387 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, 388 }; 389 390 struct nvme_lbaf { 391 __le16 ms; 392 __u8 ds; 393 __u8 rp; 394 }; 395 396 struct nvme_id_ns { 397 __le64 nsze; 398 __le64 ncap; 399 __le64 nuse; 400 __u8 nsfeat; 401 __u8 nlbaf; 402 __u8 flbas; 403 __u8 mc; 404 __u8 dpc; 405 __u8 dps; 406 __u8 nmic; 407 __u8 rescap; 408 __u8 fpi; 409 __u8 dlfeat; 410 __le16 nawun; 411 __le16 nawupf; 412 __le16 nacwu; 413 __le16 nabsn; 414 __le16 nabo; 415 __le16 nabspf; 416 __le16 noiob; 417 __u8 nvmcap[16]; 418 __le16 npwg; 419 __le16 npwa; 420 __le16 npdg; 421 __le16 npda; 422 __le16 nows; 423 __u8 rsvd74[18]; 424 __le32 anagrpid; 425 __u8 rsvd96[3]; 426 __u8 nsattr; 427 __le16 nvmsetid; 428 __le16 endgid; 429 __u8 nguid[16]; 430 __u8 eui64[8]; 431 struct nvme_lbaf lbaf[64]; 432 __u8 vs[3712]; 433 }; 434 435 /* I/O Command Set Independent Identify Namespace Data Structure */ 436 struct nvme_id_ns_cs_indep { 437 __u8 nsfeat; 438 __u8 nmic; 439 __u8 rescap; 440 __u8 fpi; 441 __le32 anagrpid; 442 __u8 nsattr; 443 __u8 rsvd9; 444 __le16 nvmsetid; 445 __le16 endgid; 446 __u8 nstat; 447 __u8 rsvd15[4081]; 448 }; 449 450 struct nvme_zns_lbafe { 451 __le64 zsze; 452 __u8 zdes; 453 __u8 rsvd9[7]; 454 }; 455 456 struct nvme_id_ns_zns { 457 __le16 zoc; 458 __le16 ozcs; 459 __le32 mar; 460 __le32 mor; 461 __le32 rrl; 462 __le32 frl; 463 __u8 rsvd20[2796]; 464 struct nvme_zns_lbafe lbafe[64]; 465 __u8 vs[256]; 466 }; 467 468 struct nvme_id_ctrl_zns { 469 __u8 zasl; 470 __u8 rsvd1[4095]; 471 }; 472 473 struct nvme_id_ns_nvm { 474 __le64 lbstm; 475 __u8 pic; 476 __u8 rsvd9[3]; 477 __le32 elbaf[64]; 478 __u8 rsvd268[3828]; 479 }; 480 481 enum { 482 NVME_ID_NS_NVM_STS_MASK = 0x7f, 483 NVME_ID_NS_NVM_GUARD_SHIFT = 7, 484 NVME_ID_NS_NVM_GUARD_MASK = 0x3, 485 }; 486 487 static inline __u8 nvme_elbaf_sts(__u32 elbaf) 488 { 489 return elbaf & NVME_ID_NS_NVM_STS_MASK; 490 } 491 492 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf) 493 { 494 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK; 495 } 496 497 struct nvme_id_ctrl_nvm { 498 __u8 vsl; 499 __u8 wzsl; 500 __u8 wusl; 501 __u8 dmrl; 502 __le32 dmrsl; 503 __le64 dmsl; 504 __u8 rsvd16[4080]; 505 }; 506 507 enum { 508 NVME_ID_CNS_NS = 0x00, 509 NVME_ID_CNS_CTRL = 0x01, 510 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 511 NVME_ID_CNS_NS_DESC_LIST = 0x03, 512 NVME_ID_CNS_CS_NS = 0x05, 513 NVME_ID_CNS_CS_CTRL = 0x06, 514 NVME_ID_CNS_NS_CS_INDEP = 0x08, 515 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 516 NVME_ID_CNS_NS_PRESENT = 0x11, 517 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 518 NVME_ID_CNS_CTRL_LIST = 0x13, 519 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, 520 NVME_ID_CNS_NS_GRANULARITY = 0x16, 521 NVME_ID_CNS_UUID_LIST = 0x17, 522 }; 523 524 enum { 525 NVME_CSI_NVM = 0, 526 NVME_CSI_ZNS = 2, 527 }; 528 529 enum { 530 NVME_DIR_IDENTIFY = 0x00, 531 NVME_DIR_STREAMS = 0x01, 532 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 533 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 534 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 535 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 536 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 537 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 538 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 539 NVME_DIR_ENDIR = 0x01, 540 }; 541 542 enum { 543 NVME_NS_FEAT_THIN = 1 << 0, 544 NVME_NS_FEAT_ATOMICS = 1 << 1, 545 NVME_NS_FEAT_IO_OPT = 1 << 4, 546 NVME_NS_ATTR_RO = 1 << 0, 547 NVME_NS_FLBAS_LBA_MASK = 0xf, 548 NVME_NS_FLBAS_LBA_UMASK = 0x60, 549 NVME_NS_FLBAS_LBA_SHIFT = 1, 550 NVME_NS_FLBAS_META_EXT = 0x10, 551 NVME_NS_NMIC_SHARED = 1 << 0, 552 NVME_LBAF_RP_BEST = 0, 553 NVME_LBAF_RP_BETTER = 1, 554 NVME_LBAF_RP_GOOD = 2, 555 NVME_LBAF_RP_DEGRADED = 3, 556 NVME_NS_DPC_PI_LAST = 1 << 4, 557 NVME_NS_DPC_PI_FIRST = 1 << 3, 558 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 559 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 560 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 561 NVME_NS_DPS_PI_FIRST = 1 << 3, 562 NVME_NS_DPS_PI_MASK = 0x7, 563 NVME_NS_DPS_PI_TYPE1 = 1, 564 NVME_NS_DPS_PI_TYPE2 = 2, 565 NVME_NS_DPS_PI_TYPE3 = 3, 566 }; 567 568 enum { 569 NVME_NSTAT_NRDY = 1 << 0, 570 }; 571 572 enum { 573 NVME_NVM_NS_16B_GUARD = 0, 574 NVME_NVM_NS_32B_GUARD = 1, 575 NVME_NVM_NS_64B_GUARD = 2, 576 }; 577 578 static inline __u8 nvme_lbaf_index(__u8 flbas) 579 { 580 return (flbas & NVME_NS_FLBAS_LBA_MASK) | 581 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT); 582 } 583 584 /* Identify Namespace Metadata Capabilities (MC): */ 585 enum { 586 NVME_MC_EXTENDED_LBA = (1 << 0), 587 NVME_MC_METADATA_PTR = (1 << 1), 588 }; 589 590 struct nvme_ns_id_desc { 591 __u8 nidt; 592 __u8 nidl; 593 __le16 reserved; 594 }; 595 596 #define NVME_NIDT_EUI64_LEN 8 597 #define NVME_NIDT_NGUID_LEN 16 598 #define NVME_NIDT_UUID_LEN 16 599 #define NVME_NIDT_CSI_LEN 1 600 601 enum { 602 NVME_NIDT_EUI64 = 0x01, 603 NVME_NIDT_NGUID = 0x02, 604 NVME_NIDT_UUID = 0x03, 605 NVME_NIDT_CSI = 0x04, 606 }; 607 608 struct nvme_smart_log { 609 __u8 critical_warning; 610 __u8 temperature[2]; 611 __u8 avail_spare; 612 __u8 spare_thresh; 613 __u8 percent_used; 614 __u8 endu_grp_crit_warn_sumry; 615 __u8 rsvd7[25]; 616 __u8 data_units_read[16]; 617 __u8 data_units_written[16]; 618 __u8 host_reads[16]; 619 __u8 host_writes[16]; 620 __u8 ctrl_busy_time[16]; 621 __u8 power_cycles[16]; 622 __u8 power_on_hours[16]; 623 __u8 unsafe_shutdowns[16]; 624 __u8 media_errors[16]; 625 __u8 num_err_log_entries[16]; 626 __le32 warning_temp_time; 627 __le32 critical_comp_time; 628 __le16 temp_sensor[8]; 629 __le32 thm_temp1_trans_count; 630 __le32 thm_temp2_trans_count; 631 __le32 thm_temp1_total_time; 632 __le32 thm_temp2_total_time; 633 __u8 rsvd232[280]; 634 }; 635 636 struct nvme_fw_slot_info_log { 637 __u8 afi; 638 __u8 rsvd1[7]; 639 __le64 frs[7]; 640 __u8 rsvd64[448]; 641 }; 642 643 enum { 644 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 645 NVME_CMD_EFFECTS_LBCC = 1 << 1, 646 NVME_CMD_EFFECTS_NCC = 1 << 2, 647 NVME_CMD_EFFECTS_NIC = 1 << 3, 648 NVME_CMD_EFFECTS_CCC = 1 << 4, 649 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), 650 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, 651 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20), 652 }; 653 654 struct nvme_effects_log { 655 __le32 acs[256]; 656 __le32 iocs[256]; 657 __u8 resv[2048]; 658 }; 659 660 enum nvme_ana_state { 661 NVME_ANA_OPTIMIZED = 0x01, 662 NVME_ANA_NONOPTIMIZED = 0x02, 663 NVME_ANA_INACCESSIBLE = 0x03, 664 NVME_ANA_PERSISTENT_LOSS = 0x04, 665 NVME_ANA_CHANGE = 0x0f, 666 }; 667 668 struct nvme_ana_group_desc { 669 __le32 grpid; 670 __le32 nnsids; 671 __le64 chgcnt; 672 __u8 state; 673 __u8 rsvd17[15]; 674 __le32 nsids[]; 675 }; 676 677 /* flag for the log specific field of the ANA log */ 678 #define NVME_ANA_LOG_RGO (1 << 0) 679 680 struct nvme_ana_rsp_hdr { 681 __le64 chgcnt; 682 __le16 ngrps; 683 __le16 rsvd10[3]; 684 }; 685 686 struct nvme_zone_descriptor { 687 __u8 zt; 688 __u8 zs; 689 __u8 za; 690 __u8 rsvd3[5]; 691 __le64 zcap; 692 __le64 zslba; 693 __le64 wp; 694 __u8 rsvd32[32]; 695 }; 696 697 enum { 698 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, 699 }; 700 701 struct nvme_zone_report { 702 __le64 nr_zones; 703 __u8 resv8[56]; 704 struct nvme_zone_descriptor entries[]; 705 }; 706 707 enum { 708 NVME_SMART_CRIT_SPARE = 1 << 0, 709 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 710 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 711 NVME_SMART_CRIT_MEDIA = 1 << 3, 712 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 713 }; 714 715 enum { 716 NVME_AER_ERROR = 0, 717 NVME_AER_SMART = 1, 718 NVME_AER_NOTICE = 2, 719 NVME_AER_CSS = 6, 720 NVME_AER_VS = 7, 721 }; 722 723 enum { 724 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03, 725 }; 726 727 enum { 728 NVME_AER_NOTICE_NS_CHANGED = 0x00, 729 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 730 NVME_AER_NOTICE_ANA = 0x03, 731 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 732 }; 733 734 enum { 735 NVME_AEN_BIT_NS_ATTR = 8, 736 NVME_AEN_BIT_FW_ACT = 9, 737 NVME_AEN_BIT_ANA_CHANGE = 11, 738 NVME_AEN_BIT_DISC_CHANGE = 31, 739 }; 740 741 enum { 742 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 743 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 744 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 745 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 746 }; 747 748 struct nvme_lba_range_type { 749 __u8 type; 750 __u8 attributes; 751 __u8 rsvd2[14]; 752 __le64 slba; 753 __le64 nlb; 754 __u8 guid[16]; 755 __u8 rsvd48[16]; 756 }; 757 758 enum { 759 NVME_LBART_TYPE_FS = 0x01, 760 NVME_LBART_TYPE_RAID = 0x02, 761 NVME_LBART_TYPE_CACHE = 0x03, 762 NVME_LBART_TYPE_SWAP = 0x04, 763 764 NVME_LBART_ATTRIB_TEMP = 1 << 0, 765 NVME_LBART_ATTRIB_HIDE = 1 << 1, 766 }; 767 768 enum nvme_pr_type { 769 NVME_PR_WRITE_EXCLUSIVE = 1, 770 NVME_PR_EXCLUSIVE_ACCESS = 2, 771 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3, 772 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4, 773 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5, 774 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6, 775 }; 776 777 enum nvme_eds { 778 NVME_EXTENDED_DATA_STRUCT = 0x1, 779 }; 780 781 struct nvme_registered_ctrl { 782 __le16 cntlid; 783 __u8 rcsts; 784 __u8 rsvd3[5]; 785 __le64 hostid; 786 __le64 rkey; 787 }; 788 789 struct nvme_reservation_status { 790 __le32 gen; 791 __u8 rtype; 792 __u8 regctl[2]; 793 __u8 resv5[2]; 794 __u8 ptpls; 795 __u8 resv10[14]; 796 struct nvme_registered_ctrl regctl_ds[]; 797 }; 798 799 struct nvme_registered_ctrl_ext { 800 __le16 cntlid; 801 __u8 rcsts; 802 __u8 rsvd3[5]; 803 __le64 rkey; 804 __u8 hostid[16]; 805 __u8 rsvd32[32]; 806 }; 807 808 struct nvme_reservation_status_ext { 809 __le32 gen; 810 __u8 rtype; 811 __u8 regctl[2]; 812 __u8 resv5[2]; 813 __u8 ptpls; 814 __u8 resv10[14]; 815 __u8 rsvd24[40]; 816 struct nvme_registered_ctrl_ext regctl_eds[]; 817 }; 818 819 enum nvme_async_event_type { 820 NVME_AER_TYPE_ERROR = 0, 821 NVME_AER_TYPE_SMART = 1, 822 NVME_AER_TYPE_NOTICE = 2, 823 }; 824 825 /* I/O commands */ 826 827 enum nvme_opcode { 828 nvme_cmd_flush = 0x00, 829 nvme_cmd_write = 0x01, 830 nvme_cmd_read = 0x02, 831 nvme_cmd_write_uncor = 0x04, 832 nvme_cmd_compare = 0x05, 833 nvme_cmd_write_zeroes = 0x08, 834 nvme_cmd_dsm = 0x09, 835 nvme_cmd_verify = 0x0c, 836 nvme_cmd_resv_register = 0x0d, 837 nvme_cmd_resv_report = 0x0e, 838 nvme_cmd_resv_acquire = 0x11, 839 nvme_cmd_resv_release = 0x15, 840 nvme_cmd_zone_mgmt_send = 0x79, 841 nvme_cmd_zone_mgmt_recv = 0x7a, 842 nvme_cmd_zone_append = 0x7d, 843 nvme_cmd_vendor_start = 0x80, 844 }; 845 846 #define nvme_opcode_name(opcode) { opcode, #opcode } 847 #define show_nvm_opcode_name(val) \ 848 __print_symbolic(val, \ 849 nvme_opcode_name(nvme_cmd_flush), \ 850 nvme_opcode_name(nvme_cmd_write), \ 851 nvme_opcode_name(nvme_cmd_read), \ 852 nvme_opcode_name(nvme_cmd_write_uncor), \ 853 nvme_opcode_name(nvme_cmd_compare), \ 854 nvme_opcode_name(nvme_cmd_write_zeroes), \ 855 nvme_opcode_name(nvme_cmd_dsm), \ 856 nvme_opcode_name(nvme_cmd_verify), \ 857 nvme_opcode_name(nvme_cmd_resv_register), \ 858 nvme_opcode_name(nvme_cmd_resv_report), \ 859 nvme_opcode_name(nvme_cmd_resv_acquire), \ 860 nvme_opcode_name(nvme_cmd_resv_release), \ 861 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ 862 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ 863 nvme_opcode_name(nvme_cmd_zone_append)) 864 865 866 867 /* 868 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 869 * 870 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 871 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 872 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 873 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 874 * request subtype 875 */ 876 enum { 877 NVME_SGL_FMT_ADDRESS = 0x00, 878 NVME_SGL_FMT_OFFSET = 0x01, 879 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 880 NVME_SGL_FMT_INVALIDATE = 0x0f, 881 }; 882 883 /* 884 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 885 * 886 * For struct nvme_sgl_desc: 887 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 888 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 889 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 890 * 891 * For struct nvme_keyed_sgl_desc: 892 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 893 * 894 * Transport-specific SGL types: 895 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 896 */ 897 enum { 898 NVME_SGL_FMT_DATA_DESC = 0x00, 899 NVME_SGL_FMT_SEG_DESC = 0x02, 900 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 901 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 902 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 903 }; 904 905 struct nvme_sgl_desc { 906 __le64 addr; 907 __le32 length; 908 __u8 rsvd[3]; 909 __u8 type; 910 }; 911 912 struct nvme_keyed_sgl_desc { 913 __le64 addr; 914 __u8 length[3]; 915 __u8 key[4]; 916 __u8 type; 917 }; 918 919 union nvme_data_ptr { 920 struct { 921 __le64 prp1; 922 __le64 prp2; 923 }; 924 struct nvme_sgl_desc sgl; 925 struct nvme_keyed_sgl_desc ksgl; 926 }; 927 928 /* 929 * Lowest two bits of our flags field (FUSE field in the spec): 930 * 931 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 932 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 933 * 934 * Highest two bits in our flags field (PSDT field in the spec): 935 * 936 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 937 * If used, MPTR contains addr of single physical buffer (byte aligned). 938 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 939 * If used, MPTR contains an address of an SGL segment containing 940 * exactly 1 SGL descriptor (qword aligned). 941 */ 942 enum { 943 NVME_CMD_FUSE_FIRST = (1 << 0), 944 NVME_CMD_FUSE_SECOND = (1 << 1), 945 946 NVME_CMD_SGL_METABUF = (1 << 6), 947 NVME_CMD_SGL_METASEG = (1 << 7), 948 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 949 }; 950 951 struct nvme_common_command { 952 __u8 opcode; 953 __u8 flags; 954 __u16 command_id; 955 __le32 nsid; 956 __le32 cdw2[2]; 957 __le64 metadata; 958 union nvme_data_ptr dptr; 959 struct_group(cdws, 960 __le32 cdw10; 961 __le32 cdw11; 962 __le32 cdw12; 963 __le32 cdw13; 964 __le32 cdw14; 965 __le32 cdw15; 966 ); 967 }; 968 969 struct nvme_rw_command { 970 __u8 opcode; 971 __u8 flags; 972 __u16 command_id; 973 __le32 nsid; 974 __le32 cdw2; 975 __le32 cdw3; 976 __le64 metadata; 977 union nvme_data_ptr dptr; 978 __le64 slba; 979 __le16 length; 980 __le16 control; 981 __le32 dsmgmt; 982 __le32 reftag; 983 __le16 apptag; 984 __le16 appmask; 985 }; 986 987 enum { 988 NVME_RW_LR = 1 << 15, 989 NVME_RW_FUA = 1 << 14, 990 NVME_RW_APPEND_PIREMAP = 1 << 9, 991 NVME_RW_DSM_FREQ_UNSPEC = 0, 992 NVME_RW_DSM_FREQ_TYPICAL = 1, 993 NVME_RW_DSM_FREQ_RARE = 2, 994 NVME_RW_DSM_FREQ_READS = 3, 995 NVME_RW_DSM_FREQ_WRITES = 4, 996 NVME_RW_DSM_FREQ_RW = 5, 997 NVME_RW_DSM_FREQ_ONCE = 6, 998 NVME_RW_DSM_FREQ_PREFETCH = 7, 999 NVME_RW_DSM_FREQ_TEMP = 8, 1000 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 1001 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 1002 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 1003 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 1004 NVME_RW_DSM_SEQ_REQ = 1 << 6, 1005 NVME_RW_DSM_COMPRESSED = 1 << 7, 1006 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 1007 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 1008 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 1009 NVME_RW_PRINFO_PRACT = 1 << 13, 1010 NVME_RW_DTYPE_STREAMS = 1 << 4, 1011 NVME_WZ_DEAC = 1 << 9, 1012 }; 1013 1014 struct nvme_dsm_cmd { 1015 __u8 opcode; 1016 __u8 flags; 1017 __u16 command_id; 1018 __le32 nsid; 1019 __u64 rsvd2[2]; 1020 union nvme_data_ptr dptr; 1021 __le32 nr; 1022 __le32 attributes; 1023 __u32 rsvd12[4]; 1024 }; 1025 1026 enum { 1027 NVME_DSMGMT_IDR = 1 << 0, 1028 NVME_DSMGMT_IDW = 1 << 1, 1029 NVME_DSMGMT_AD = 1 << 2, 1030 }; 1031 1032 #define NVME_DSM_MAX_RANGES 256 1033 1034 struct nvme_dsm_range { 1035 __le32 cattr; 1036 __le32 nlb; 1037 __le64 slba; 1038 }; 1039 1040 struct nvme_write_zeroes_cmd { 1041 __u8 opcode; 1042 __u8 flags; 1043 __u16 command_id; 1044 __le32 nsid; 1045 __u64 rsvd2; 1046 __le64 metadata; 1047 union nvme_data_ptr dptr; 1048 __le64 slba; 1049 __le16 length; 1050 __le16 control; 1051 __le32 dsmgmt; 1052 __le32 reftag; 1053 __le16 apptag; 1054 __le16 appmask; 1055 }; 1056 1057 enum nvme_zone_mgmt_action { 1058 NVME_ZONE_CLOSE = 0x1, 1059 NVME_ZONE_FINISH = 0x2, 1060 NVME_ZONE_OPEN = 0x3, 1061 NVME_ZONE_RESET = 0x4, 1062 NVME_ZONE_OFFLINE = 0x5, 1063 NVME_ZONE_SET_DESC_EXT = 0x10, 1064 }; 1065 1066 struct nvme_zone_mgmt_send_cmd { 1067 __u8 opcode; 1068 __u8 flags; 1069 __u16 command_id; 1070 __le32 nsid; 1071 __le32 cdw2[2]; 1072 __le64 metadata; 1073 union nvme_data_ptr dptr; 1074 __le64 slba; 1075 __le32 cdw12; 1076 __u8 zsa; 1077 __u8 select_all; 1078 __u8 rsvd13[2]; 1079 __le32 cdw14[2]; 1080 }; 1081 1082 struct nvme_zone_mgmt_recv_cmd { 1083 __u8 opcode; 1084 __u8 flags; 1085 __u16 command_id; 1086 __le32 nsid; 1087 __le64 rsvd2[2]; 1088 union nvme_data_ptr dptr; 1089 __le64 slba; 1090 __le32 numd; 1091 __u8 zra; 1092 __u8 zrasf; 1093 __u8 pr; 1094 __u8 rsvd13; 1095 __le32 cdw14[2]; 1096 }; 1097 1098 enum { 1099 NVME_ZRA_ZONE_REPORT = 0, 1100 NVME_ZRASF_ZONE_REPORT_ALL = 0, 1101 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, 1102 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, 1103 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, 1104 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, 1105 NVME_ZRASF_ZONE_STATE_READONLY = 0x05, 1106 NVME_ZRASF_ZONE_STATE_FULL = 0x06, 1107 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, 1108 NVME_REPORT_ZONE_PARTIAL = 1, 1109 }; 1110 1111 /* Features */ 1112 1113 enum { 1114 NVME_TEMP_THRESH_MASK = 0xffff, 1115 NVME_TEMP_THRESH_SELECT_SHIFT = 16, 1116 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, 1117 }; 1118 1119 struct nvme_feat_auto_pst { 1120 __le64 entries[32]; 1121 }; 1122 1123 enum { 1124 NVME_HOST_MEM_ENABLE = (1 << 0), 1125 NVME_HOST_MEM_RETURN = (1 << 1), 1126 }; 1127 1128 struct nvme_feat_host_behavior { 1129 __u8 acre; 1130 __u8 etdas; 1131 __u8 lbafee; 1132 __u8 resv1[509]; 1133 }; 1134 1135 enum { 1136 NVME_ENABLE_ACRE = 1, 1137 NVME_ENABLE_LBAFEE = 1, 1138 }; 1139 1140 /* Admin commands */ 1141 1142 enum nvme_admin_opcode { 1143 nvme_admin_delete_sq = 0x00, 1144 nvme_admin_create_sq = 0x01, 1145 nvme_admin_get_log_page = 0x02, 1146 nvme_admin_delete_cq = 0x04, 1147 nvme_admin_create_cq = 0x05, 1148 nvme_admin_identify = 0x06, 1149 nvme_admin_abort_cmd = 0x08, 1150 nvme_admin_set_features = 0x09, 1151 nvme_admin_get_features = 0x0a, 1152 nvme_admin_async_event = 0x0c, 1153 nvme_admin_ns_mgmt = 0x0d, 1154 nvme_admin_activate_fw = 0x10, 1155 nvme_admin_download_fw = 0x11, 1156 nvme_admin_dev_self_test = 0x14, 1157 nvme_admin_ns_attach = 0x15, 1158 nvme_admin_keep_alive = 0x18, 1159 nvme_admin_directive_send = 0x19, 1160 nvme_admin_directive_recv = 0x1a, 1161 nvme_admin_virtual_mgmt = 0x1c, 1162 nvme_admin_nvme_mi_send = 0x1d, 1163 nvme_admin_nvme_mi_recv = 0x1e, 1164 nvme_admin_dbbuf = 0x7C, 1165 nvme_admin_format_nvm = 0x80, 1166 nvme_admin_security_send = 0x81, 1167 nvme_admin_security_recv = 0x82, 1168 nvme_admin_sanitize_nvm = 0x84, 1169 nvme_admin_get_lba_status = 0x86, 1170 nvme_admin_vendor_start = 0xC0, 1171 }; 1172 1173 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 1174 #define show_admin_opcode_name(val) \ 1175 __print_symbolic(val, \ 1176 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 1177 nvme_admin_opcode_name(nvme_admin_create_sq), \ 1178 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 1179 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 1180 nvme_admin_opcode_name(nvme_admin_create_cq), \ 1181 nvme_admin_opcode_name(nvme_admin_identify), \ 1182 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 1183 nvme_admin_opcode_name(nvme_admin_set_features), \ 1184 nvme_admin_opcode_name(nvme_admin_get_features), \ 1185 nvme_admin_opcode_name(nvme_admin_async_event), \ 1186 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 1187 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 1188 nvme_admin_opcode_name(nvme_admin_download_fw), \ 1189 nvme_admin_opcode_name(nvme_admin_dev_self_test), \ 1190 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 1191 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 1192 nvme_admin_opcode_name(nvme_admin_directive_send), \ 1193 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 1194 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \ 1195 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \ 1196 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \ 1197 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 1198 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 1199 nvme_admin_opcode_name(nvme_admin_security_send), \ 1200 nvme_admin_opcode_name(nvme_admin_security_recv), \ 1201 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 1202 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 1203 1204 enum { 1205 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 1206 NVME_CQ_IRQ_ENABLED = (1 << 1), 1207 NVME_SQ_PRIO_URGENT = (0 << 1), 1208 NVME_SQ_PRIO_HIGH = (1 << 1), 1209 NVME_SQ_PRIO_MEDIUM = (2 << 1), 1210 NVME_SQ_PRIO_LOW = (3 << 1), 1211 NVME_FEAT_ARBITRATION = 0x01, 1212 NVME_FEAT_POWER_MGMT = 0x02, 1213 NVME_FEAT_LBA_RANGE = 0x03, 1214 NVME_FEAT_TEMP_THRESH = 0x04, 1215 NVME_FEAT_ERR_RECOVERY = 0x05, 1216 NVME_FEAT_VOLATILE_WC = 0x06, 1217 NVME_FEAT_NUM_QUEUES = 0x07, 1218 NVME_FEAT_IRQ_COALESCE = 0x08, 1219 NVME_FEAT_IRQ_CONFIG = 0x09, 1220 NVME_FEAT_WRITE_ATOMIC = 0x0a, 1221 NVME_FEAT_ASYNC_EVENT = 0x0b, 1222 NVME_FEAT_AUTO_PST = 0x0c, 1223 NVME_FEAT_HOST_MEM_BUF = 0x0d, 1224 NVME_FEAT_TIMESTAMP = 0x0e, 1225 NVME_FEAT_KATO = 0x0f, 1226 NVME_FEAT_HCTM = 0x10, 1227 NVME_FEAT_NOPSC = 0x11, 1228 NVME_FEAT_RRL = 0x12, 1229 NVME_FEAT_PLM_CONFIG = 0x13, 1230 NVME_FEAT_PLM_WINDOW = 0x14, 1231 NVME_FEAT_HOST_BEHAVIOR = 0x16, 1232 NVME_FEAT_SANITIZE = 0x17, 1233 NVME_FEAT_SW_PROGRESS = 0x80, 1234 NVME_FEAT_HOST_ID = 0x81, 1235 NVME_FEAT_RESV_MASK = 0x82, 1236 NVME_FEAT_RESV_PERSIST = 0x83, 1237 NVME_FEAT_WRITE_PROTECT = 0x84, 1238 NVME_FEAT_VENDOR_START = 0xC0, 1239 NVME_FEAT_VENDOR_END = 0xFF, 1240 NVME_LOG_ERROR = 0x01, 1241 NVME_LOG_SMART = 0x02, 1242 NVME_LOG_FW_SLOT = 0x03, 1243 NVME_LOG_CHANGED_NS = 0x04, 1244 NVME_LOG_CMD_EFFECTS = 0x05, 1245 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1246 NVME_LOG_TELEMETRY_HOST = 0x07, 1247 NVME_LOG_TELEMETRY_CTRL = 0x08, 1248 NVME_LOG_ENDURANCE_GROUP = 0x09, 1249 NVME_LOG_ANA = 0x0c, 1250 NVME_LOG_DISC = 0x70, 1251 NVME_LOG_RESERVATION = 0x80, 1252 NVME_FWACT_REPL = (0 << 3), 1253 NVME_FWACT_REPL_ACTV = (1 << 3), 1254 NVME_FWACT_ACTV = (2 << 3), 1255 }; 1256 1257 /* NVMe Namespace Write Protect State */ 1258 enum { 1259 NVME_NS_NO_WRITE_PROTECT = 0, 1260 NVME_NS_WRITE_PROTECT, 1261 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 1262 NVME_NS_WRITE_PROTECT_PERMANENT, 1263 }; 1264 1265 #define NVME_MAX_CHANGED_NAMESPACES 1024 1266 1267 struct nvme_identify { 1268 __u8 opcode; 1269 __u8 flags; 1270 __u16 command_id; 1271 __le32 nsid; 1272 __u64 rsvd2[2]; 1273 union nvme_data_ptr dptr; 1274 __u8 cns; 1275 __u8 rsvd3; 1276 __le16 ctrlid; 1277 __u8 rsvd11[3]; 1278 __u8 csi; 1279 __u32 rsvd12[4]; 1280 }; 1281 1282 #define NVME_IDENTIFY_DATA_SIZE 4096 1283 1284 struct nvme_features { 1285 __u8 opcode; 1286 __u8 flags; 1287 __u16 command_id; 1288 __le32 nsid; 1289 __u64 rsvd2[2]; 1290 union nvme_data_ptr dptr; 1291 __le32 fid; 1292 __le32 dword11; 1293 __le32 dword12; 1294 __le32 dword13; 1295 __le32 dword14; 1296 __le32 dword15; 1297 }; 1298 1299 struct nvme_host_mem_buf_desc { 1300 __le64 addr; 1301 __le32 size; 1302 __u32 rsvd; 1303 }; 1304 1305 struct nvme_create_cq { 1306 __u8 opcode; 1307 __u8 flags; 1308 __u16 command_id; 1309 __u32 rsvd1[5]; 1310 __le64 prp1; 1311 __u64 rsvd8; 1312 __le16 cqid; 1313 __le16 qsize; 1314 __le16 cq_flags; 1315 __le16 irq_vector; 1316 __u32 rsvd12[4]; 1317 }; 1318 1319 struct nvme_create_sq { 1320 __u8 opcode; 1321 __u8 flags; 1322 __u16 command_id; 1323 __u32 rsvd1[5]; 1324 __le64 prp1; 1325 __u64 rsvd8; 1326 __le16 sqid; 1327 __le16 qsize; 1328 __le16 sq_flags; 1329 __le16 cqid; 1330 __u32 rsvd12[4]; 1331 }; 1332 1333 struct nvme_delete_queue { 1334 __u8 opcode; 1335 __u8 flags; 1336 __u16 command_id; 1337 __u32 rsvd1[9]; 1338 __le16 qid; 1339 __u16 rsvd10; 1340 __u32 rsvd11[5]; 1341 }; 1342 1343 struct nvme_abort_cmd { 1344 __u8 opcode; 1345 __u8 flags; 1346 __u16 command_id; 1347 __u32 rsvd1[9]; 1348 __le16 sqid; 1349 __u16 cid; 1350 __u32 rsvd11[5]; 1351 }; 1352 1353 struct nvme_download_firmware { 1354 __u8 opcode; 1355 __u8 flags; 1356 __u16 command_id; 1357 __u32 rsvd1[5]; 1358 union nvme_data_ptr dptr; 1359 __le32 numd; 1360 __le32 offset; 1361 __u32 rsvd12[4]; 1362 }; 1363 1364 struct nvme_format_cmd { 1365 __u8 opcode; 1366 __u8 flags; 1367 __u16 command_id; 1368 __le32 nsid; 1369 __u64 rsvd2[4]; 1370 __le32 cdw10; 1371 __u32 rsvd11[5]; 1372 }; 1373 1374 struct nvme_get_log_page_command { 1375 __u8 opcode; 1376 __u8 flags; 1377 __u16 command_id; 1378 __le32 nsid; 1379 __u64 rsvd2[2]; 1380 union nvme_data_ptr dptr; 1381 __u8 lid; 1382 __u8 lsp; /* upper 4 bits reserved */ 1383 __le16 numdl; 1384 __le16 numdu; 1385 __u16 rsvd11; 1386 union { 1387 struct { 1388 __le32 lpol; 1389 __le32 lpou; 1390 }; 1391 __le64 lpo; 1392 }; 1393 __u8 rsvd14[3]; 1394 __u8 csi; 1395 __u32 rsvd15; 1396 }; 1397 1398 struct nvme_directive_cmd { 1399 __u8 opcode; 1400 __u8 flags; 1401 __u16 command_id; 1402 __le32 nsid; 1403 __u64 rsvd2[2]; 1404 union nvme_data_ptr dptr; 1405 __le32 numd; 1406 __u8 doper; 1407 __u8 dtype; 1408 __le16 dspec; 1409 __u8 endir; 1410 __u8 tdtype; 1411 __u16 rsvd15; 1412 1413 __u32 rsvd16[3]; 1414 }; 1415 1416 /* 1417 * Fabrics subcommands. 1418 */ 1419 enum nvmf_fabrics_opcode { 1420 nvme_fabrics_command = 0x7f, 1421 }; 1422 1423 enum nvmf_capsule_command { 1424 nvme_fabrics_type_property_set = 0x00, 1425 nvme_fabrics_type_connect = 0x01, 1426 nvme_fabrics_type_property_get = 0x04, 1427 nvme_fabrics_type_auth_send = 0x05, 1428 nvme_fabrics_type_auth_receive = 0x06, 1429 }; 1430 1431 #define nvme_fabrics_type_name(type) { type, #type } 1432 #define show_fabrics_type_name(type) \ 1433 __print_symbolic(type, \ 1434 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1435 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1436 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \ 1437 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \ 1438 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive)) 1439 1440 /* 1441 * If not fabrics command, fctype will be ignored. 1442 */ 1443 #define show_opcode_name(qid, opcode, fctype) \ 1444 ((opcode) == nvme_fabrics_command ? \ 1445 show_fabrics_type_name(fctype) : \ 1446 ((qid) ? \ 1447 show_nvm_opcode_name(opcode) : \ 1448 show_admin_opcode_name(opcode))) 1449 1450 struct nvmf_common_command { 1451 __u8 opcode; 1452 __u8 resv1; 1453 __u16 command_id; 1454 __u8 fctype; 1455 __u8 resv2[35]; 1456 __u8 ts[24]; 1457 }; 1458 1459 /* 1460 * The legal cntlid range a NVMe Target will provide. 1461 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1462 * Devices based on earlier specs did not have the subsystem concept; 1463 * therefore, those devices had their cntlid value set to 0 as a result. 1464 */ 1465 #define NVME_CNTLID_MIN 1 1466 #define NVME_CNTLID_MAX 0xffef 1467 #define NVME_CNTLID_DYNAMIC 0xffff 1468 1469 #define MAX_DISC_LOGS 255 1470 1471 /* Discovery log page entry flags (EFLAGS): */ 1472 enum { 1473 NVME_DISC_EFLAGS_EPCSD = (1 << 1), 1474 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0), 1475 }; 1476 1477 /* Discovery log page entry */ 1478 struct nvmf_disc_rsp_page_entry { 1479 __u8 trtype; 1480 __u8 adrfam; 1481 __u8 subtype; 1482 __u8 treq; 1483 __le16 portid; 1484 __le16 cntlid; 1485 __le16 asqsz; 1486 __le16 eflags; 1487 __u8 resv10[20]; 1488 char trsvcid[NVMF_TRSVCID_SIZE]; 1489 __u8 resv64[192]; 1490 char subnqn[NVMF_NQN_FIELD_LEN]; 1491 char traddr[NVMF_TRADDR_SIZE]; 1492 union tsas { 1493 char common[NVMF_TSAS_SIZE]; 1494 struct rdma { 1495 __u8 qptype; 1496 __u8 prtype; 1497 __u8 cms; 1498 __u8 resv3[5]; 1499 __u16 pkey; 1500 __u8 resv10[246]; 1501 } rdma; 1502 struct tcp { 1503 __u8 sectype; 1504 } tcp; 1505 } tsas; 1506 }; 1507 1508 /* Discovery log page header */ 1509 struct nvmf_disc_rsp_page_hdr { 1510 __le64 genctr; 1511 __le64 numrec; 1512 __le16 recfmt; 1513 __u8 resv14[1006]; 1514 struct nvmf_disc_rsp_page_entry entries[]; 1515 }; 1516 1517 enum { 1518 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1519 }; 1520 1521 struct nvmf_connect_command { 1522 __u8 opcode; 1523 __u8 resv1; 1524 __u16 command_id; 1525 __u8 fctype; 1526 __u8 resv2[19]; 1527 union nvme_data_ptr dptr; 1528 __le16 recfmt; 1529 __le16 qid; 1530 __le16 sqsize; 1531 __u8 cattr; 1532 __u8 resv3; 1533 __le32 kato; 1534 __u8 resv4[12]; 1535 }; 1536 1537 enum { 1538 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18), 1539 NVME_CONNECT_AUTHREQ_ATR = (1U << 17), 1540 }; 1541 1542 struct nvmf_connect_data { 1543 uuid_t hostid; 1544 __le16 cntlid; 1545 char resv4[238]; 1546 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1547 char hostnqn[NVMF_NQN_FIELD_LEN]; 1548 char resv5[256]; 1549 }; 1550 1551 struct nvmf_property_set_command { 1552 __u8 opcode; 1553 __u8 resv1; 1554 __u16 command_id; 1555 __u8 fctype; 1556 __u8 resv2[35]; 1557 __u8 attrib; 1558 __u8 resv3[3]; 1559 __le32 offset; 1560 __le64 value; 1561 __u8 resv4[8]; 1562 }; 1563 1564 struct nvmf_property_get_command { 1565 __u8 opcode; 1566 __u8 resv1; 1567 __u16 command_id; 1568 __u8 fctype; 1569 __u8 resv2[35]; 1570 __u8 attrib; 1571 __u8 resv3[3]; 1572 __le32 offset; 1573 __u8 resv4[16]; 1574 }; 1575 1576 struct nvmf_auth_common_command { 1577 __u8 opcode; 1578 __u8 resv1; 1579 __u16 command_id; 1580 __u8 fctype; 1581 __u8 resv2[19]; 1582 union nvme_data_ptr dptr; 1583 __u8 resv3; 1584 __u8 spsp0; 1585 __u8 spsp1; 1586 __u8 secp; 1587 __le32 al_tl; 1588 __u8 resv4[16]; 1589 }; 1590 1591 struct nvmf_auth_send_command { 1592 __u8 opcode; 1593 __u8 resv1; 1594 __u16 command_id; 1595 __u8 fctype; 1596 __u8 resv2[19]; 1597 union nvme_data_ptr dptr; 1598 __u8 resv3; 1599 __u8 spsp0; 1600 __u8 spsp1; 1601 __u8 secp; 1602 __le32 tl; 1603 __u8 resv4[16]; 1604 }; 1605 1606 struct nvmf_auth_receive_command { 1607 __u8 opcode; 1608 __u8 resv1; 1609 __u16 command_id; 1610 __u8 fctype; 1611 __u8 resv2[19]; 1612 union nvme_data_ptr dptr; 1613 __u8 resv3; 1614 __u8 spsp0; 1615 __u8 spsp1; 1616 __u8 secp; 1617 __le32 al; 1618 __u8 resv4[16]; 1619 }; 1620 1621 /* Value for secp */ 1622 enum { 1623 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9, 1624 }; 1625 1626 /* Defined value for auth_type */ 1627 enum { 1628 NVME_AUTH_COMMON_MESSAGES = 0x00, 1629 NVME_AUTH_DHCHAP_MESSAGES = 0x01, 1630 }; 1631 1632 /* Defined messages for auth_id */ 1633 enum { 1634 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00, 1635 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01, 1636 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02, 1637 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03, 1638 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04, 1639 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0, 1640 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1, 1641 }; 1642 1643 struct nvmf_auth_dhchap_protocol_descriptor { 1644 __u8 authid; 1645 __u8 rsvd; 1646 __u8 halen; 1647 __u8 dhlen; 1648 __u8 idlist[60]; 1649 }; 1650 1651 enum { 1652 NVME_AUTH_DHCHAP_AUTH_ID = 0x01, 1653 }; 1654 1655 /* Defined hash functions for DH-HMAC-CHAP authentication */ 1656 enum { 1657 NVME_AUTH_HASH_SHA256 = 0x01, 1658 NVME_AUTH_HASH_SHA384 = 0x02, 1659 NVME_AUTH_HASH_SHA512 = 0x03, 1660 NVME_AUTH_HASH_INVALID = 0xff, 1661 }; 1662 1663 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */ 1664 enum { 1665 NVME_AUTH_DHGROUP_NULL = 0x00, 1666 NVME_AUTH_DHGROUP_2048 = 0x01, 1667 NVME_AUTH_DHGROUP_3072 = 0x02, 1668 NVME_AUTH_DHGROUP_4096 = 0x03, 1669 NVME_AUTH_DHGROUP_6144 = 0x04, 1670 NVME_AUTH_DHGROUP_8192 = 0x05, 1671 NVME_AUTH_DHGROUP_INVALID = 0xff, 1672 }; 1673 1674 union nvmf_auth_protocol { 1675 struct nvmf_auth_dhchap_protocol_descriptor dhchap; 1676 }; 1677 1678 struct nvmf_auth_dhchap_negotiate_data { 1679 __u8 auth_type; 1680 __u8 auth_id; 1681 __le16 rsvd; 1682 __le16 t_id; 1683 __u8 sc_c; 1684 __u8 napd; 1685 union nvmf_auth_protocol auth_protocol[]; 1686 }; 1687 1688 struct nvmf_auth_dhchap_challenge_data { 1689 __u8 auth_type; 1690 __u8 auth_id; 1691 __u16 rsvd1; 1692 __le16 t_id; 1693 __u8 hl; 1694 __u8 rsvd2; 1695 __u8 hashid; 1696 __u8 dhgid; 1697 __le16 dhvlen; 1698 __le32 seqnum; 1699 /* 'hl' bytes of challenge value */ 1700 __u8 cval[]; 1701 /* followed by 'dhvlen' bytes of DH value */ 1702 }; 1703 1704 struct nvmf_auth_dhchap_reply_data { 1705 __u8 auth_type; 1706 __u8 auth_id; 1707 __le16 rsvd1; 1708 __le16 t_id; 1709 __u8 hl; 1710 __u8 rsvd2; 1711 __u8 cvalid; 1712 __u8 rsvd3; 1713 __le16 dhvlen; 1714 __le32 seqnum; 1715 /* 'hl' bytes of response data */ 1716 __u8 rval[]; 1717 /* followed by 'hl' bytes of Challenge value */ 1718 /* followed by 'dhvlen' bytes of DH value */ 1719 }; 1720 1721 enum { 1722 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0), 1723 }; 1724 1725 struct nvmf_auth_dhchap_success1_data { 1726 __u8 auth_type; 1727 __u8 auth_id; 1728 __le16 rsvd1; 1729 __le16 t_id; 1730 __u8 hl; 1731 __u8 rsvd2; 1732 __u8 rvalid; 1733 __u8 rsvd3[7]; 1734 /* 'hl' bytes of response value */ 1735 __u8 rval[]; 1736 }; 1737 1738 struct nvmf_auth_dhchap_success2_data { 1739 __u8 auth_type; 1740 __u8 auth_id; 1741 __le16 rsvd1; 1742 __le16 t_id; 1743 __u8 rsvd2[10]; 1744 }; 1745 1746 struct nvmf_auth_dhchap_failure_data { 1747 __u8 auth_type; 1748 __u8 auth_id; 1749 __le16 rsvd1; 1750 __le16 t_id; 1751 __u8 rescode; 1752 __u8 rescode_exp; 1753 }; 1754 1755 enum { 1756 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01, 1757 }; 1758 1759 enum { 1760 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01, 1761 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02, 1762 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03, 1763 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04, 1764 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05, 1765 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06, 1766 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07, 1767 }; 1768 1769 1770 struct nvme_dbbuf { 1771 __u8 opcode; 1772 __u8 flags; 1773 __u16 command_id; 1774 __u32 rsvd1[5]; 1775 __le64 prp1; 1776 __le64 prp2; 1777 __u32 rsvd12[6]; 1778 }; 1779 1780 struct streams_directive_params { 1781 __le16 msl; 1782 __le16 nssa; 1783 __le16 nsso; 1784 __u8 rsvd[10]; 1785 __le32 sws; 1786 __le16 sgs; 1787 __le16 nsa; 1788 __le16 nso; 1789 __u8 rsvd2[6]; 1790 }; 1791 1792 struct nvme_command { 1793 union { 1794 struct nvme_common_command common; 1795 struct nvme_rw_command rw; 1796 struct nvme_identify identify; 1797 struct nvme_features features; 1798 struct nvme_create_cq create_cq; 1799 struct nvme_create_sq create_sq; 1800 struct nvme_delete_queue delete_queue; 1801 struct nvme_download_firmware dlfw; 1802 struct nvme_format_cmd format; 1803 struct nvme_dsm_cmd dsm; 1804 struct nvme_write_zeroes_cmd write_zeroes; 1805 struct nvme_zone_mgmt_send_cmd zms; 1806 struct nvme_zone_mgmt_recv_cmd zmr; 1807 struct nvme_abort_cmd abort; 1808 struct nvme_get_log_page_command get_log_page; 1809 struct nvmf_common_command fabrics; 1810 struct nvmf_connect_command connect; 1811 struct nvmf_property_set_command prop_set; 1812 struct nvmf_property_get_command prop_get; 1813 struct nvmf_auth_common_command auth_common; 1814 struct nvmf_auth_send_command auth_send; 1815 struct nvmf_auth_receive_command auth_receive; 1816 struct nvme_dbbuf dbbuf; 1817 struct nvme_directive_cmd directive; 1818 }; 1819 }; 1820 1821 static inline bool nvme_is_fabrics(struct nvme_command *cmd) 1822 { 1823 return cmd->common.opcode == nvme_fabrics_command; 1824 } 1825 1826 struct nvme_error_slot { 1827 __le64 error_count; 1828 __le16 sqid; 1829 __le16 cmdid; 1830 __le16 status_field; 1831 __le16 param_error_location; 1832 __le64 lba; 1833 __le32 nsid; 1834 __u8 vs; 1835 __u8 resv[3]; 1836 __le64 cs; 1837 __u8 resv2[24]; 1838 }; 1839 1840 static inline bool nvme_is_write(struct nvme_command *cmd) 1841 { 1842 /* 1843 * What a mess... 1844 * 1845 * Why can't we simply have a Fabrics In and Fabrics out command? 1846 */ 1847 if (unlikely(nvme_is_fabrics(cmd))) 1848 return cmd->fabrics.fctype & 1; 1849 return cmd->common.opcode & 1; 1850 } 1851 1852 enum { 1853 /* 1854 * Generic Command Status: 1855 */ 1856 NVME_SC_SUCCESS = 0x0, 1857 NVME_SC_INVALID_OPCODE = 0x1, 1858 NVME_SC_INVALID_FIELD = 0x2, 1859 NVME_SC_CMDID_CONFLICT = 0x3, 1860 NVME_SC_DATA_XFER_ERROR = 0x4, 1861 NVME_SC_POWER_LOSS = 0x5, 1862 NVME_SC_INTERNAL = 0x6, 1863 NVME_SC_ABORT_REQ = 0x7, 1864 NVME_SC_ABORT_QUEUE = 0x8, 1865 NVME_SC_FUSED_FAIL = 0x9, 1866 NVME_SC_FUSED_MISSING = 0xa, 1867 NVME_SC_INVALID_NS = 0xb, 1868 NVME_SC_CMD_SEQ_ERROR = 0xc, 1869 NVME_SC_SGL_INVALID_LAST = 0xd, 1870 NVME_SC_SGL_INVALID_COUNT = 0xe, 1871 NVME_SC_SGL_INVALID_DATA = 0xf, 1872 NVME_SC_SGL_INVALID_METADATA = 0x10, 1873 NVME_SC_SGL_INVALID_TYPE = 0x11, 1874 NVME_SC_CMB_INVALID_USE = 0x12, 1875 NVME_SC_PRP_INVALID_OFFSET = 0x13, 1876 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, 1877 NVME_SC_OP_DENIED = 0x15, 1878 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1879 NVME_SC_RESERVED = 0x17, 1880 NVME_SC_HOST_ID_INCONSIST = 0x18, 1881 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, 1882 NVME_SC_KA_TIMEOUT_INVALID = 0x1A, 1883 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, 1884 NVME_SC_SANITIZE_FAILED = 0x1C, 1885 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, 1886 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, 1887 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, 1888 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1889 NVME_SC_CMD_INTERRUPTED = 0x21, 1890 NVME_SC_TRANSIENT_TR_ERR = 0x22, 1891 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24, 1892 NVME_SC_INVALID_IO_CMD_SET = 0x2C, 1893 1894 NVME_SC_LBA_RANGE = 0x80, 1895 NVME_SC_CAP_EXCEEDED = 0x81, 1896 NVME_SC_NS_NOT_READY = 0x82, 1897 NVME_SC_RESERVATION_CONFLICT = 0x83, 1898 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 1899 1900 /* 1901 * Command Specific Status: 1902 */ 1903 NVME_SC_CQ_INVALID = 0x100, 1904 NVME_SC_QID_INVALID = 0x101, 1905 NVME_SC_QUEUE_SIZE = 0x102, 1906 NVME_SC_ABORT_LIMIT = 0x103, 1907 NVME_SC_ABORT_MISSING = 0x104, 1908 NVME_SC_ASYNC_LIMIT = 0x105, 1909 NVME_SC_FIRMWARE_SLOT = 0x106, 1910 NVME_SC_FIRMWARE_IMAGE = 0x107, 1911 NVME_SC_INVALID_VECTOR = 0x108, 1912 NVME_SC_INVALID_LOG_PAGE = 0x109, 1913 NVME_SC_INVALID_FORMAT = 0x10a, 1914 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1915 NVME_SC_INVALID_QUEUE = 0x10c, 1916 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1917 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1918 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1919 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1920 NVME_SC_FW_NEEDS_RESET = 0x111, 1921 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1922 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1923 NVME_SC_OVERLAPPING_RANGE = 0x114, 1924 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1925 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1926 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1927 NVME_SC_NS_IS_PRIVATE = 0x119, 1928 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1929 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1930 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1931 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, 1932 NVME_SC_BP_WRITE_PROHIBITED = 0x11e, 1933 NVME_SC_CTRL_ID_INVALID = 0x11f, 1934 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, 1935 NVME_SC_CTRL_RES_NUM_INVALID = 0x121, 1936 NVME_SC_RES_ID_INVALID = 0x122, 1937 NVME_SC_PMR_SAN_PROHIBITED = 0x123, 1938 NVME_SC_ANA_GROUP_ID_INVALID = 0x124, 1939 NVME_SC_ANA_ATTACH_FAILED = 0x125, 1940 1941 /* 1942 * I/O Command Set Specific - NVM commands: 1943 */ 1944 NVME_SC_BAD_ATTRIBUTES = 0x180, 1945 NVME_SC_INVALID_PI = 0x181, 1946 NVME_SC_READ_ONLY = 0x182, 1947 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1948 1949 /* 1950 * I/O Command Set Specific - Fabrics commands: 1951 */ 1952 NVME_SC_CONNECT_FORMAT = 0x180, 1953 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1954 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1955 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1956 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1957 1958 NVME_SC_DISCOVERY_RESTART = 0x190, 1959 NVME_SC_AUTH_REQUIRED = 0x191, 1960 1961 /* 1962 * I/O Command Set Specific - Zoned commands: 1963 */ 1964 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, 1965 NVME_SC_ZONE_FULL = 0x1b9, 1966 NVME_SC_ZONE_READ_ONLY = 0x1ba, 1967 NVME_SC_ZONE_OFFLINE = 0x1bb, 1968 NVME_SC_ZONE_INVALID_WRITE = 0x1bc, 1969 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, 1970 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, 1971 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, 1972 1973 /* 1974 * Media and Data Integrity Errors: 1975 */ 1976 NVME_SC_WRITE_FAULT = 0x280, 1977 NVME_SC_READ_ERROR = 0x281, 1978 NVME_SC_GUARD_CHECK = 0x282, 1979 NVME_SC_APPTAG_CHECK = 0x283, 1980 NVME_SC_REFTAG_CHECK = 0x284, 1981 NVME_SC_COMPARE_FAILED = 0x285, 1982 NVME_SC_ACCESS_DENIED = 0x286, 1983 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1984 1985 /* 1986 * Path-related Errors: 1987 */ 1988 NVME_SC_INTERNAL_PATH_ERROR = 0x300, 1989 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1990 NVME_SC_ANA_INACCESSIBLE = 0x302, 1991 NVME_SC_ANA_TRANSITION = 0x303, 1992 NVME_SC_CTRL_PATH_ERROR = 0x360, 1993 NVME_SC_HOST_PATH_ERROR = 0x370, 1994 NVME_SC_HOST_ABORTED_CMD = 0x371, 1995 1996 NVME_SC_CRD = 0x1800, 1997 NVME_SC_MORE = 0x2000, 1998 NVME_SC_DNR = 0x4000, 1999 }; 2000 2001 struct nvme_completion { 2002 /* 2003 * Used by Admin and Fabrics commands to return data: 2004 */ 2005 union nvme_result { 2006 __le16 u16; 2007 __le32 u32; 2008 __le64 u64; 2009 } result; 2010 __le16 sq_head; /* how much of this queue may be reclaimed */ 2011 __le16 sq_id; /* submission queue that generated this entry */ 2012 __u16 command_id; /* of the command which completed */ 2013 __le16 status; /* did the command fail, and if so, why? */ 2014 }; 2015 2016 #define NVME_VS(major, minor, tertiary) \ 2017 (((major) << 16) | ((minor) << 8) | (tertiary)) 2018 2019 #define NVME_MAJOR(ver) ((ver) >> 16) 2020 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 2021 #define NVME_TERTIARY(ver) ((ver) & 0xff) 2022 2023 #endif /* _LINUX_NVME_H */ 2024