1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <linux/types.h> 19 #include <linux/uuid.h> 20 21 /* NQN names in commands fields specified one size */ 22 #define NVMF_NQN_FIELD_LEN 256 23 24 /* However the max length of a qualified name is another size */ 25 #define NVMF_NQN_SIZE 223 26 27 #define NVMF_TRSVCID_SIZE 32 28 #define NVMF_TRADDR_SIZE 256 29 #define NVMF_TSAS_SIZE 256 30 31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 32 33 #define NVME_RDMA_IP_PORT 4420 34 35 #define NVME_NSID_ALL 0xffffffff 36 37 enum nvme_subsys_type { 38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 39 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 40 }; 41 42 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 43 enum { 44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 49 }; 50 51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 52 enum { 53 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 55 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 56 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 57 NVMF_TRTYPE_MAX, 58 }; 59 60 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 61 enum { 62 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 63 NVMF_TREQ_REQUIRED = 1, /* Required */ 64 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 65 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 66 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 67 68 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 69 }; 70 71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 72 * RDMA_QPTYPE field 73 */ 74 enum { 75 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 76 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 77 }; 78 79 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 80 * RDMA_QPTYPE field 81 */ 82 enum { 83 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 84 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 85 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 86 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 87 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 88 }; 89 90 /* RDMA Connection Management Service Type codes for Discovery Log Page 91 * entry TSAS RDMA_CMS field 92 */ 93 enum { 94 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 95 }; 96 97 #define NVME_AQ_DEPTH 32 98 #define NVME_NR_AEN_COMMANDS 1 99 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 100 101 /* 102 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 103 * NVM-Express 1.2 specification, section 4.1.2. 104 */ 105 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 106 107 enum { 108 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 109 NVME_REG_VS = 0x0008, /* Version */ 110 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 111 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 112 NVME_REG_CC = 0x0014, /* Controller Configuration */ 113 NVME_REG_CSTS = 0x001c, /* Controller Status */ 114 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 115 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 116 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 117 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 118 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 119 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 120 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 121 }; 122 123 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 124 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 125 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 126 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 127 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 128 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 129 130 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 131 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 132 133 enum { 134 NVME_CMBSZ_SQS = 1 << 0, 135 NVME_CMBSZ_CQS = 1 << 1, 136 NVME_CMBSZ_LISTS = 1 << 2, 137 NVME_CMBSZ_RDS = 1 << 3, 138 NVME_CMBSZ_WDS = 1 << 4, 139 140 NVME_CMBSZ_SZ_SHIFT = 12, 141 NVME_CMBSZ_SZ_MASK = 0xfffff, 142 143 NVME_CMBSZ_SZU_SHIFT = 8, 144 NVME_CMBSZ_SZU_MASK = 0xf, 145 }; 146 147 /* 148 * Submission and Completion Queue Entry Sizes for the NVM command set. 149 * (In bytes and specified as a power of two (2^n)). 150 */ 151 #define NVME_NVM_IOSQES 6 152 #define NVME_NVM_IOCQES 4 153 154 enum { 155 NVME_CC_ENABLE = 1 << 0, 156 NVME_CC_CSS_NVM = 0 << 4, 157 NVME_CC_EN_SHIFT = 0, 158 NVME_CC_CSS_SHIFT = 4, 159 NVME_CC_MPS_SHIFT = 7, 160 NVME_CC_AMS_SHIFT = 11, 161 NVME_CC_SHN_SHIFT = 14, 162 NVME_CC_IOSQES_SHIFT = 16, 163 NVME_CC_IOCQES_SHIFT = 20, 164 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 165 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 166 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 167 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 168 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 169 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 170 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 171 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 172 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 173 NVME_CSTS_RDY = 1 << 0, 174 NVME_CSTS_CFS = 1 << 1, 175 NVME_CSTS_NSSRO = 1 << 4, 176 NVME_CSTS_PP = 1 << 5, 177 NVME_CSTS_SHST_NORMAL = 0 << 2, 178 NVME_CSTS_SHST_OCCUR = 1 << 2, 179 NVME_CSTS_SHST_CMPLT = 2 << 2, 180 NVME_CSTS_SHST_MASK = 3 << 2, 181 }; 182 183 struct nvme_id_power_state { 184 __le16 max_power; /* centiwatts */ 185 __u8 rsvd2; 186 __u8 flags; 187 __le32 entry_lat; /* microseconds */ 188 __le32 exit_lat; /* microseconds */ 189 __u8 read_tput; 190 __u8 read_lat; 191 __u8 write_tput; 192 __u8 write_lat; 193 __le16 idle_power; 194 __u8 idle_scale; 195 __u8 rsvd19; 196 __le16 active_power; 197 __u8 active_work_scale; 198 __u8 rsvd23[9]; 199 }; 200 201 enum { 202 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 203 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 204 }; 205 206 enum nvme_ctrl_attr { 207 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 208 NVME_CTRL_ATTR_TBKAS = (1 << 6), 209 }; 210 211 struct nvme_id_ctrl { 212 __le16 vid; 213 __le16 ssvid; 214 char sn[20]; 215 char mn[40]; 216 char fr[8]; 217 __u8 rab; 218 __u8 ieee[3]; 219 __u8 cmic; 220 __u8 mdts; 221 __le16 cntlid; 222 __le32 ver; 223 __le32 rtd3r; 224 __le32 rtd3e; 225 __le32 oaes; 226 __le32 ctratt; 227 __u8 rsvd100[28]; 228 __le16 crdt1; 229 __le16 crdt2; 230 __le16 crdt3; 231 __u8 rsvd134[122]; 232 __le16 oacs; 233 __u8 acl; 234 __u8 aerl; 235 __u8 frmw; 236 __u8 lpa; 237 __u8 elpe; 238 __u8 npss; 239 __u8 avscc; 240 __u8 apsta; 241 __le16 wctemp; 242 __le16 cctemp; 243 __le16 mtfa; 244 __le32 hmpre; 245 __le32 hmmin; 246 __u8 tnvmcap[16]; 247 __u8 unvmcap[16]; 248 __le32 rpmbs; 249 __le16 edstt; 250 __u8 dsto; 251 __u8 fwug; 252 __le16 kas; 253 __le16 hctma; 254 __le16 mntmt; 255 __le16 mxtmt; 256 __le32 sanicap; 257 __le32 hmminds; 258 __le16 hmmaxd; 259 __u8 rsvd338[4]; 260 __u8 anatt; 261 __u8 anacap; 262 __le32 anagrpmax; 263 __le32 nanagrpid; 264 __u8 rsvd352[160]; 265 __u8 sqes; 266 __u8 cqes; 267 __le16 maxcmd; 268 __le32 nn; 269 __le16 oncs; 270 __le16 fuses; 271 __u8 fna; 272 __u8 vwc; 273 __le16 awun; 274 __le16 awupf; 275 __u8 nvscc; 276 __u8 nwpc; 277 __le16 acwu; 278 __u8 rsvd534[2]; 279 __le32 sgls; 280 __le32 mnan; 281 __u8 rsvd544[224]; 282 char subnqn[256]; 283 __u8 rsvd1024[768]; 284 __le32 ioccsz; 285 __le32 iorcsz; 286 __le16 icdoff; 287 __u8 ctrattr; 288 __u8 msdbd; 289 __u8 rsvd1804[244]; 290 struct nvme_id_power_state psd[32]; 291 __u8 vs[1024]; 292 }; 293 294 enum { 295 NVME_CTRL_ONCS_COMPARE = 1 << 0, 296 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 297 NVME_CTRL_ONCS_DSM = 1 << 2, 298 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 299 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 300 NVME_CTRL_VWC_PRESENT = 1 << 0, 301 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 302 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 303 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 304 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 305 }; 306 307 struct nvme_lbaf { 308 __le16 ms; 309 __u8 ds; 310 __u8 rp; 311 }; 312 313 struct nvme_id_ns { 314 __le64 nsze; 315 __le64 ncap; 316 __le64 nuse; 317 __u8 nsfeat; 318 __u8 nlbaf; 319 __u8 flbas; 320 __u8 mc; 321 __u8 dpc; 322 __u8 dps; 323 __u8 nmic; 324 __u8 rescap; 325 __u8 fpi; 326 __u8 rsvd33; 327 __le16 nawun; 328 __le16 nawupf; 329 __le16 nacwu; 330 __le16 nabsn; 331 __le16 nabo; 332 __le16 nabspf; 333 __le16 noiob; 334 __u8 nvmcap[16]; 335 __u8 rsvd64[28]; 336 __le32 anagrpid; 337 __u8 rsvd96[3]; 338 __u8 nsattr; 339 __u8 rsvd100[4]; 340 __u8 nguid[16]; 341 __u8 eui64[8]; 342 struct nvme_lbaf lbaf[16]; 343 __u8 rsvd192[192]; 344 __u8 vs[3712]; 345 }; 346 347 enum { 348 NVME_ID_CNS_NS = 0x00, 349 NVME_ID_CNS_CTRL = 0x01, 350 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 351 NVME_ID_CNS_NS_DESC_LIST = 0x03, 352 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 353 NVME_ID_CNS_NS_PRESENT = 0x11, 354 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 355 NVME_ID_CNS_CTRL_LIST = 0x13, 356 }; 357 358 enum { 359 NVME_DIR_IDENTIFY = 0x00, 360 NVME_DIR_STREAMS = 0x01, 361 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 362 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 363 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 364 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 365 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 366 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 367 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 368 NVME_DIR_ENDIR = 0x01, 369 }; 370 371 enum { 372 NVME_NS_FEAT_THIN = 1 << 0, 373 NVME_NS_FLBAS_LBA_MASK = 0xf, 374 NVME_NS_FLBAS_META_EXT = 0x10, 375 NVME_LBAF_RP_BEST = 0, 376 NVME_LBAF_RP_BETTER = 1, 377 NVME_LBAF_RP_GOOD = 2, 378 NVME_LBAF_RP_DEGRADED = 3, 379 NVME_NS_DPC_PI_LAST = 1 << 4, 380 NVME_NS_DPC_PI_FIRST = 1 << 3, 381 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 382 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 383 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 384 NVME_NS_DPS_PI_FIRST = 1 << 3, 385 NVME_NS_DPS_PI_MASK = 0x7, 386 NVME_NS_DPS_PI_TYPE1 = 1, 387 NVME_NS_DPS_PI_TYPE2 = 2, 388 NVME_NS_DPS_PI_TYPE3 = 3, 389 }; 390 391 struct nvme_ns_id_desc { 392 __u8 nidt; 393 __u8 nidl; 394 __le16 reserved; 395 }; 396 397 #define NVME_NIDT_EUI64_LEN 8 398 #define NVME_NIDT_NGUID_LEN 16 399 #define NVME_NIDT_UUID_LEN 16 400 401 enum { 402 NVME_NIDT_EUI64 = 0x01, 403 NVME_NIDT_NGUID = 0x02, 404 NVME_NIDT_UUID = 0x03, 405 }; 406 407 struct nvme_smart_log { 408 __u8 critical_warning; 409 __u8 temperature[2]; 410 __u8 avail_spare; 411 __u8 spare_thresh; 412 __u8 percent_used; 413 __u8 rsvd6[26]; 414 __u8 data_units_read[16]; 415 __u8 data_units_written[16]; 416 __u8 host_reads[16]; 417 __u8 host_writes[16]; 418 __u8 ctrl_busy_time[16]; 419 __u8 power_cycles[16]; 420 __u8 power_on_hours[16]; 421 __u8 unsafe_shutdowns[16]; 422 __u8 media_errors[16]; 423 __u8 num_err_log_entries[16]; 424 __le32 warning_temp_time; 425 __le32 critical_comp_time; 426 __le16 temp_sensor[8]; 427 __u8 rsvd216[296]; 428 }; 429 430 struct nvme_fw_slot_info_log { 431 __u8 afi; 432 __u8 rsvd1[7]; 433 __le64 frs[7]; 434 __u8 rsvd64[448]; 435 }; 436 437 enum { 438 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 439 NVME_CMD_EFFECTS_LBCC = 1 << 1, 440 NVME_CMD_EFFECTS_NCC = 1 << 2, 441 NVME_CMD_EFFECTS_NIC = 1 << 3, 442 NVME_CMD_EFFECTS_CCC = 1 << 4, 443 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, 444 }; 445 446 struct nvme_effects_log { 447 __le32 acs[256]; 448 __le32 iocs[256]; 449 __u8 resv[2048]; 450 }; 451 452 enum nvme_ana_state { 453 NVME_ANA_OPTIMIZED = 0x01, 454 NVME_ANA_NONOPTIMIZED = 0x02, 455 NVME_ANA_INACCESSIBLE = 0x03, 456 NVME_ANA_PERSISTENT_LOSS = 0x04, 457 NVME_ANA_CHANGE = 0x0f, 458 }; 459 460 struct nvme_ana_group_desc { 461 __le32 grpid; 462 __le32 nnsids; 463 __le64 chgcnt; 464 __u8 state; 465 __u8 rsvd17[15]; 466 __le32 nsids[]; 467 }; 468 469 /* flag for the log specific field of the ANA log */ 470 #define NVME_ANA_LOG_RGO (1 << 0) 471 472 struct nvme_ana_rsp_hdr { 473 __le64 chgcnt; 474 __le16 ngrps; 475 __le16 rsvd10[3]; 476 }; 477 478 enum { 479 NVME_SMART_CRIT_SPARE = 1 << 0, 480 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 481 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 482 NVME_SMART_CRIT_MEDIA = 1 << 3, 483 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 484 }; 485 486 enum { 487 NVME_AER_ERROR = 0, 488 NVME_AER_SMART = 1, 489 NVME_AER_NOTICE = 2, 490 NVME_AER_CSS = 6, 491 NVME_AER_VS = 7, 492 }; 493 494 enum { 495 NVME_AER_NOTICE_NS_CHANGED = 0x00, 496 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 497 NVME_AER_NOTICE_ANA = 0x03, 498 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 499 }; 500 501 enum { 502 NVME_AEN_BIT_NS_ATTR = 8, 503 NVME_AEN_BIT_FW_ACT = 9, 504 NVME_AEN_BIT_ANA_CHANGE = 11, 505 NVME_AEN_BIT_DISC_CHANGE = 31, 506 }; 507 508 enum { 509 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 510 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 511 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 512 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 513 }; 514 515 struct nvme_lba_range_type { 516 __u8 type; 517 __u8 attributes; 518 __u8 rsvd2[14]; 519 __u64 slba; 520 __u64 nlb; 521 __u8 guid[16]; 522 __u8 rsvd48[16]; 523 }; 524 525 enum { 526 NVME_LBART_TYPE_FS = 0x01, 527 NVME_LBART_TYPE_RAID = 0x02, 528 NVME_LBART_TYPE_CACHE = 0x03, 529 NVME_LBART_TYPE_SWAP = 0x04, 530 531 NVME_LBART_ATTRIB_TEMP = 1 << 0, 532 NVME_LBART_ATTRIB_HIDE = 1 << 1, 533 }; 534 535 struct nvme_reservation_status { 536 __le32 gen; 537 __u8 rtype; 538 __u8 regctl[2]; 539 __u8 resv5[2]; 540 __u8 ptpls; 541 __u8 resv10[13]; 542 struct { 543 __le16 cntlid; 544 __u8 rcsts; 545 __u8 resv3[5]; 546 __le64 hostid; 547 __le64 rkey; 548 } regctl_ds[]; 549 }; 550 551 enum nvme_async_event_type { 552 NVME_AER_TYPE_ERROR = 0, 553 NVME_AER_TYPE_SMART = 1, 554 NVME_AER_TYPE_NOTICE = 2, 555 }; 556 557 /* I/O commands */ 558 559 enum nvme_opcode { 560 nvme_cmd_flush = 0x00, 561 nvme_cmd_write = 0x01, 562 nvme_cmd_read = 0x02, 563 nvme_cmd_write_uncor = 0x04, 564 nvme_cmd_compare = 0x05, 565 nvme_cmd_write_zeroes = 0x08, 566 nvme_cmd_dsm = 0x09, 567 nvme_cmd_resv_register = 0x0d, 568 nvme_cmd_resv_report = 0x0e, 569 nvme_cmd_resv_acquire = 0x11, 570 nvme_cmd_resv_release = 0x15, 571 }; 572 573 /* 574 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 575 * 576 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 577 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 578 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 579 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 580 * request subtype 581 */ 582 enum { 583 NVME_SGL_FMT_ADDRESS = 0x00, 584 NVME_SGL_FMT_OFFSET = 0x01, 585 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 586 NVME_SGL_FMT_INVALIDATE = 0x0f, 587 }; 588 589 /* 590 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 591 * 592 * For struct nvme_sgl_desc: 593 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 594 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 595 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 596 * 597 * For struct nvme_keyed_sgl_desc: 598 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 599 * 600 * Transport-specific SGL types: 601 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 602 */ 603 enum { 604 NVME_SGL_FMT_DATA_DESC = 0x00, 605 NVME_SGL_FMT_SEG_DESC = 0x02, 606 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 607 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 608 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 609 }; 610 611 struct nvme_sgl_desc { 612 __le64 addr; 613 __le32 length; 614 __u8 rsvd[3]; 615 __u8 type; 616 }; 617 618 struct nvme_keyed_sgl_desc { 619 __le64 addr; 620 __u8 length[3]; 621 __u8 key[4]; 622 __u8 type; 623 }; 624 625 union nvme_data_ptr { 626 struct { 627 __le64 prp1; 628 __le64 prp2; 629 }; 630 struct nvme_sgl_desc sgl; 631 struct nvme_keyed_sgl_desc ksgl; 632 }; 633 634 /* 635 * Lowest two bits of our flags field (FUSE field in the spec): 636 * 637 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 638 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 639 * 640 * Highest two bits in our flags field (PSDT field in the spec): 641 * 642 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 643 * If used, MPTR contains addr of single physical buffer (byte aligned). 644 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 645 * If used, MPTR contains an address of an SGL segment containing 646 * exactly 1 SGL descriptor (qword aligned). 647 */ 648 enum { 649 NVME_CMD_FUSE_FIRST = (1 << 0), 650 NVME_CMD_FUSE_SECOND = (1 << 1), 651 652 NVME_CMD_SGL_METABUF = (1 << 6), 653 NVME_CMD_SGL_METASEG = (1 << 7), 654 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 655 }; 656 657 struct nvme_common_command { 658 __u8 opcode; 659 __u8 flags; 660 __u16 command_id; 661 __le32 nsid; 662 __le32 cdw2[2]; 663 __le64 metadata; 664 union nvme_data_ptr dptr; 665 __le32 cdw10; 666 __le32 cdw11; 667 __le32 cdw12; 668 __le32 cdw13; 669 __le32 cdw14; 670 __le32 cdw15; 671 }; 672 673 struct nvme_rw_command { 674 __u8 opcode; 675 __u8 flags; 676 __u16 command_id; 677 __le32 nsid; 678 __u64 rsvd2; 679 __le64 metadata; 680 union nvme_data_ptr dptr; 681 __le64 slba; 682 __le16 length; 683 __le16 control; 684 __le32 dsmgmt; 685 __le32 reftag; 686 __le16 apptag; 687 __le16 appmask; 688 }; 689 690 enum { 691 NVME_RW_LR = 1 << 15, 692 NVME_RW_FUA = 1 << 14, 693 NVME_RW_DSM_FREQ_UNSPEC = 0, 694 NVME_RW_DSM_FREQ_TYPICAL = 1, 695 NVME_RW_DSM_FREQ_RARE = 2, 696 NVME_RW_DSM_FREQ_READS = 3, 697 NVME_RW_DSM_FREQ_WRITES = 4, 698 NVME_RW_DSM_FREQ_RW = 5, 699 NVME_RW_DSM_FREQ_ONCE = 6, 700 NVME_RW_DSM_FREQ_PREFETCH = 7, 701 NVME_RW_DSM_FREQ_TEMP = 8, 702 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 703 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 704 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 705 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 706 NVME_RW_DSM_SEQ_REQ = 1 << 6, 707 NVME_RW_DSM_COMPRESSED = 1 << 7, 708 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 709 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 710 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 711 NVME_RW_PRINFO_PRACT = 1 << 13, 712 NVME_RW_DTYPE_STREAMS = 1 << 4, 713 }; 714 715 struct nvme_dsm_cmd { 716 __u8 opcode; 717 __u8 flags; 718 __u16 command_id; 719 __le32 nsid; 720 __u64 rsvd2[2]; 721 union nvme_data_ptr dptr; 722 __le32 nr; 723 __le32 attributes; 724 __u32 rsvd12[4]; 725 }; 726 727 enum { 728 NVME_DSMGMT_IDR = 1 << 0, 729 NVME_DSMGMT_IDW = 1 << 1, 730 NVME_DSMGMT_AD = 1 << 2, 731 }; 732 733 #define NVME_DSM_MAX_RANGES 256 734 735 struct nvme_dsm_range { 736 __le32 cattr; 737 __le32 nlb; 738 __le64 slba; 739 }; 740 741 struct nvme_write_zeroes_cmd { 742 __u8 opcode; 743 __u8 flags; 744 __u16 command_id; 745 __le32 nsid; 746 __u64 rsvd2; 747 __le64 metadata; 748 union nvme_data_ptr dptr; 749 __le64 slba; 750 __le16 length; 751 __le16 control; 752 __le32 dsmgmt; 753 __le32 reftag; 754 __le16 apptag; 755 __le16 appmask; 756 }; 757 758 /* Features */ 759 760 struct nvme_feat_auto_pst { 761 __le64 entries[32]; 762 }; 763 764 enum { 765 NVME_HOST_MEM_ENABLE = (1 << 0), 766 NVME_HOST_MEM_RETURN = (1 << 1), 767 }; 768 769 struct nvme_feat_host_behavior { 770 __u8 acre; 771 __u8 resv1[511]; 772 }; 773 774 enum { 775 NVME_ENABLE_ACRE = 1, 776 }; 777 778 /* Admin commands */ 779 780 enum nvme_admin_opcode { 781 nvme_admin_delete_sq = 0x00, 782 nvme_admin_create_sq = 0x01, 783 nvme_admin_get_log_page = 0x02, 784 nvme_admin_delete_cq = 0x04, 785 nvme_admin_create_cq = 0x05, 786 nvme_admin_identify = 0x06, 787 nvme_admin_abort_cmd = 0x08, 788 nvme_admin_set_features = 0x09, 789 nvme_admin_get_features = 0x0a, 790 nvme_admin_async_event = 0x0c, 791 nvme_admin_ns_mgmt = 0x0d, 792 nvme_admin_activate_fw = 0x10, 793 nvme_admin_download_fw = 0x11, 794 nvme_admin_ns_attach = 0x15, 795 nvme_admin_keep_alive = 0x18, 796 nvme_admin_directive_send = 0x19, 797 nvme_admin_directive_recv = 0x1a, 798 nvme_admin_dbbuf = 0x7C, 799 nvme_admin_format_nvm = 0x80, 800 nvme_admin_security_send = 0x81, 801 nvme_admin_security_recv = 0x82, 802 nvme_admin_sanitize_nvm = 0x84, 803 }; 804 805 enum { 806 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 807 NVME_CQ_IRQ_ENABLED = (1 << 1), 808 NVME_SQ_PRIO_URGENT = (0 << 1), 809 NVME_SQ_PRIO_HIGH = (1 << 1), 810 NVME_SQ_PRIO_MEDIUM = (2 << 1), 811 NVME_SQ_PRIO_LOW = (3 << 1), 812 NVME_FEAT_ARBITRATION = 0x01, 813 NVME_FEAT_POWER_MGMT = 0x02, 814 NVME_FEAT_LBA_RANGE = 0x03, 815 NVME_FEAT_TEMP_THRESH = 0x04, 816 NVME_FEAT_ERR_RECOVERY = 0x05, 817 NVME_FEAT_VOLATILE_WC = 0x06, 818 NVME_FEAT_NUM_QUEUES = 0x07, 819 NVME_FEAT_IRQ_COALESCE = 0x08, 820 NVME_FEAT_IRQ_CONFIG = 0x09, 821 NVME_FEAT_WRITE_ATOMIC = 0x0a, 822 NVME_FEAT_ASYNC_EVENT = 0x0b, 823 NVME_FEAT_AUTO_PST = 0x0c, 824 NVME_FEAT_HOST_MEM_BUF = 0x0d, 825 NVME_FEAT_TIMESTAMP = 0x0e, 826 NVME_FEAT_KATO = 0x0f, 827 NVME_FEAT_HCTM = 0x10, 828 NVME_FEAT_NOPSC = 0x11, 829 NVME_FEAT_RRL = 0x12, 830 NVME_FEAT_PLM_CONFIG = 0x13, 831 NVME_FEAT_PLM_WINDOW = 0x14, 832 NVME_FEAT_HOST_BEHAVIOR = 0x16, 833 NVME_FEAT_SW_PROGRESS = 0x80, 834 NVME_FEAT_HOST_ID = 0x81, 835 NVME_FEAT_RESV_MASK = 0x82, 836 NVME_FEAT_RESV_PERSIST = 0x83, 837 NVME_FEAT_WRITE_PROTECT = 0x84, 838 NVME_LOG_ERROR = 0x01, 839 NVME_LOG_SMART = 0x02, 840 NVME_LOG_FW_SLOT = 0x03, 841 NVME_LOG_CHANGED_NS = 0x04, 842 NVME_LOG_CMD_EFFECTS = 0x05, 843 NVME_LOG_ANA = 0x0c, 844 NVME_LOG_DISC = 0x70, 845 NVME_LOG_RESERVATION = 0x80, 846 NVME_FWACT_REPL = (0 << 3), 847 NVME_FWACT_REPL_ACTV = (1 << 3), 848 NVME_FWACT_ACTV = (2 << 3), 849 }; 850 851 /* NVMe Namespace Write Protect State */ 852 enum { 853 NVME_NS_NO_WRITE_PROTECT = 0, 854 NVME_NS_WRITE_PROTECT, 855 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 856 NVME_NS_WRITE_PROTECT_PERMANENT, 857 }; 858 859 #define NVME_MAX_CHANGED_NAMESPACES 1024 860 861 struct nvme_identify { 862 __u8 opcode; 863 __u8 flags; 864 __u16 command_id; 865 __le32 nsid; 866 __u64 rsvd2[2]; 867 union nvme_data_ptr dptr; 868 __u8 cns; 869 __u8 rsvd3; 870 __le16 ctrlid; 871 __u32 rsvd11[5]; 872 }; 873 874 #define NVME_IDENTIFY_DATA_SIZE 4096 875 876 struct nvme_features { 877 __u8 opcode; 878 __u8 flags; 879 __u16 command_id; 880 __le32 nsid; 881 __u64 rsvd2[2]; 882 union nvme_data_ptr dptr; 883 __le32 fid; 884 __le32 dword11; 885 __le32 dword12; 886 __le32 dword13; 887 __le32 dword14; 888 __le32 dword15; 889 }; 890 891 struct nvme_host_mem_buf_desc { 892 __le64 addr; 893 __le32 size; 894 __u32 rsvd; 895 }; 896 897 struct nvme_create_cq { 898 __u8 opcode; 899 __u8 flags; 900 __u16 command_id; 901 __u32 rsvd1[5]; 902 __le64 prp1; 903 __u64 rsvd8; 904 __le16 cqid; 905 __le16 qsize; 906 __le16 cq_flags; 907 __le16 irq_vector; 908 __u32 rsvd12[4]; 909 }; 910 911 struct nvme_create_sq { 912 __u8 opcode; 913 __u8 flags; 914 __u16 command_id; 915 __u32 rsvd1[5]; 916 __le64 prp1; 917 __u64 rsvd8; 918 __le16 sqid; 919 __le16 qsize; 920 __le16 sq_flags; 921 __le16 cqid; 922 __u32 rsvd12[4]; 923 }; 924 925 struct nvme_delete_queue { 926 __u8 opcode; 927 __u8 flags; 928 __u16 command_id; 929 __u32 rsvd1[9]; 930 __le16 qid; 931 __u16 rsvd10; 932 __u32 rsvd11[5]; 933 }; 934 935 struct nvme_abort_cmd { 936 __u8 opcode; 937 __u8 flags; 938 __u16 command_id; 939 __u32 rsvd1[9]; 940 __le16 sqid; 941 __u16 cid; 942 __u32 rsvd11[5]; 943 }; 944 945 struct nvme_download_firmware { 946 __u8 opcode; 947 __u8 flags; 948 __u16 command_id; 949 __u32 rsvd1[5]; 950 union nvme_data_ptr dptr; 951 __le32 numd; 952 __le32 offset; 953 __u32 rsvd12[4]; 954 }; 955 956 struct nvme_format_cmd { 957 __u8 opcode; 958 __u8 flags; 959 __u16 command_id; 960 __le32 nsid; 961 __u64 rsvd2[4]; 962 __le32 cdw10; 963 __u32 rsvd11[5]; 964 }; 965 966 struct nvme_get_log_page_command { 967 __u8 opcode; 968 __u8 flags; 969 __u16 command_id; 970 __le32 nsid; 971 __u64 rsvd2[2]; 972 union nvme_data_ptr dptr; 973 __u8 lid; 974 __u8 lsp; /* upper 4 bits reserved */ 975 __le16 numdl; 976 __le16 numdu; 977 __u16 rsvd11; 978 __le32 lpol; 979 __le32 lpou; 980 __u32 rsvd14[2]; 981 }; 982 983 struct nvme_directive_cmd { 984 __u8 opcode; 985 __u8 flags; 986 __u16 command_id; 987 __le32 nsid; 988 __u64 rsvd2[2]; 989 union nvme_data_ptr dptr; 990 __le32 numd; 991 __u8 doper; 992 __u8 dtype; 993 __le16 dspec; 994 __u8 endir; 995 __u8 tdtype; 996 __u16 rsvd15; 997 998 __u32 rsvd16[3]; 999 }; 1000 1001 /* 1002 * Fabrics subcommands. 1003 */ 1004 enum nvmf_fabrics_opcode { 1005 nvme_fabrics_command = 0x7f, 1006 }; 1007 1008 enum nvmf_capsule_command { 1009 nvme_fabrics_type_property_set = 0x00, 1010 nvme_fabrics_type_connect = 0x01, 1011 nvme_fabrics_type_property_get = 0x04, 1012 }; 1013 1014 struct nvmf_common_command { 1015 __u8 opcode; 1016 __u8 resv1; 1017 __u16 command_id; 1018 __u8 fctype; 1019 __u8 resv2[35]; 1020 __u8 ts[24]; 1021 }; 1022 1023 /* 1024 * The legal cntlid range a NVMe Target will provide. 1025 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1026 * Devices based on earlier specs did not have the subsystem concept; 1027 * therefore, those devices had their cntlid value set to 0 as a result. 1028 */ 1029 #define NVME_CNTLID_MIN 1 1030 #define NVME_CNTLID_MAX 0xffef 1031 #define NVME_CNTLID_DYNAMIC 0xffff 1032 1033 #define MAX_DISC_LOGS 255 1034 1035 /* Discovery log page entry */ 1036 struct nvmf_disc_rsp_page_entry { 1037 __u8 trtype; 1038 __u8 adrfam; 1039 __u8 subtype; 1040 __u8 treq; 1041 __le16 portid; 1042 __le16 cntlid; 1043 __le16 asqsz; 1044 __u8 resv8[22]; 1045 char trsvcid[NVMF_TRSVCID_SIZE]; 1046 __u8 resv64[192]; 1047 char subnqn[NVMF_NQN_FIELD_LEN]; 1048 char traddr[NVMF_TRADDR_SIZE]; 1049 union tsas { 1050 char common[NVMF_TSAS_SIZE]; 1051 struct rdma { 1052 __u8 qptype; 1053 __u8 prtype; 1054 __u8 cms; 1055 __u8 resv3[5]; 1056 __u16 pkey; 1057 __u8 resv10[246]; 1058 } rdma; 1059 } tsas; 1060 }; 1061 1062 /* Discovery log page header */ 1063 struct nvmf_disc_rsp_page_hdr { 1064 __le64 genctr; 1065 __le64 numrec; 1066 __le16 recfmt; 1067 __u8 resv14[1006]; 1068 struct nvmf_disc_rsp_page_entry entries[0]; 1069 }; 1070 1071 enum { 1072 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1073 }; 1074 1075 struct nvmf_connect_command { 1076 __u8 opcode; 1077 __u8 resv1; 1078 __u16 command_id; 1079 __u8 fctype; 1080 __u8 resv2[19]; 1081 union nvme_data_ptr dptr; 1082 __le16 recfmt; 1083 __le16 qid; 1084 __le16 sqsize; 1085 __u8 cattr; 1086 __u8 resv3; 1087 __le32 kato; 1088 __u8 resv4[12]; 1089 }; 1090 1091 struct nvmf_connect_data { 1092 uuid_t hostid; 1093 __le16 cntlid; 1094 char resv4[238]; 1095 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1096 char hostnqn[NVMF_NQN_FIELD_LEN]; 1097 char resv5[256]; 1098 }; 1099 1100 struct nvmf_property_set_command { 1101 __u8 opcode; 1102 __u8 resv1; 1103 __u16 command_id; 1104 __u8 fctype; 1105 __u8 resv2[35]; 1106 __u8 attrib; 1107 __u8 resv3[3]; 1108 __le32 offset; 1109 __le64 value; 1110 __u8 resv4[8]; 1111 }; 1112 1113 struct nvmf_property_get_command { 1114 __u8 opcode; 1115 __u8 resv1; 1116 __u16 command_id; 1117 __u8 fctype; 1118 __u8 resv2[35]; 1119 __u8 attrib; 1120 __u8 resv3[3]; 1121 __le32 offset; 1122 __u8 resv4[16]; 1123 }; 1124 1125 struct nvme_dbbuf { 1126 __u8 opcode; 1127 __u8 flags; 1128 __u16 command_id; 1129 __u32 rsvd1[5]; 1130 __le64 prp1; 1131 __le64 prp2; 1132 __u32 rsvd12[6]; 1133 }; 1134 1135 struct streams_directive_params { 1136 __le16 msl; 1137 __le16 nssa; 1138 __le16 nsso; 1139 __u8 rsvd[10]; 1140 __le32 sws; 1141 __le16 sgs; 1142 __le16 nsa; 1143 __le16 nso; 1144 __u8 rsvd2[6]; 1145 }; 1146 1147 struct nvme_command { 1148 union { 1149 struct nvme_common_command common; 1150 struct nvme_rw_command rw; 1151 struct nvme_identify identify; 1152 struct nvme_features features; 1153 struct nvme_create_cq create_cq; 1154 struct nvme_create_sq create_sq; 1155 struct nvme_delete_queue delete_queue; 1156 struct nvme_download_firmware dlfw; 1157 struct nvme_format_cmd format; 1158 struct nvme_dsm_cmd dsm; 1159 struct nvme_write_zeroes_cmd write_zeroes; 1160 struct nvme_abort_cmd abort; 1161 struct nvme_get_log_page_command get_log_page; 1162 struct nvmf_common_command fabrics; 1163 struct nvmf_connect_command connect; 1164 struct nvmf_property_set_command prop_set; 1165 struct nvmf_property_get_command prop_get; 1166 struct nvme_dbbuf dbbuf; 1167 struct nvme_directive_cmd directive; 1168 }; 1169 }; 1170 1171 struct nvme_error_slot { 1172 __le64 error_count; 1173 __le16 sqid; 1174 __le16 cmdid; 1175 __le16 status_field; 1176 __le16 param_error_location; 1177 __le64 lba; 1178 __le32 nsid; 1179 __u8 vs; 1180 __u8 resv[3]; 1181 __le64 cs; 1182 __u8 resv2[24]; 1183 }; 1184 1185 static inline bool nvme_is_write(struct nvme_command *cmd) 1186 { 1187 /* 1188 * What a mess... 1189 * 1190 * Why can't we simply have a Fabrics In and Fabrics out command? 1191 */ 1192 if (unlikely(cmd->common.opcode == nvme_fabrics_command)) 1193 return cmd->fabrics.fctype & 1; 1194 return cmd->common.opcode & 1; 1195 } 1196 1197 enum { 1198 /* 1199 * Generic Command Status: 1200 */ 1201 NVME_SC_SUCCESS = 0x0, 1202 NVME_SC_INVALID_OPCODE = 0x1, 1203 NVME_SC_INVALID_FIELD = 0x2, 1204 NVME_SC_CMDID_CONFLICT = 0x3, 1205 NVME_SC_DATA_XFER_ERROR = 0x4, 1206 NVME_SC_POWER_LOSS = 0x5, 1207 NVME_SC_INTERNAL = 0x6, 1208 NVME_SC_ABORT_REQ = 0x7, 1209 NVME_SC_ABORT_QUEUE = 0x8, 1210 NVME_SC_FUSED_FAIL = 0x9, 1211 NVME_SC_FUSED_MISSING = 0xa, 1212 NVME_SC_INVALID_NS = 0xb, 1213 NVME_SC_CMD_SEQ_ERROR = 0xc, 1214 NVME_SC_SGL_INVALID_LAST = 0xd, 1215 NVME_SC_SGL_INVALID_COUNT = 0xe, 1216 NVME_SC_SGL_INVALID_DATA = 0xf, 1217 NVME_SC_SGL_INVALID_METADATA = 0x10, 1218 NVME_SC_SGL_INVALID_TYPE = 0x11, 1219 1220 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1221 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 1222 1223 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1224 1225 NVME_SC_LBA_RANGE = 0x80, 1226 NVME_SC_CAP_EXCEEDED = 0x81, 1227 NVME_SC_NS_NOT_READY = 0x82, 1228 NVME_SC_RESERVATION_CONFLICT = 0x83, 1229 1230 /* 1231 * Command Specific Status: 1232 */ 1233 NVME_SC_CQ_INVALID = 0x100, 1234 NVME_SC_QID_INVALID = 0x101, 1235 NVME_SC_QUEUE_SIZE = 0x102, 1236 NVME_SC_ABORT_LIMIT = 0x103, 1237 NVME_SC_ABORT_MISSING = 0x104, 1238 NVME_SC_ASYNC_LIMIT = 0x105, 1239 NVME_SC_FIRMWARE_SLOT = 0x106, 1240 NVME_SC_FIRMWARE_IMAGE = 0x107, 1241 NVME_SC_INVALID_VECTOR = 0x108, 1242 NVME_SC_INVALID_LOG_PAGE = 0x109, 1243 NVME_SC_INVALID_FORMAT = 0x10a, 1244 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1245 NVME_SC_INVALID_QUEUE = 0x10c, 1246 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1247 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1248 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1249 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1250 NVME_SC_FW_NEEDS_RESET = 0x111, 1251 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1252 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, 1253 NVME_SC_OVERLAPPING_RANGE = 0x114, 1254 NVME_SC_NS_INSUFFICENT_CAP = 0x115, 1255 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1256 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1257 NVME_SC_NS_IS_PRIVATE = 0x119, 1258 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1259 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1260 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1261 1262 /* 1263 * I/O Command Set Specific - NVM commands: 1264 */ 1265 NVME_SC_BAD_ATTRIBUTES = 0x180, 1266 NVME_SC_INVALID_PI = 0x181, 1267 NVME_SC_READ_ONLY = 0x182, 1268 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1269 1270 /* 1271 * I/O Command Set Specific - Fabrics commands: 1272 */ 1273 NVME_SC_CONNECT_FORMAT = 0x180, 1274 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1275 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1276 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1277 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1278 1279 NVME_SC_DISCOVERY_RESTART = 0x190, 1280 NVME_SC_AUTH_REQUIRED = 0x191, 1281 1282 /* 1283 * Media and Data Integrity Errors: 1284 */ 1285 NVME_SC_WRITE_FAULT = 0x280, 1286 NVME_SC_READ_ERROR = 0x281, 1287 NVME_SC_GUARD_CHECK = 0x282, 1288 NVME_SC_APPTAG_CHECK = 0x283, 1289 NVME_SC_REFTAG_CHECK = 0x284, 1290 NVME_SC_COMPARE_FAILED = 0x285, 1291 NVME_SC_ACCESS_DENIED = 0x286, 1292 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1293 1294 /* 1295 * Path-related Errors: 1296 */ 1297 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1298 NVME_SC_ANA_INACCESSIBLE = 0x302, 1299 NVME_SC_ANA_TRANSITION = 0x303, 1300 NVME_SC_HOST_PATH_ERROR = 0x370, 1301 1302 NVME_SC_CRD = 0x1800, 1303 NVME_SC_DNR = 0x4000, 1304 }; 1305 1306 struct nvme_completion { 1307 /* 1308 * Used by Admin and Fabrics commands to return data: 1309 */ 1310 union nvme_result { 1311 __le16 u16; 1312 __le32 u32; 1313 __le64 u64; 1314 } result; 1315 __le16 sq_head; /* how much of this queue may be reclaimed */ 1316 __le16 sq_id; /* submission queue that generated this entry */ 1317 __u16 command_id; /* of the command which completed */ 1318 __le16 status; /* did the command fail, and if so, why? */ 1319 }; 1320 1321 #define NVME_VS(major, minor, tertiary) \ 1322 (((major) << 16) | ((minor) << 8) | (tertiary)) 1323 1324 #define NVME_MAJOR(ver) ((ver) >> 16) 1325 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1326 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1327 1328 #endif /* _LINUX_NVME_H */ 1329