1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <linux/types.h> 19 #include <linux/uuid.h> 20 21 /* NQN names in commands fields specified one size */ 22 #define NVMF_NQN_FIELD_LEN 256 23 24 /* However the max length of a qualified name is another size */ 25 #define NVMF_NQN_SIZE 223 26 27 #define NVMF_TRSVCID_SIZE 32 28 #define NVMF_TRADDR_SIZE 256 29 #define NVMF_TSAS_SIZE 256 30 31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 32 33 #define NVME_RDMA_IP_PORT 4420 34 35 enum nvme_subsys_type { 36 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 37 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 38 }; 39 40 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 41 enum { 42 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 43 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 44 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 45 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 46 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 47 }; 48 49 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 50 enum { 51 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 52 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 53 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 54 NVMF_TRTYPE_MAX, 55 }; 56 57 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 58 enum { 59 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 60 NVMF_TREQ_REQUIRED = 1, /* Required */ 61 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 62 }; 63 64 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 65 * RDMA_QPTYPE field 66 */ 67 enum { 68 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 69 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 70 }; 71 72 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 73 * RDMA_QPTYPE field 74 */ 75 enum { 76 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 77 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 78 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 79 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 80 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 81 }; 82 83 /* RDMA Connection Management Service Type codes for Discovery Log Page 84 * entry TSAS RDMA_CMS field 85 */ 86 enum { 87 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 88 }; 89 90 #define NVME_AQ_DEPTH 32 91 92 enum { 93 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 94 NVME_REG_VS = 0x0008, /* Version */ 95 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 96 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 97 NVME_REG_CC = 0x0014, /* Controller Configuration */ 98 NVME_REG_CSTS = 0x001c, /* Controller Status */ 99 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 100 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 101 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 102 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 103 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 104 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 105 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 106 }; 107 108 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 109 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 110 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 111 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 112 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 113 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 114 115 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 116 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 117 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) 118 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) 119 120 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) 121 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) 122 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) 123 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) 124 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) 125 126 /* 127 * Submission and Completion Queue Entry Sizes for the NVM command set. 128 * (In bytes and specified as a power of two (2^n)). 129 */ 130 #define NVME_NVM_IOSQES 6 131 #define NVME_NVM_IOCQES 4 132 133 enum { 134 NVME_CC_ENABLE = 1 << 0, 135 NVME_CC_CSS_NVM = 0 << 4, 136 NVME_CC_MPS_SHIFT = 7, 137 NVME_CC_ARB_RR = 0 << 11, 138 NVME_CC_ARB_WRRU = 1 << 11, 139 NVME_CC_ARB_VS = 7 << 11, 140 NVME_CC_SHN_NONE = 0 << 14, 141 NVME_CC_SHN_NORMAL = 1 << 14, 142 NVME_CC_SHN_ABRUPT = 2 << 14, 143 NVME_CC_SHN_MASK = 3 << 14, 144 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16, 145 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20, 146 NVME_CSTS_RDY = 1 << 0, 147 NVME_CSTS_CFS = 1 << 1, 148 NVME_CSTS_NSSRO = 1 << 4, 149 NVME_CSTS_SHST_NORMAL = 0 << 2, 150 NVME_CSTS_SHST_OCCUR = 1 << 2, 151 NVME_CSTS_SHST_CMPLT = 2 << 2, 152 NVME_CSTS_SHST_MASK = 3 << 2, 153 }; 154 155 struct nvme_id_power_state { 156 __le16 max_power; /* centiwatts */ 157 __u8 rsvd2; 158 __u8 flags; 159 __le32 entry_lat; /* microseconds */ 160 __le32 exit_lat; /* microseconds */ 161 __u8 read_tput; 162 __u8 read_lat; 163 __u8 write_tput; 164 __u8 write_lat; 165 __le16 idle_power; 166 __u8 idle_scale; 167 __u8 rsvd19; 168 __le16 active_power; 169 __u8 active_work_scale; 170 __u8 rsvd23[9]; 171 }; 172 173 enum { 174 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 175 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 176 }; 177 178 struct nvme_id_ctrl { 179 __le16 vid; 180 __le16 ssvid; 181 char sn[20]; 182 char mn[40]; 183 char fr[8]; 184 __u8 rab; 185 __u8 ieee[3]; 186 __u8 cmic; 187 __u8 mdts; 188 __le16 cntlid; 189 __le32 ver; 190 __le32 rtd3r; 191 __le32 rtd3e; 192 __le32 oaes; 193 __le32 ctratt; 194 __u8 rsvd100[156]; 195 __le16 oacs; 196 __u8 acl; 197 __u8 aerl; 198 __u8 frmw; 199 __u8 lpa; 200 __u8 elpe; 201 __u8 npss; 202 __u8 avscc; 203 __u8 apsta; 204 __le16 wctemp; 205 __le16 cctemp; 206 __le16 mtfa; 207 __le32 hmpre; 208 __le32 hmmin; 209 __u8 tnvmcap[16]; 210 __u8 unvmcap[16]; 211 __le32 rpmbs; 212 __le16 edstt; 213 __u8 dsto; 214 __u8 fwug; 215 __le16 kas; 216 __le16 hctma; 217 __le16 mntmt; 218 __le16 mxtmt; 219 __le32 sanicap; 220 __u8 rsvd332[180]; 221 __u8 sqes; 222 __u8 cqes; 223 __le16 maxcmd; 224 __le32 nn; 225 __le16 oncs; 226 __le16 fuses; 227 __u8 fna; 228 __u8 vwc; 229 __le16 awun; 230 __le16 awupf; 231 __u8 nvscc; 232 __u8 rsvd531; 233 __le16 acwu; 234 __u8 rsvd534[2]; 235 __le32 sgls; 236 __u8 rsvd540[228]; 237 char subnqn[256]; 238 __u8 rsvd1024[768]; 239 __le32 ioccsz; 240 __le32 iorcsz; 241 __le16 icdoff; 242 __u8 ctrattr; 243 __u8 msdbd; 244 __u8 rsvd1804[244]; 245 struct nvme_id_power_state psd[32]; 246 __u8 vs[1024]; 247 }; 248 249 enum { 250 NVME_CTRL_ONCS_COMPARE = 1 << 0, 251 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 252 NVME_CTRL_ONCS_DSM = 1 << 2, 253 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 254 NVME_CTRL_VWC_PRESENT = 1 << 0, 255 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 256 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 257 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7, 258 }; 259 260 struct nvme_lbaf { 261 __le16 ms; 262 __u8 ds; 263 __u8 rp; 264 }; 265 266 struct nvme_id_ns { 267 __le64 nsze; 268 __le64 ncap; 269 __le64 nuse; 270 __u8 nsfeat; 271 __u8 nlbaf; 272 __u8 flbas; 273 __u8 mc; 274 __u8 dpc; 275 __u8 dps; 276 __u8 nmic; 277 __u8 rescap; 278 __u8 fpi; 279 __u8 rsvd33; 280 __le16 nawun; 281 __le16 nawupf; 282 __le16 nacwu; 283 __le16 nabsn; 284 __le16 nabo; 285 __le16 nabspf; 286 __le16 noiob; 287 __u8 nvmcap[16]; 288 __u8 rsvd64[40]; 289 __u8 nguid[16]; 290 __u8 eui64[8]; 291 struct nvme_lbaf lbaf[16]; 292 __u8 rsvd192[192]; 293 __u8 vs[3712]; 294 }; 295 296 enum { 297 NVME_ID_CNS_NS = 0x00, 298 NVME_ID_CNS_CTRL = 0x01, 299 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 300 NVME_ID_CNS_NS_DESC_LIST = 0x03, 301 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 302 NVME_ID_CNS_NS_PRESENT = 0x11, 303 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 304 NVME_ID_CNS_CTRL_LIST = 0x13, 305 }; 306 307 enum { 308 NVME_DIR_IDENTIFY = 0x00, 309 NVME_DIR_STREAMS = 0x01, 310 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 311 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 312 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 313 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 314 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 315 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 316 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 317 NVME_DIR_ENDIR = 0x01, 318 }; 319 320 enum { 321 NVME_NS_FEAT_THIN = 1 << 0, 322 NVME_NS_FLBAS_LBA_MASK = 0xf, 323 NVME_NS_FLBAS_META_EXT = 0x10, 324 NVME_LBAF_RP_BEST = 0, 325 NVME_LBAF_RP_BETTER = 1, 326 NVME_LBAF_RP_GOOD = 2, 327 NVME_LBAF_RP_DEGRADED = 3, 328 NVME_NS_DPC_PI_LAST = 1 << 4, 329 NVME_NS_DPC_PI_FIRST = 1 << 3, 330 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 331 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 332 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 333 NVME_NS_DPS_PI_FIRST = 1 << 3, 334 NVME_NS_DPS_PI_MASK = 0x7, 335 NVME_NS_DPS_PI_TYPE1 = 1, 336 NVME_NS_DPS_PI_TYPE2 = 2, 337 NVME_NS_DPS_PI_TYPE3 = 3, 338 }; 339 340 struct nvme_ns_id_desc { 341 __u8 nidt; 342 __u8 nidl; 343 __le16 reserved; 344 }; 345 346 #define NVME_NIDT_EUI64_LEN 8 347 #define NVME_NIDT_NGUID_LEN 16 348 #define NVME_NIDT_UUID_LEN 16 349 350 enum { 351 NVME_NIDT_EUI64 = 0x01, 352 NVME_NIDT_NGUID = 0x02, 353 NVME_NIDT_UUID = 0x03, 354 }; 355 356 struct nvme_smart_log { 357 __u8 critical_warning; 358 __u8 temperature[2]; 359 __u8 avail_spare; 360 __u8 spare_thresh; 361 __u8 percent_used; 362 __u8 rsvd6[26]; 363 __u8 data_units_read[16]; 364 __u8 data_units_written[16]; 365 __u8 host_reads[16]; 366 __u8 host_writes[16]; 367 __u8 ctrl_busy_time[16]; 368 __u8 power_cycles[16]; 369 __u8 power_on_hours[16]; 370 __u8 unsafe_shutdowns[16]; 371 __u8 media_errors[16]; 372 __u8 num_err_log_entries[16]; 373 __le32 warning_temp_time; 374 __le32 critical_comp_time; 375 __le16 temp_sensor[8]; 376 __u8 rsvd216[296]; 377 }; 378 379 enum { 380 NVME_SMART_CRIT_SPARE = 1 << 0, 381 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 382 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 383 NVME_SMART_CRIT_MEDIA = 1 << 3, 384 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 385 }; 386 387 enum { 388 NVME_AER_NOTICE_NS_CHANGED = 0x0002, 389 }; 390 391 struct nvme_lba_range_type { 392 __u8 type; 393 __u8 attributes; 394 __u8 rsvd2[14]; 395 __u64 slba; 396 __u64 nlb; 397 __u8 guid[16]; 398 __u8 rsvd48[16]; 399 }; 400 401 enum { 402 NVME_LBART_TYPE_FS = 0x01, 403 NVME_LBART_TYPE_RAID = 0x02, 404 NVME_LBART_TYPE_CACHE = 0x03, 405 NVME_LBART_TYPE_SWAP = 0x04, 406 407 NVME_LBART_ATTRIB_TEMP = 1 << 0, 408 NVME_LBART_ATTRIB_HIDE = 1 << 1, 409 }; 410 411 struct nvme_reservation_status { 412 __le32 gen; 413 __u8 rtype; 414 __u8 regctl[2]; 415 __u8 resv5[2]; 416 __u8 ptpls; 417 __u8 resv10[13]; 418 struct { 419 __le16 cntlid; 420 __u8 rcsts; 421 __u8 resv3[5]; 422 __le64 hostid; 423 __le64 rkey; 424 } regctl_ds[]; 425 }; 426 427 enum nvme_async_event_type { 428 NVME_AER_TYPE_ERROR = 0, 429 NVME_AER_TYPE_SMART = 1, 430 NVME_AER_TYPE_NOTICE = 2, 431 }; 432 433 /* I/O commands */ 434 435 enum nvme_opcode { 436 nvme_cmd_flush = 0x00, 437 nvme_cmd_write = 0x01, 438 nvme_cmd_read = 0x02, 439 nvme_cmd_write_uncor = 0x04, 440 nvme_cmd_compare = 0x05, 441 nvme_cmd_write_zeroes = 0x08, 442 nvme_cmd_dsm = 0x09, 443 nvme_cmd_resv_register = 0x0d, 444 nvme_cmd_resv_report = 0x0e, 445 nvme_cmd_resv_acquire = 0x11, 446 nvme_cmd_resv_release = 0x15, 447 }; 448 449 /* 450 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 451 * 452 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 453 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 454 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 455 * request subtype 456 */ 457 enum { 458 NVME_SGL_FMT_ADDRESS = 0x00, 459 NVME_SGL_FMT_OFFSET = 0x01, 460 NVME_SGL_FMT_INVALIDATE = 0x0f, 461 }; 462 463 /* 464 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 465 * 466 * For struct nvme_sgl_desc: 467 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 468 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 469 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 470 * 471 * For struct nvme_keyed_sgl_desc: 472 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 473 */ 474 enum { 475 NVME_SGL_FMT_DATA_DESC = 0x00, 476 NVME_SGL_FMT_SEG_DESC = 0x02, 477 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 478 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 479 }; 480 481 struct nvme_sgl_desc { 482 __le64 addr; 483 __le32 length; 484 __u8 rsvd[3]; 485 __u8 type; 486 }; 487 488 struct nvme_keyed_sgl_desc { 489 __le64 addr; 490 __u8 length[3]; 491 __u8 key[4]; 492 __u8 type; 493 }; 494 495 union nvme_data_ptr { 496 struct { 497 __le64 prp1; 498 __le64 prp2; 499 }; 500 struct nvme_sgl_desc sgl; 501 struct nvme_keyed_sgl_desc ksgl; 502 }; 503 504 /* 505 * Lowest two bits of our flags field (FUSE field in the spec): 506 * 507 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 508 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 509 * 510 * Highest two bits in our flags field (PSDT field in the spec): 511 * 512 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 513 * If used, MPTR contains addr of single physical buffer (byte aligned). 514 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 515 * If used, MPTR contains an address of an SGL segment containing 516 * exactly 1 SGL descriptor (qword aligned). 517 */ 518 enum { 519 NVME_CMD_FUSE_FIRST = (1 << 0), 520 NVME_CMD_FUSE_SECOND = (1 << 1), 521 522 NVME_CMD_SGL_METABUF = (1 << 6), 523 NVME_CMD_SGL_METASEG = (1 << 7), 524 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 525 }; 526 527 struct nvme_common_command { 528 __u8 opcode; 529 __u8 flags; 530 __u16 command_id; 531 __le32 nsid; 532 __le32 cdw2[2]; 533 __le64 metadata; 534 union nvme_data_ptr dptr; 535 __le32 cdw10[6]; 536 }; 537 538 struct nvme_rw_command { 539 __u8 opcode; 540 __u8 flags; 541 __u16 command_id; 542 __le32 nsid; 543 __u64 rsvd2; 544 __le64 metadata; 545 union nvme_data_ptr dptr; 546 __le64 slba; 547 __le16 length; 548 __le16 control; 549 __le32 dsmgmt; 550 __le32 reftag; 551 __le16 apptag; 552 __le16 appmask; 553 }; 554 555 enum { 556 NVME_RW_LR = 1 << 15, 557 NVME_RW_FUA = 1 << 14, 558 NVME_RW_DSM_FREQ_UNSPEC = 0, 559 NVME_RW_DSM_FREQ_TYPICAL = 1, 560 NVME_RW_DSM_FREQ_RARE = 2, 561 NVME_RW_DSM_FREQ_READS = 3, 562 NVME_RW_DSM_FREQ_WRITES = 4, 563 NVME_RW_DSM_FREQ_RW = 5, 564 NVME_RW_DSM_FREQ_ONCE = 6, 565 NVME_RW_DSM_FREQ_PREFETCH = 7, 566 NVME_RW_DSM_FREQ_TEMP = 8, 567 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 568 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 569 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 570 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 571 NVME_RW_DSM_SEQ_REQ = 1 << 6, 572 NVME_RW_DSM_COMPRESSED = 1 << 7, 573 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 574 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 575 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 576 NVME_RW_PRINFO_PRACT = 1 << 13, 577 NVME_RW_DTYPE_STREAMS = 1 << 4, 578 }; 579 580 struct nvme_dsm_cmd { 581 __u8 opcode; 582 __u8 flags; 583 __u16 command_id; 584 __le32 nsid; 585 __u64 rsvd2[2]; 586 union nvme_data_ptr dptr; 587 __le32 nr; 588 __le32 attributes; 589 __u32 rsvd12[4]; 590 }; 591 592 enum { 593 NVME_DSMGMT_IDR = 1 << 0, 594 NVME_DSMGMT_IDW = 1 << 1, 595 NVME_DSMGMT_AD = 1 << 2, 596 }; 597 598 #define NVME_DSM_MAX_RANGES 256 599 600 struct nvme_dsm_range { 601 __le32 cattr; 602 __le32 nlb; 603 __le64 slba; 604 }; 605 606 struct nvme_write_zeroes_cmd { 607 __u8 opcode; 608 __u8 flags; 609 __u16 command_id; 610 __le32 nsid; 611 __u64 rsvd2; 612 __le64 metadata; 613 union nvme_data_ptr dptr; 614 __le64 slba; 615 __le16 length; 616 __le16 control; 617 __le32 dsmgmt; 618 __le32 reftag; 619 __le16 apptag; 620 __le16 appmask; 621 }; 622 623 /* Features */ 624 625 struct nvme_feat_auto_pst { 626 __le64 entries[32]; 627 }; 628 629 enum { 630 NVME_HOST_MEM_ENABLE = (1 << 0), 631 NVME_HOST_MEM_RETURN = (1 << 1), 632 }; 633 634 /* Admin commands */ 635 636 enum nvme_admin_opcode { 637 nvme_admin_delete_sq = 0x00, 638 nvme_admin_create_sq = 0x01, 639 nvme_admin_get_log_page = 0x02, 640 nvme_admin_delete_cq = 0x04, 641 nvme_admin_create_cq = 0x05, 642 nvme_admin_identify = 0x06, 643 nvme_admin_abort_cmd = 0x08, 644 nvme_admin_set_features = 0x09, 645 nvme_admin_get_features = 0x0a, 646 nvme_admin_async_event = 0x0c, 647 nvme_admin_ns_mgmt = 0x0d, 648 nvme_admin_activate_fw = 0x10, 649 nvme_admin_download_fw = 0x11, 650 nvme_admin_ns_attach = 0x15, 651 nvme_admin_keep_alive = 0x18, 652 nvme_admin_directive_send = 0x19, 653 nvme_admin_directive_recv = 0x1a, 654 nvme_admin_dbbuf = 0x7C, 655 nvme_admin_format_nvm = 0x80, 656 nvme_admin_security_send = 0x81, 657 nvme_admin_security_recv = 0x82, 658 }; 659 660 enum { 661 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 662 NVME_CQ_IRQ_ENABLED = (1 << 1), 663 NVME_SQ_PRIO_URGENT = (0 << 1), 664 NVME_SQ_PRIO_HIGH = (1 << 1), 665 NVME_SQ_PRIO_MEDIUM = (2 << 1), 666 NVME_SQ_PRIO_LOW = (3 << 1), 667 NVME_FEAT_ARBITRATION = 0x01, 668 NVME_FEAT_POWER_MGMT = 0x02, 669 NVME_FEAT_LBA_RANGE = 0x03, 670 NVME_FEAT_TEMP_THRESH = 0x04, 671 NVME_FEAT_ERR_RECOVERY = 0x05, 672 NVME_FEAT_VOLATILE_WC = 0x06, 673 NVME_FEAT_NUM_QUEUES = 0x07, 674 NVME_FEAT_IRQ_COALESCE = 0x08, 675 NVME_FEAT_IRQ_CONFIG = 0x09, 676 NVME_FEAT_WRITE_ATOMIC = 0x0a, 677 NVME_FEAT_ASYNC_EVENT = 0x0b, 678 NVME_FEAT_AUTO_PST = 0x0c, 679 NVME_FEAT_HOST_MEM_BUF = 0x0d, 680 NVME_FEAT_KATO = 0x0f, 681 NVME_FEAT_SW_PROGRESS = 0x80, 682 NVME_FEAT_HOST_ID = 0x81, 683 NVME_FEAT_RESV_MASK = 0x82, 684 NVME_FEAT_RESV_PERSIST = 0x83, 685 NVME_LOG_ERROR = 0x01, 686 NVME_LOG_SMART = 0x02, 687 NVME_LOG_FW_SLOT = 0x03, 688 NVME_LOG_DISC = 0x70, 689 NVME_LOG_RESERVATION = 0x80, 690 NVME_FWACT_REPL = (0 << 3), 691 NVME_FWACT_REPL_ACTV = (1 << 3), 692 NVME_FWACT_ACTV = (2 << 3), 693 }; 694 695 struct nvme_identify { 696 __u8 opcode; 697 __u8 flags; 698 __u16 command_id; 699 __le32 nsid; 700 __u64 rsvd2[2]; 701 union nvme_data_ptr dptr; 702 __u8 cns; 703 __u8 rsvd3; 704 __le16 ctrlid; 705 __u32 rsvd11[5]; 706 }; 707 708 #define NVME_IDENTIFY_DATA_SIZE 4096 709 710 struct nvme_features { 711 __u8 opcode; 712 __u8 flags; 713 __u16 command_id; 714 __le32 nsid; 715 __u64 rsvd2[2]; 716 union nvme_data_ptr dptr; 717 __le32 fid; 718 __le32 dword11; 719 __le32 dword12; 720 __le32 dword13; 721 __le32 dword14; 722 __le32 dword15; 723 }; 724 725 struct nvme_host_mem_buf_desc { 726 __le64 addr; 727 __le32 size; 728 __u32 rsvd; 729 }; 730 731 struct nvme_create_cq { 732 __u8 opcode; 733 __u8 flags; 734 __u16 command_id; 735 __u32 rsvd1[5]; 736 __le64 prp1; 737 __u64 rsvd8; 738 __le16 cqid; 739 __le16 qsize; 740 __le16 cq_flags; 741 __le16 irq_vector; 742 __u32 rsvd12[4]; 743 }; 744 745 struct nvme_create_sq { 746 __u8 opcode; 747 __u8 flags; 748 __u16 command_id; 749 __u32 rsvd1[5]; 750 __le64 prp1; 751 __u64 rsvd8; 752 __le16 sqid; 753 __le16 qsize; 754 __le16 sq_flags; 755 __le16 cqid; 756 __u32 rsvd12[4]; 757 }; 758 759 struct nvme_delete_queue { 760 __u8 opcode; 761 __u8 flags; 762 __u16 command_id; 763 __u32 rsvd1[9]; 764 __le16 qid; 765 __u16 rsvd10; 766 __u32 rsvd11[5]; 767 }; 768 769 struct nvme_abort_cmd { 770 __u8 opcode; 771 __u8 flags; 772 __u16 command_id; 773 __u32 rsvd1[9]; 774 __le16 sqid; 775 __u16 cid; 776 __u32 rsvd11[5]; 777 }; 778 779 struct nvme_download_firmware { 780 __u8 opcode; 781 __u8 flags; 782 __u16 command_id; 783 __u32 rsvd1[5]; 784 union nvme_data_ptr dptr; 785 __le32 numd; 786 __le32 offset; 787 __u32 rsvd12[4]; 788 }; 789 790 struct nvme_format_cmd { 791 __u8 opcode; 792 __u8 flags; 793 __u16 command_id; 794 __le32 nsid; 795 __u64 rsvd2[4]; 796 __le32 cdw10; 797 __u32 rsvd11[5]; 798 }; 799 800 struct nvme_get_log_page_command { 801 __u8 opcode; 802 __u8 flags; 803 __u16 command_id; 804 __le32 nsid; 805 __u64 rsvd2[2]; 806 union nvme_data_ptr dptr; 807 __u8 lid; 808 __u8 rsvd10; 809 __le16 numdl; 810 __le16 numdu; 811 __u16 rsvd11; 812 __le32 lpol; 813 __le32 lpou; 814 __u32 rsvd14[2]; 815 }; 816 817 struct nvme_directive_cmd { 818 __u8 opcode; 819 __u8 flags; 820 __u16 command_id; 821 __le32 nsid; 822 __u64 rsvd2[2]; 823 union nvme_data_ptr dptr; 824 __le32 numd; 825 __u8 doper; 826 __u8 dtype; 827 __le16 dspec; 828 __u8 endir; 829 __u8 tdtype; 830 __u16 rsvd15; 831 832 __u32 rsvd16[3]; 833 }; 834 835 /* 836 * Fabrics subcommands. 837 */ 838 enum nvmf_fabrics_opcode { 839 nvme_fabrics_command = 0x7f, 840 }; 841 842 enum nvmf_capsule_command { 843 nvme_fabrics_type_property_set = 0x00, 844 nvme_fabrics_type_connect = 0x01, 845 nvme_fabrics_type_property_get = 0x04, 846 }; 847 848 struct nvmf_common_command { 849 __u8 opcode; 850 __u8 resv1; 851 __u16 command_id; 852 __u8 fctype; 853 __u8 resv2[35]; 854 __u8 ts[24]; 855 }; 856 857 /* 858 * The legal cntlid range a NVMe Target will provide. 859 * Note that cntlid of value 0 is considered illegal in the fabrics world. 860 * Devices based on earlier specs did not have the subsystem concept; 861 * therefore, those devices had their cntlid value set to 0 as a result. 862 */ 863 #define NVME_CNTLID_MIN 1 864 #define NVME_CNTLID_MAX 0xffef 865 #define NVME_CNTLID_DYNAMIC 0xffff 866 867 #define MAX_DISC_LOGS 255 868 869 /* Discovery log page entry */ 870 struct nvmf_disc_rsp_page_entry { 871 __u8 trtype; 872 __u8 adrfam; 873 __u8 subtype; 874 __u8 treq; 875 __le16 portid; 876 __le16 cntlid; 877 __le16 asqsz; 878 __u8 resv8[22]; 879 char trsvcid[NVMF_TRSVCID_SIZE]; 880 __u8 resv64[192]; 881 char subnqn[NVMF_NQN_FIELD_LEN]; 882 char traddr[NVMF_TRADDR_SIZE]; 883 union tsas { 884 char common[NVMF_TSAS_SIZE]; 885 struct rdma { 886 __u8 qptype; 887 __u8 prtype; 888 __u8 cms; 889 __u8 resv3[5]; 890 __u16 pkey; 891 __u8 resv10[246]; 892 } rdma; 893 } tsas; 894 }; 895 896 /* Discovery log page header */ 897 struct nvmf_disc_rsp_page_hdr { 898 __le64 genctr; 899 __le64 numrec; 900 __le16 recfmt; 901 __u8 resv14[1006]; 902 struct nvmf_disc_rsp_page_entry entries[0]; 903 }; 904 905 struct nvmf_connect_command { 906 __u8 opcode; 907 __u8 resv1; 908 __u16 command_id; 909 __u8 fctype; 910 __u8 resv2[19]; 911 union nvme_data_ptr dptr; 912 __le16 recfmt; 913 __le16 qid; 914 __le16 sqsize; 915 __u8 cattr; 916 __u8 resv3; 917 __le32 kato; 918 __u8 resv4[12]; 919 }; 920 921 struct nvmf_connect_data { 922 uuid_t hostid; 923 __le16 cntlid; 924 char resv4[238]; 925 char subsysnqn[NVMF_NQN_FIELD_LEN]; 926 char hostnqn[NVMF_NQN_FIELD_LEN]; 927 char resv5[256]; 928 }; 929 930 struct nvmf_property_set_command { 931 __u8 opcode; 932 __u8 resv1; 933 __u16 command_id; 934 __u8 fctype; 935 __u8 resv2[35]; 936 __u8 attrib; 937 __u8 resv3[3]; 938 __le32 offset; 939 __le64 value; 940 __u8 resv4[8]; 941 }; 942 943 struct nvmf_property_get_command { 944 __u8 opcode; 945 __u8 resv1; 946 __u16 command_id; 947 __u8 fctype; 948 __u8 resv2[35]; 949 __u8 attrib; 950 __u8 resv3[3]; 951 __le32 offset; 952 __u8 resv4[16]; 953 }; 954 955 struct nvme_dbbuf { 956 __u8 opcode; 957 __u8 flags; 958 __u16 command_id; 959 __u32 rsvd1[5]; 960 __le64 prp1; 961 __le64 prp2; 962 __u32 rsvd12[6]; 963 }; 964 965 struct streams_directive_params { 966 __le16 msl; 967 __le16 nssa; 968 __le16 nsso; 969 __u8 rsvd[10]; 970 __le32 sws; 971 __le16 sgs; 972 __le16 nsa; 973 __le16 nso; 974 __u8 rsvd2[6]; 975 }; 976 977 struct nvme_command { 978 union { 979 struct nvme_common_command common; 980 struct nvme_rw_command rw; 981 struct nvme_identify identify; 982 struct nvme_features features; 983 struct nvme_create_cq create_cq; 984 struct nvme_create_sq create_sq; 985 struct nvme_delete_queue delete_queue; 986 struct nvme_download_firmware dlfw; 987 struct nvme_format_cmd format; 988 struct nvme_dsm_cmd dsm; 989 struct nvme_write_zeroes_cmd write_zeroes; 990 struct nvme_abort_cmd abort; 991 struct nvme_get_log_page_command get_log_page; 992 struct nvmf_common_command fabrics; 993 struct nvmf_connect_command connect; 994 struct nvmf_property_set_command prop_set; 995 struct nvmf_property_get_command prop_get; 996 struct nvme_dbbuf dbbuf; 997 struct nvme_directive_cmd directive; 998 }; 999 }; 1000 1001 static inline bool nvme_is_write(struct nvme_command *cmd) 1002 { 1003 /* 1004 * What a mess... 1005 * 1006 * Why can't we simply have a Fabrics In and Fabrics out command? 1007 */ 1008 if (unlikely(cmd->common.opcode == nvme_fabrics_command)) 1009 return cmd->fabrics.fctype & 1; 1010 return cmd->common.opcode & 1; 1011 } 1012 1013 enum { 1014 /* 1015 * Generic Command Status: 1016 */ 1017 NVME_SC_SUCCESS = 0x0, 1018 NVME_SC_INVALID_OPCODE = 0x1, 1019 NVME_SC_INVALID_FIELD = 0x2, 1020 NVME_SC_CMDID_CONFLICT = 0x3, 1021 NVME_SC_DATA_XFER_ERROR = 0x4, 1022 NVME_SC_POWER_LOSS = 0x5, 1023 NVME_SC_INTERNAL = 0x6, 1024 NVME_SC_ABORT_REQ = 0x7, 1025 NVME_SC_ABORT_QUEUE = 0x8, 1026 NVME_SC_FUSED_FAIL = 0x9, 1027 NVME_SC_FUSED_MISSING = 0xa, 1028 NVME_SC_INVALID_NS = 0xb, 1029 NVME_SC_CMD_SEQ_ERROR = 0xc, 1030 NVME_SC_SGL_INVALID_LAST = 0xd, 1031 NVME_SC_SGL_INVALID_COUNT = 0xe, 1032 NVME_SC_SGL_INVALID_DATA = 0xf, 1033 NVME_SC_SGL_INVALID_METADATA = 0x10, 1034 NVME_SC_SGL_INVALID_TYPE = 0x11, 1035 1036 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1037 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 1038 1039 NVME_SC_LBA_RANGE = 0x80, 1040 NVME_SC_CAP_EXCEEDED = 0x81, 1041 NVME_SC_NS_NOT_READY = 0x82, 1042 NVME_SC_RESERVATION_CONFLICT = 0x83, 1043 1044 /* 1045 * Command Specific Status: 1046 */ 1047 NVME_SC_CQ_INVALID = 0x100, 1048 NVME_SC_QID_INVALID = 0x101, 1049 NVME_SC_QUEUE_SIZE = 0x102, 1050 NVME_SC_ABORT_LIMIT = 0x103, 1051 NVME_SC_ABORT_MISSING = 0x104, 1052 NVME_SC_ASYNC_LIMIT = 0x105, 1053 NVME_SC_FIRMWARE_SLOT = 0x106, 1054 NVME_SC_FIRMWARE_IMAGE = 0x107, 1055 NVME_SC_INVALID_VECTOR = 0x108, 1056 NVME_SC_INVALID_LOG_PAGE = 0x109, 1057 NVME_SC_INVALID_FORMAT = 0x10a, 1058 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1059 NVME_SC_INVALID_QUEUE = 0x10c, 1060 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1061 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1062 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1063 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1064 NVME_SC_FW_NEEDS_RESET = 0x111, 1065 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1066 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, 1067 NVME_SC_OVERLAPPING_RANGE = 0x114, 1068 NVME_SC_NS_INSUFFICENT_CAP = 0x115, 1069 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1070 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1071 NVME_SC_NS_IS_PRIVATE = 0x119, 1072 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1073 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1074 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1075 1076 /* 1077 * I/O Command Set Specific - NVM commands: 1078 */ 1079 NVME_SC_BAD_ATTRIBUTES = 0x180, 1080 NVME_SC_INVALID_PI = 0x181, 1081 NVME_SC_READ_ONLY = 0x182, 1082 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1083 1084 /* 1085 * I/O Command Set Specific - Fabrics commands: 1086 */ 1087 NVME_SC_CONNECT_FORMAT = 0x180, 1088 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1089 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1090 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1091 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1092 1093 NVME_SC_DISCOVERY_RESTART = 0x190, 1094 NVME_SC_AUTH_REQUIRED = 0x191, 1095 1096 /* 1097 * Media and Data Integrity Errors: 1098 */ 1099 NVME_SC_WRITE_FAULT = 0x280, 1100 NVME_SC_READ_ERROR = 0x281, 1101 NVME_SC_GUARD_CHECK = 0x282, 1102 NVME_SC_APPTAG_CHECK = 0x283, 1103 NVME_SC_REFTAG_CHECK = 0x284, 1104 NVME_SC_COMPARE_FAILED = 0x285, 1105 NVME_SC_ACCESS_DENIED = 0x286, 1106 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1107 1108 NVME_SC_DNR = 0x4000, 1109 1110 1111 /* 1112 * FC Transport-specific error status values for NVME commands 1113 * 1114 * Transport-specific status code values must be in the range 0xB0..0xBF 1115 */ 1116 1117 /* Generic FC failure - catchall */ 1118 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0, 1119 1120 /* I/O failure due to FC ABTS'd */ 1121 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1, 1122 }; 1123 1124 struct nvme_completion { 1125 /* 1126 * Used by Admin and Fabrics commands to return data: 1127 */ 1128 union nvme_result { 1129 __le16 u16; 1130 __le32 u32; 1131 __le64 u64; 1132 } result; 1133 __le16 sq_head; /* how much of this queue may be reclaimed */ 1134 __le16 sq_id; /* submission queue that generated this entry */ 1135 __u16 command_id; /* of the command which completed */ 1136 __le16 status; /* did the command fail, and if so, why? */ 1137 }; 1138 1139 #define NVME_VS(major, minor, tertiary) \ 1140 (((major) << 16) | ((minor) << 8) | (tertiary)) 1141 1142 #define NVME_MAJOR(ver) ((ver) >> 16) 1143 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1144 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1145 1146 #endif /* _LINUX_NVME_H */ 1147