1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <linux/types.h> 19 20 enum { 21 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 22 NVME_REG_VS = 0x0008, /* Version */ 23 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 24 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 25 NVME_REG_CC = 0x0014, /* Controller Configuration */ 26 NVME_REG_CSTS = 0x001c, /* Controller Status */ 27 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 28 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 29 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 30 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 31 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 32 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 33 }; 34 35 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 36 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 37 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 38 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 39 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 40 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 41 42 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 43 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 44 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) 45 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) 46 47 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) 48 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) 49 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) 50 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) 51 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) 52 53 enum { 54 NVME_CC_ENABLE = 1 << 0, 55 NVME_CC_CSS_NVM = 0 << 4, 56 NVME_CC_MPS_SHIFT = 7, 57 NVME_CC_ARB_RR = 0 << 11, 58 NVME_CC_ARB_WRRU = 1 << 11, 59 NVME_CC_ARB_VS = 7 << 11, 60 NVME_CC_SHN_NONE = 0 << 14, 61 NVME_CC_SHN_NORMAL = 1 << 14, 62 NVME_CC_SHN_ABRUPT = 2 << 14, 63 NVME_CC_SHN_MASK = 3 << 14, 64 NVME_CC_IOSQES = 6 << 16, 65 NVME_CC_IOCQES = 4 << 20, 66 NVME_CSTS_RDY = 1 << 0, 67 NVME_CSTS_CFS = 1 << 1, 68 NVME_CSTS_NSSRO = 1 << 4, 69 NVME_CSTS_SHST_NORMAL = 0 << 2, 70 NVME_CSTS_SHST_OCCUR = 1 << 2, 71 NVME_CSTS_SHST_CMPLT = 2 << 2, 72 NVME_CSTS_SHST_MASK = 3 << 2, 73 }; 74 75 struct nvme_id_power_state { 76 __le16 max_power; /* centiwatts */ 77 __u8 rsvd2; 78 __u8 flags; 79 __le32 entry_lat; /* microseconds */ 80 __le32 exit_lat; /* microseconds */ 81 __u8 read_tput; 82 __u8 read_lat; 83 __u8 write_tput; 84 __u8 write_lat; 85 __le16 idle_power; 86 __u8 idle_scale; 87 __u8 rsvd19; 88 __le16 active_power; 89 __u8 active_work_scale; 90 __u8 rsvd23[9]; 91 }; 92 93 enum { 94 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 95 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 96 }; 97 98 struct nvme_id_ctrl { 99 __le16 vid; 100 __le16 ssvid; 101 char sn[20]; 102 char mn[40]; 103 char fr[8]; 104 __u8 rab; 105 __u8 ieee[3]; 106 __u8 mic; 107 __u8 mdts; 108 __le16 cntlid; 109 __le32 ver; 110 __u8 rsvd84[172]; 111 __le16 oacs; 112 __u8 acl; 113 __u8 aerl; 114 __u8 frmw; 115 __u8 lpa; 116 __u8 elpe; 117 __u8 npss; 118 __u8 avscc; 119 __u8 apsta; 120 __le16 wctemp; 121 __le16 cctemp; 122 __u8 rsvd270[242]; 123 __u8 sqes; 124 __u8 cqes; 125 __u8 rsvd514[2]; 126 __le32 nn; 127 __le16 oncs; 128 __le16 fuses; 129 __u8 fna; 130 __u8 vwc; 131 __le16 awun; 132 __le16 awupf; 133 __u8 nvscc; 134 __u8 rsvd531; 135 __le16 acwu; 136 __u8 rsvd534[2]; 137 __le32 sgls; 138 __u8 rsvd540[1508]; 139 struct nvme_id_power_state psd[32]; 140 __u8 vs[1024]; 141 }; 142 143 enum { 144 NVME_CTRL_ONCS_COMPARE = 1 << 0, 145 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 146 NVME_CTRL_ONCS_DSM = 1 << 2, 147 NVME_CTRL_VWC_PRESENT = 1 << 0, 148 }; 149 150 struct nvme_lbaf { 151 __le16 ms; 152 __u8 ds; 153 __u8 rp; 154 }; 155 156 struct nvme_id_ns { 157 __le64 nsze; 158 __le64 ncap; 159 __le64 nuse; 160 __u8 nsfeat; 161 __u8 nlbaf; 162 __u8 flbas; 163 __u8 mc; 164 __u8 dpc; 165 __u8 dps; 166 __u8 nmic; 167 __u8 rescap; 168 __u8 fpi; 169 __u8 rsvd33; 170 __le16 nawun; 171 __le16 nawupf; 172 __le16 nacwu; 173 __le16 nabsn; 174 __le16 nabo; 175 __le16 nabspf; 176 __u16 rsvd46; 177 __le64 nvmcap[2]; 178 __u8 rsvd64[40]; 179 __u8 nguid[16]; 180 __u8 eui64[8]; 181 struct nvme_lbaf lbaf[16]; 182 __u8 rsvd192[192]; 183 __u8 vs[3712]; 184 }; 185 186 enum { 187 NVME_NS_FEAT_THIN = 1 << 0, 188 NVME_NS_FLBAS_LBA_MASK = 0xf, 189 NVME_NS_FLBAS_META_EXT = 0x10, 190 NVME_LBAF_RP_BEST = 0, 191 NVME_LBAF_RP_BETTER = 1, 192 NVME_LBAF_RP_GOOD = 2, 193 NVME_LBAF_RP_DEGRADED = 3, 194 NVME_NS_DPC_PI_LAST = 1 << 4, 195 NVME_NS_DPC_PI_FIRST = 1 << 3, 196 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 197 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 198 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 199 NVME_NS_DPS_PI_FIRST = 1 << 3, 200 NVME_NS_DPS_PI_MASK = 0x7, 201 NVME_NS_DPS_PI_TYPE1 = 1, 202 NVME_NS_DPS_PI_TYPE2 = 2, 203 NVME_NS_DPS_PI_TYPE3 = 3, 204 }; 205 206 struct nvme_smart_log { 207 __u8 critical_warning; 208 __u8 temperature[2]; 209 __u8 avail_spare; 210 __u8 spare_thresh; 211 __u8 percent_used; 212 __u8 rsvd6[26]; 213 __u8 data_units_read[16]; 214 __u8 data_units_written[16]; 215 __u8 host_reads[16]; 216 __u8 host_writes[16]; 217 __u8 ctrl_busy_time[16]; 218 __u8 power_cycles[16]; 219 __u8 power_on_hours[16]; 220 __u8 unsafe_shutdowns[16]; 221 __u8 media_errors[16]; 222 __u8 num_err_log_entries[16]; 223 __le32 warning_temp_time; 224 __le32 critical_comp_time; 225 __le16 temp_sensor[8]; 226 __u8 rsvd216[296]; 227 }; 228 229 enum { 230 NVME_SMART_CRIT_SPARE = 1 << 0, 231 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 232 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 233 NVME_SMART_CRIT_MEDIA = 1 << 3, 234 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 235 }; 236 237 enum { 238 NVME_AER_NOTICE_NS_CHANGED = 0x0002, 239 }; 240 241 struct nvme_lba_range_type { 242 __u8 type; 243 __u8 attributes; 244 __u8 rsvd2[14]; 245 __u64 slba; 246 __u64 nlb; 247 __u8 guid[16]; 248 __u8 rsvd48[16]; 249 }; 250 251 enum { 252 NVME_LBART_TYPE_FS = 0x01, 253 NVME_LBART_TYPE_RAID = 0x02, 254 NVME_LBART_TYPE_CACHE = 0x03, 255 NVME_LBART_TYPE_SWAP = 0x04, 256 257 NVME_LBART_ATTRIB_TEMP = 1 << 0, 258 NVME_LBART_ATTRIB_HIDE = 1 << 1, 259 }; 260 261 struct nvme_reservation_status { 262 __le32 gen; 263 __u8 rtype; 264 __u8 regctl[2]; 265 __u8 resv5[2]; 266 __u8 ptpls; 267 __u8 resv10[13]; 268 struct { 269 __le16 cntlid; 270 __u8 rcsts; 271 __u8 resv3[5]; 272 __le64 hostid; 273 __le64 rkey; 274 } regctl_ds[]; 275 }; 276 277 /* I/O commands */ 278 279 enum nvme_opcode { 280 nvme_cmd_flush = 0x00, 281 nvme_cmd_write = 0x01, 282 nvme_cmd_read = 0x02, 283 nvme_cmd_write_uncor = 0x04, 284 nvme_cmd_compare = 0x05, 285 nvme_cmd_write_zeroes = 0x08, 286 nvme_cmd_dsm = 0x09, 287 nvme_cmd_resv_register = 0x0d, 288 nvme_cmd_resv_report = 0x0e, 289 nvme_cmd_resv_acquire = 0x11, 290 nvme_cmd_resv_release = 0x15, 291 }; 292 293 struct nvme_common_command { 294 __u8 opcode; 295 __u8 flags; 296 __u16 command_id; 297 __le32 nsid; 298 __le32 cdw2[2]; 299 __le64 metadata; 300 __le64 prp1; 301 __le64 prp2; 302 __le32 cdw10[6]; 303 }; 304 305 struct nvme_rw_command { 306 __u8 opcode; 307 __u8 flags; 308 __u16 command_id; 309 __le32 nsid; 310 __u64 rsvd2; 311 __le64 metadata; 312 __le64 prp1; 313 __le64 prp2; 314 __le64 slba; 315 __le16 length; 316 __le16 control; 317 __le32 dsmgmt; 318 __le32 reftag; 319 __le16 apptag; 320 __le16 appmask; 321 }; 322 323 enum { 324 NVME_RW_LR = 1 << 15, 325 NVME_RW_FUA = 1 << 14, 326 NVME_RW_DSM_FREQ_UNSPEC = 0, 327 NVME_RW_DSM_FREQ_TYPICAL = 1, 328 NVME_RW_DSM_FREQ_RARE = 2, 329 NVME_RW_DSM_FREQ_READS = 3, 330 NVME_RW_DSM_FREQ_WRITES = 4, 331 NVME_RW_DSM_FREQ_RW = 5, 332 NVME_RW_DSM_FREQ_ONCE = 6, 333 NVME_RW_DSM_FREQ_PREFETCH = 7, 334 NVME_RW_DSM_FREQ_TEMP = 8, 335 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 336 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 337 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 338 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 339 NVME_RW_DSM_SEQ_REQ = 1 << 6, 340 NVME_RW_DSM_COMPRESSED = 1 << 7, 341 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 342 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 343 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 344 NVME_RW_PRINFO_PRACT = 1 << 13, 345 }; 346 347 struct nvme_dsm_cmd { 348 __u8 opcode; 349 __u8 flags; 350 __u16 command_id; 351 __le32 nsid; 352 __u64 rsvd2[2]; 353 __le64 prp1; 354 __le64 prp2; 355 __le32 nr; 356 __le32 attributes; 357 __u32 rsvd12[4]; 358 }; 359 360 enum { 361 NVME_DSMGMT_IDR = 1 << 0, 362 NVME_DSMGMT_IDW = 1 << 1, 363 NVME_DSMGMT_AD = 1 << 2, 364 }; 365 366 struct nvme_dsm_range { 367 __le32 cattr; 368 __le32 nlb; 369 __le64 slba; 370 }; 371 372 /* Admin commands */ 373 374 enum nvme_admin_opcode { 375 nvme_admin_delete_sq = 0x00, 376 nvme_admin_create_sq = 0x01, 377 nvme_admin_get_log_page = 0x02, 378 nvme_admin_delete_cq = 0x04, 379 nvme_admin_create_cq = 0x05, 380 nvme_admin_identify = 0x06, 381 nvme_admin_abort_cmd = 0x08, 382 nvme_admin_set_features = 0x09, 383 nvme_admin_get_features = 0x0a, 384 nvme_admin_async_event = 0x0c, 385 nvme_admin_activate_fw = 0x10, 386 nvme_admin_download_fw = 0x11, 387 nvme_admin_format_nvm = 0x80, 388 nvme_admin_security_send = 0x81, 389 nvme_admin_security_recv = 0x82, 390 }; 391 392 enum { 393 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 394 NVME_CQ_IRQ_ENABLED = (1 << 1), 395 NVME_SQ_PRIO_URGENT = (0 << 1), 396 NVME_SQ_PRIO_HIGH = (1 << 1), 397 NVME_SQ_PRIO_MEDIUM = (2 << 1), 398 NVME_SQ_PRIO_LOW = (3 << 1), 399 NVME_FEAT_ARBITRATION = 0x01, 400 NVME_FEAT_POWER_MGMT = 0x02, 401 NVME_FEAT_LBA_RANGE = 0x03, 402 NVME_FEAT_TEMP_THRESH = 0x04, 403 NVME_FEAT_ERR_RECOVERY = 0x05, 404 NVME_FEAT_VOLATILE_WC = 0x06, 405 NVME_FEAT_NUM_QUEUES = 0x07, 406 NVME_FEAT_IRQ_COALESCE = 0x08, 407 NVME_FEAT_IRQ_CONFIG = 0x09, 408 NVME_FEAT_WRITE_ATOMIC = 0x0a, 409 NVME_FEAT_ASYNC_EVENT = 0x0b, 410 NVME_FEAT_AUTO_PST = 0x0c, 411 NVME_FEAT_SW_PROGRESS = 0x80, 412 NVME_FEAT_HOST_ID = 0x81, 413 NVME_FEAT_RESV_MASK = 0x82, 414 NVME_FEAT_RESV_PERSIST = 0x83, 415 NVME_LOG_ERROR = 0x01, 416 NVME_LOG_SMART = 0x02, 417 NVME_LOG_FW_SLOT = 0x03, 418 NVME_LOG_RESERVATION = 0x80, 419 NVME_FWACT_REPL = (0 << 3), 420 NVME_FWACT_REPL_ACTV = (1 << 3), 421 NVME_FWACT_ACTV = (2 << 3), 422 }; 423 424 struct nvme_identify { 425 __u8 opcode; 426 __u8 flags; 427 __u16 command_id; 428 __le32 nsid; 429 __u64 rsvd2[2]; 430 __le64 prp1; 431 __le64 prp2; 432 __le32 cns; 433 __u32 rsvd11[5]; 434 }; 435 436 struct nvme_features { 437 __u8 opcode; 438 __u8 flags; 439 __u16 command_id; 440 __le32 nsid; 441 __u64 rsvd2[2]; 442 __le64 prp1; 443 __le64 prp2; 444 __le32 fid; 445 __le32 dword11; 446 __u32 rsvd12[4]; 447 }; 448 449 struct nvme_create_cq { 450 __u8 opcode; 451 __u8 flags; 452 __u16 command_id; 453 __u32 rsvd1[5]; 454 __le64 prp1; 455 __u64 rsvd8; 456 __le16 cqid; 457 __le16 qsize; 458 __le16 cq_flags; 459 __le16 irq_vector; 460 __u32 rsvd12[4]; 461 }; 462 463 struct nvme_create_sq { 464 __u8 opcode; 465 __u8 flags; 466 __u16 command_id; 467 __u32 rsvd1[5]; 468 __le64 prp1; 469 __u64 rsvd8; 470 __le16 sqid; 471 __le16 qsize; 472 __le16 sq_flags; 473 __le16 cqid; 474 __u32 rsvd12[4]; 475 }; 476 477 struct nvme_delete_queue { 478 __u8 opcode; 479 __u8 flags; 480 __u16 command_id; 481 __u32 rsvd1[9]; 482 __le16 qid; 483 __u16 rsvd10; 484 __u32 rsvd11[5]; 485 }; 486 487 struct nvme_abort_cmd { 488 __u8 opcode; 489 __u8 flags; 490 __u16 command_id; 491 __u32 rsvd1[9]; 492 __le16 sqid; 493 __u16 cid; 494 __u32 rsvd11[5]; 495 }; 496 497 struct nvme_download_firmware { 498 __u8 opcode; 499 __u8 flags; 500 __u16 command_id; 501 __u32 rsvd1[5]; 502 __le64 prp1; 503 __le64 prp2; 504 __le32 numd; 505 __le32 offset; 506 __u32 rsvd12[4]; 507 }; 508 509 struct nvme_format_cmd { 510 __u8 opcode; 511 __u8 flags; 512 __u16 command_id; 513 __le32 nsid; 514 __u64 rsvd2[4]; 515 __le32 cdw10; 516 __u32 rsvd11[5]; 517 }; 518 519 struct nvme_command { 520 union { 521 struct nvme_common_command common; 522 struct nvme_rw_command rw; 523 struct nvme_identify identify; 524 struct nvme_features features; 525 struct nvme_create_cq create_cq; 526 struct nvme_create_sq create_sq; 527 struct nvme_delete_queue delete_queue; 528 struct nvme_download_firmware dlfw; 529 struct nvme_format_cmd format; 530 struct nvme_dsm_cmd dsm; 531 struct nvme_abort_cmd abort; 532 }; 533 }; 534 535 enum { 536 NVME_SC_SUCCESS = 0x0, 537 NVME_SC_INVALID_OPCODE = 0x1, 538 NVME_SC_INVALID_FIELD = 0x2, 539 NVME_SC_CMDID_CONFLICT = 0x3, 540 NVME_SC_DATA_XFER_ERROR = 0x4, 541 NVME_SC_POWER_LOSS = 0x5, 542 NVME_SC_INTERNAL = 0x6, 543 NVME_SC_ABORT_REQ = 0x7, 544 NVME_SC_ABORT_QUEUE = 0x8, 545 NVME_SC_FUSED_FAIL = 0x9, 546 NVME_SC_FUSED_MISSING = 0xa, 547 NVME_SC_INVALID_NS = 0xb, 548 NVME_SC_CMD_SEQ_ERROR = 0xc, 549 NVME_SC_SGL_INVALID_LAST = 0xd, 550 NVME_SC_SGL_INVALID_COUNT = 0xe, 551 NVME_SC_SGL_INVALID_DATA = 0xf, 552 NVME_SC_SGL_INVALID_METADATA = 0x10, 553 NVME_SC_SGL_INVALID_TYPE = 0x11, 554 NVME_SC_LBA_RANGE = 0x80, 555 NVME_SC_CAP_EXCEEDED = 0x81, 556 NVME_SC_NS_NOT_READY = 0x82, 557 NVME_SC_RESERVATION_CONFLICT = 0x83, 558 NVME_SC_CQ_INVALID = 0x100, 559 NVME_SC_QID_INVALID = 0x101, 560 NVME_SC_QUEUE_SIZE = 0x102, 561 NVME_SC_ABORT_LIMIT = 0x103, 562 NVME_SC_ABORT_MISSING = 0x104, 563 NVME_SC_ASYNC_LIMIT = 0x105, 564 NVME_SC_FIRMWARE_SLOT = 0x106, 565 NVME_SC_FIRMWARE_IMAGE = 0x107, 566 NVME_SC_INVALID_VECTOR = 0x108, 567 NVME_SC_INVALID_LOG_PAGE = 0x109, 568 NVME_SC_INVALID_FORMAT = 0x10a, 569 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 570 NVME_SC_INVALID_QUEUE = 0x10c, 571 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 572 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 573 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 574 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 575 NVME_SC_BAD_ATTRIBUTES = 0x180, 576 NVME_SC_INVALID_PI = 0x181, 577 NVME_SC_READ_ONLY = 0x182, 578 NVME_SC_WRITE_FAULT = 0x280, 579 NVME_SC_READ_ERROR = 0x281, 580 NVME_SC_GUARD_CHECK = 0x282, 581 NVME_SC_APPTAG_CHECK = 0x283, 582 NVME_SC_REFTAG_CHECK = 0x284, 583 NVME_SC_COMPARE_FAILED = 0x285, 584 NVME_SC_ACCESS_DENIED = 0x286, 585 NVME_SC_DNR = 0x4000, 586 }; 587 588 struct nvme_completion { 589 __le32 result; /* Used by admin commands to return data */ 590 __u32 rsvd; 591 __le16 sq_head; /* how much of this queue may be reclaimed */ 592 __le16 sq_id; /* submission queue that generated this entry */ 593 __u16 command_id; /* of the command which completed */ 594 __le16 status; /* did the command fail, and if so, why? */ 595 }; 596 597 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 598 599 #endif /* _LINUX_NVME_H */ 600