1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/types.h> 11 #include <linux/uuid.h> 12 13 /* NQN names in commands fields specified one size */ 14 #define NVMF_NQN_FIELD_LEN 256 15 16 /* However the max length of a qualified name is another size */ 17 #define NVMF_NQN_SIZE 223 18 19 #define NVMF_TRSVCID_SIZE 32 20 #define NVMF_TRADDR_SIZE 256 21 #define NVMF_TSAS_SIZE 256 22 23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 24 25 #define NVME_RDMA_IP_PORT 4420 26 27 #define NVME_NSID_ALL 0xffffffff 28 29 enum nvme_subsys_type { 30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 31 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 32 }; 33 34 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 35 enum { 36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 41 }; 42 43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 44 enum { 45 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 46 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 47 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 48 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 49 NVMF_TRTYPE_MAX, 50 }; 51 52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 53 enum { 54 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 55 NVMF_TREQ_REQUIRED = 1, /* Required */ 56 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 57 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 59 60 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 61 }; 62 63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 64 * RDMA_QPTYPE field 65 */ 66 enum { 67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 69 }; 70 71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 72 * RDMA_QPTYPE field 73 */ 74 enum { 75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 80 }; 81 82 /* RDMA Connection Management Service Type codes for Discovery Log Page 83 * entry TSAS RDMA_CMS field 84 */ 85 enum { 86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 87 }; 88 89 #define NVME_AQ_DEPTH 32 90 #define NVME_NR_AEN_COMMANDS 1 91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 92 93 /* 94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 95 * NVM-Express 1.2 specification, section 4.1.2. 96 */ 97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 98 99 enum { 100 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 101 NVME_REG_VS = 0x0008, /* Version */ 102 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 103 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 104 NVME_REG_CC = 0x0014, /* Controller Configuration */ 105 NVME_REG_CSTS = 0x001c, /* Controller Status */ 106 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 107 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 108 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 109 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 110 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 111 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 112 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 113 }; 114 115 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 116 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 117 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 118 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 119 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 120 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 121 122 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 123 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 124 125 enum { 126 NVME_CMBSZ_SQS = 1 << 0, 127 NVME_CMBSZ_CQS = 1 << 1, 128 NVME_CMBSZ_LISTS = 1 << 2, 129 NVME_CMBSZ_RDS = 1 << 3, 130 NVME_CMBSZ_WDS = 1 << 4, 131 132 NVME_CMBSZ_SZ_SHIFT = 12, 133 NVME_CMBSZ_SZ_MASK = 0xfffff, 134 135 NVME_CMBSZ_SZU_SHIFT = 8, 136 NVME_CMBSZ_SZU_MASK = 0xf, 137 }; 138 139 /* 140 * Submission and Completion Queue Entry Sizes for the NVM command set. 141 * (In bytes and specified as a power of two (2^n)). 142 */ 143 #define NVME_NVM_IOSQES 6 144 #define NVME_NVM_IOCQES 4 145 146 enum { 147 NVME_CC_ENABLE = 1 << 0, 148 NVME_CC_CSS_NVM = 0 << 4, 149 NVME_CC_EN_SHIFT = 0, 150 NVME_CC_CSS_SHIFT = 4, 151 NVME_CC_MPS_SHIFT = 7, 152 NVME_CC_AMS_SHIFT = 11, 153 NVME_CC_SHN_SHIFT = 14, 154 NVME_CC_IOSQES_SHIFT = 16, 155 NVME_CC_IOCQES_SHIFT = 20, 156 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 157 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 158 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 159 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 160 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 161 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 162 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 163 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 164 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 165 NVME_CSTS_RDY = 1 << 0, 166 NVME_CSTS_CFS = 1 << 1, 167 NVME_CSTS_NSSRO = 1 << 4, 168 NVME_CSTS_PP = 1 << 5, 169 NVME_CSTS_SHST_NORMAL = 0 << 2, 170 NVME_CSTS_SHST_OCCUR = 1 << 2, 171 NVME_CSTS_SHST_CMPLT = 2 << 2, 172 NVME_CSTS_SHST_MASK = 3 << 2, 173 }; 174 175 struct nvme_id_power_state { 176 __le16 max_power; /* centiwatts */ 177 __u8 rsvd2; 178 __u8 flags; 179 __le32 entry_lat; /* microseconds */ 180 __le32 exit_lat; /* microseconds */ 181 __u8 read_tput; 182 __u8 read_lat; 183 __u8 write_tput; 184 __u8 write_lat; 185 __le16 idle_power; 186 __u8 idle_scale; 187 __u8 rsvd19; 188 __le16 active_power; 189 __u8 active_work_scale; 190 __u8 rsvd23[9]; 191 }; 192 193 enum { 194 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 195 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 196 }; 197 198 enum nvme_ctrl_attr { 199 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 200 NVME_CTRL_ATTR_TBKAS = (1 << 6), 201 }; 202 203 struct nvme_id_ctrl { 204 __le16 vid; 205 __le16 ssvid; 206 char sn[20]; 207 char mn[40]; 208 char fr[8]; 209 __u8 rab; 210 __u8 ieee[3]; 211 __u8 cmic; 212 __u8 mdts; 213 __le16 cntlid; 214 __le32 ver; 215 __le32 rtd3r; 216 __le32 rtd3e; 217 __le32 oaes; 218 __le32 ctratt; 219 __u8 rsvd100[28]; 220 __le16 crdt1; 221 __le16 crdt2; 222 __le16 crdt3; 223 __u8 rsvd134[122]; 224 __le16 oacs; 225 __u8 acl; 226 __u8 aerl; 227 __u8 frmw; 228 __u8 lpa; 229 __u8 elpe; 230 __u8 npss; 231 __u8 avscc; 232 __u8 apsta; 233 __le16 wctemp; 234 __le16 cctemp; 235 __le16 mtfa; 236 __le32 hmpre; 237 __le32 hmmin; 238 __u8 tnvmcap[16]; 239 __u8 unvmcap[16]; 240 __le32 rpmbs; 241 __le16 edstt; 242 __u8 dsto; 243 __u8 fwug; 244 __le16 kas; 245 __le16 hctma; 246 __le16 mntmt; 247 __le16 mxtmt; 248 __le32 sanicap; 249 __le32 hmminds; 250 __le16 hmmaxd; 251 __u8 rsvd338[4]; 252 __u8 anatt; 253 __u8 anacap; 254 __le32 anagrpmax; 255 __le32 nanagrpid; 256 __u8 rsvd352[160]; 257 __u8 sqes; 258 __u8 cqes; 259 __le16 maxcmd; 260 __le32 nn; 261 __le16 oncs; 262 __le16 fuses; 263 __u8 fna; 264 __u8 vwc; 265 __le16 awun; 266 __le16 awupf; 267 __u8 nvscc; 268 __u8 nwpc; 269 __le16 acwu; 270 __u8 rsvd534[2]; 271 __le32 sgls; 272 __le32 mnan; 273 __u8 rsvd544[224]; 274 char subnqn[256]; 275 __u8 rsvd1024[768]; 276 __le32 ioccsz; 277 __le32 iorcsz; 278 __le16 icdoff; 279 __u8 ctrattr; 280 __u8 msdbd; 281 __u8 rsvd1804[244]; 282 struct nvme_id_power_state psd[32]; 283 __u8 vs[1024]; 284 }; 285 286 enum { 287 NVME_CTRL_ONCS_COMPARE = 1 << 0, 288 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 289 NVME_CTRL_ONCS_DSM = 1 << 2, 290 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 291 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 292 NVME_CTRL_VWC_PRESENT = 1 << 0, 293 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 294 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 295 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 296 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 297 }; 298 299 struct nvme_lbaf { 300 __le16 ms; 301 __u8 ds; 302 __u8 rp; 303 }; 304 305 struct nvme_id_ns { 306 __le64 nsze; 307 __le64 ncap; 308 __le64 nuse; 309 __u8 nsfeat; 310 __u8 nlbaf; 311 __u8 flbas; 312 __u8 mc; 313 __u8 dpc; 314 __u8 dps; 315 __u8 nmic; 316 __u8 rescap; 317 __u8 fpi; 318 __u8 dlfeat; 319 __le16 nawun; 320 __le16 nawupf; 321 __le16 nacwu; 322 __le16 nabsn; 323 __le16 nabo; 324 __le16 nabspf; 325 __le16 noiob; 326 __u8 nvmcap[16]; 327 __le16 npwg; 328 __le16 npwa; 329 __le16 npdg; 330 __le16 npda; 331 __le16 nows; 332 __u8 rsvd74[18]; 333 __le32 anagrpid; 334 __u8 rsvd96[3]; 335 __u8 nsattr; 336 __le16 nvmsetid; 337 __le16 endgid; 338 __u8 nguid[16]; 339 __u8 eui64[8]; 340 struct nvme_lbaf lbaf[16]; 341 __u8 rsvd192[192]; 342 __u8 vs[3712]; 343 }; 344 345 enum { 346 NVME_ID_CNS_NS = 0x00, 347 NVME_ID_CNS_CTRL = 0x01, 348 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 349 NVME_ID_CNS_NS_DESC_LIST = 0x03, 350 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 351 NVME_ID_CNS_NS_PRESENT = 0x11, 352 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 353 NVME_ID_CNS_CTRL_LIST = 0x13, 354 }; 355 356 enum { 357 NVME_DIR_IDENTIFY = 0x00, 358 NVME_DIR_STREAMS = 0x01, 359 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 360 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 361 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 362 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 363 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 364 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 365 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 366 NVME_DIR_ENDIR = 0x01, 367 }; 368 369 enum { 370 NVME_NS_FEAT_THIN = 1 << 0, 371 NVME_NS_FLBAS_LBA_MASK = 0xf, 372 NVME_NS_FLBAS_META_EXT = 0x10, 373 NVME_LBAF_RP_BEST = 0, 374 NVME_LBAF_RP_BETTER = 1, 375 NVME_LBAF_RP_GOOD = 2, 376 NVME_LBAF_RP_DEGRADED = 3, 377 NVME_NS_DPC_PI_LAST = 1 << 4, 378 NVME_NS_DPC_PI_FIRST = 1 << 3, 379 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 380 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 381 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 382 NVME_NS_DPS_PI_FIRST = 1 << 3, 383 NVME_NS_DPS_PI_MASK = 0x7, 384 NVME_NS_DPS_PI_TYPE1 = 1, 385 NVME_NS_DPS_PI_TYPE2 = 2, 386 NVME_NS_DPS_PI_TYPE3 = 3, 387 }; 388 389 struct nvme_ns_id_desc { 390 __u8 nidt; 391 __u8 nidl; 392 __le16 reserved; 393 }; 394 395 #define NVME_NIDT_EUI64_LEN 8 396 #define NVME_NIDT_NGUID_LEN 16 397 #define NVME_NIDT_UUID_LEN 16 398 399 enum { 400 NVME_NIDT_EUI64 = 0x01, 401 NVME_NIDT_NGUID = 0x02, 402 NVME_NIDT_UUID = 0x03, 403 }; 404 405 struct nvme_smart_log { 406 __u8 critical_warning; 407 __u8 temperature[2]; 408 __u8 avail_spare; 409 __u8 spare_thresh; 410 __u8 percent_used; 411 __u8 rsvd6[26]; 412 __u8 data_units_read[16]; 413 __u8 data_units_written[16]; 414 __u8 host_reads[16]; 415 __u8 host_writes[16]; 416 __u8 ctrl_busy_time[16]; 417 __u8 power_cycles[16]; 418 __u8 power_on_hours[16]; 419 __u8 unsafe_shutdowns[16]; 420 __u8 media_errors[16]; 421 __u8 num_err_log_entries[16]; 422 __le32 warning_temp_time; 423 __le32 critical_comp_time; 424 __le16 temp_sensor[8]; 425 __u8 rsvd216[296]; 426 }; 427 428 struct nvme_fw_slot_info_log { 429 __u8 afi; 430 __u8 rsvd1[7]; 431 __le64 frs[7]; 432 __u8 rsvd64[448]; 433 }; 434 435 enum { 436 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 437 NVME_CMD_EFFECTS_LBCC = 1 << 1, 438 NVME_CMD_EFFECTS_NCC = 1 << 2, 439 NVME_CMD_EFFECTS_NIC = 1 << 3, 440 NVME_CMD_EFFECTS_CCC = 1 << 4, 441 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, 442 }; 443 444 struct nvme_effects_log { 445 __le32 acs[256]; 446 __le32 iocs[256]; 447 __u8 resv[2048]; 448 }; 449 450 enum nvme_ana_state { 451 NVME_ANA_OPTIMIZED = 0x01, 452 NVME_ANA_NONOPTIMIZED = 0x02, 453 NVME_ANA_INACCESSIBLE = 0x03, 454 NVME_ANA_PERSISTENT_LOSS = 0x04, 455 NVME_ANA_CHANGE = 0x0f, 456 }; 457 458 struct nvme_ana_group_desc { 459 __le32 grpid; 460 __le32 nnsids; 461 __le64 chgcnt; 462 __u8 state; 463 __u8 rsvd17[15]; 464 __le32 nsids[]; 465 }; 466 467 /* flag for the log specific field of the ANA log */ 468 #define NVME_ANA_LOG_RGO (1 << 0) 469 470 struct nvme_ana_rsp_hdr { 471 __le64 chgcnt; 472 __le16 ngrps; 473 __le16 rsvd10[3]; 474 }; 475 476 enum { 477 NVME_SMART_CRIT_SPARE = 1 << 0, 478 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 479 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 480 NVME_SMART_CRIT_MEDIA = 1 << 3, 481 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 482 }; 483 484 enum { 485 NVME_AER_ERROR = 0, 486 NVME_AER_SMART = 1, 487 NVME_AER_NOTICE = 2, 488 NVME_AER_CSS = 6, 489 NVME_AER_VS = 7, 490 }; 491 492 enum { 493 NVME_AER_NOTICE_NS_CHANGED = 0x00, 494 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 495 NVME_AER_NOTICE_ANA = 0x03, 496 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 497 }; 498 499 enum { 500 NVME_AEN_BIT_NS_ATTR = 8, 501 NVME_AEN_BIT_FW_ACT = 9, 502 NVME_AEN_BIT_ANA_CHANGE = 11, 503 NVME_AEN_BIT_DISC_CHANGE = 31, 504 }; 505 506 enum { 507 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 508 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 509 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 510 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 511 }; 512 513 struct nvme_lba_range_type { 514 __u8 type; 515 __u8 attributes; 516 __u8 rsvd2[14]; 517 __u64 slba; 518 __u64 nlb; 519 __u8 guid[16]; 520 __u8 rsvd48[16]; 521 }; 522 523 enum { 524 NVME_LBART_TYPE_FS = 0x01, 525 NVME_LBART_TYPE_RAID = 0x02, 526 NVME_LBART_TYPE_CACHE = 0x03, 527 NVME_LBART_TYPE_SWAP = 0x04, 528 529 NVME_LBART_ATTRIB_TEMP = 1 << 0, 530 NVME_LBART_ATTRIB_HIDE = 1 << 1, 531 }; 532 533 struct nvme_reservation_status { 534 __le32 gen; 535 __u8 rtype; 536 __u8 regctl[2]; 537 __u8 resv5[2]; 538 __u8 ptpls; 539 __u8 resv10[13]; 540 struct { 541 __le16 cntlid; 542 __u8 rcsts; 543 __u8 resv3[5]; 544 __le64 hostid; 545 __le64 rkey; 546 } regctl_ds[]; 547 }; 548 549 enum nvme_async_event_type { 550 NVME_AER_TYPE_ERROR = 0, 551 NVME_AER_TYPE_SMART = 1, 552 NVME_AER_TYPE_NOTICE = 2, 553 }; 554 555 /* I/O commands */ 556 557 enum nvme_opcode { 558 nvme_cmd_flush = 0x00, 559 nvme_cmd_write = 0x01, 560 nvme_cmd_read = 0x02, 561 nvme_cmd_write_uncor = 0x04, 562 nvme_cmd_compare = 0x05, 563 nvme_cmd_write_zeroes = 0x08, 564 nvme_cmd_dsm = 0x09, 565 nvme_cmd_resv_register = 0x0d, 566 nvme_cmd_resv_report = 0x0e, 567 nvme_cmd_resv_acquire = 0x11, 568 nvme_cmd_resv_release = 0x15, 569 }; 570 571 #define nvme_opcode_name(opcode) { opcode, #opcode } 572 #define show_nvm_opcode_name(val) \ 573 __print_symbolic(val, \ 574 nvme_opcode_name(nvme_cmd_flush), \ 575 nvme_opcode_name(nvme_cmd_write), \ 576 nvme_opcode_name(nvme_cmd_read), \ 577 nvme_opcode_name(nvme_cmd_write_uncor), \ 578 nvme_opcode_name(nvme_cmd_compare), \ 579 nvme_opcode_name(nvme_cmd_write_zeroes), \ 580 nvme_opcode_name(nvme_cmd_dsm), \ 581 nvme_opcode_name(nvme_cmd_resv_register), \ 582 nvme_opcode_name(nvme_cmd_resv_report), \ 583 nvme_opcode_name(nvme_cmd_resv_acquire), \ 584 nvme_opcode_name(nvme_cmd_resv_release)) 585 586 587 /* 588 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 589 * 590 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 591 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 592 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 593 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 594 * request subtype 595 */ 596 enum { 597 NVME_SGL_FMT_ADDRESS = 0x00, 598 NVME_SGL_FMT_OFFSET = 0x01, 599 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 600 NVME_SGL_FMT_INVALIDATE = 0x0f, 601 }; 602 603 /* 604 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 605 * 606 * For struct nvme_sgl_desc: 607 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 608 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 609 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 610 * 611 * For struct nvme_keyed_sgl_desc: 612 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 613 * 614 * Transport-specific SGL types: 615 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 616 */ 617 enum { 618 NVME_SGL_FMT_DATA_DESC = 0x00, 619 NVME_SGL_FMT_SEG_DESC = 0x02, 620 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 621 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 622 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 623 }; 624 625 struct nvme_sgl_desc { 626 __le64 addr; 627 __le32 length; 628 __u8 rsvd[3]; 629 __u8 type; 630 }; 631 632 struct nvme_keyed_sgl_desc { 633 __le64 addr; 634 __u8 length[3]; 635 __u8 key[4]; 636 __u8 type; 637 }; 638 639 union nvme_data_ptr { 640 struct { 641 __le64 prp1; 642 __le64 prp2; 643 }; 644 struct nvme_sgl_desc sgl; 645 struct nvme_keyed_sgl_desc ksgl; 646 }; 647 648 /* 649 * Lowest two bits of our flags field (FUSE field in the spec): 650 * 651 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 652 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 653 * 654 * Highest two bits in our flags field (PSDT field in the spec): 655 * 656 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 657 * If used, MPTR contains addr of single physical buffer (byte aligned). 658 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 659 * If used, MPTR contains an address of an SGL segment containing 660 * exactly 1 SGL descriptor (qword aligned). 661 */ 662 enum { 663 NVME_CMD_FUSE_FIRST = (1 << 0), 664 NVME_CMD_FUSE_SECOND = (1 << 1), 665 666 NVME_CMD_SGL_METABUF = (1 << 6), 667 NVME_CMD_SGL_METASEG = (1 << 7), 668 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 669 }; 670 671 struct nvme_common_command { 672 __u8 opcode; 673 __u8 flags; 674 __u16 command_id; 675 __le32 nsid; 676 __le32 cdw2[2]; 677 __le64 metadata; 678 union nvme_data_ptr dptr; 679 __le32 cdw10; 680 __le32 cdw11; 681 __le32 cdw12; 682 __le32 cdw13; 683 __le32 cdw14; 684 __le32 cdw15; 685 }; 686 687 struct nvme_rw_command { 688 __u8 opcode; 689 __u8 flags; 690 __u16 command_id; 691 __le32 nsid; 692 __u64 rsvd2; 693 __le64 metadata; 694 union nvme_data_ptr dptr; 695 __le64 slba; 696 __le16 length; 697 __le16 control; 698 __le32 dsmgmt; 699 __le32 reftag; 700 __le16 apptag; 701 __le16 appmask; 702 }; 703 704 enum { 705 NVME_RW_LR = 1 << 15, 706 NVME_RW_FUA = 1 << 14, 707 NVME_RW_DSM_FREQ_UNSPEC = 0, 708 NVME_RW_DSM_FREQ_TYPICAL = 1, 709 NVME_RW_DSM_FREQ_RARE = 2, 710 NVME_RW_DSM_FREQ_READS = 3, 711 NVME_RW_DSM_FREQ_WRITES = 4, 712 NVME_RW_DSM_FREQ_RW = 5, 713 NVME_RW_DSM_FREQ_ONCE = 6, 714 NVME_RW_DSM_FREQ_PREFETCH = 7, 715 NVME_RW_DSM_FREQ_TEMP = 8, 716 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 717 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 718 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 719 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 720 NVME_RW_DSM_SEQ_REQ = 1 << 6, 721 NVME_RW_DSM_COMPRESSED = 1 << 7, 722 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 723 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 724 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 725 NVME_RW_PRINFO_PRACT = 1 << 13, 726 NVME_RW_DTYPE_STREAMS = 1 << 4, 727 }; 728 729 struct nvme_dsm_cmd { 730 __u8 opcode; 731 __u8 flags; 732 __u16 command_id; 733 __le32 nsid; 734 __u64 rsvd2[2]; 735 union nvme_data_ptr dptr; 736 __le32 nr; 737 __le32 attributes; 738 __u32 rsvd12[4]; 739 }; 740 741 enum { 742 NVME_DSMGMT_IDR = 1 << 0, 743 NVME_DSMGMT_IDW = 1 << 1, 744 NVME_DSMGMT_AD = 1 << 2, 745 }; 746 747 #define NVME_DSM_MAX_RANGES 256 748 749 struct nvme_dsm_range { 750 __le32 cattr; 751 __le32 nlb; 752 __le64 slba; 753 }; 754 755 struct nvme_write_zeroes_cmd { 756 __u8 opcode; 757 __u8 flags; 758 __u16 command_id; 759 __le32 nsid; 760 __u64 rsvd2; 761 __le64 metadata; 762 union nvme_data_ptr dptr; 763 __le64 slba; 764 __le16 length; 765 __le16 control; 766 __le32 dsmgmt; 767 __le32 reftag; 768 __le16 apptag; 769 __le16 appmask; 770 }; 771 772 /* Features */ 773 774 struct nvme_feat_auto_pst { 775 __le64 entries[32]; 776 }; 777 778 enum { 779 NVME_HOST_MEM_ENABLE = (1 << 0), 780 NVME_HOST_MEM_RETURN = (1 << 1), 781 }; 782 783 struct nvme_feat_host_behavior { 784 __u8 acre; 785 __u8 resv1[511]; 786 }; 787 788 enum { 789 NVME_ENABLE_ACRE = 1, 790 }; 791 792 /* Admin commands */ 793 794 enum nvme_admin_opcode { 795 nvme_admin_delete_sq = 0x00, 796 nvme_admin_create_sq = 0x01, 797 nvme_admin_get_log_page = 0x02, 798 nvme_admin_delete_cq = 0x04, 799 nvme_admin_create_cq = 0x05, 800 nvme_admin_identify = 0x06, 801 nvme_admin_abort_cmd = 0x08, 802 nvme_admin_set_features = 0x09, 803 nvme_admin_get_features = 0x0a, 804 nvme_admin_async_event = 0x0c, 805 nvme_admin_ns_mgmt = 0x0d, 806 nvme_admin_activate_fw = 0x10, 807 nvme_admin_download_fw = 0x11, 808 nvme_admin_ns_attach = 0x15, 809 nvme_admin_keep_alive = 0x18, 810 nvme_admin_directive_send = 0x19, 811 nvme_admin_directive_recv = 0x1a, 812 nvme_admin_dbbuf = 0x7C, 813 nvme_admin_format_nvm = 0x80, 814 nvme_admin_security_send = 0x81, 815 nvme_admin_security_recv = 0x82, 816 nvme_admin_sanitize_nvm = 0x84, 817 }; 818 819 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 820 #define show_admin_opcode_name(val) \ 821 __print_symbolic(val, \ 822 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 823 nvme_admin_opcode_name(nvme_admin_create_sq), \ 824 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 825 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 826 nvme_admin_opcode_name(nvme_admin_create_cq), \ 827 nvme_admin_opcode_name(nvme_admin_identify), \ 828 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 829 nvme_admin_opcode_name(nvme_admin_set_features), \ 830 nvme_admin_opcode_name(nvme_admin_get_features), \ 831 nvme_admin_opcode_name(nvme_admin_async_event), \ 832 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 833 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 834 nvme_admin_opcode_name(nvme_admin_download_fw), \ 835 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 836 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 837 nvme_admin_opcode_name(nvme_admin_directive_send), \ 838 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 839 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 840 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 841 nvme_admin_opcode_name(nvme_admin_security_send), \ 842 nvme_admin_opcode_name(nvme_admin_security_recv), \ 843 nvme_admin_opcode_name(nvme_admin_sanitize_nvm)) 844 845 enum { 846 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 847 NVME_CQ_IRQ_ENABLED = (1 << 1), 848 NVME_SQ_PRIO_URGENT = (0 << 1), 849 NVME_SQ_PRIO_HIGH = (1 << 1), 850 NVME_SQ_PRIO_MEDIUM = (2 << 1), 851 NVME_SQ_PRIO_LOW = (3 << 1), 852 NVME_FEAT_ARBITRATION = 0x01, 853 NVME_FEAT_POWER_MGMT = 0x02, 854 NVME_FEAT_LBA_RANGE = 0x03, 855 NVME_FEAT_TEMP_THRESH = 0x04, 856 NVME_FEAT_ERR_RECOVERY = 0x05, 857 NVME_FEAT_VOLATILE_WC = 0x06, 858 NVME_FEAT_NUM_QUEUES = 0x07, 859 NVME_FEAT_IRQ_COALESCE = 0x08, 860 NVME_FEAT_IRQ_CONFIG = 0x09, 861 NVME_FEAT_WRITE_ATOMIC = 0x0a, 862 NVME_FEAT_ASYNC_EVENT = 0x0b, 863 NVME_FEAT_AUTO_PST = 0x0c, 864 NVME_FEAT_HOST_MEM_BUF = 0x0d, 865 NVME_FEAT_TIMESTAMP = 0x0e, 866 NVME_FEAT_KATO = 0x0f, 867 NVME_FEAT_HCTM = 0x10, 868 NVME_FEAT_NOPSC = 0x11, 869 NVME_FEAT_RRL = 0x12, 870 NVME_FEAT_PLM_CONFIG = 0x13, 871 NVME_FEAT_PLM_WINDOW = 0x14, 872 NVME_FEAT_HOST_BEHAVIOR = 0x16, 873 NVME_FEAT_SW_PROGRESS = 0x80, 874 NVME_FEAT_HOST_ID = 0x81, 875 NVME_FEAT_RESV_MASK = 0x82, 876 NVME_FEAT_RESV_PERSIST = 0x83, 877 NVME_FEAT_WRITE_PROTECT = 0x84, 878 NVME_LOG_ERROR = 0x01, 879 NVME_LOG_SMART = 0x02, 880 NVME_LOG_FW_SLOT = 0x03, 881 NVME_LOG_CHANGED_NS = 0x04, 882 NVME_LOG_CMD_EFFECTS = 0x05, 883 NVME_LOG_ANA = 0x0c, 884 NVME_LOG_DISC = 0x70, 885 NVME_LOG_RESERVATION = 0x80, 886 NVME_FWACT_REPL = (0 << 3), 887 NVME_FWACT_REPL_ACTV = (1 << 3), 888 NVME_FWACT_ACTV = (2 << 3), 889 }; 890 891 /* NVMe Namespace Write Protect State */ 892 enum { 893 NVME_NS_NO_WRITE_PROTECT = 0, 894 NVME_NS_WRITE_PROTECT, 895 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 896 NVME_NS_WRITE_PROTECT_PERMANENT, 897 }; 898 899 #define NVME_MAX_CHANGED_NAMESPACES 1024 900 901 struct nvme_identify { 902 __u8 opcode; 903 __u8 flags; 904 __u16 command_id; 905 __le32 nsid; 906 __u64 rsvd2[2]; 907 union nvme_data_ptr dptr; 908 __u8 cns; 909 __u8 rsvd3; 910 __le16 ctrlid; 911 __u32 rsvd11[5]; 912 }; 913 914 #define NVME_IDENTIFY_DATA_SIZE 4096 915 916 struct nvme_features { 917 __u8 opcode; 918 __u8 flags; 919 __u16 command_id; 920 __le32 nsid; 921 __u64 rsvd2[2]; 922 union nvme_data_ptr dptr; 923 __le32 fid; 924 __le32 dword11; 925 __le32 dword12; 926 __le32 dword13; 927 __le32 dword14; 928 __le32 dword15; 929 }; 930 931 struct nvme_host_mem_buf_desc { 932 __le64 addr; 933 __le32 size; 934 __u32 rsvd; 935 }; 936 937 struct nvme_create_cq { 938 __u8 opcode; 939 __u8 flags; 940 __u16 command_id; 941 __u32 rsvd1[5]; 942 __le64 prp1; 943 __u64 rsvd8; 944 __le16 cqid; 945 __le16 qsize; 946 __le16 cq_flags; 947 __le16 irq_vector; 948 __u32 rsvd12[4]; 949 }; 950 951 struct nvme_create_sq { 952 __u8 opcode; 953 __u8 flags; 954 __u16 command_id; 955 __u32 rsvd1[5]; 956 __le64 prp1; 957 __u64 rsvd8; 958 __le16 sqid; 959 __le16 qsize; 960 __le16 sq_flags; 961 __le16 cqid; 962 __u32 rsvd12[4]; 963 }; 964 965 struct nvme_delete_queue { 966 __u8 opcode; 967 __u8 flags; 968 __u16 command_id; 969 __u32 rsvd1[9]; 970 __le16 qid; 971 __u16 rsvd10; 972 __u32 rsvd11[5]; 973 }; 974 975 struct nvme_abort_cmd { 976 __u8 opcode; 977 __u8 flags; 978 __u16 command_id; 979 __u32 rsvd1[9]; 980 __le16 sqid; 981 __u16 cid; 982 __u32 rsvd11[5]; 983 }; 984 985 struct nvme_download_firmware { 986 __u8 opcode; 987 __u8 flags; 988 __u16 command_id; 989 __u32 rsvd1[5]; 990 union nvme_data_ptr dptr; 991 __le32 numd; 992 __le32 offset; 993 __u32 rsvd12[4]; 994 }; 995 996 struct nvme_format_cmd { 997 __u8 opcode; 998 __u8 flags; 999 __u16 command_id; 1000 __le32 nsid; 1001 __u64 rsvd2[4]; 1002 __le32 cdw10; 1003 __u32 rsvd11[5]; 1004 }; 1005 1006 struct nvme_get_log_page_command { 1007 __u8 opcode; 1008 __u8 flags; 1009 __u16 command_id; 1010 __le32 nsid; 1011 __u64 rsvd2[2]; 1012 union nvme_data_ptr dptr; 1013 __u8 lid; 1014 __u8 lsp; /* upper 4 bits reserved */ 1015 __le16 numdl; 1016 __le16 numdu; 1017 __u16 rsvd11; 1018 union { 1019 struct { 1020 __le32 lpol; 1021 __le32 lpou; 1022 }; 1023 __le64 lpo; 1024 }; 1025 __u32 rsvd14[2]; 1026 }; 1027 1028 struct nvme_directive_cmd { 1029 __u8 opcode; 1030 __u8 flags; 1031 __u16 command_id; 1032 __le32 nsid; 1033 __u64 rsvd2[2]; 1034 union nvme_data_ptr dptr; 1035 __le32 numd; 1036 __u8 doper; 1037 __u8 dtype; 1038 __le16 dspec; 1039 __u8 endir; 1040 __u8 tdtype; 1041 __u16 rsvd15; 1042 1043 __u32 rsvd16[3]; 1044 }; 1045 1046 /* 1047 * Fabrics subcommands. 1048 */ 1049 enum nvmf_fabrics_opcode { 1050 nvme_fabrics_command = 0x7f, 1051 }; 1052 1053 enum nvmf_capsule_command { 1054 nvme_fabrics_type_property_set = 0x00, 1055 nvme_fabrics_type_connect = 0x01, 1056 nvme_fabrics_type_property_get = 0x04, 1057 }; 1058 1059 #define nvme_fabrics_type_name(type) { type, #type } 1060 #define show_fabrics_type_name(type) \ 1061 __print_symbolic(type, \ 1062 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1063 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1064 nvme_fabrics_type_name(nvme_fabrics_type_property_get)) 1065 1066 /* 1067 * If not fabrics command, fctype will be ignored. 1068 */ 1069 #define show_opcode_name(qid, opcode, fctype) \ 1070 ((opcode) == nvme_fabrics_command ? \ 1071 show_fabrics_type_name(fctype) : \ 1072 ((qid) ? \ 1073 show_nvm_opcode_name(opcode) : \ 1074 show_admin_opcode_name(opcode))) 1075 1076 struct nvmf_common_command { 1077 __u8 opcode; 1078 __u8 resv1; 1079 __u16 command_id; 1080 __u8 fctype; 1081 __u8 resv2[35]; 1082 __u8 ts[24]; 1083 }; 1084 1085 /* 1086 * The legal cntlid range a NVMe Target will provide. 1087 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1088 * Devices based on earlier specs did not have the subsystem concept; 1089 * therefore, those devices had their cntlid value set to 0 as a result. 1090 */ 1091 #define NVME_CNTLID_MIN 1 1092 #define NVME_CNTLID_MAX 0xffef 1093 #define NVME_CNTLID_DYNAMIC 0xffff 1094 1095 #define MAX_DISC_LOGS 255 1096 1097 /* Discovery log page entry */ 1098 struct nvmf_disc_rsp_page_entry { 1099 __u8 trtype; 1100 __u8 adrfam; 1101 __u8 subtype; 1102 __u8 treq; 1103 __le16 portid; 1104 __le16 cntlid; 1105 __le16 asqsz; 1106 __u8 resv8[22]; 1107 char trsvcid[NVMF_TRSVCID_SIZE]; 1108 __u8 resv64[192]; 1109 char subnqn[NVMF_NQN_FIELD_LEN]; 1110 char traddr[NVMF_TRADDR_SIZE]; 1111 union tsas { 1112 char common[NVMF_TSAS_SIZE]; 1113 struct rdma { 1114 __u8 qptype; 1115 __u8 prtype; 1116 __u8 cms; 1117 __u8 resv3[5]; 1118 __u16 pkey; 1119 __u8 resv10[246]; 1120 } rdma; 1121 } tsas; 1122 }; 1123 1124 /* Discovery log page header */ 1125 struct nvmf_disc_rsp_page_hdr { 1126 __le64 genctr; 1127 __le64 numrec; 1128 __le16 recfmt; 1129 __u8 resv14[1006]; 1130 struct nvmf_disc_rsp_page_entry entries[0]; 1131 }; 1132 1133 enum { 1134 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1135 }; 1136 1137 struct nvmf_connect_command { 1138 __u8 opcode; 1139 __u8 resv1; 1140 __u16 command_id; 1141 __u8 fctype; 1142 __u8 resv2[19]; 1143 union nvme_data_ptr dptr; 1144 __le16 recfmt; 1145 __le16 qid; 1146 __le16 sqsize; 1147 __u8 cattr; 1148 __u8 resv3; 1149 __le32 kato; 1150 __u8 resv4[12]; 1151 }; 1152 1153 struct nvmf_connect_data { 1154 uuid_t hostid; 1155 __le16 cntlid; 1156 char resv4[238]; 1157 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1158 char hostnqn[NVMF_NQN_FIELD_LEN]; 1159 char resv5[256]; 1160 }; 1161 1162 struct nvmf_property_set_command { 1163 __u8 opcode; 1164 __u8 resv1; 1165 __u16 command_id; 1166 __u8 fctype; 1167 __u8 resv2[35]; 1168 __u8 attrib; 1169 __u8 resv3[3]; 1170 __le32 offset; 1171 __le64 value; 1172 __u8 resv4[8]; 1173 }; 1174 1175 struct nvmf_property_get_command { 1176 __u8 opcode; 1177 __u8 resv1; 1178 __u16 command_id; 1179 __u8 fctype; 1180 __u8 resv2[35]; 1181 __u8 attrib; 1182 __u8 resv3[3]; 1183 __le32 offset; 1184 __u8 resv4[16]; 1185 }; 1186 1187 struct nvme_dbbuf { 1188 __u8 opcode; 1189 __u8 flags; 1190 __u16 command_id; 1191 __u32 rsvd1[5]; 1192 __le64 prp1; 1193 __le64 prp2; 1194 __u32 rsvd12[6]; 1195 }; 1196 1197 struct streams_directive_params { 1198 __le16 msl; 1199 __le16 nssa; 1200 __le16 nsso; 1201 __u8 rsvd[10]; 1202 __le32 sws; 1203 __le16 sgs; 1204 __le16 nsa; 1205 __le16 nso; 1206 __u8 rsvd2[6]; 1207 }; 1208 1209 struct nvme_command { 1210 union { 1211 struct nvme_common_command common; 1212 struct nvme_rw_command rw; 1213 struct nvme_identify identify; 1214 struct nvme_features features; 1215 struct nvme_create_cq create_cq; 1216 struct nvme_create_sq create_sq; 1217 struct nvme_delete_queue delete_queue; 1218 struct nvme_download_firmware dlfw; 1219 struct nvme_format_cmd format; 1220 struct nvme_dsm_cmd dsm; 1221 struct nvme_write_zeroes_cmd write_zeroes; 1222 struct nvme_abort_cmd abort; 1223 struct nvme_get_log_page_command get_log_page; 1224 struct nvmf_common_command fabrics; 1225 struct nvmf_connect_command connect; 1226 struct nvmf_property_set_command prop_set; 1227 struct nvmf_property_get_command prop_get; 1228 struct nvme_dbbuf dbbuf; 1229 struct nvme_directive_cmd directive; 1230 }; 1231 }; 1232 1233 static inline bool nvme_is_fabrics(struct nvme_command *cmd) 1234 { 1235 return cmd->common.opcode == nvme_fabrics_command; 1236 } 1237 1238 struct nvme_error_slot { 1239 __le64 error_count; 1240 __le16 sqid; 1241 __le16 cmdid; 1242 __le16 status_field; 1243 __le16 param_error_location; 1244 __le64 lba; 1245 __le32 nsid; 1246 __u8 vs; 1247 __u8 resv[3]; 1248 __le64 cs; 1249 __u8 resv2[24]; 1250 }; 1251 1252 static inline bool nvme_is_write(struct nvme_command *cmd) 1253 { 1254 /* 1255 * What a mess... 1256 * 1257 * Why can't we simply have a Fabrics In and Fabrics out command? 1258 */ 1259 if (unlikely(nvme_is_fabrics(cmd))) 1260 return cmd->fabrics.fctype & 1; 1261 return cmd->common.opcode & 1; 1262 } 1263 1264 enum { 1265 /* 1266 * Generic Command Status: 1267 */ 1268 NVME_SC_SUCCESS = 0x0, 1269 NVME_SC_INVALID_OPCODE = 0x1, 1270 NVME_SC_INVALID_FIELD = 0x2, 1271 NVME_SC_CMDID_CONFLICT = 0x3, 1272 NVME_SC_DATA_XFER_ERROR = 0x4, 1273 NVME_SC_POWER_LOSS = 0x5, 1274 NVME_SC_INTERNAL = 0x6, 1275 NVME_SC_ABORT_REQ = 0x7, 1276 NVME_SC_ABORT_QUEUE = 0x8, 1277 NVME_SC_FUSED_FAIL = 0x9, 1278 NVME_SC_FUSED_MISSING = 0xa, 1279 NVME_SC_INVALID_NS = 0xb, 1280 NVME_SC_CMD_SEQ_ERROR = 0xc, 1281 NVME_SC_SGL_INVALID_LAST = 0xd, 1282 NVME_SC_SGL_INVALID_COUNT = 0xe, 1283 NVME_SC_SGL_INVALID_DATA = 0xf, 1284 NVME_SC_SGL_INVALID_METADATA = 0x10, 1285 NVME_SC_SGL_INVALID_TYPE = 0x11, 1286 1287 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1288 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 1289 1290 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1291 1292 NVME_SC_LBA_RANGE = 0x80, 1293 NVME_SC_CAP_EXCEEDED = 0x81, 1294 NVME_SC_NS_NOT_READY = 0x82, 1295 NVME_SC_RESERVATION_CONFLICT = 0x83, 1296 1297 /* 1298 * Command Specific Status: 1299 */ 1300 NVME_SC_CQ_INVALID = 0x100, 1301 NVME_SC_QID_INVALID = 0x101, 1302 NVME_SC_QUEUE_SIZE = 0x102, 1303 NVME_SC_ABORT_LIMIT = 0x103, 1304 NVME_SC_ABORT_MISSING = 0x104, 1305 NVME_SC_ASYNC_LIMIT = 0x105, 1306 NVME_SC_FIRMWARE_SLOT = 0x106, 1307 NVME_SC_FIRMWARE_IMAGE = 0x107, 1308 NVME_SC_INVALID_VECTOR = 0x108, 1309 NVME_SC_INVALID_LOG_PAGE = 0x109, 1310 NVME_SC_INVALID_FORMAT = 0x10a, 1311 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1312 NVME_SC_INVALID_QUEUE = 0x10c, 1313 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1314 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1315 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1316 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1317 NVME_SC_FW_NEEDS_RESET = 0x111, 1318 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1319 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1320 NVME_SC_OVERLAPPING_RANGE = 0x114, 1321 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1322 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1323 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1324 NVME_SC_NS_IS_PRIVATE = 0x119, 1325 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1326 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1327 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1328 1329 /* 1330 * I/O Command Set Specific - NVM commands: 1331 */ 1332 NVME_SC_BAD_ATTRIBUTES = 0x180, 1333 NVME_SC_INVALID_PI = 0x181, 1334 NVME_SC_READ_ONLY = 0x182, 1335 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1336 1337 /* 1338 * I/O Command Set Specific - Fabrics commands: 1339 */ 1340 NVME_SC_CONNECT_FORMAT = 0x180, 1341 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1342 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1343 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1344 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1345 1346 NVME_SC_DISCOVERY_RESTART = 0x190, 1347 NVME_SC_AUTH_REQUIRED = 0x191, 1348 1349 /* 1350 * Media and Data Integrity Errors: 1351 */ 1352 NVME_SC_WRITE_FAULT = 0x280, 1353 NVME_SC_READ_ERROR = 0x281, 1354 NVME_SC_GUARD_CHECK = 0x282, 1355 NVME_SC_APPTAG_CHECK = 0x283, 1356 NVME_SC_REFTAG_CHECK = 0x284, 1357 NVME_SC_COMPARE_FAILED = 0x285, 1358 NVME_SC_ACCESS_DENIED = 0x286, 1359 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1360 1361 /* 1362 * Path-related Errors: 1363 */ 1364 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1365 NVME_SC_ANA_INACCESSIBLE = 0x302, 1366 NVME_SC_ANA_TRANSITION = 0x303, 1367 NVME_SC_HOST_PATH_ERROR = 0x370, 1368 1369 NVME_SC_CRD = 0x1800, 1370 NVME_SC_DNR = 0x4000, 1371 }; 1372 1373 struct nvme_completion { 1374 /* 1375 * Used by Admin and Fabrics commands to return data: 1376 */ 1377 union nvme_result { 1378 __le16 u16; 1379 __le32 u32; 1380 __le64 u64; 1381 } result; 1382 __le16 sq_head; /* how much of this queue may be reclaimed */ 1383 __le16 sq_id; /* submission queue that generated this entry */ 1384 __u16 command_id; /* of the command which completed */ 1385 __le16 status; /* did the command fail, and if so, why? */ 1386 }; 1387 1388 #define NVME_VS(major, minor, tertiary) \ 1389 (((major) << 16) | ((minor) << 8) | (tertiary)) 1390 1391 #define NVME_MAJOR(ver) ((ver) >> 16) 1392 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1393 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1394 1395 #endif /* _LINUX_NVME_H */ 1396