1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2013, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #ifndef _LINUX_NVME_H 20 #define _LINUX_NVME_H 21 22 #include <uapi/linux/nvme.h> 23 #include <linux/pci.h> 24 #include <linux/miscdevice.h> 25 #include <linux/kref.h> 26 27 struct nvme_bar { 28 __u64 cap; /* Controller Capabilities */ 29 __u32 vs; /* Version */ 30 __u32 intms; /* Interrupt Mask Set */ 31 __u32 intmc; /* Interrupt Mask Clear */ 32 __u32 cc; /* Controller Configuration */ 33 __u32 rsvd1; /* Reserved */ 34 __u32 csts; /* Controller Status */ 35 __u32 rsvd2; /* Reserved */ 36 __u32 aqa; /* Admin Queue Attributes */ 37 __u64 asq; /* Admin SQ Base Address */ 38 __u64 acq; /* Admin CQ Base Address */ 39 }; 40 41 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 42 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 43 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 44 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 45 46 enum { 47 NVME_CC_ENABLE = 1 << 0, 48 NVME_CC_CSS_NVM = 0 << 4, 49 NVME_CC_MPS_SHIFT = 7, 50 NVME_CC_ARB_RR = 0 << 11, 51 NVME_CC_ARB_WRRU = 1 << 11, 52 NVME_CC_ARB_VS = 7 << 11, 53 NVME_CC_SHN_NONE = 0 << 14, 54 NVME_CC_SHN_NORMAL = 1 << 14, 55 NVME_CC_SHN_ABRUPT = 2 << 14, 56 NVME_CC_SHN_MASK = 3 << 14, 57 NVME_CC_IOSQES = 6 << 16, 58 NVME_CC_IOCQES = 4 << 20, 59 NVME_CSTS_RDY = 1 << 0, 60 NVME_CSTS_CFS = 1 << 1, 61 NVME_CSTS_SHST_NORMAL = 0 << 2, 62 NVME_CSTS_SHST_OCCUR = 1 << 2, 63 NVME_CSTS_SHST_CMPLT = 2 << 2, 64 NVME_CSTS_SHST_MASK = 3 << 2, 65 }; 66 67 #define NVME_VS(major, minor) (major << 16 | minor) 68 69 #define NVME_IO_TIMEOUT (5 * HZ) 70 71 /* 72 * Represents an NVM Express device. Each nvme_dev is a PCI function. 73 */ 74 struct nvme_dev { 75 struct list_head node; 76 struct nvme_queue **queues; 77 u32 __iomem *dbs; 78 struct pci_dev *pci_dev; 79 struct dma_pool *prp_page_pool; 80 struct dma_pool *prp_small_pool; 81 int instance; 82 int queue_count; 83 u32 db_stride; 84 u32 ctrl_config; 85 struct msix_entry *entry; 86 struct nvme_bar __iomem *bar; 87 struct list_head namespaces; 88 struct kref kref; 89 struct miscdevice miscdev; 90 struct work_struct reset_work; 91 char name[12]; 92 char serial[20]; 93 char model[40]; 94 char firmware_rev[8]; 95 u32 max_hw_sectors; 96 u32 stripe_size; 97 u16 oncs; 98 u16 abort_limit; 99 u8 initialized; 100 }; 101 102 /* 103 * An NVM Express namespace is equivalent to a SCSI LUN 104 */ 105 struct nvme_ns { 106 struct list_head list; 107 108 struct nvme_dev *dev; 109 struct request_queue *queue; 110 struct gendisk *disk; 111 112 unsigned ns_id; 113 int lba_shift; 114 int ms; 115 u64 mode_select_num_blocks; 116 u32 mode_select_block_len; 117 }; 118 119 /* 120 * The nvme_iod describes the data in an I/O, including the list of PRP 121 * entries. You can't see it in this data structure because C doesn't let 122 * me express that. Use nvme_alloc_iod to ensure there's enough space 123 * allocated to store the PRP list. 124 */ 125 struct nvme_iod { 126 void *private; /* For the use of the submitter of the I/O */ 127 int npages; /* In the PRP list. 0 means small pool in use */ 128 int offset; /* Of PRP list */ 129 int nents; /* Used in scatterlist */ 130 int length; /* Of data, in bytes */ 131 unsigned long start_time; 132 dma_addr_t first_dma; 133 struct scatterlist sg[0]; 134 }; 135 136 static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) 137 { 138 return (sector >> (ns->lba_shift - 9)); 139 } 140 141 /** 142 * nvme_free_iod - frees an nvme_iod 143 * @dev: The device that the I/O was submitted to 144 * @iod: The memory to free 145 */ 146 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod); 147 148 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, 149 struct nvme_iod *iod, int total_len, gfp_t gfp); 150 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, 151 unsigned long addr, unsigned length); 152 void nvme_unmap_user_pages(struct nvme_dev *dev, int write, 153 struct nvme_iod *iod); 154 struct nvme_queue *get_nvmeq(struct nvme_dev *dev); 155 void put_nvmeq(struct nvme_queue *nvmeq); 156 int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 157 u32 *result, unsigned timeout); 158 int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns); 159 int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *, 160 u32 *result); 161 int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns, 162 dma_addr_t dma_addr); 163 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, 164 dma_addr_t dma_addr, u32 *result); 165 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, 166 dma_addr_t dma_addr, u32 *result); 167 168 struct sg_io_hdr; 169 170 int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); 171 int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); 172 int nvme_sg_get_version_num(int __user *ip); 173 174 #endif /* _LINUX_NVME_H */ 175