1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <linux/types.h> 19 20 /* NQN names in commands fields specified one size */ 21 #define NVMF_NQN_FIELD_LEN 256 22 23 /* However the max length of a qualified name is another size */ 24 #define NVMF_NQN_SIZE 223 25 26 #define NVMF_TRSVCID_SIZE 32 27 #define NVMF_TRADDR_SIZE 256 28 #define NVMF_TSAS_SIZE 256 29 30 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 31 32 #define NVME_RDMA_IP_PORT 4420 33 34 enum nvme_subsys_type { 35 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 36 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 37 }; 38 39 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 40 enum { 41 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 42 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 43 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 44 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 45 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 46 }; 47 48 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 49 enum { 50 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 51 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 52 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 53 NVMF_TRTYPE_MAX, 54 }; 55 56 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 57 enum { 58 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 59 NVMF_TREQ_REQUIRED = 1, /* Required */ 60 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 61 }; 62 63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 64 * RDMA_QPTYPE field 65 */ 66 enum { 67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 69 }; 70 71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 72 * RDMA_QPTYPE field 73 */ 74 enum { 75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 80 }; 81 82 /* RDMA Connection Management Service Type codes for Discovery Log Page 83 * entry TSAS RDMA_CMS field 84 */ 85 enum { 86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 87 }; 88 89 #define NVMF_AQ_DEPTH 32 90 91 enum { 92 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 93 NVME_REG_VS = 0x0008, /* Version */ 94 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 95 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 96 NVME_REG_CC = 0x0014, /* Controller Configuration */ 97 NVME_REG_CSTS = 0x001c, /* Controller Status */ 98 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 99 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 100 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 101 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 102 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 103 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 104 }; 105 106 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 107 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 108 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 109 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 110 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 111 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 112 113 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 114 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 115 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) 116 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) 117 118 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) 119 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) 120 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) 121 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) 122 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) 123 124 /* 125 * Submission and Completion Queue Entry Sizes for the NVM command set. 126 * (In bytes and specified as a power of two (2^n)). 127 */ 128 #define NVME_NVM_IOSQES 6 129 #define NVME_NVM_IOCQES 4 130 131 enum { 132 NVME_CC_ENABLE = 1 << 0, 133 NVME_CC_CSS_NVM = 0 << 4, 134 NVME_CC_MPS_SHIFT = 7, 135 NVME_CC_ARB_RR = 0 << 11, 136 NVME_CC_ARB_WRRU = 1 << 11, 137 NVME_CC_ARB_VS = 7 << 11, 138 NVME_CC_SHN_NONE = 0 << 14, 139 NVME_CC_SHN_NORMAL = 1 << 14, 140 NVME_CC_SHN_ABRUPT = 2 << 14, 141 NVME_CC_SHN_MASK = 3 << 14, 142 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16, 143 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20, 144 NVME_CSTS_RDY = 1 << 0, 145 NVME_CSTS_CFS = 1 << 1, 146 NVME_CSTS_NSSRO = 1 << 4, 147 NVME_CSTS_SHST_NORMAL = 0 << 2, 148 NVME_CSTS_SHST_OCCUR = 1 << 2, 149 NVME_CSTS_SHST_CMPLT = 2 << 2, 150 NVME_CSTS_SHST_MASK = 3 << 2, 151 }; 152 153 struct nvme_id_power_state { 154 __le16 max_power; /* centiwatts */ 155 __u8 rsvd2; 156 __u8 flags; 157 __le32 entry_lat; /* microseconds */ 158 __le32 exit_lat; /* microseconds */ 159 __u8 read_tput; 160 __u8 read_lat; 161 __u8 write_tput; 162 __u8 write_lat; 163 __le16 idle_power; 164 __u8 idle_scale; 165 __u8 rsvd19; 166 __le16 active_power; 167 __u8 active_work_scale; 168 __u8 rsvd23[9]; 169 }; 170 171 enum { 172 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 173 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 174 }; 175 176 struct nvme_id_ctrl { 177 __le16 vid; 178 __le16 ssvid; 179 char sn[20]; 180 char mn[40]; 181 char fr[8]; 182 __u8 rab; 183 __u8 ieee[3]; 184 __u8 cmic; 185 __u8 mdts; 186 __le16 cntlid; 187 __le32 ver; 188 __le32 rtd3r; 189 __le32 rtd3e; 190 __le32 oaes; 191 __le32 ctratt; 192 __u8 rsvd100[156]; 193 __le16 oacs; 194 __u8 acl; 195 __u8 aerl; 196 __u8 frmw; 197 __u8 lpa; 198 __u8 elpe; 199 __u8 npss; 200 __u8 avscc; 201 __u8 apsta; 202 __le16 wctemp; 203 __le16 cctemp; 204 __le16 mtfa; 205 __le32 hmpre; 206 __le32 hmmin; 207 __u8 tnvmcap[16]; 208 __u8 unvmcap[16]; 209 __le32 rpmbs; 210 __u8 rsvd316[4]; 211 __le16 kas; 212 __u8 rsvd322[190]; 213 __u8 sqes; 214 __u8 cqes; 215 __le16 maxcmd; 216 __le32 nn; 217 __le16 oncs; 218 __le16 fuses; 219 __u8 fna; 220 __u8 vwc; 221 __le16 awun; 222 __le16 awupf; 223 __u8 nvscc; 224 __u8 rsvd531; 225 __le16 acwu; 226 __u8 rsvd534[2]; 227 __le32 sgls; 228 __u8 rsvd540[228]; 229 char subnqn[256]; 230 __u8 rsvd1024[768]; 231 __le32 ioccsz; 232 __le32 iorcsz; 233 __le16 icdoff; 234 __u8 ctrattr; 235 __u8 msdbd; 236 __u8 rsvd1804[244]; 237 struct nvme_id_power_state psd[32]; 238 __u8 vs[1024]; 239 }; 240 241 enum { 242 NVME_CTRL_ONCS_COMPARE = 1 << 0, 243 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 244 NVME_CTRL_ONCS_DSM = 1 << 2, 245 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 246 NVME_CTRL_VWC_PRESENT = 1 << 0, 247 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 248 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7, 249 }; 250 251 struct nvme_lbaf { 252 __le16 ms; 253 __u8 ds; 254 __u8 rp; 255 }; 256 257 struct nvme_id_ns { 258 __le64 nsze; 259 __le64 ncap; 260 __le64 nuse; 261 __u8 nsfeat; 262 __u8 nlbaf; 263 __u8 flbas; 264 __u8 mc; 265 __u8 dpc; 266 __u8 dps; 267 __u8 nmic; 268 __u8 rescap; 269 __u8 fpi; 270 __u8 rsvd33; 271 __le16 nawun; 272 __le16 nawupf; 273 __le16 nacwu; 274 __le16 nabsn; 275 __le16 nabo; 276 __le16 nabspf; 277 __u16 rsvd46; 278 __u8 nvmcap[16]; 279 __u8 rsvd64[40]; 280 __u8 nguid[16]; 281 __u8 eui64[8]; 282 struct nvme_lbaf lbaf[16]; 283 __u8 rsvd192[192]; 284 __u8 vs[3712]; 285 }; 286 287 enum { 288 NVME_ID_CNS_NS = 0x00, 289 NVME_ID_CNS_CTRL = 0x01, 290 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 291 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 292 NVME_ID_CNS_NS_PRESENT = 0x11, 293 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 294 NVME_ID_CNS_CTRL_LIST = 0x13, 295 }; 296 297 enum { 298 NVME_NS_FEAT_THIN = 1 << 0, 299 NVME_NS_FLBAS_LBA_MASK = 0xf, 300 NVME_NS_FLBAS_META_EXT = 0x10, 301 NVME_LBAF_RP_BEST = 0, 302 NVME_LBAF_RP_BETTER = 1, 303 NVME_LBAF_RP_GOOD = 2, 304 NVME_LBAF_RP_DEGRADED = 3, 305 NVME_NS_DPC_PI_LAST = 1 << 4, 306 NVME_NS_DPC_PI_FIRST = 1 << 3, 307 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 308 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 309 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 310 NVME_NS_DPS_PI_FIRST = 1 << 3, 311 NVME_NS_DPS_PI_MASK = 0x7, 312 NVME_NS_DPS_PI_TYPE1 = 1, 313 NVME_NS_DPS_PI_TYPE2 = 2, 314 NVME_NS_DPS_PI_TYPE3 = 3, 315 }; 316 317 struct nvme_smart_log { 318 __u8 critical_warning; 319 __u8 temperature[2]; 320 __u8 avail_spare; 321 __u8 spare_thresh; 322 __u8 percent_used; 323 __u8 rsvd6[26]; 324 __u8 data_units_read[16]; 325 __u8 data_units_written[16]; 326 __u8 host_reads[16]; 327 __u8 host_writes[16]; 328 __u8 ctrl_busy_time[16]; 329 __u8 power_cycles[16]; 330 __u8 power_on_hours[16]; 331 __u8 unsafe_shutdowns[16]; 332 __u8 media_errors[16]; 333 __u8 num_err_log_entries[16]; 334 __le32 warning_temp_time; 335 __le32 critical_comp_time; 336 __le16 temp_sensor[8]; 337 __u8 rsvd216[296]; 338 }; 339 340 enum { 341 NVME_SMART_CRIT_SPARE = 1 << 0, 342 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 343 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 344 NVME_SMART_CRIT_MEDIA = 1 << 3, 345 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 346 }; 347 348 enum { 349 NVME_AER_NOTICE_NS_CHANGED = 0x0002, 350 }; 351 352 struct nvme_lba_range_type { 353 __u8 type; 354 __u8 attributes; 355 __u8 rsvd2[14]; 356 __u64 slba; 357 __u64 nlb; 358 __u8 guid[16]; 359 __u8 rsvd48[16]; 360 }; 361 362 enum { 363 NVME_LBART_TYPE_FS = 0x01, 364 NVME_LBART_TYPE_RAID = 0x02, 365 NVME_LBART_TYPE_CACHE = 0x03, 366 NVME_LBART_TYPE_SWAP = 0x04, 367 368 NVME_LBART_ATTRIB_TEMP = 1 << 0, 369 NVME_LBART_ATTRIB_HIDE = 1 << 1, 370 }; 371 372 struct nvme_reservation_status { 373 __le32 gen; 374 __u8 rtype; 375 __u8 regctl[2]; 376 __u8 resv5[2]; 377 __u8 ptpls; 378 __u8 resv10[13]; 379 struct { 380 __le16 cntlid; 381 __u8 rcsts; 382 __u8 resv3[5]; 383 __le64 hostid; 384 __le64 rkey; 385 } regctl_ds[]; 386 }; 387 388 enum nvme_async_event_type { 389 NVME_AER_TYPE_ERROR = 0, 390 NVME_AER_TYPE_SMART = 1, 391 NVME_AER_TYPE_NOTICE = 2, 392 }; 393 394 /* I/O commands */ 395 396 enum nvme_opcode { 397 nvme_cmd_flush = 0x00, 398 nvme_cmd_write = 0x01, 399 nvme_cmd_read = 0x02, 400 nvme_cmd_write_uncor = 0x04, 401 nvme_cmd_compare = 0x05, 402 nvme_cmd_write_zeroes = 0x08, 403 nvme_cmd_dsm = 0x09, 404 nvme_cmd_resv_register = 0x0d, 405 nvme_cmd_resv_report = 0x0e, 406 nvme_cmd_resv_acquire = 0x11, 407 nvme_cmd_resv_release = 0x15, 408 }; 409 410 /* 411 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 412 * 413 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 414 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 415 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 416 * request subtype 417 */ 418 enum { 419 NVME_SGL_FMT_ADDRESS = 0x00, 420 NVME_SGL_FMT_OFFSET = 0x01, 421 NVME_SGL_FMT_INVALIDATE = 0x0f, 422 }; 423 424 /* 425 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 426 * 427 * For struct nvme_sgl_desc: 428 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 429 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 430 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 431 * 432 * For struct nvme_keyed_sgl_desc: 433 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 434 */ 435 enum { 436 NVME_SGL_FMT_DATA_DESC = 0x00, 437 NVME_SGL_FMT_SEG_DESC = 0x02, 438 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 439 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 440 }; 441 442 struct nvme_sgl_desc { 443 __le64 addr; 444 __le32 length; 445 __u8 rsvd[3]; 446 __u8 type; 447 }; 448 449 struct nvme_keyed_sgl_desc { 450 __le64 addr; 451 __u8 length[3]; 452 __u8 key[4]; 453 __u8 type; 454 }; 455 456 union nvme_data_ptr { 457 struct { 458 __le64 prp1; 459 __le64 prp2; 460 }; 461 struct nvme_sgl_desc sgl; 462 struct nvme_keyed_sgl_desc ksgl; 463 }; 464 465 /* 466 * Lowest two bits of our flags field (FUSE field in the spec): 467 * 468 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 469 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 470 * 471 * Highest two bits in our flags field (PSDT field in the spec): 472 * 473 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 474 * If used, MPTR contains addr of single physical buffer (byte aligned). 475 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 476 * If used, MPTR contains an address of an SGL segment containing 477 * exactly 1 SGL descriptor (qword aligned). 478 */ 479 enum { 480 NVME_CMD_FUSE_FIRST = (1 << 0), 481 NVME_CMD_FUSE_SECOND = (1 << 1), 482 483 NVME_CMD_SGL_METABUF = (1 << 6), 484 NVME_CMD_SGL_METASEG = (1 << 7), 485 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 486 }; 487 488 struct nvme_common_command { 489 __u8 opcode; 490 __u8 flags; 491 __u16 command_id; 492 __le32 nsid; 493 __le32 cdw2[2]; 494 __le64 metadata; 495 union nvme_data_ptr dptr; 496 __le32 cdw10[6]; 497 }; 498 499 struct nvme_rw_command { 500 __u8 opcode; 501 __u8 flags; 502 __u16 command_id; 503 __le32 nsid; 504 __u64 rsvd2; 505 __le64 metadata; 506 union nvme_data_ptr dptr; 507 __le64 slba; 508 __le16 length; 509 __le16 control; 510 __le32 dsmgmt; 511 __le32 reftag; 512 __le16 apptag; 513 __le16 appmask; 514 }; 515 516 enum { 517 NVME_RW_LR = 1 << 15, 518 NVME_RW_FUA = 1 << 14, 519 NVME_RW_DSM_FREQ_UNSPEC = 0, 520 NVME_RW_DSM_FREQ_TYPICAL = 1, 521 NVME_RW_DSM_FREQ_RARE = 2, 522 NVME_RW_DSM_FREQ_READS = 3, 523 NVME_RW_DSM_FREQ_WRITES = 4, 524 NVME_RW_DSM_FREQ_RW = 5, 525 NVME_RW_DSM_FREQ_ONCE = 6, 526 NVME_RW_DSM_FREQ_PREFETCH = 7, 527 NVME_RW_DSM_FREQ_TEMP = 8, 528 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 529 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 530 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 531 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 532 NVME_RW_DSM_SEQ_REQ = 1 << 6, 533 NVME_RW_DSM_COMPRESSED = 1 << 7, 534 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 535 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 536 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 537 NVME_RW_PRINFO_PRACT = 1 << 13, 538 }; 539 540 struct nvme_dsm_cmd { 541 __u8 opcode; 542 __u8 flags; 543 __u16 command_id; 544 __le32 nsid; 545 __u64 rsvd2[2]; 546 union nvme_data_ptr dptr; 547 __le32 nr; 548 __le32 attributes; 549 __u32 rsvd12[4]; 550 }; 551 552 enum { 553 NVME_DSMGMT_IDR = 1 << 0, 554 NVME_DSMGMT_IDW = 1 << 1, 555 NVME_DSMGMT_AD = 1 << 2, 556 }; 557 558 #define NVME_DSM_MAX_RANGES 256 559 560 struct nvme_dsm_range { 561 __le32 cattr; 562 __le32 nlb; 563 __le64 slba; 564 }; 565 566 struct nvme_write_zeroes_cmd { 567 __u8 opcode; 568 __u8 flags; 569 __u16 command_id; 570 __le32 nsid; 571 __u64 rsvd2; 572 __le64 metadata; 573 union nvme_data_ptr dptr; 574 __le64 slba; 575 __le16 length; 576 __le16 control; 577 __le32 dsmgmt; 578 __le32 reftag; 579 __le16 apptag; 580 __le16 appmask; 581 }; 582 583 /* Features */ 584 585 struct nvme_feat_auto_pst { 586 __le64 entries[32]; 587 }; 588 589 /* Admin commands */ 590 591 enum nvme_admin_opcode { 592 nvme_admin_delete_sq = 0x00, 593 nvme_admin_create_sq = 0x01, 594 nvme_admin_get_log_page = 0x02, 595 nvme_admin_delete_cq = 0x04, 596 nvme_admin_create_cq = 0x05, 597 nvme_admin_identify = 0x06, 598 nvme_admin_abort_cmd = 0x08, 599 nvme_admin_set_features = 0x09, 600 nvme_admin_get_features = 0x0a, 601 nvme_admin_async_event = 0x0c, 602 nvme_admin_ns_mgmt = 0x0d, 603 nvme_admin_activate_fw = 0x10, 604 nvme_admin_download_fw = 0x11, 605 nvme_admin_ns_attach = 0x15, 606 nvme_admin_keep_alive = 0x18, 607 nvme_admin_dbbuf = 0x7C, 608 nvme_admin_format_nvm = 0x80, 609 nvme_admin_security_send = 0x81, 610 nvme_admin_security_recv = 0x82, 611 }; 612 613 enum { 614 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 615 NVME_CQ_IRQ_ENABLED = (1 << 1), 616 NVME_SQ_PRIO_URGENT = (0 << 1), 617 NVME_SQ_PRIO_HIGH = (1 << 1), 618 NVME_SQ_PRIO_MEDIUM = (2 << 1), 619 NVME_SQ_PRIO_LOW = (3 << 1), 620 NVME_FEAT_ARBITRATION = 0x01, 621 NVME_FEAT_POWER_MGMT = 0x02, 622 NVME_FEAT_LBA_RANGE = 0x03, 623 NVME_FEAT_TEMP_THRESH = 0x04, 624 NVME_FEAT_ERR_RECOVERY = 0x05, 625 NVME_FEAT_VOLATILE_WC = 0x06, 626 NVME_FEAT_NUM_QUEUES = 0x07, 627 NVME_FEAT_IRQ_COALESCE = 0x08, 628 NVME_FEAT_IRQ_CONFIG = 0x09, 629 NVME_FEAT_WRITE_ATOMIC = 0x0a, 630 NVME_FEAT_ASYNC_EVENT = 0x0b, 631 NVME_FEAT_AUTO_PST = 0x0c, 632 NVME_FEAT_HOST_MEM_BUF = 0x0d, 633 NVME_FEAT_KATO = 0x0f, 634 NVME_FEAT_SW_PROGRESS = 0x80, 635 NVME_FEAT_HOST_ID = 0x81, 636 NVME_FEAT_RESV_MASK = 0x82, 637 NVME_FEAT_RESV_PERSIST = 0x83, 638 NVME_LOG_ERROR = 0x01, 639 NVME_LOG_SMART = 0x02, 640 NVME_LOG_FW_SLOT = 0x03, 641 NVME_LOG_DISC = 0x70, 642 NVME_LOG_RESERVATION = 0x80, 643 NVME_FWACT_REPL = (0 << 3), 644 NVME_FWACT_REPL_ACTV = (1 << 3), 645 NVME_FWACT_ACTV = (2 << 3), 646 }; 647 648 struct nvme_identify { 649 __u8 opcode; 650 __u8 flags; 651 __u16 command_id; 652 __le32 nsid; 653 __u64 rsvd2[2]; 654 union nvme_data_ptr dptr; 655 __u8 cns; 656 __u8 rsvd3; 657 __le16 ctrlid; 658 __u32 rsvd11[5]; 659 }; 660 661 struct nvme_features { 662 __u8 opcode; 663 __u8 flags; 664 __u16 command_id; 665 __le32 nsid; 666 __u64 rsvd2[2]; 667 union nvme_data_ptr dptr; 668 __le32 fid; 669 __le32 dword11; 670 __u32 rsvd12[4]; 671 }; 672 673 struct nvme_create_cq { 674 __u8 opcode; 675 __u8 flags; 676 __u16 command_id; 677 __u32 rsvd1[5]; 678 __le64 prp1; 679 __u64 rsvd8; 680 __le16 cqid; 681 __le16 qsize; 682 __le16 cq_flags; 683 __le16 irq_vector; 684 __u32 rsvd12[4]; 685 }; 686 687 struct nvme_create_sq { 688 __u8 opcode; 689 __u8 flags; 690 __u16 command_id; 691 __u32 rsvd1[5]; 692 __le64 prp1; 693 __u64 rsvd8; 694 __le16 sqid; 695 __le16 qsize; 696 __le16 sq_flags; 697 __le16 cqid; 698 __u32 rsvd12[4]; 699 }; 700 701 struct nvme_delete_queue { 702 __u8 opcode; 703 __u8 flags; 704 __u16 command_id; 705 __u32 rsvd1[9]; 706 __le16 qid; 707 __u16 rsvd10; 708 __u32 rsvd11[5]; 709 }; 710 711 struct nvme_abort_cmd { 712 __u8 opcode; 713 __u8 flags; 714 __u16 command_id; 715 __u32 rsvd1[9]; 716 __le16 sqid; 717 __u16 cid; 718 __u32 rsvd11[5]; 719 }; 720 721 struct nvme_download_firmware { 722 __u8 opcode; 723 __u8 flags; 724 __u16 command_id; 725 __u32 rsvd1[5]; 726 union nvme_data_ptr dptr; 727 __le32 numd; 728 __le32 offset; 729 __u32 rsvd12[4]; 730 }; 731 732 struct nvme_format_cmd { 733 __u8 opcode; 734 __u8 flags; 735 __u16 command_id; 736 __le32 nsid; 737 __u64 rsvd2[4]; 738 __le32 cdw10; 739 __u32 rsvd11[5]; 740 }; 741 742 struct nvme_get_log_page_command { 743 __u8 opcode; 744 __u8 flags; 745 __u16 command_id; 746 __le32 nsid; 747 __u64 rsvd2[2]; 748 union nvme_data_ptr dptr; 749 __u8 lid; 750 __u8 rsvd10; 751 __le16 numdl; 752 __le16 numdu; 753 __u16 rsvd11; 754 __le32 lpol; 755 __le32 lpou; 756 __u32 rsvd14[2]; 757 }; 758 759 /* 760 * Fabrics subcommands. 761 */ 762 enum nvmf_fabrics_opcode { 763 nvme_fabrics_command = 0x7f, 764 }; 765 766 enum nvmf_capsule_command { 767 nvme_fabrics_type_property_set = 0x00, 768 nvme_fabrics_type_connect = 0x01, 769 nvme_fabrics_type_property_get = 0x04, 770 }; 771 772 struct nvmf_common_command { 773 __u8 opcode; 774 __u8 resv1; 775 __u16 command_id; 776 __u8 fctype; 777 __u8 resv2[35]; 778 __u8 ts[24]; 779 }; 780 781 /* 782 * The legal cntlid range a NVMe Target will provide. 783 * Note that cntlid of value 0 is considered illegal in the fabrics world. 784 * Devices based on earlier specs did not have the subsystem concept; 785 * therefore, those devices had their cntlid value set to 0 as a result. 786 */ 787 #define NVME_CNTLID_MIN 1 788 #define NVME_CNTLID_MAX 0xffef 789 #define NVME_CNTLID_DYNAMIC 0xffff 790 791 #define MAX_DISC_LOGS 255 792 793 /* Discovery log page entry */ 794 struct nvmf_disc_rsp_page_entry { 795 __u8 trtype; 796 __u8 adrfam; 797 __u8 subtype; 798 __u8 treq; 799 __le16 portid; 800 __le16 cntlid; 801 __le16 asqsz; 802 __u8 resv8[22]; 803 char trsvcid[NVMF_TRSVCID_SIZE]; 804 __u8 resv64[192]; 805 char subnqn[NVMF_NQN_FIELD_LEN]; 806 char traddr[NVMF_TRADDR_SIZE]; 807 union tsas { 808 char common[NVMF_TSAS_SIZE]; 809 struct rdma { 810 __u8 qptype; 811 __u8 prtype; 812 __u8 cms; 813 __u8 resv3[5]; 814 __u16 pkey; 815 __u8 resv10[246]; 816 } rdma; 817 } tsas; 818 }; 819 820 /* Discovery log page header */ 821 struct nvmf_disc_rsp_page_hdr { 822 __le64 genctr; 823 __le64 numrec; 824 __le16 recfmt; 825 __u8 resv14[1006]; 826 struct nvmf_disc_rsp_page_entry entries[0]; 827 }; 828 829 struct nvmf_connect_command { 830 __u8 opcode; 831 __u8 resv1; 832 __u16 command_id; 833 __u8 fctype; 834 __u8 resv2[19]; 835 union nvme_data_ptr dptr; 836 __le16 recfmt; 837 __le16 qid; 838 __le16 sqsize; 839 __u8 cattr; 840 __u8 resv3; 841 __le32 kato; 842 __u8 resv4[12]; 843 }; 844 845 struct nvmf_connect_data { 846 __u8 hostid[16]; 847 __le16 cntlid; 848 char resv4[238]; 849 char subsysnqn[NVMF_NQN_FIELD_LEN]; 850 char hostnqn[NVMF_NQN_FIELD_LEN]; 851 char resv5[256]; 852 }; 853 854 struct nvmf_property_set_command { 855 __u8 opcode; 856 __u8 resv1; 857 __u16 command_id; 858 __u8 fctype; 859 __u8 resv2[35]; 860 __u8 attrib; 861 __u8 resv3[3]; 862 __le32 offset; 863 __le64 value; 864 __u8 resv4[8]; 865 }; 866 867 struct nvmf_property_get_command { 868 __u8 opcode; 869 __u8 resv1; 870 __u16 command_id; 871 __u8 fctype; 872 __u8 resv2[35]; 873 __u8 attrib; 874 __u8 resv3[3]; 875 __le32 offset; 876 __u8 resv4[16]; 877 }; 878 879 struct nvme_dbbuf { 880 __u8 opcode; 881 __u8 flags; 882 __u16 command_id; 883 __u32 rsvd1[5]; 884 __le64 prp1; 885 __le64 prp2; 886 __u32 rsvd12[6]; 887 }; 888 889 struct nvme_command { 890 union { 891 struct nvme_common_command common; 892 struct nvme_rw_command rw; 893 struct nvme_identify identify; 894 struct nvme_features features; 895 struct nvme_create_cq create_cq; 896 struct nvme_create_sq create_sq; 897 struct nvme_delete_queue delete_queue; 898 struct nvme_download_firmware dlfw; 899 struct nvme_format_cmd format; 900 struct nvme_dsm_cmd dsm; 901 struct nvme_write_zeroes_cmd write_zeroes; 902 struct nvme_abort_cmd abort; 903 struct nvme_get_log_page_command get_log_page; 904 struct nvmf_common_command fabrics; 905 struct nvmf_connect_command connect; 906 struct nvmf_property_set_command prop_set; 907 struct nvmf_property_get_command prop_get; 908 struct nvme_dbbuf dbbuf; 909 }; 910 }; 911 912 static inline bool nvme_is_write(struct nvme_command *cmd) 913 { 914 /* 915 * What a mess... 916 * 917 * Why can't we simply have a Fabrics In and Fabrics out command? 918 */ 919 if (unlikely(cmd->common.opcode == nvme_fabrics_command)) 920 return cmd->fabrics.opcode & 1; 921 return cmd->common.opcode & 1; 922 } 923 924 enum { 925 /* 926 * Generic Command Status: 927 */ 928 NVME_SC_SUCCESS = 0x0, 929 NVME_SC_INVALID_OPCODE = 0x1, 930 NVME_SC_INVALID_FIELD = 0x2, 931 NVME_SC_CMDID_CONFLICT = 0x3, 932 NVME_SC_DATA_XFER_ERROR = 0x4, 933 NVME_SC_POWER_LOSS = 0x5, 934 NVME_SC_INTERNAL = 0x6, 935 NVME_SC_ABORT_REQ = 0x7, 936 NVME_SC_ABORT_QUEUE = 0x8, 937 NVME_SC_FUSED_FAIL = 0x9, 938 NVME_SC_FUSED_MISSING = 0xa, 939 NVME_SC_INVALID_NS = 0xb, 940 NVME_SC_CMD_SEQ_ERROR = 0xc, 941 NVME_SC_SGL_INVALID_LAST = 0xd, 942 NVME_SC_SGL_INVALID_COUNT = 0xe, 943 NVME_SC_SGL_INVALID_DATA = 0xf, 944 NVME_SC_SGL_INVALID_METADATA = 0x10, 945 NVME_SC_SGL_INVALID_TYPE = 0x11, 946 947 NVME_SC_SGL_INVALID_OFFSET = 0x16, 948 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 949 950 NVME_SC_LBA_RANGE = 0x80, 951 NVME_SC_CAP_EXCEEDED = 0x81, 952 NVME_SC_NS_NOT_READY = 0x82, 953 NVME_SC_RESERVATION_CONFLICT = 0x83, 954 955 /* 956 * Command Specific Status: 957 */ 958 NVME_SC_CQ_INVALID = 0x100, 959 NVME_SC_QID_INVALID = 0x101, 960 NVME_SC_QUEUE_SIZE = 0x102, 961 NVME_SC_ABORT_LIMIT = 0x103, 962 NVME_SC_ABORT_MISSING = 0x104, 963 NVME_SC_ASYNC_LIMIT = 0x105, 964 NVME_SC_FIRMWARE_SLOT = 0x106, 965 NVME_SC_FIRMWARE_IMAGE = 0x107, 966 NVME_SC_INVALID_VECTOR = 0x108, 967 NVME_SC_INVALID_LOG_PAGE = 0x109, 968 NVME_SC_INVALID_FORMAT = 0x10a, 969 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 970 NVME_SC_INVALID_QUEUE = 0x10c, 971 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 972 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 973 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 974 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 975 NVME_SC_FW_NEEDS_RESET = 0x111, 976 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 977 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, 978 NVME_SC_OVERLAPPING_RANGE = 0x114, 979 NVME_SC_NS_INSUFFICENT_CAP = 0x115, 980 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 981 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 982 NVME_SC_NS_IS_PRIVATE = 0x119, 983 NVME_SC_NS_NOT_ATTACHED = 0x11a, 984 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 985 NVME_SC_CTRL_LIST_INVALID = 0x11c, 986 987 /* 988 * I/O Command Set Specific - NVM commands: 989 */ 990 NVME_SC_BAD_ATTRIBUTES = 0x180, 991 NVME_SC_INVALID_PI = 0x181, 992 NVME_SC_READ_ONLY = 0x182, 993 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 994 995 /* 996 * I/O Command Set Specific - Fabrics commands: 997 */ 998 NVME_SC_CONNECT_FORMAT = 0x180, 999 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1000 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1001 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1002 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1003 1004 NVME_SC_DISCOVERY_RESTART = 0x190, 1005 NVME_SC_AUTH_REQUIRED = 0x191, 1006 1007 /* 1008 * Media and Data Integrity Errors: 1009 */ 1010 NVME_SC_WRITE_FAULT = 0x280, 1011 NVME_SC_READ_ERROR = 0x281, 1012 NVME_SC_GUARD_CHECK = 0x282, 1013 NVME_SC_APPTAG_CHECK = 0x283, 1014 NVME_SC_REFTAG_CHECK = 0x284, 1015 NVME_SC_COMPARE_FAILED = 0x285, 1016 NVME_SC_ACCESS_DENIED = 0x286, 1017 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1018 1019 NVME_SC_DNR = 0x4000, 1020 1021 1022 /* 1023 * FC Transport-specific error status values for NVME commands 1024 * 1025 * Transport-specific status code values must be in the range 0xB0..0xBF 1026 */ 1027 1028 /* Generic FC failure - catchall */ 1029 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0, 1030 1031 /* I/O failure due to FC ABTS'd */ 1032 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1, 1033 }; 1034 1035 struct nvme_completion { 1036 /* 1037 * Used by Admin and Fabrics commands to return data: 1038 */ 1039 union nvme_result { 1040 __le16 u16; 1041 __le32 u32; 1042 __le64 u64; 1043 } result; 1044 __le16 sq_head; /* how much of this queue may be reclaimed */ 1045 __le16 sq_id; /* submission queue that generated this entry */ 1046 __u16 command_id; /* of the command which completed */ 1047 __le16 status; /* did the command fail, and if so, why? */ 1048 }; 1049 1050 #define NVME_VS(major, minor, tertiary) \ 1051 (((major) << 16) | ((minor) << 8) | (tertiary)) 1052 1053 #endif /* _LINUX_NVME_H */ 1054