1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/types.h> 11 #include <linux/uuid.h> 12 13 /* NQN names in commands fields specified one size */ 14 #define NVMF_NQN_FIELD_LEN 256 15 16 /* However the max length of a qualified name is another size */ 17 #define NVMF_NQN_SIZE 223 18 19 #define NVMF_TRSVCID_SIZE 32 20 #define NVMF_TRADDR_SIZE 256 21 #define NVMF_TSAS_SIZE 256 22 23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 24 25 #define NVME_RDMA_IP_PORT 4420 26 27 #define NVME_NSID_ALL 0xffffffff 28 29 enum nvme_subsys_type { 30 /* Referral to another discovery type target subsystem */ 31 NVME_NQN_DISC = 1, 32 33 /* NVME type target subsystem */ 34 NVME_NQN_NVME = 2, 35 36 /* Current discovery type target subsystem */ 37 NVME_NQN_CURR = 3, 38 }; 39 40 enum nvme_ctrl_type { 41 NVME_CTRL_IO = 1, /* I/O controller */ 42 NVME_CTRL_DISC = 2, /* Discovery controller */ 43 NVME_CTRL_ADMIN = 3, /* Administrative controller */ 44 }; 45 46 enum nvme_dctype { 47 NVME_DCTYPE_NOT_REPORTED = 0, 48 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */ 49 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */ 50 }; 51 52 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 53 enum { 54 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 55 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 56 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 57 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 58 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 59 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ 60 NVMF_ADDR_FAMILY_MAX, 61 }; 62 63 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 64 enum { 65 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 66 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 67 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 68 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 69 NVMF_TRTYPE_MAX, 70 }; 71 72 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 73 enum { 74 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 75 NVMF_TREQ_REQUIRED = 1, /* Required */ 76 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 77 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 78 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 79 80 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 81 }; 82 83 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 84 * RDMA_QPTYPE field 85 */ 86 enum { 87 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 88 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 89 }; 90 91 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 92 * RDMA_QPTYPE field 93 */ 94 enum { 95 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 96 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 97 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 98 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 99 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 100 }; 101 102 /* RDMA Connection Management Service Type codes for Discovery Log Page 103 * entry TSAS RDMA_CMS field 104 */ 105 enum { 106 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 107 }; 108 109 #define NVME_AQ_DEPTH 32 110 #define NVME_NR_AEN_COMMANDS 1 111 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 112 113 /* 114 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 115 * NVM-Express 1.2 specification, section 4.1.2. 116 */ 117 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 118 119 enum { 120 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 121 NVME_REG_VS = 0x0008, /* Version */ 122 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 123 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 124 NVME_REG_CC = 0x0014, /* Controller Configuration */ 125 NVME_REG_CSTS = 0x001c, /* Controller Status */ 126 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 127 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 128 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 129 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 130 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 131 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 132 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ 133 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ 134 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer 135 * Location 136 */ 137 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory 138 * Space Control 139 */ 140 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ 141 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ 142 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ 143 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity 144 * Buffer Size 145 */ 146 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained 147 * Write Throughput 148 */ 149 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 150 }; 151 152 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 153 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 154 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 155 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 156 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) 157 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 158 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 159 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) 160 161 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 162 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 163 164 enum { 165 NVME_CMBSZ_SQS = 1 << 0, 166 NVME_CMBSZ_CQS = 1 << 1, 167 NVME_CMBSZ_LISTS = 1 << 2, 168 NVME_CMBSZ_RDS = 1 << 3, 169 NVME_CMBSZ_WDS = 1 << 4, 170 171 NVME_CMBSZ_SZ_SHIFT = 12, 172 NVME_CMBSZ_SZ_MASK = 0xfffff, 173 174 NVME_CMBSZ_SZU_SHIFT = 8, 175 NVME_CMBSZ_SZU_MASK = 0xf, 176 }; 177 178 /* 179 * Submission and Completion Queue Entry Sizes for the NVM command set. 180 * (In bytes and specified as a power of two (2^n)). 181 */ 182 #define NVME_ADM_SQES 6 183 #define NVME_NVM_IOSQES 6 184 #define NVME_NVM_IOCQES 4 185 186 enum { 187 NVME_CC_ENABLE = 1 << 0, 188 NVME_CC_EN_SHIFT = 0, 189 NVME_CC_CSS_SHIFT = 4, 190 NVME_CC_MPS_SHIFT = 7, 191 NVME_CC_AMS_SHIFT = 11, 192 NVME_CC_SHN_SHIFT = 14, 193 NVME_CC_IOSQES_SHIFT = 16, 194 NVME_CC_IOCQES_SHIFT = 20, 195 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, 196 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, 197 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, 198 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 199 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 200 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 201 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 202 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 203 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 204 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 205 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 206 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 207 NVME_CAP_CSS_NVM = 1 << 0, 208 NVME_CAP_CSS_CSI = 1 << 6, 209 NVME_CSTS_RDY = 1 << 0, 210 NVME_CSTS_CFS = 1 << 1, 211 NVME_CSTS_NSSRO = 1 << 4, 212 NVME_CSTS_PP = 1 << 5, 213 NVME_CSTS_SHST_NORMAL = 0 << 2, 214 NVME_CSTS_SHST_OCCUR = 1 << 2, 215 NVME_CSTS_SHST_CMPLT = 2 << 2, 216 NVME_CSTS_SHST_MASK = 3 << 2, 217 NVME_CMBMSC_CRE = 1 << 0, 218 NVME_CMBMSC_CMSE = 1 << 1, 219 }; 220 221 struct nvme_id_power_state { 222 __le16 max_power; /* centiwatts */ 223 __u8 rsvd2; 224 __u8 flags; 225 __le32 entry_lat; /* microseconds */ 226 __le32 exit_lat; /* microseconds */ 227 __u8 read_tput; 228 __u8 read_lat; 229 __u8 write_tput; 230 __u8 write_lat; 231 __le16 idle_power; 232 __u8 idle_scale; 233 __u8 rsvd19; 234 __le16 active_power; 235 __u8 active_work_scale; 236 __u8 rsvd23[9]; 237 }; 238 239 enum { 240 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 241 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 242 }; 243 244 enum nvme_ctrl_attr { 245 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 246 NVME_CTRL_ATTR_TBKAS = (1 << 6), 247 NVME_CTRL_ATTR_ELBAS = (1 << 15), 248 }; 249 250 struct nvme_id_ctrl { 251 __le16 vid; 252 __le16 ssvid; 253 char sn[20]; 254 char mn[40]; 255 char fr[8]; 256 __u8 rab; 257 __u8 ieee[3]; 258 __u8 cmic; 259 __u8 mdts; 260 __le16 cntlid; 261 __le32 ver; 262 __le32 rtd3r; 263 __le32 rtd3e; 264 __le32 oaes; 265 __le32 ctratt; 266 __u8 rsvd100[11]; 267 __u8 cntrltype; 268 __u8 fguid[16]; 269 __le16 crdt1; 270 __le16 crdt2; 271 __le16 crdt3; 272 __u8 rsvd134[122]; 273 __le16 oacs; 274 __u8 acl; 275 __u8 aerl; 276 __u8 frmw; 277 __u8 lpa; 278 __u8 elpe; 279 __u8 npss; 280 __u8 avscc; 281 __u8 apsta; 282 __le16 wctemp; 283 __le16 cctemp; 284 __le16 mtfa; 285 __le32 hmpre; 286 __le32 hmmin; 287 __u8 tnvmcap[16]; 288 __u8 unvmcap[16]; 289 __le32 rpmbs; 290 __le16 edstt; 291 __u8 dsto; 292 __u8 fwug; 293 __le16 kas; 294 __le16 hctma; 295 __le16 mntmt; 296 __le16 mxtmt; 297 __le32 sanicap; 298 __le32 hmminds; 299 __le16 hmmaxd; 300 __u8 rsvd338[4]; 301 __u8 anatt; 302 __u8 anacap; 303 __le32 anagrpmax; 304 __le32 nanagrpid; 305 __u8 rsvd352[160]; 306 __u8 sqes; 307 __u8 cqes; 308 __le16 maxcmd; 309 __le32 nn; 310 __le16 oncs; 311 __le16 fuses; 312 __u8 fna; 313 __u8 vwc; 314 __le16 awun; 315 __le16 awupf; 316 __u8 nvscc; 317 __u8 nwpc; 318 __le16 acwu; 319 __u8 rsvd534[2]; 320 __le32 sgls; 321 __le32 mnan; 322 __u8 rsvd544[224]; 323 char subnqn[256]; 324 __u8 rsvd1024[768]; 325 __le32 ioccsz; 326 __le32 iorcsz; 327 __le16 icdoff; 328 __u8 ctrattr; 329 __u8 msdbd; 330 __u8 rsvd1804[2]; 331 __u8 dctype; 332 __u8 rsvd1807[241]; 333 struct nvme_id_power_state psd[32]; 334 __u8 vs[1024]; 335 }; 336 337 enum { 338 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, 339 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, 340 NVME_CTRL_CMIC_ANA = 1 << 3, 341 NVME_CTRL_ONCS_COMPARE = 1 << 0, 342 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 343 NVME_CTRL_ONCS_DSM = 1 << 2, 344 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 345 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, 346 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 347 NVME_CTRL_VWC_PRESENT = 1 << 0, 348 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 349 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, 350 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 351 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 352 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 353 NVME_CTRL_CTRATT_128_ID = 1 << 0, 354 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, 355 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, 356 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, 357 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, 358 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, 359 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, 360 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, 361 }; 362 363 struct nvme_lbaf { 364 __le16 ms; 365 __u8 ds; 366 __u8 rp; 367 }; 368 369 struct nvme_id_ns { 370 __le64 nsze; 371 __le64 ncap; 372 __le64 nuse; 373 __u8 nsfeat; 374 __u8 nlbaf; 375 __u8 flbas; 376 __u8 mc; 377 __u8 dpc; 378 __u8 dps; 379 __u8 nmic; 380 __u8 rescap; 381 __u8 fpi; 382 __u8 dlfeat; 383 __le16 nawun; 384 __le16 nawupf; 385 __le16 nacwu; 386 __le16 nabsn; 387 __le16 nabo; 388 __le16 nabspf; 389 __le16 noiob; 390 __u8 nvmcap[16]; 391 __le16 npwg; 392 __le16 npwa; 393 __le16 npdg; 394 __le16 npda; 395 __le16 nows; 396 __u8 rsvd74[18]; 397 __le32 anagrpid; 398 __u8 rsvd96[3]; 399 __u8 nsattr; 400 __le16 nvmsetid; 401 __le16 endgid; 402 __u8 nguid[16]; 403 __u8 eui64[8]; 404 struct nvme_lbaf lbaf[64]; 405 __u8 vs[3712]; 406 }; 407 408 struct nvme_zns_lbafe { 409 __le64 zsze; 410 __u8 zdes; 411 __u8 rsvd9[7]; 412 }; 413 414 struct nvme_id_ns_zns { 415 __le16 zoc; 416 __le16 ozcs; 417 __le32 mar; 418 __le32 mor; 419 __le32 rrl; 420 __le32 frl; 421 __u8 rsvd20[2796]; 422 struct nvme_zns_lbafe lbafe[64]; 423 __u8 vs[256]; 424 }; 425 426 struct nvme_id_ctrl_zns { 427 __u8 zasl; 428 __u8 rsvd1[4095]; 429 }; 430 431 struct nvme_id_ns_nvm { 432 __le64 lbstm; 433 __u8 pic; 434 __u8 rsvd9[3]; 435 __le32 elbaf[64]; 436 __u8 rsvd268[3828]; 437 }; 438 439 enum { 440 NVME_ID_NS_NVM_STS_MASK = 0x3f, 441 NVME_ID_NS_NVM_GUARD_SHIFT = 7, 442 NVME_ID_NS_NVM_GUARD_MASK = 0x3, 443 }; 444 445 static inline __u8 nvme_elbaf_sts(__u32 elbaf) 446 { 447 return elbaf & NVME_ID_NS_NVM_STS_MASK; 448 } 449 450 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf) 451 { 452 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK; 453 } 454 455 struct nvme_id_ctrl_nvm { 456 __u8 vsl; 457 __u8 wzsl; 458 __u8 wusl; 459 __u8 dmrl; 460 __le32 dmrsl; 461 __le64 dmsl; 462 __u8 rsvd16[4080]; 463 }; 464 465 enum { 466 NVME_ID_CNS_NS = 0x00, 467 NVME_ID_CNS_CTRL = 0x01, 468 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 469 NVME_ID_CNS_NS_DESC_LIST = 0x03, 470 NVME_ID_CNS_CS_NS = 0x05, 471 NVME_ID_CNS_CS_CTRL = 0x06, 472 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 473 NVME_ID_CNS_NS_PRESENT = 0x11, 474 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 475 NVME_ID_CNS_CTRL_LIST = 0x13, 476 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, 477 NVME_ID_CNS_NS_GRANULARITY = 0x16, 478 NVME_ID_CNS_UUID_LIST = 0x17, 479 }; 480 481 enum { 482 NVME_CSI_NVM = 0, 483 NVME_CSI_ZNS = 2, 484 }; 485 486 enum { 487 NVME_DIR_IDENTIFY = 0x00, 488 NVME_DIR_STREAMS = 0x01, 489 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 490 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 491 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 492 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 493 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 494 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 495 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 496 NVME_DIR_ENDIR = 0x01, 497 }; 498 499 enum { 500 NVME_NS_FEAT_THIN = 1 << 0, 501 NVME_NS_FEAT_ATOMICS = 1 << 1, 502 NVME_NS_FEAT_IO_OPT = 1 << 4, 503 NVME_NS_ATTR_RO = 1 << 0, 504 NVME_NS_FLBAS_LBA_MASK = 0xf, 505 NVME_NS_FLBAS_LBA_UMASK = 0x60, 506 NVME_NS_FLBAS_LBA_SHIFT = 1, 507 NVME_NS_FLBAS_META_EXT = 0x10, 508 NVME_NS_NMIC_SHARED = 1 << 0, 509 NVME_LBAF_RP_BEST = 0, 510 NVME_LBAF_RP_BETTER = 1, 511 NVME_LBAF_RP_GOOD = 2, 512 NVME_LBAF_RP_DEGRADED = 3, 513 NVME_NS_DPC_PI_LAST = 1 << 4, 514 NVME_NS_DPC_PI_FIRST = 1 << 3, 515 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 516 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 517 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 518 NVME_NS_DPS_PI_FIRST = 1 << 3, 519 NVME_NS_DPS_PI_MASK = 0x7, 520 NVME_NS_DPS_PI_TYPE1 = 1, 521 NVME_NS_DPS_PI_TYPE2 = 2, 522 NVME_NS_DPS_PI_TYPE3 = 3, 523 }; 524 525 enum { 526 NVME_NVM_NS_16B_GUARD = 0, 527 NVME_NVM_NS_32B_GUARD = 1, 528 NVME_NVM_NS_64B_GUARD = 2, 529 }; 530 531 static inline __u8 nvme_lbaf_index(__u8 flbas) 532 { 533 return (flbas & NVME_NS_FLBAS_LBA_MASK) | 534 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT); 535 } 536 537 /* Identify Namespace Metadata Capabilities (MC): */ 538 enum { 539 NVME_MC_EXTENDED_LBA = (1 << 0), 540 NVME_MC_METADATA_PTR = (1 << 1), 541 }; 542 543 struct nvme_ns_id_desc { 544 __u8 nidt; 545 __u8 nidl; 546 __le16 reserved; 547 }; 548 549 #define NVME_NIDT_EUI64_LEN 8 550 #define NVME_NIDT_NGUID_LEN 16 551 #define NVME_NIDT_UUID_LEN 16 552 #define NVME_NIDT_CSI_LEN 1 553 554 enum { 555 NVME_NIDT_EUI64 = 0x01, 556 NVME_NIDT_NGUID = 0x02, 557 NVME_NIDT_UUID = 0x03, 558 NVME_NIDT_CSI = 0x04, 559 }; 560 561 struct nvme_smart_log { 562 __u8 critical_warning; 563 __u8 temperature[2]; 564 __u8 avail_spare; 565 __u8 spare_thresh; 566 __u8 percent_used; 567 __u8 endu_grp_crit_warn_sumry; 568 __u8 rsvd7[25]; 569 __u8 data_units_read[16]; 570 __u8 data_units_written[16]; 571 __u8 host_reads[16]; 572 __u8 host_writes[16]; 573 __u8 ctrl_busy_time[16]; 574 __u8 power_cycles[16]; 575 __u8 power_on_hours[16]; 576 __u8 unsafe_shutdowns[16]; 577 __u8 media_errors[16]; 578 __u8 num_err_log_entries[16]; 579 __le32 warning_temp_time; 580 __le32 critical_comp_time; 581 __le16 temp_sensor[8]; 582 __le32 thm_temp1_trans_count; 583 __le32 thm_temp2_trans_count; 584 __le32 thm_temp1_total_time; 585 __le32 thm_temp2_total_time; 586 __u8 rsvd232[280]; 587 }; 588 589 struct nvme_fw_slot_info_log { 590 __u8 afi; 591 __u8 rsvd1[7]; 592 __le64 frs[7]; 593 __u8 rsvd64[448]; 594 }; 595 596 enum { 597 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 598 NVME_CMD_EFFECTS_LBCC = 1 << 1, 599 NVME_CMD_EFFECTS_NCC = 1 << 2, 600 NVME_CMD_EFFECTS_NIC = 1 << 3, 601 NVME_CMD_EFFECTS_CCC = 1 << 4, 602 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, 603 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, 604 }; 605 606 struct nvme_effects_log { 607 __le32 acs[256]; 608 __le32 iocs[256]; 609 __u8 resv[2048]; 610 }; 611 612 enum nvme_ana_state { 613 NVME_ANA_OPTIMIZED = 0x01, 614 NVME_ANA_NONOPTIMIZED = 0x02, 615 NVME_ANA_INACCESSIBLE = 0x03, 616 NVME_ANA_PERSISTENT_LOSS = 0x04, 617 NVME_ANA_CHANGE = 0x0f, 618 }; 619 620 struct nvme_ana_group_desc { 621 __le32 grpid; 622 __le32 nnsids; 623 __le64 chgcnt; 624 __u8 state; 625 __u8 rsvd17[15]; 626 __le32 nsids[]; 627 }; 628 629 /* flag for the log specific field of the ANA log */ 630 #define NVME_ANA_LOG_RGO (1 << 0) 631 632 struct nvme_ana_rsp_hdr { 633 __le64 chgcnt; 634 __le16 ngrps; 635 __le16 rsvd10[3]; 636 }; 637 638 struct nvme_zone_descriptor { 639 __u8 zt; 640 __u8 zs; 641 __u8 za; 642 __u8 rsvd3[5]; 643 __le64 zcap; 644 __le64 zslba; 645 __le64 wp; 646 __u8 rsvd32[32]; 647 }; 648 649 enum { 650 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, 651 }; 652 653 struct nvme_zone_report { 654 __le64 nr_zones; 655 __u8 resv8[56]; 656 struct nvme_zone_descriptor entries[]; 657 }; 658 659 enum { 660 NVME_SMART_CRIT_SPARE = 1 << 0, 661 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 662 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 663 NVME_SMART_CRIT_MEDIA = 1 << 3, 664 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 665 }; 666 667 enum { 668 NVME_AER_ERROR = 0, 669 NVME_AER_SMART = 1, 670 NVME_AER_NOTICE = 2, 671 NVME_AER_CSS = 6, 672 NVME_AER_VS = 7, 673 }; 674 675 enum { 676 NVME_AER_NOTICE_NS_CHANGED = 0x00, 677 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 678 NVME_AER_NOTICE_ANA = 0x03, 679 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 680 }; 681 682 enum { 683 NVME_AEN_BIT_NS_ATTR = 8, 684 NVME_AEN_BIT_FW_ACT = 9, 685 NVME_AEN_BIT_ANA_CHANGE = 11, 686 NVME_AEN_BIT_DISC_CHANGE = 31, 687 }; 688 689 enum { 690 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 691 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 692 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 693 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 694 }; 695 696 struct nvme_lba_range_type { 697 __u8 type; 698 __u8 attributes; 699 __u8 rsvd2[14]; 700 __le64 slba; 701 __le64 nlb; 702 __u8 guid[16]; 703 __u8 rsvd48[16]; 704 }; 705 706 enum { 707 NVME_LBART_TYPE_FS = 0x01, 708 NVME_LBART_TYPE_RAID = 0x02, 709 NVME_LBART_TYPE_CACHE = 0x03, 710 NVME_LBART_TYPE_SWAP = 0x04, 711 712 NVME_LBART_ATTRIB_TEMP = 1 << 0, 713 NVME_LBART_ATTRIB_HIDE = 1 << 1, 714 }; 715 716 struct nvme_reservation_status { 717 __le32 gen; 718 __u8 rtype; 719 __u8 regctl[2]; 720 __u8 resv5[2]; 721 __u8 ptpls; 722 __u8 resv10[13]; 723 struct { 724 __le16 cntlid; 725 __u8 rcsts; 726 __u8 resv3[5]; 727 __le64 hostid; 728 __le64 rkey; 729 } regctl_ds[]; 730 }; 731 732 enum nvme_async_event_type { 733 NVME_AER_TYPE_ERROR = 0, 734 NVME_AER_TYPE_SMART = 1, 735 NVME_AER_TYPE_NOTICE = 2, 736 }; 737 738 /* I/O commands */ 739 740 enum nvme_opcode { 741 nvme_cmd_flush = 0x00, 742 nvme_cmd_write = 0x01, 743 nvme_cmd_read = 0x02, 744 nvme_cmd_write_uncor = 0x04, 745 nvme_cmd_compare = 0x05, 746 nvme_cmd_write_zeroes = 0x08, 747 nvme_cmd_dsm = 0x09, 748 nvme_cmd_verify = 0x0c, 749 nvme_cmd_resv_register = 0x0d, 750 nvme_cmd_resv_report = 0x0e, 751 nvme_cmd_resv_acquire = 0x11, 752 nvme_cmd_resv_release = 0x15, 753 nvme_cmd_zone_mgmt_send = 0x79, 754 nvme_cmd_zone_mgmt_recv = 0x7a, 755 nvme_cmd_zone_append = 0x7d, 756 }; 757 758 #define nvme_opcode_name(opcode) { opcode, #opcode } 759 #define show_nvm_opcode_name(val) \ 760 __print_symbolic(val, \ 761 nvme_opcode_name(nvme_cmd_flush), \ 762 nvme_opcode_name(nvme_cmd_write), \ 763 nvme_opcode_name(nvme_cmd_read), \ 764 nvme_opcode_name(nvme_cmd_write_uncor), \ 765 nvme_opcode_name(nvme_cmd_compare), \ 766 nvme_opcode_name(nvme_cmd_write_zeroes), \ 767 nvme_opcode_name(nvme_cmd_dsm), \ 768 nvme_opcode_name(nvme_cmd_resv_register), \ 769 nvme_opcode_name(nvme_cmd_resv_report), \ 770 nvme_opcode_name(nvme_cmd_resv_acquire), \ 771 nvme_opcode_name(nvme_cmd_resv_release), \ 772 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ 773 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ 774 nvme_opcode_name(nvme_cmd_zone_append)) 775 776 777 778 /* 779 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 780 * 781 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 782 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 783 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 784 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 785 * request subtype 786 */ 787 enum { 788 NVME_SGL_FMT_ADDRESS = 0x00, 789 NVME_SGL_FMT_OFFSET = 0x01, 790 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 791 NVME_SGL_FMT_INVALIDATE = 0x0f, 792 }; 793 794 /* 795 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 796 * 797 * For struct nvme_sgl_desc: 798 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 799 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 800 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 801 * 802 * For struct nvme_keyed_sgl_desc: 803 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 804 * 805 * Transport-specific SGL types: 806 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 807 */ 808 enum { 809 NVME_SGL_FMT_DATA_DESC = 0x00, 810 NVME_SGL_FMT_SEG_DESC = 0x02, 811 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 812 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 813 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 814 }; 815 816 struct nvme_sgl_desc { 817 __le64 addr; 818 __le32 length; 819 __u8 rsvd[3]; 820 __u8 type; 821 }; 822 823 struct nvme_keyed_sgl_desc { 824 __le64 addr; 825 __u8 length[3]; 826 __u8 key[4]; 827 __u8 type; 828 }; 829 830 union nvme_data_ptr { 831 struct { 832 __le64 prp1; 833 __le64 prp2; 834 }; 835 struct nvme_sgl_desc sgl; 836 struct nvme_keyed_sgl_desc ksgl; 837 }; 838 839 /* 840 * Lowest two bits of our flags field (FUSE field in the spec): 841 * 842 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 843 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 844 * 845 * Highest two bits in our flags field (PSDT field in the spec): 846 * 847 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 848 * If used, MPTR contains addr of single physical buffer (byte aligned). 849 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 850 * If used, MPTR contains an address of an SGL segment containing 851 * exactly 1 SGL descriptor (qword aligned). 852 */ 853 enum { 854 NVME_CMD_FUSE_FIRST = (1 << 0), 855 NVME_CMD_FUSE_SECOND = (1 << 1), 856 857 NVME_CMD_SGL_METABUF = (1 << 6), 858 NVME_CMD_SGL_METASEG = (1 << 7), 859 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 860 }; 861 862 struct nvme_common_command { 863 __u8 opcode; 864 __u8 flags; 865 __u16 command_id; 866 __le32 nsid; 867 __le32 cdw2[2]; 868 __le64 metadata; 869 union nvme_data_ptr dptr; 870 __le32 cdw10; 871 __le32 cdw11; 872 __le32 cdw12; 873 __le32 cdw13; 874 __le32 cdw14; 875 __le32 cdw15; 876 }; 877 878 struct nvme_rw_command { 879 __u8 opcode; 880 __u8 flags; 881 __u16 command_id; 882 __le32 nsid; 883 __le32 cdw2; 884 __le32 cdw3; 885 __le64 metadata; 886 union nvme_data_ptr dptr; 887 __le64 slba; 888 __le16 length; 889 __le16 control; 890 __le32 dsmgmt; 891 __le32 reftag; 892 __le16 apptag; 893 __le16 appmask; 894 }; 895 896 enum { 897 NVME_RW_LR = 1 << 15, 898 NVME_RW_FUA = 1 << 14, 899 NVME_RW_APPEND_PIREMAP = 1 << 9, 900 NVME_RW_DSM_FREQ_UNSPEC = 0, 901 NVME_RW_DSM_FREQ_TYPICAL = 1, 902 NVME_RW_DSM_FREQ_RARE = 2, 903 NVME_RW_DSM_FREQ_READS = 3, 904 NVME_RW_DSM_FREQ_WRITES = 4, 905 NVME_RW_DSM_FREQ_RW = 5, 906 NVME_RW_DSM_FREQ_ONCE = 6, 907 NVME_RW_DSM_FREQ_PREFETCH = 7, 908 NVME_RW_DSM_FREQ_TEMP = 8, 909 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 910 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 911 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 912 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 913 NVME_RW_DSM_SEQ_REQ = 1 << 6, 914 NVME_RW_DSM_COMPRESSED = 1 << 7, 915 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 916 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 917 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 918 NVME_RW_PRINFO_PRACT = 1 << 13, 919 NVME_RW_DTYPE_STREAMS = 1 << 4, 920 }; 921 922 struct nvme_dsm_cmd { 923 __u8 opcode; 924 __u8 flags; 925 __u16 command_id; 926 __le32 nsid; 927 __u64 rsvd2[2]; 928 union nvme_data_ptr dptr; 929 __le32 nr; 930 __le32 attributes; 931 __u32 rsvd12[4]; 932 }; 933 934 enum { 935 NVME_DSMGMT_IDR = 1 << 0, 936 NVME_DSMGMT_IDW = 1 << 1, 937 NVME_DSMGMT_AD = 1 << 2, 938 }; 939 940 #define NVME_DSM_MAX_RANGES 256 941 942 struct nvme_dsm_range { 943 __le32 cattr; 944 __le32 nlb; 945 __le64 slba; 946 }; 947 948 struct nvme_write_zeroes_cmd { 949 __u8 opcode; 950 __u8 flags; 951 __u16 command_id; 952 __le32 nsid; 953 __u64 rsvd2; 954 __le64 metadata; 955 union nvme_data_ptr dptr; 956 __le64 slba; 957 __le16 length; 958 __le16 control; 959 __le32 dsmgmt; 960 __le32 reftag; 961 __le16 apptag; 962 __le16 appmask; 963 }; 964 965 enum nvme_zone_mgmt_action { 966 NVME_ZONE_CLOSE = 0x1, 967 NVME_ZONE_FINISH = 0x2, 968 NVME_ZONE_OPEN = 0x3, 969 NVME_ZONE_RESET = 0x4, 970 NVME_ZONE_OFFLINE = 0x5, 971 NVME_ZONE_SET_DESC_EXT = 0x10, 972 }; 973 974 struct nvme_zone_mgmt_send_cmd { 975 __u8 opcode; 976 __u8 flags; 977 __u16 command_id; 978 __le32 nsid; 979 __le32 cdw2[2]; 980 __le64 metadata; 981 union nvme_data_ptr dptr; 982 __le64 slba; 983 __le32 cdw12; 984 __u8 zsa; 985 __u8 select_all; 986 __u8 rsvd13[2]; 987 __le32 cdw14[2]; 988 }; 989 990 struct nvme_zone_mgmt_recv_cmd { 991 __u8 opcode; 992 __u8 flags; 993 __u16 command_id; 994 __le32 nsid; 995 __le64 rsvd2[2]; 996 union nvme_data_ptr dptr; 997 __le64 slba; 998 __le32 numd; 999 __u8 zra; 1000 __u8 zrasf; 1001 __u8 pr; 1002 __u8 rsvd13; 1003 __le32 cdw14[2]; 1004 }; 1005 1006 enum { 1007 NVME_ZRA_ZONE_REPORT = 0, 1008 NVME_ZRASF_ZONE_REPORT_ALL = 0, 1009 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, 1010 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, 1011 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, 1012 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, 1013 NVME_ZRASF_ZONE_STATE_READONLY = 0x05, 1014 NVME_ZRASF_ZONE_STATE_FULL = 0x06, 1015 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, 1016 NVME_REPORT_ZONE_PARTIAL = 1, 1017 }; 1018 1019 /* Features */ 1020 1021 enum { 1022 NVME_TEMP_THRESH_MASK = 0xffff, 1023 NVME_TEMP_THRESH_SELECT_SHIFT = 16, 1024 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, 1025 }; 1026 1027 struct nvme_feat_auto_pst { 1028 __le64 entries[32]; 1029 }; 1030 1031 enum { 1032 NVME_HOST_MEM_ENABLE = (1 << 0), 1033 NVME_HOST_MEM_RETURN = (1 << 1), 1034 }; 1035 1036 struct nvme_feat_host_behavior { 1037 __u8 acre; 1038 __u8 etdas; 1039 __u8 lbafee; 1040 __u8 resv1[509]; 1041 }; 1042 1043 enum { 1044 NVME_ENABLE_ACRE = 1, 1045 NVME_ENABLE_LBAFEE = 1, 1046 }; 1047 1048 /* Admin commands */ 1049 1050 enum nvme_admin_opcode { 1051 nvme_admin_delete_sq = 0x00, 1052 nvme_admin_create_sq = 0x01, 1053 nvme_admin_get_log_page = 0x02, 1054 nvme_admin_delete_cq = 0x04, 1055 nvme_admin_create_cq = 0x05, 1056 nvme_admin_identify = 0x06, 1057 nvme_admin_abort_cmd = 0x08, 1058 nvme_admin_set_features = 0x09, 1059 nvme_admin_get_features = 0x0a, 1060 nvme_admin_async_event = 0x0c, 1061 nvme_admin_ns_mgmt = 0x0d, 1062 nvme_admin_activate_fw = 0x10, 1063 nvme_admin_download_fw = 0x11, 1064 nvme_admin_dev_self_test = 0x14, 1065 nvme_admin_ns_attach = 0x15, 1066 nvme_admin_keep_alive = 0x18, 1067 nvme_admin_directive_send = 0x19, 1068 nvme_admin_directive_recv = 0x1a, 1069 nvme_admin_virtual_mgmt = 0x1c, 1070 nvme_admin_nvme_mi_send = 0x1d, 1071 nvme_admin_nvme_mi_recv = 0x1e, 1072 nvme_admin_dbbuf = 0x7C, 1073 nvme_admin_format_nvm = 0x80, 1074 nvme_admin_security_send = 0x81, 1075 nvme_admin_security_recv = 0x82, 1076 nvme_admin_sanitize_nvm = 0x84, 1077 nvme_admin_get_lba_status = 0x86, 1078 nvme_admin_vendor_start = 0xC0, 1079 }; 1080 1081 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 1082 #define show_admin_opcode_name(val) \ 1083 __print_symbolic(val, \ 1084 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 1085 nvme_admin_opcode_name(nvme_admin_create_sq), \ 1086 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 1087 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 1088 nvme_admin_opcode_name(nvme_admin_create_cq), \ 1089 nvme_admin_opcode_name(nvme_admin_identify), \ 1090 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 1091 nvme_admin_opcode_name(nvme_admin_set_features), \ 1092 nvme_admin_opcode_name(nvme_admin_get_features), \ 1093 nvme_admin_opcode_name(nvme_admin_async_event), \ 1094 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 1095 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 1096 nvme_admin_opcode_name(nvme_admin_download_fw), \ 1097 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 1098 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 1099 nvme_admin_opcode_name(nvme_admin_directive_send), \ 1100 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 1101 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 1102 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 1103 nvme_admin_opcode_name(nvme_admin_security_send), \ 1104 nvme_admin_opcode_name(nvme_admin_security_recv), \ 1105 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 1106 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 1107 1108 enum { 1109 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 1110 NVME_CQ_IRQ_ENABLED = (1 << 1), 1111 NVME_SQ_PRIO_URGENT = (0 << 1), 1112 NVME_SQ_PRIO_HIGH = (1 << 1), 1113 NVME_SQ_PRIO_MEDIUM = (2 << 1), 1114 NVME_SQ_PRIO_LOW = (3 << 1), 1115 NVME_FEAT_ARBITRATION = 0x01, 1116 NVME_FEAT_POWER_MGMT = 0x02, 1117 NVME_FEAT_LBA_RANGE = 0x03, 1118 NVME_FEAT_TEMP_THRESH = 0x04, 1119 NVME_FEAT_ERR_RECOVERY = 0x05, 1120 NVME_FEAT_VOLATILE_WC = 0x06, 1121 NVME_FEAT_NUM_QUEUES = 0x07, 1122 NVME_FEAT_IRQ_COALESCE = 0x08, 1123 NVME_FEAT_IRQ_CONFIG = 0x09, 1124 NVME_FEAT_WRITE_ATOMIC = 0x0a, 1125 NVME_FEAT_ASYNC_EVENT = 0x0b, 1126 NVME_FEAT_AUTO_PST = 0x0c, 1127 NVME_FEAT_HOST_MEM_BUF = 0x0d, 1128 NVME_FEAT_TIMESTAMP = 0x0e, 1129 NVME_FEAT_KATO = 0x0f, 1130 NVME_FEAT_HCTM = 0x10, 1131 NVME_FEAT_NOPSC = 0x11, 1132 NVME_FEAT_RRL = 0x12, 1133 NVME_FEAT_PLM_CONFIG = 0x13, 1134 NVME_FEAT_PLM_WINDOW = 0x14, 1135 NVME_FEAT_HOST_BEHAVIOR = 0x16, 1136 NVME_FEAT_SANITIZE = 0x17, 1137 NVME_FEAT_SW_PROGRESS = 0x80, 1138 NVME_FEAT_HOST_ID = 0x81, 1139 NVME_FEAT_RESV_MASK = 0x82, 1140 NVME_FEAT_RESV_PERSIST = 0x83, 1141 NVME_FEAT_WRITE_PROTECT = 0x84, 1142 NVME_FEAT_VENDOR_START = 0xC0, 1143 NVME_FEAT_VENDOR_END = 0xFF, 1144 NVME_LOG_ERROR = 0x01, 1145 NVME_LOG_SMART = 0x02, 1146 NVME_LOG_FW_SLOT = 0x03, 1147 NVME_LOG_CHANGED_NS = 0x04, 1148 NVME_LOG_CMD_EFFECTS = 0x05, 1149 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1150 NVME_LOG_TELEMETRY_HOST = 0x07, 1151 NVME_LOG_TELEMETRY_CTRL = 0x08, 1152 NVME_LOG_ENDURANCE_GROUP = 0x09, 1153 NVME_LOG_ANA = 0x0c, 1154 NVME_LOG_DISC = 0x70, 1155 NVME_LOG_RESERVATION = 0x80, 1156 NVME_FWACT_REPL = (0 << 3), 1157 NVME_FWACT_REPL_ACTV = (1 << 3), 1158 NVME_FWACT_ACTV = (2 << 3), 1159 }; 1160 1161 /* NVMe Namespace Write Protect State */ 1162 enum { 1163 NVME_NS_NO_WRITE_PROTECT = 0, 1164 NVME_NS_WRITE_PROTECT, 1165 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 1166 NVME_NS_WRITE_PROTECT_PERMANENT, 1167 }; 1168 1169 #define NVME_MAX_CHANGED_NAMESPACES 1024 1170 1171 struct nvme_identify { 1172 __u8 opcode; 1173 __u8 flags; 1174 __u16 command_id; 1175 __le32 nsid; 1176 __u64 rsvd2[2]; 1177 union nvme_data_ptr dptr; 1178 __u8 cns; 1179 __u8 rsvd3; 1180 __le16 ctrlid; 1181 __u8 rsvd11[3]; 1182 __u8 csi; 1183 __u32 rsvd12[4]; 1184 }; 1185 1186 #define NVME_IDENTIFY_DATA_SIZE 4096 1187 1188 struct nvme_features { 1189 __u8 opcode; 1190 __u8 flags; 1191 __u16 command_id; 1192 __le32 nsid; 1193 __u64 rsvd2[2]; 1194 union nvme_data_ptr dptr; 1195 __le32 fid; 1196 __le32 dword11; 1197 __le32 dword12; 1198 __le32 dword13; 1199 __le32 dword14; 1200 __le32 dword15; 1201 }; 1202 1203 struct nvme_host_mem_buf_desc { 1204 __le64 addr; 1205 __le32 size; 1206 __u32 rsvd; 1207 }; 1208 1209 struct nvme_create_cq { 1210 __u8 opcode; 1211 __u8 flags; 1212 __u16 command_id; 1213 __u32 rsvd1[5]; 1214 __le64 prp1; 1215 __u64 rsvd8; 1216 __le16 cqid; 1217 __le16 qsize; 1218 __le16 cq_flags; 1219 __le16 irq_vector; 1220 __u32 rsvd12[4]; 1221 }; 1222 1223 struct nvme_create_sq { 1224 __u8 opcode; 1225 __u8 flags; 1226 __u16 command_id; 1227 __u32 rsvd1[5]; 1228 __le64 prp1; 1229 __u64 rsvd8; 1230 __le16 sqid; 1231 __le16 qsize; 1232 __le16 sq_flags; 1233 __le16 cqid; 1234 __u32 rsvd12[4]; 1235 }; 1236 1237 struct nvme_delete_queue { 1238 __u8 opcode; 1239 __u8 flags; 1240 __u16 command_id; 1241 __u32 rsvd1[9]; 1242 __le16 qid; 1243 __u16 rsvd10; 1244 __u32 rsvd11[5]; 1245 }; 1246 1247 struct nvme_abort_cmd { 1248 __u8 opcode; 1249 __u8 flags; 1250 __u16 command_id; 1251 __u32 rsvd1[9]; 1252 __le16 sqid; 1253 __u16 cid; 1254 __u32 rsvd11[5]; 1255 }; 1256 1257 struct nvme_download_firmware { 1258 __u8 opcode; 1259 __u8 flags; 1260 __u16 command_id; 1261 __u32 rsvd1[5]; 1262 union nvme_data_ptr dptr; 1263 __le32 numd; 1264 __le32 offset; 1265 __u32 rsvd12[4]; 1266 }; 1267 1268 struct nvme_format_cmd { 1269 __u8 opcode; 1270 __u8 flags; 1271 __u16 command_id; 1272 __le32 nsid; 1273 __u64 rsvd2[4]; 1274 __le32 cdw10; 1275 __u32 rsvd11[5]; 1276 }; 1277 1278 struct nvme_get_log_page_command { 1279 __u8 opcode; 1280 __u8 flags; 1281 __u16 command_id; 1282 __le32 nsid; 1283 __u64 rsvd2[2]; 1284 union nvme_data_ptr dptr; 1285 __u8 lid; 1286 __u8 lsp; /* upper 4 bits reserved */ 1287 __le16 numdl; 1288 __le16 numdu; 1289 __u16 rsvd11; 1290 union { 1291 struct { 1292 __le32 lpol; 1293 __le32 lpou; 1294 }; 1295 __le64 lpo; 1296 }; 1297 __u8 rsvd14[3]; 1298 __u8 csi; 1299 __u32 rsvd15; 1300 }; 1301 1302 struct nvme_directive_cmd { 1303 __u8 opcode; 1304 __u8 flags; 1305 __u16 command_id; 1306 __le32 nsid; 1307 __u64 rsvd2[2]; 1308 union nvme_data_ptr dptr; 1309 __le32 numd; 1310 __u8 doper; 1311 __u8 dtype; 1312 __le16 dspec; 1313 __u8 endir; 1314 __u8 tdtype; 1315 __u16 rsvd15; 1316 1317 __u32 rsvd16[3]; 1318 }; 1319 1320 /* 1321 * Fabrics subcommands. 1322 */ 1323 enum nvmf_fabrics_opcode { 1324 nvme_fabrics_command = 0x7f, 1325 }; 1326 1327 enum nvmf_capsule_command { 1328 nvme_fabrics_type_property_set = 0x00, 1329 nvme_fabrics_type_connect = 0x01, 1330 nvme_fabrics_type_property_get = 0x04, 1331 }; 1332 1333 #define nvme_fabrics_type_name(type) { type, #type } 1334 #define show_fabrics_type_name(type) \ 1335 __print_symbolic(type, \ 1336 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1337 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1338 nvme_fabrics_type_name(nvme_fabrics_type_property_get)) 1339 1340 /* 1341 * If not fabrics command, fctype will be ignored. 1342 */ 1343 #define show_opcode_name(qid, opcode, fctype) \ 1344 ((opcode) == nvme_fabrics_command ? \ 1345 show_fabrics_type_name(fctype) : \ 1346 ((qid) ? \ 1347 show_nvm_opcode_name(opcode) : \ 1348 show_admin_opcode_name(opcode))) 1349 1350 struct nvmf_common_command { 1351 __u8 opcode; 1352 __u8 resv1; 1353 __u16 command_id; 1354 __u8 fctype; 1355 __u8 resv2[35]; 1356 __u8 ts[24]; 1357 }; 1358 1359 /* 1360 * The legal cntlid range a NVMe Target will provide. 1361 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1362 * Devices based on earlier specs did not have the subsystem concept; 1363 * therefore, those devices had their cntlid value set to 0 as a result. 1364 */ 1365 #define NVME_CNTLID_MIN 1 1366 #define NVME_CNTLID_MAX 0xffef 1367 #define NVME_CNTLID_DYNAMIC 0xffff 1368 1369 #define MAX_DISC_LOGS 255 1370 1371 /* Discovery log page entry flags (EFLAGS): */ 1372 enum { 1373 NVME_DISC_EFLAGS_EPCSD = (1 << 1), 1374 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0), 1375 }; 1376 1377 /* Discovery log page entry */ 1378 struct nvmf_disc_rsp_page_entry { 1379 __u8 trtype; 1380 __u8 adrfam; 1381 __u8 subtype; 1382 __u8 treq; 1383 __le16 portid; 1384 __le16 cntlid; 1385 __le16 asqsz; 1386 __le16 eflags; 1387 __u8 resv10[20]; 1388 char trsvcid[NVMF_TRSVCID_SIZE]; 1389 __u8 resv64[192]; 1390 char subnqn[NVMF_NQN_FIELD_LEN]; 1391 char traddr[NVMF_TRADDR_SIZE]; 1392 union tsas { 1393 char common[NVMF_TSAS_SIZE]; 1394 struct rdma { 1395 __u8 qptype; 1396 __u8 prtype; 1397 __u8 cms; 1398 __u8 resv3[5]; 1399 __u16 pkey; 1400 __u8 resv10[246]; 1401 } rdma; 1402 } tsas; 1403 }; 1404 1405 /* Discovery log page header */ 1406 struct nvmf_disc_rsp_page_hdr { 1407 __le64 genctr; 1408 __le64 numrec; 1409 __le16 recfmt; 1410 __u8 resv14[1006]; 1411 struct nvmf_disc_rsp_page_entry entries[]; 1412 }; 1413 1414 enum { 1415 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1416 }; 1417 1418 struct nvmf_connect_command { 1419 __u8 opcode; 1420 __u8 resv1; 1421 __u16 command_id; 1422 __u8 fctype; 1423 __u8 resv2[19]; 1424 union nvme_data_ptr dptr; 1425 __le16 recfmt; 1426 __le16 qid; 1427 __le16 sqsize; 1428 __u8 cattr; 1429 __u8 resv3; 1430 __le32 kato; 1431 __u8 resv4[12]; 1432 }; 1433 1434 struct nvmf_connect_data { 1435 uuid_t hostid; 1436 __le16 cntlid; 1437 char resv4[238]; 1438 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1439 char hostnqn[NVMF_NQN_FIELD_LEN]; 1440 char resv5[256]; 1441 }; 1442 1443 struct nvmf_property_set_command { 1444 __u8 opcode; 1445 __u8 resv1; 1446 __u16 command_id; 1447 __u8 fctype; 1448 __u8 resv2[35]; 1449 __u8 attrib; 1450 __u8 resv3[3]; 1451 __le32 offset; 1452 __le64 value; 1453 __u8 resv4[8]; 1454 }; 1455 1456 struct nvmf_property_get_command { 1457 __u8 opcode; 1458 __u8 resv1; 1459 __u16 command_id; 1460 __u8 fctype; 1461 __u8 resv2[35]; 1462 __u8 attrib; 1463 __u8 resv3[3]; 1464 __le32 offset; 1465 __u8 resv4[16]; 1466 }; 1467 1468 struct nvme_dbbuf { 1469 __u8 opcode; 1470 __u8 flags; 1471 __u16 command_id; 1472 __u32 rsvd1[5]; 1473 __le64 prp1; 1474 __le64 prp2; 1475 __u32 rsvd12[6]; 1476 }; 1477 1478 struct streams_directive_params { 1479 __le16 msl; 1480 __le16 nssa; 1481 __le16 nsso; 1482 __u8 rsvd[10]; 1483 __le32 sws; 1484 __le16 sgs; 1485 __le16 nsa; 1486 __le16 nso; 1487 __u8 rsvd2[6]; 1488 }; 1489 1490 struct nvme_command { 1491 union { 1492 struct nvme_common_command common; 1493 struct nvme_rw_command rw; 1494 struct nvme_identify identify; 1495 struct nvme_features features; 1496 struct nvme_create_cq create_cq; 1497 struct nvme_create_sq create_sq; 1498 struct nvme_delete_queue delete_queue; 1499 struct nvme_download_firmware dlfw; 1500 struct nvme_format_cmd format; 1501 struct nvme_dsm_cmd dsm; 1502 struct nvme_write_zeroes_cmd write_zeroes; 1503 struct nvme_zone_mgmt_send_cmd zms; 1504 struct nvme_zone_mgmt_recv_cmd zmr; 1505 struct nvme_abort_cmd abort; 1506 struct nvme_get_log_page_command get_log_page; 1507 struct nvmf_common_command fabrics; 1508 struct nvmf_connect_command connect; 1509 struct nvmf_property_set_command prop_set; 1510 struct nvmf_property_get_command prop_get; 1511 struct nvme_dbbuf dbbuf; 1512 struct nvme_directive_cmd directive; 1513 }; 1514 }; 1515 1516 static inline bool nvme_is_fabrics(struct nvme_command *cmd) 1517 { 1518 return cmd->common.opcode == nvme_fabrics_command; 1519 } 1520 1521 struct nvme_error_slot { 1522 __le64 error_count; 1523 __le16 sqid; 1524 __le16 cmdid; 1525 __le16 status_field; 1526 __le16 param_error_location; 1527 __le64 lba; 1528 __le32 nsid; 1529 __u8 vs; 1530 __u8 resv[3]; 1531 __le64 cs; 1532 __u8 resv2[24]; 1533 }; 1534 1535 static inline bool nvme_is_write(struct nvme_command *cmd) 1536 { 1537 /* 1538 * What a mess... 1539 * 1540 * Why can't we simply have a Fabrics In and Fabrics out command? 1541 */ 1542 if (unlikely(nvme_is_fabrics(cmd))) 1543 return cmd->fabrics.fctype & 1; 1544 return cmd->common.opcode & 1; 1545 } 1546 1547 enum { 1548 /* 1549 * Generic Command Status: 1550 */ 1551 NVME_SC_SUCCESS = 0x0, 1552 NVME_SC_INVALID_OPCODE = 0x1, 1553 NVME_SC_INVALID_FIELD = 0x2, 1554 NVME_SC_CMDID_CONFLICT = 0x3, 1555 NVME_SC_DATA_XFER_ERROR = 0x4, 1556 NVME_SC_POWER_LOSS = 0x5, 1557 NVME_SC_INTERNAL = 0x6, 1558 NVME_SC_ABORT_REQ = 0x7, 1559 NVME_SC_ABORT_QUEUE = 0x8, 1560 NVME_SC_FUSED_FAIL = 0x9, 1561 NVME_SC_FUSED_MISSING = 0xa, 1562 NVME_SC_INVALID_NS = 0xb, 1563 NVME_SC_CMD_SEQ_ERROR = 0xc, 1564 NVME_SC_SGL_INVALID_LAST = 0xd, 1565 NVME_SC_SGL_INVALID_COUNT = 0xe, 1566 NVME_SC_SGL_INVALID_DATA = 0xf, 1567 NVME_SC_SGL_INVALID_METADATA = 0x10, 1568 NVME_SC_SGL_INVALID_TYPE = 0x11, 1569 NVME_SC_CMB_INVALID_USE = 0x12, 1570 NVME_SC_PRP_INVALID_OFFSET = 0x13, 1571 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, 1572 NVME_SC_OP_DENIED = 0x15, 1573 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1574 NVME_SC_RESERVED = 0x17, 1575 NVME_SC_HOST_ID_INCONSIST = 0x18, 1576 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, 1577 NVME_SC_KA_TIMEOUT_INVALID = 0x1A, 1578 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, 1579 NVME_SC_SANITIZE_FAILED = 0x1C, 1580 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, 1581 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, 1582 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, 1583 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1584 NVME_SC_CMD_INTERRUPTED = 0x21, 1585 NVME_SC_TRANSIENT_TR_ERR = 0x22, 1586 NVME_SC_INVALID_IO_CMD_SET = 0x2C, 1587 1588 NVME_SC_LBA_RANGE = 0x80, 1589 NVME_SC_CAP_EXCEEDED = 0x81, 1590 NVME_SC_NS_NOT_READY = 0x82, 1591 NVME_SC_RESERVATION_CONFLICT = 0x83, 1592 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 1593 1594 /* 1595 * Command Specific Status: 1596 */ 1597 NVME_SC_CQ_INVALID = 0x100, 1598 NVME_SC_QID_INVALID = 0x101, 1599 NVME_SC_QUEUE_SIZE = 0x102, 1600 NVME_SC_ABORT_LIMIT = 0x103, 1601 NVME_SC_ABORT_MISSING = 0x104, 1602 NVME_SC_ASYNC_LIMIT = 0x105, 1603 NVME_SC_FIRMWARE_SLOT = 0x106, 1604 NVME_SC_FIRMWARE_IMAGE = 0x107, 1605 NVME_SC_INVALID_VECTOR = 0x108, 1606 NVME_SC_INVALID_LOG_PAGE = 0x109, 1607 NVME_SC_INVALID_FORMAT = 0x10a, 1608 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1609 NVME_SC_INVALID_QUEUE = 0x10c, 1610 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1611 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1612 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1613 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1614 NVME_SC_FW_NEEDS_RESET = 0x111, 1615 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1616 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1617 NVME_SC_OVERLAPPING_RANGE = 0x114, 1618 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1619 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1620 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1621 NVME_SC_NS_IS_PRIVATE = 0x119, 1622 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1623 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1624 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1625 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, 1626 NVME_SC_BP_WRITE_PROHIBITED = 0x11e, 1627 NVME_SC_CTRL_ID_INVALID = 0x11f, 1628 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, 1629 NVME_SC_CTRL_RES_NUM_INVALID = 0x121, 1630 NVME_SC_RES_ID_INVALID = 0x122, 1631 NVME_SC_PMR_SAN_PROHIBITED = 0x123, 1632 NVME_SC_ANA_GROUP_ID_INVALID = 0x124, 1633 NVME_SC_ANA_ATTACH_FAILED = 0x125, 1634 1635 /* 1636 * I/O Command Set Specific - NVM commands: 1637 */ 1638 NVME_SC_BAD_ATTRIBUTES = 0x180, 1639 NVME_SC_INVALID_PI = 0x181, 1640 NVME_SC_READ_ONLY = 0x182, 1641 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1642 1643 /* 1644 * I/O Command Set Specific - Fabrics commands: 1645 */ 1646 NVME_SC_CONNECT_FORMAT = 0x180, 1647 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1648 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1649 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1650 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1651 1652 NVME_SC_DISCOVERY_RESTART = 0x190, 1653 NVME_SC_AUTH_REQUIRED = 0x191, 1654 1655 /* 1656 * I/O Command Set Specific - Zoned commands: 1657 */ 1658 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, 1659 NVME_SC_ZONE_FULL = 0x1b9, 1660 NVME_SC_ZONE_READ_ONLY = 0x1ba, 1661 NVME_SC_ZONE_OFFLINE = 0x1bb, 1662 NVME_SC_ZONE_INVALID_WRITE = 0x1bc, 1663 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, 1664 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, 1665 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, 1666 1667 /* 1668 * Media and Data Integrity Errors: 1669 */ 1670 NVME_SC_WRITE_FAULT = 0x280, 1671 NVME_SC_READ_ERROR = 0x281, 1672 NVME_SC_GUARD_CHECK = 0x282, 1673 NVME_SC_APPTAG_CHECK = 0x283, 1674 NVME_SC_REFTAG_CHECK = 0x284, 1675 NVME_SC_COMPARE_FAILED = 0x285, 1676 NVME_SC_ACCESS_DENIED = 0x286, 1677 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1678 1679 /* 1680 * Path-related Errors: 1681 */ 1682 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1683 NVME_SC_ANA_INACCESSIBLE = 0x302, 1684 NVME_SC_ANA_TRANSITION = 0x303, 1685 NVME_SC_HOST_PATH_ERROR = 0x370, 1686 NVME_SC_HOST_ABORTED_CMD = 0x371, 1687 1688 NVME_SC_CRD = 0x1800, 1689 NVME_SC_MORE = 0x2000, 1690 NVME_SC_DNR = 0x4000, 1691 }; 1692 1693 struct nvme_completion { 1694 /* 1695 * Used by Admin and Fabrics commands to return data: 1696 */ 1697 union nvme_result { 1698 __le16 u16; 1699 __le32 u32; 1700 __le64 u64; 1701 } result; 1702 __le16 sq_head; /* how much of this queue may be reclaimed */ 1703 __le16 sq_id; /* submission queue that generated this entry */ 1704 __u16 command_id; /* of the command which completed */ 1705 __le16 status; /* did the command fail, and if so, why? */ 1706 }; 1707 1708 #define NVME_VS(major, minor, tertiary) \ 1709 (((major) << 16) | ((minor) << 8) | (tertiary)) 1710 1711 #define NVME_MAJOR(ver) ((ver) >> 16) 1712 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1713 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1714 1715 #endif /* _LINUX_NVME_H */ 1716