1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/bits.h> 11 #include <linux/types.h> 12 #include <linux/uuid.h> 13 14 /* NQN names in commands fields specified one size */ 15 #define NVMF_NQN_FIELD_LEN 256 16 17 /* However the max length of a qualified name is another size */ 18 #define NVMF_NQN_SIZE 223 19 20 #define NVMF_TRSVCID_SIZE 32 21 #define NVMF_TRADDR_SIZE 256 22 #define NVMF_TSAS_SIZE 256 23 24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 25 26 #define NVME_NSID_ALL 0xffffffff 27 28 /* Special NSSR value, 'NVMe' */ 29 #define NVME_SUBSYS_RESET 0x4E564D65 30 31 enum nvme_subsys_type { 32 /* Referral to another discovery type target subsystem */ 33 NVME_NQN_DISC = 1, 34 35 /* NVME type target subsystem */ 36 NVME_NQN_NVME = 2, 37 38 /* Current discovery type target subsystem */ 39 NVME_NQN_CURR = 3, 40 }; 41 42 enum nvme_ctrl_type { 43 NVME_CTRL_IO = 1, /* I/O controller */ 44 NVME_CTRL_DISC = 2, /* Discovery controller */ 45 NVME_CTRL_ADMIN = 3, /* Administrative controller */ 46 }; 47 48 enum nvme_dctype { 49 NVME_DCTYPE_NOT_REPORTED = 0, 50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */ 51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */ 52 }; 53 54 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 55 enum { 56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ 62 NVMF_ADDR_FAMILY_MAX, 63 }; 64 65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 66 enum { 67 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 71 NVMF_TRTYPE_MAX, 72 }; 73 74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 75 enum { 76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 77 NVMF_TREQ_REQUIRED = 1, /* Required */ 78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 79 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 81 82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 83 }; 84 85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 86 * RDMA_QPTYPE field 87 */ 88 enum { 89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 91 NVMF_RDMA_QPTYPE_INVALID = 0xff, 92 }; 93 94 /* RDMA Provider Type codes for Discovery Log Page entry TSAS 95 * RDMA_PRTYPE field 96 */ 97 enum { 98 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 99 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 100 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 101 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 102 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 103 }; 104 105 /* RDMA Connection Management Service Type codes for Discovery Log Page 106 * entry TSAS RDMA_CMS field 107 */ 108 enum { 109 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 110 }; 111 112 /* TSAS SECTYPE for TCP transport */ 113 enum { 114 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */ 115 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 116 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 117 NVMF_TCP_SECTYPE_INVALID = 0xff, 118 }; 119 120 #define NVME_AQ_DEPTH 32 121 #define NVME_NR_AEN_COMMANDS 1 122 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 123 124 /* 125 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 126 * NVM-Express 1.2 specification, section 4.1.2. 127 */ 128 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 129 130 enum { 131 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 132 NVME_REG_VS = 0x0008, /* Version */ 133 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 134 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 135 NVME_REG_CC = 0x0014, /* Controller Configuration */ 136 NVME_REG_CSTS = 0x001c, /* Controller Status */ 137 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 138 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 139 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 140 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 141 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 142 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 143 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ 144 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ 145 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer 146 * Location 147 */ 148 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory 149 * Space Control 150 */ 151 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */ 152 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ 153 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ 154 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ 155 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity 156 * Buffer Size 157 */ 158 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained 159 * Write Throughput 160 */ 161 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 162 }; 163 164 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 165 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 166 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 167 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 168 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) 169 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 170 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 171 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) 172 173 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 174 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 175 176 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16) 177 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff) 178 179 enum { 180 NVME_CMBSZ_SQS = 1 << 0, 181 NVME_CMBSZ_CQS = 1 << 1, 182 NVME_CMBSZ_LISTS = 1 << 2, 183 NVME_CMBSZ_RDS = 1 << 3, 184 NVME_CMBSZ_WDS = 1 << 4, 185 186 NVME_CMBSZ_SZ_SHIFT = 12, 187 NVME_CMBSZ_SZ_MASK = 0xfffff, 188 189 NVME_CMBSZ_SZU_SHIFT = 8, 190 NVME_CMBSZ_SZU_MASK = 0xf, 191 }; 192 193 /* 194 * Submission and Completion Queue Entry Sizes for the NVM command set. 195 * (In bytes and specified as a power of two (2^n)). 196 */ 197 #define NVME_ADM_SQES 6 198 #define NVME_NVM_IOSQES 6 199 #define NVME_NVM_IOCQES 4 200 201 enum { 202 NVME_CC_ENABLE = 1 << 0, 203 NVME_CC_EN_SHIFT = 0, 204 NVME_CC_CSS_SHIFT = 4, 205 NVME_CC_MPS_SHIFT = 7, 206 NVME_CC_AMS_SHIFT = 11, 207 NVME_CC_SHN_SHIFT = 14, 208 NVME_CC_IOSQES_SHIFT = 16, 209 NVME_CC_IOCQES_SHIFT = 20, 210 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, 211 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, 212 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, 213 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 214 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 215 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 216 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 217 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 218 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 219 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 220 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 221 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 222 NVME_CC_CRIME = 1 << 24, 223 }; 224 225 enum { 226 NVME_CSTS_RDY = 1 << 0, 227 NVME_CSTS_CFS = 1 << 1, 228 NVME_CSTS_NSSRO = 1 << 4, 229 NVME_CSTS_PP = 1 << 5, 230 NVME_CSTS_SHST_NORMAL = 0 << 2, 231 NVME_CSTS_SHST_OCCUR = 1 << 2, 232 NVME_CSTS_SHST_CMPLT = 2 << 2, 233 NVME_CSTS_SHST_MASK = 3 << 2, 234 }; 235 236 enum { 237 NVME_CMBMSC_CRE = 1 << 0, 238 NVME_CMBMSC_CMSE = 1 << 1, 239 }; 240 241 enum { 242 NVME_CAP_CSS_NVM = 1 << 0, 243 NVME_CAP_CSS_CSI = 1 << 6, 244 }; 245 246 enum { 247 NVME_CAP_CRMS_CRWMS = 1ULL << 59, 248 NVME_CAP_CRMS_CRIMS = 1ULL << 60, 249 }; 250 251 struct nvme_id_power_state { 252 __le16 max_power; /* centiwatts */ 253 __u8 rsvd2; 254 __u8 flags; 255 __le32 entry_lat; /* microseconds */ 256 __le32 exit_lat; /* microseconds */ 257 __u8 read_tput; 258 __u8 read_lat; 259 __u8 write_tput; 260 __u8 write_lat; 261 __le16 idle_power; 262 __u8 idle_scale; 263 __u8 rsvd19; 264 __le16 active_power; 265 __u8 active_work_scale; 266 __u8 rsvd23[9]; 267 }; 268 269 enum { 270 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 271 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 272 }; 273 274 enum nvme_ctrl_attr { 275 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 276 NVME_CTRL_ATTR_TBKAS = (1 << 6), 277 NVME_CTRL_ATTR_ELBAS = (1 << 15), 278 }; 279 280 struct nvme_id_ctrl { 281 __le16 vid; 282 __le16 ssvid; 283 char sn[20]; 284 char mn[40]; 285 char fr[8]; 286 __u8 rab; 287 __u8 ieee[3]; 288 __u8 cmic; 289 __u8 mdts; 290 __le16 cntlid; 291 __le32 ver; 292 __le32 rtd3r; 293 __le32 rtd3e; 294 __le32 oaes; 295 __le32 ctratt; 296 __u8 rsvd100[11]; 297 __u8 cntrltype; 298 __u8 fguid[16]; 299 __le16 crdt1; 300 __le16 crdt2; 301 __le16 crdt3; 302 __u8 rsvd134[122]; 303 __le16 oacs; 304 __u8 acl; 305 __u8 aerl; 306 __u8 frmw; 307 __u8 lpa; 308 __u8 elpe; 309 __u8 npss; 310 __u8 avscc; 311 __u8 apsta; 312 __le16 wctemp; 313 __le16 cctemp; 314 __le16 mtfa; 315 __le32 hmpre; 316 __le32 hmmin; 317 __u8 tnvmcap[16]; 318 __u8 unvmcap[16]; 319 __le32 rpmbs; 320 __le16 edstt; 321 __u8 dsto; 322 __u8 fwug; 323 __le16 kas; 324 __le16 hctma; 325 __le16 mntmt; 326 __le16 mxtmt; 327 __le32 sanicap; 328 __le32 hmminds; 329 __le16 hmmaxd; 330 __le16 nvmsetidmax; 331 __le16 endgidmax; 332 __u8 anatt; 333 __u8 anacap; 334 __le32 anagrpmax; 335 __le32 nanagrpid; 336 __u8 rsvd352[160]; 337 __u8 sqes; 338 __u8 cqes; 339 __le16 maxcmd; 340 __le32 nn; 341 __le16 oncs; 342 __le16 fuses; 343 __u8 fna; 344 __u8 vwc; 345 __le16 awun; 346 __le16 awupf; 347 __u8 nvscc; 348 __u8 nwpc; 349 __le16 acwu; 350 __u8 rsvd534[2]; 351 __le32 sgls; 352 __le32 mnan; 353 __u8 rsvd544[224]; 354 char subnqn[256]; 355 __u8 rsvd1024[768]; 356 __le32 ioccsz; 357 __le32 iorcsz; 358 __le16 icdoff; 359 __u8 ctrattr; 360 __u8 msdbd; 361 __u8 rsvd1804[2]; 362 __u8 dctype; 363 __u8 rsvd1807[241]; 364 struct nvme_id_power_state psd[32]; 365 __u8 vs[1024]; 366 }; 367 368 enum { 369 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, 370 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, 371 NVME_CTRL_CMIC_ANA = 1 << 3, 372 NVME_CTRL_ONCS_COMPARE = 1 << 0, 373 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 374 NVME_CTRL_ONCS_DSM = 1 << 2, 375 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 376 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, 377 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 378 NVME_CTRL_VWC_PRESENT = 1 << 0, 379 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 380 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, 381 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 382 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 383 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 384 NVME_CTRL_CTRATT_128_ID = 1 << 0, 385 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, 386 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, 387 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, 388 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, 389 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, 390 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, 391 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, 392 }; 393 394 struct nvme_lbaf { 395 __le16 ms; 396 __u8 ds; 397 __u8 rp; 398 }; 399 400 struct nvme_id_ns { 401 __le64 nsze; 402 __le64 ncap; 403 __le64 nuse; 404 __u8 nsfeat; 405 __u8 nlbaf; 406 __u8 flbas; 407 __u8 mc; 408 __u8 dpc; 409 __u8 dps; 410 __u8 nmic; 411 __u8 rescap; 412 __u8 fpi; 413 __u8 dlfeat; 414 __le16 nawun; 415 __le16 nawupf; 416 __le16 nacwu; 417 __le16 nabsn; 418 __le16 nabo; 419 __le16 nabspf; 420 __le16 noiob; 421 __u8 nvmcap[16]; 422 __le16 npwg; 423 __le16 npwa; 424 __le16 npdg; 425 __le16 npda; 426 __le16 nows; 427 __u8 rsvd74[18]; 428 __le32 anagrpid; 429 __u8 rsvd96[3]; 430 __u8 nsattr; 431 __le16 nvmsetid; 432 __le16 endgid; 433 __u8 nguid[16]; 434 __u8 eui64[8]; 435 struct nvme_lbaf lbaf[64]; 436 __u8 vs[3712]; 437 }; 438 439 /* I/O Command Set Independent Identify Namespace Data Structure */ 440 struct nvme_id_ns_cs_indep { 441 __u8 nsfeat; 442 __u8 nmic; 443 __u8 rescap; 444 __u8 fpi; 445 __le32 anagrpid; 446 __u8 nsattr; 447 __u8 rsvd9; 448 __le16 nvmsetid; 449 __le16 endgid; 450 __u8 nstat; 451 __u8 rsvd15[4081]; 452 }; 453 454 struct nvme_zns_lbafe { 455 __le64 zsze; 456 __u8 zdes; 457 __u8 rsvd9[7]; 458 }; 459 460 struct nvme_id_ns_zns { 461 __le16 zoc; 462 __le16 ozcs; 463 __le32 mar; 464 __le32 mor; 465 __le32 rrl; 466 __le32 frl; 467 __u8 rsvd20[2796]; 468 struct nvme_zns_lbafe lbafe[64]; 469 __u8 vs[256]; 470 }; 471 472 struct nvme_id_ctrl_zns { 473 __u8 zasl; 474 __u8 rsvd1[4095]; 475 }; 476 477 struct nvme_id_ns_nvm { 478 __le64 lbstm; 479 __u8 pic; 480 __u8 rsvd9[3]; 481 __le32 elbaf[64]; 482 __u8 rsvd268[3828]; 483 }; 484 485 enum { 486 NVME_ID_NS_NVM_STS_MASK = 0x7f, 487 NVME_ID_NS_NVM_GUARD_SHIFT = 7, 488 NVME_ID_NS_NVM_GUARD_MASK = 0x3, 489 NVME_ID_NS_NVM_QPIF_SHIFT = 9, 490 NVME_ID_NS_NVM_QPIF_MASK = 0xf, 491 NVME_ID_NS_NVM_QPIFS = 1 << 3, 492 }; 493 494 static inline __u8 nvme_elbaf_sts(__u32 elbaf) 495 { 496 return elbaf & NVME_ID_NS_NVM_STS_MASK; 497 } 498 499 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf) 500 { 501 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK; 502 } 503 504 static inline __u8 nvme_elbaf_qualified_guard_type(__u32 elbaf) 505 { 506 return (elbaf >> NVME_ID_NS_NVM_QPIF_SHIFT) & NVME_ID_NS_NVM_QPIF_MASK; 507 } 508 509 struct nvme_id_ctrl_nvm { 510 __u8 vsl; 511 __u8 wzsl; 512 __u8 wusl; 513 __u8 dmrl; 514 __le32 dmrsl; 515 __le64 dmsl; 516 __u8 rsvd16[4080]; 517 }; 518 519 enum { 520 NVME_ID_CNS_NS = 0x00, 521 NVME_ID_CNS_CTRL = 0x01, 522 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 523 NVME_ID_CNS_NS_DESC_LIST = 0x03, 524 NVME_ID_CNS_CS_NS = 0x05, 525 NVME_ID_CNS_CS_CTRL = 0x06, 526 NVME_ID_CNS_NS_ACTIVE_LIST_CS = 0x07, 527 NVME_ID_CNS_NS_CS_INDEP = 0x08, 528 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 529 NVME_ID_CNS_NS_PRESENT = 0x11, 530 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 531 NVME_ID_CNS_CTRL_LIST = 0x13, 532 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, 533 NVME_ID_CNS_NS_GRANULARITY = 0x16, 534 NVME_ID_CNS_UUID_LIST = 0x17, 535 NVME_ID_CNS_ENDGRP_LIST = 0x19, 536 }; 537 538 enum { 539 NVME_CSI_NVM = 0, 540 NVME_CSI_ZNS = 2, 541 }; 542 543 enum { 544 NVME_DIR_IDENTIFY = 0x00, 545 NVME_DIR_STREAMS = 0x01, 546 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 547 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 548 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 549 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 550 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 551 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 552 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 553 NVME_DIR_ENDIR = 0x01, 554 }; 555 556 enum { 557 NVME_NS_FEAT_THIN = 1 << 0, 558 NVME_NS_FEAT_ATOMICS = 1 << 1, 559 NVME_NS_FEAT_IO_OPT = 1 << 4, 560 NVME_NS_ATTR_RO = 1 << 0, 561 NVME_NS_FLBAS_LBA_MASK = 0xf, 562 NVME_NS_FLBAS_LBA_UMASK = 0x60, 563 NVME_NS_FLBAS_LBA_SHIFT = 1, 564 NVME_NS_FLBAS_META_EXT = 0x10, 565 NVME_NS_NMIC_SHARED = 1 << 0, 566 NVME_LBAF_RP_BEST = 0, 567 NVME_LBAF_RP_BETTER = 1, 568 NVME_LBAF_RP_GOOD = 2, 569 NVME_LBAF_RP_DEGRADED = 3, 570 NVME_NS_DPC_PI_LAST = 1 << 4, 571 NVME_NS_DPC_PI_FIRST = 1 << 3, 572 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 573 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 574 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 575 NVME_NS_DPS_PI_FIRST = 1 << 3, 576 NVME_NS_DPS_PI_MASK = 0x7, 577 NVME_NS_DPS_PI_TYPE1 = 1, 578 NVME_NS_DPS_PI_TYPE2 = 2, 579 NVME_NS_DPS_PI_TYPE3 = 3, 580 }; 581 582 enum { 583 NVME_NSTAT_NRDY = 1 << 0, 584 }; 585 586 enum { 587 NVME_NVM_NS_16B_GUARD = 0, 588 NVME_NVM_NS_32B_GUARD = 1, 589 NVME_NVM_NS_64B_GUARD = 2, 590 NVME_NVM_NS_QTYPE_GUARD = 3, 591 }; 592 593 static inline __u8 nvme_lbaf_index(__u8 flbas) 594 { 595 return (flbas & NVME_NS_FLBAS_LBA_MASK) | 596 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT); 597 } 598 599 /* Identify Namespace Metadata Capabilities (MC): */ 600 enum { 601 NVME_MC_EXTENDED_LBA = (1 << 0), 602 NVME_MC_METADATA_PTR = (1 << 1), 603 }; 604 605 struct nvme_ns_id_desc { 606 __u8 nidt; 607 __u8 nidl; 608 __le16 reserved; 609 }; 610 611 #define NVME_NIDT_EUI64_LEN 8 612 #define NVME_NIDT_NGUID_LEN 16 613 #define NVME_NIDT_UUID_LEN 16 614 #define NVME_NIDT_CSI_LEN 1 615 616 enum { 617 NVME_NIDT_EUI64 = 0x01, 618 NVME_NIDT_NGUID = 0x02, 619 NVME_NIDT_UUID = 0x03, 620 NVME_NIDT_CSI = 0x04, 621 }; 622 623 struct nvme_endurance_group_log { 624 __u8 egcw; 625 __u8 egfeat; 626 __u8 rsvd2; 627 __u8 avsp; 628 __u8 avspt; 629 __u8 pused; 630 __le16 did; 631 __u8 rsvd8[24]; 632 __u8 ee[16]; 633 __u8 dur[16]; 634 __u8 duw[16]; 635 __u8 muw[16]; 636 __u8 hrc[16]; 637 __u8 hwc[16]; 638 __u8 mdie[16]; 639 __u8 neile[16]; 640 __u8 tegcap[16]; 641 __u8 uegcap[16]; 642 __u8 rsvd192[320]; 643 }; 644 645 struct nvme_rotational_media_log { 646 __le16 endgid; 647 __le16 numa; 648 __le16 nrs; 649 __u8 rsvd6[2]; 650 __le32 spinc; 651 __le32 fspinc; 652 __le32 ldc; 653 __le32 fldc; 654 __u8 rsvd24[488]; 655 }; 656 657 struct nvme_smart_log { 658 __u8 critical_warning; 659 __u8 temperature[2]; 660 __u8 avail_spare; 661 __u8 spare_thresh; 662 __u8 percent_used; 663 __u8 endu_grp_crit_warn_sumry; 664 __u8 rsvd7[25]; 665 __u8 data_units_read[16]; 666 __u8 data_units_written[16]; 667 __u8 host_reads[16]; 668 __u8 host_writes[16]; 669 __u8 ctrl_busy_time[16]; 670 __u8 power_cycles[16]; 671 __u8 power_on_hours[16]; 672 __u8 unsafe_shutdowns[16]; 673 __u8 media_errors[16]; 674 __u8 num_err_log_entries[16]; 675 __le32 warning_temp_time; 676 __le32 critical_comp_time; 677 __le16 temp_sensor[8]; 678 __le32 thm_temp1_trans_count; 679 __le32 thm_temp2_trans_count; 680 __le32 thm_temp1_total_time; 681 __le32 thm_temp2_total_time; 682 __u8 rsvd232[280]; 683 }; 684 685 struct nvme_fw_slot_info_log { 686 __u8 afi; 687 __u8 rsvd1[7]; 688 __le64 frs[7]; 689 __u8 rsvd64[448]; 690 }; 691 692 enum { 693 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 694 NVME_CMD_EFFECTS_LBCC = 1 << 1, 695 NVME_CMD_EFFECTS_NCC = 1 << 2, 696 NVME_CMD_EFFECTS_NIC = 1 << 3, 697 NVME_CMD_EFFECTS_CCC = 1 << 4, 698 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14), 699 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), 700 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, 701 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20), 702 }; 703 704 struct nvme_effects_log { 705 __le32 acs[256]; 706 __le32 iocs[256]; 707 __u8 resv[2048]; 708 }; 709 710 enum nvme_ana_state { 711 NVME_ANA_OPTIMIZED = 0x01, 712 NVME_ANA_NONOPTIMIZED = 0x02, 713 NVME_ANA_INACCESSIBLE = 0x03, 714 NVME_ANA_PERSISTENT_LOSS = 0x04, 715 NVME_ANA_CHANGE = 0x0f, 716 }; 717 718 struct nvme_ana_group_desc { 719 __le32 grpid; 720 __le32 nnsids; 721 __le64 chgcnt; 722 __u8 state; 723 __u8 rsvd17[15]; 724 __le32 nsids[]; 725 }; 726 727 /* flag for the log specific field of the ANA log */ 728 #define NVME_ANA_LOG_RGO (1 << 0) 729 730 struct nvme_ana_rsp_hdr { 731 __le64 chgcnt; 732 __le16 ngrps; 733 __le16 rsvd10[3]; 734 }; 735 736 struct nvme_zone_descriptor { 737 __u8 zt; 738 __u8 zs; 739 __u8 za; 740 __u8 rsvd3[5]; 741 __le64 zcap; 742 __le64 zslba; 743 __le64 wp; 744 __u8 rsvd32[32]; 745 }; 746 747 enum { 748 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, 749 }; 750 751 struct nvme_zone_report { 752 __le64 nr_zones; 753 __u8 resv8[56]; 754 struct nvme_zone_descriptor entries[]; 755 }; 756 757 enum { 758 NVME_SMART_CRIT_SPARE = 1 << 0, 759 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 760 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 761 NVME_SMART_CRIT_MEDIA = 1 << 3, 762 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 763 }; 764 765 enum { 766 NVME_AER_ERROR = 0, 767 NVME_AER_SMART = 1, 768 NVME_AER_NOTICE = 2, 769 NVME_AER_CSS = 6, 770 NVME_AER_VS = 7, 771 }; 772 773 enum { 774 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03, 775 }; 776 777 enum { 778 NVME_AER_NOTICE_NS_CHANGED = 0x00, 779 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 780 NVME_AER_NOTICE_ANA = 0x03, 781 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 782 }; 783 784 enum { 785 NVME_AEN_BIT_NS_ATTR = 8, 786 NVME_AEN_BIT_FW_ACT = 9, 787 NVME_AEN_BIT_ANA_CHANGE = 11, 788 NVME_AEN_BIT_DISC_CHANGE = 31, 789 }; 790 791 enum { 792 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 793 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 794 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 795 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 796 }; 797 798 struct nvme_lba_range_type { 799 __u8 type; 800 __u8 attributes; 801 __u8 rsvd2[14]; 802 __le64 slba; 803 __le64 nlb; 804 __u8 guid[16]; 805 __u8 rsvd48[16]; 806 }; 807 808 enum { 809 NVME_LBART_TYPE_FS = 0x01, 810 NVME_LBART_TYPE_RAID = 0x02, 811 NVME_LBART_TYPE_CACHE = 0x03, 812 NVME_LBART_TYPE_SWAP = 0x04, 813 814 NVME_LBART_ATTRIB_TEMP = 1 << 0, 815 NVME_LBART_ATTRIB_HIDE = 1 << 1, 816 }; 817 818 enum nvme_pr_type { 819 NVME_PR_WRITE_EXCLUSIVE = 1, 820 NVME_PR_EXCLUSIVE_ACCESS = 2, 821 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3, 822 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4, 823 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5, 824 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6, 825 }; 826 827 enum nvme_eds { 828 NVME_EXTENDED_DATA_STRUCT = 0x1, 829 }; 830 831 struct nvme_registered_ctrl { 832 __le16 cntlid; 833 __u8 rcsts; 834 __u8 rsvd3[5]; 835 __le64 hostid; 836 __le64 rkey; 837 }; 838 839 struct nvme_reservation_status { 840 __le32 gen; 841 __u8 rtype; 842 __u8 regctl[2]; 843 __u8 resv5[2]; 844 __u8 ptpls; 845 __u8 resv10[14]; 846 struct nvme_registered_ctrl regctl_ds[]; 847 }; 848 849 struct nvme_registered_ctrl_ext { 850 __le16 cntlid; 851 __u8 rcsts; 852 __u8 rsvd3[5]; 853 __le64 rkey; 854 __u8 hostid[16]; 855 __u8 rsvd32[32]; 856 }; 857 858 struct nvme_reservation_status_ext { 859 __le32 gen; 860 __u8 rtype; 861 __u8 regctl[2]; 862 __u8 resv5[2]; 863 __u8 ptpls; 864 __u8 resv10[14]; 865 __u8 rsvd24[40]; 866 struct nvme_registered_ctrl_ext regctl_eds[]; 867 }; 868 869 /* I/O commands */ 870 871 enum nvme_opcode { 872 nvme_cmd_flush = 0x00, 873 nvme_cmd_write = 0x01, 874 nvme_cmd_read = 0x02, 875 nvme_cmd_write_uncor = 0x04, 876 nvme_cmd_compare = 0x05, 877 nvme_cmd_write_zeroes = 0x08, 878 nvme_cmd_dsm = 0x09, 879 nvme_cmd_verify = 0x0c, 880 nvme_cmd_resv_register = 0x0d, 881 nvme_cmd_resv_report = 0x0e, 882 nvme_cmd_resv_acquire = 0x11, 883 nvme_cmd_resv_release = 0x15, 884 nvme_cmd_zone_mgmt_send = 0x79, 885 nvme_cmd_zone_mgmt_recv = 0x7a, 886 nvme_cmd_zone_append = 0x7d, 887 nvme_cmd_vendor_start = 0x80, 888 }; 889 890 #define nvme_opcode_name(opcode) { opcode, #opcode } 891 #define show_nvm_opcode_name(val) \ 892 __print_symbolic(val, \ 893 nvme_opcode_name(nvme_cmd_flush), \ 894 nvme_opcode_name(nvme_cmd_write), \ 895 nvme_opcode_name(nvme_cmd_read), \ 896 nvme_opcode_name(nvme_cmd_write_uncor), \ 897 nvme_opcode_name(nvme_cmd_compare), \ 898 nvme_opcode_name(nvme_cmd_write_zeroes), \ 899 nvme_opcode_name(nvme_cmd_dsm), \ 900 nvme_opcode_name(nvme_cmd_verify), \ 901 nvme_opcode_name(nvme_cmd_resv_register), \ 902 nvme_opcode_name(nvme_cmd_resv_report), \ 903 nvme_opcode_name(nvme_cmd_resv_acquire), \ 904 nvme_opcode_name(nvme_cmd_resv_release), \ 905 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ 906 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ 907 nvme_opcode_name(nvme_cmd_zone_append)) 908 909 910 911 /* 912 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 913 * 914 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 915 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 916 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 917 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 918 * request subtype 919 */ 920 enum { 921 NVME_SGL_FMT_ADDRESS = 0x00, 922 NVME_SGL_FMT_OFFSET = 0x01, 923 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 924 NVME_SGL_FMT_INVALIDATE = 0x0f, 925 }; 926 927 /* 928 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 929 * 930 * For struct nvme_sgl_desc: 931 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 932 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 933 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 934 * 935 * For struct nvme_keyed_sgl_desc: 936 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 937 * 938 * Transport-specific SGL types: 939 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 940 */ 941 enum { 942 NVME_SGL_FMT_DATA_DESC = 0x00, 943 NVME_SGL_FMT_SEG_DESC = 0x02, 944 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 945 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 946 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 947 }; 948 949 struct nvme_sgl_desc { 950 __le64 addr; 951 __le32 length; 952 __u8 rsvd[3]; 953 __u8 type; 954 }; 955 956 struct nvme_keyed_sgl_desc { 957 __le64 addr; 958 __u8 length[3]; 959 __u8 key[4]; 960 __u8 type; 961 }; 962 963 union nvme_data_ptr { 964 struct { 965 __le64 prp1; 966 __le64 prp2; 967 }; 968 struct nvme_sgl_desc sgl; 969 struct nvme_keyed_sgl_desc ksgl; 970 }; 971 972 /* 973 * Lowest two bits of our flags field (FUSE field in the spec): 974 * 975 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 976 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 977 * 978 * Highest two bits in our flags field (PSDT field in the spec): 979 * 980 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 981 * If used, MPTR contains addr of single physical buffer (byte aligned). 982 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 983 * If used, MPTR contains an address of an SGL segment containing 984 * exactly 1 SGL descriptor (qword aligned). 985 */ 986 enum { 987 NVME_CMD_FUSE_FIRST = (1 << 0), 988 NVME_CMD_FUSE_SECOND = (1 << 1), 989 990 NVME_CMD_SGL_METABUF = (1 << 6), 991 NVME_CMD_SGL_METASEG = (1 << 7), 992 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 993 }; 994 995 struct nvme_common_command { 996 __u8 opcode; 997 __u8 flags; 998 __u16 command_id; 999 __le32 nsid; 1000 __le32 cdw2[2]; 1001 __le64 metadata; 1002 union nvme_data_ptr dptr; 1003 struct_group(cdws, 1004 __le32 cdw10; 1005 __le32 cdw11; 1006 __le32 cdw12; 1007 __le32 cdw13; 1008 __le32 cdw14; 1009 __le32 cdw15; 1010 ); 1011 }; 1012 1013 struct nvme_rw_command { 1014 __u8 opcode; 1015 __u8 flags; 1016 __u16 command_id; 1017 __le32 nsid; 1018 __le32 cdw2; 1019 __le32 cdw3; 1020 __le64 metadata; 1021 union nvme_data_ptr dptr; 1022 __le64 slba; 1023 __le16 length; 1024 __le16 control; 1025 __le32 dsmgmt; 1026 __le32 reftag; 1027 __le16 lbat; 1028 __le16 lbatm; 1029 }; 1030 1031 enum { 1032 NVME_RW_LR = 1 << 15, 1033 NVME_RW_FUA = 1 << 14, 1034 NVME_RW_APPEND_PIREMAP = 1 << 9, 1035 NVME_RW_DSM_FREQ_UNSPEC = 0, 1036 NVME_RW_DSM_FREQ_TYPICAL = 1, 1037 NVME_RW_DSM_FREQ_RARE = 2, 1038 NVME_RW_DSM_FREQ_READS = 3, 1039 NVME_RW_DSM_FREQ_WRITES = 4, 1040 NVME_RW_DSM_FREQ_RW = 5, 1041 NVME_RW_DSM_FREQ_ONCE = 6, 1042 NVME_RW_DSM_FREQ_PREFETCH = 7, 1043 NVME_RW_DSM_FREQ_TEMP = 8, 1044 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 1045 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 1046 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 1047 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 1048 NVME_RW_DSM_SEQ_REQ = 1 << 6, 1049 NVME_RW_DSM_COMPRESSED = 1 << 7, 1050 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 1051 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 1052 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 1053 NVME_RW_PRINFO_PRACT = 1 << 13, 1054 NVME_RW_DTYPE_STREAMS = 1 << 4, 1055 NVME_WZ_DEAC = 1 << 9, 1056 }; 1057 1058 struct nvme_dsm_cmd { 1059 __u8 opcode; 1060 __u8 flags; 1061 __u16 command_id; 1062 __le32 nsid; 1063 __u64 rsvd2[2]; 1064 union nvme_data_ptr dptr; 1065 __le32 nr; 1066 __le32 attributes; 1067 __u32 rsvd12[4]; 1068 }; 1069 1070 enum { 1071 NVME_DSMGMT_IDR = 1 << 0, 1072 NVME_DSMGMT_IDW = 1 << 1, 1073 NVME_DSMGMT_AD = 1 << 2, 1074 }; 1075 1076 #define NVME_DSM_MAX_RANGES 256 1077 1078 struct nvme_dsm_range { 1079 __le32 cattr; 1080 __le32 nlb; 1081 __le64 slba; 1082 }; 1083 1084 struct nvme_write_zeroes_cmd { 1085 __u8 opcode; 1086 __u8 flags; 1087 __u16 command_id; 1088 __le32 nsid; 1089 __u64 rsvd2; 1090 __le64 metadata; 1091 union nvme_data_ptr dptr; 1092 __le64 slba; 1093 __le16 length; 1094 __le16 control; 1095 __le32 dsmgmt; 1096 __le32 reftag; 1097 __le16 lbat; 1098 __le16 lbatm; 1099 }; 1100 1101 enum nvme_zone_mgmt_action { 1102 NVME_ZONE_CLOSE = 0x1, 1103 NVME_ZONE_FINISH = 0x2, 1104 NVME_ZONE_OPEN = 0x3, 1105 NVME_ZONE_RESET = 0x4, 1106 NVME_ZONE_OFFLINE = 0x5, 1107 NVME_ZONE_SET_DESC_EXT = 0x10, 1108 }; 1109 1110 struct nvme_zone_mgmt_send_cmd { 1111 __u8 opcode; 1112 __u8 flags; 1113 __u16 command_id; 1114 __le32 nsid; 1115 __le32 cdw2[2]; 1116 __le64 metadata; 1117 union nvme_data_ptr dptr; 1118 __le64 slba; 1119 __le32 cdw12; 1120 __u8 zsa; 1121 __u8 select_all; 1122 __u8 rsvd13[2]; 1123 __le32 cdw14[2]; 1124 }; 1125 1126 struct nvme_zone_mgmt_recv_cmd { 1127 __u8 opcode; 1128 __u8 flags; 1129 __u16 command_id; 1130 __le32 nsid; 1131 __le64 rsvd2[2]; 1132 union nvme_data_ptr dptr; 1133 __le64 slba; 1134 __le32 numd; 1135 __u8 zra; 1136 __u8 zrasf; 1137 __u8 pr; 1138 __u8 rsvd13; 1139 __le32 cdw14[2]; 1140 }; 1141 1142 enum { 1143 NVME_ZRA_ZONE_REPORT = 0, 1144 NVME_ZRASF_ZONE_REPORT_ALL = 0, 1145 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, 1146 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, 1147 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, 1148 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, 1149 NVME_ZRASF_ZONE_STATE_READONLY = 0x05, 1150 NVME_ZRASF_ZONE_STATE_FULL = 0x06, 1151 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, 1152 NVME_REPORT_ZONE_PARTIAL = 1, 1153 }; 1154 1155 /* Features */ 1156 1157 enum { 1158 NVME_TEMP_THRESH_MASK = 0xffff, 1159 NVME_TEMP_THRESH_SELECT_SHIFT = 16, 1160 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, 1161 }; 1162 1163 struct nvme_feat_auto_pst { 1164 __le64 entries[32]; 1165 }; 1166 1167 enum { 1168 NVME_HOST_MEM_ENABLE = (1 << 0), 1169 NVME_HOST_MEM_RETURN = (1 << 1), 1170 }; 1171 1172 struct nvme_feat_host_behavior { 1173 __u8 acre; 1174 __u8 etdas; 1175 __u8 lbafee; 1176 __u8 resv1[509]; 1177 }; 1178 1179 enum { 1180 NVME_ENABLE_ACRE = 1, 1181 NVME_ENABLE_LBAFEE = 1, 1182 }; 1183 1184 /* Admin commands */ 1185 1186 enum nvme_admin_opcode { 1187 nvme_admin_delete_sq = 0x00, 1188 nvme_admin_create_sq = 0x01, 1189 nvme_admin_get_log_page = 0x02, 1190 nvme_admin_delete_cq = 0x04, 1191 nvme_admin_create_cq = 0x05, 1192 nvme_admin_identify = 0x06, 1193 nvme_admin_abort_cmd = 0x08, 1194 nvme_admin_set_features = 0x09, 1195 nvme_admin_get_features = 0x0a, 1196 nvme_admin_async_event = 0x0c, 1197 nvme_admin_ns_mgmt = 0x0d, 1198 nvme_admin_activate_fw = 0x10, 1199 nvme_admin_download_fw = 0x11, 1200 nvme_admin_dev_self_test = 0x14, 1201 nvme_admin_ns_attach = 0x15, 1202 nvme_admin_keep_alive = 0x18, 1203 nvme_admin_directive_send = 0x19, 1204 nvme_admin_directive_recv = 0x1a, 1205 nvme_admin_virtual_mgmt = 0x1c, 1206 nvme_admin_nvme_mi_send = 0x1d, 1207 nvme_admin_nvme_mi_recv = 0x1e, 1208 nvme_admin_dbbuf = 0x7C, 1209 nvme_admin_format_nvm = 0x80, 1210 nvme_admin_security_send = 0x81, 1211 nvme_admin_security_recv = 0x82, 1212 nvme_admin_sanitize_nvm = 0x84, 1213 nvme_admin_get_lba_status = 0x86, 1214 nvme_admin_vendor_start = 0xC0, 1215 }; 1216 1217 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 1218 #define show_admin_opcode_name(val) \ 1219 __print_symbolic(val, \ 1220 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 1221 nvme_admin_opcode_name(nvme_admin_create_sq), \ 1222 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 1223 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 1224 nvme_admin_opcode_name(nvme_admin_create_cq), \ 1225 nvme_admin_opcode_name(nvme_admin_identify), \ 1226 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 1227 nvme_admin_opcode_name(nvme_admin_set_features), \ 1228 nvme_admin_opcode_name(nvme_admin_get_features), \ 1229 nvme_admin_opcode_name(nvme_admin_async_event), \ 1230 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 1231 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 1232 nvme_admin_opcode_name(nvme_admin_download_fw), \ 1233 nvme_admin_opcode_name(nvme_admin_dev_self_test), \ 1234 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 1235 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 1236 nvme_admin_opcode_name(nvme_admin_directive_send), \ 1237 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 1238 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \ 1239 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \ 1240 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \ 1241 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 1242 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 1243 nvme_admin_opcode_name(nvme_admin_security_send), \ 1244 nvme_admin_opcode_name(nvme_admin_security_recv), \ 1245 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 1246 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 1247 1248 enum { 1249 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 1250 NVME_CQ_IRQ_ENABLED = (1 << 1), 1251 NVME_SQ_PRIO_URGENT = (0 << 1), 1252 NVME_SQ_PRIO_HIGH = (1 << 1), 1253 NVME_SQ_PRIO_MEDIUM = (2 << 1), 1254 NVME_SQ_PRIO_LOW = (3 << 1), 1255 NVME_FEAT_ARBITRATION = 0x01, 1256 NVME_FEAT_POWER_MGMT = 0x02, 1257 NVME_FEAT_LBA_RANGE = 0x03, 1258 NVME_FEAT_TEMP_THRESH = 0x04, 1259 NVME_FEAT_ERR_RECOVERY = 0x05, 1260 NVME_FEAT_VOLATILE_WC = 0x06, 1261 NVME_FEAT_NUM_QUEUES = 0x07, 1262 NVME_FEAT_IRQ_COALESCE = 0x08, 1263 NVME_FEAT_IRQ_CONFIG = 0x09, 1264 NVME_FEAT_WRITE_ATOMIC = 0x0a, 1265 NVME_FEAT_ASYNC_EVENT = 0x0b, 1266 NVME_FEAT_AUTO_PST = 0x0c, 1267 NVME_FEAT_HOST_MEM_BUF = 0x0d, 1268 NVME_FEAT_TIMESTAMP = 0x0e, 1269 NVME_FEAT_KATO = 0x0f, 1270 NVME_FEAT_HCTM = 0x10, 1271 NVME_FEAT_NOPSC = 0x11, 1272 NVME_FEAT_RRL = 0x12, 1273 NVME_FEAT_PLM_CONFIG = 0x13, 1274 NVME_FEAT_PLM_WINDOW = 0x14, 1275 NVME_FEAT_HOST_BEHAVIOR = 0x16, 1276 NVME_FEAT_SANITIZE = 0x17, 1277 NVME_FEAT_SW_PROGRESS = 0x80, 1278 NVME_FEAT_HOST_ID = 0x81, 1279 NVME_FEAT_RESV_MASK = 0x82, 1280 NVME_FEAT_RESV_PERSIST = 0x83, 1281 NVME_FEAT_WRITE_PROTECT = 0x84, 1282 NVME_FEAT_VENDOR_START = 0xC0, 1283 NVME_FEAT_VENDOR_END = 0xFF, 1284 NVME_LOG_SUPPORTED = 0x00, 1285 NVME_LOG_ERROR = 0x01, 1286 NVME_LOG_SMART = 0x02, 1287 NVME_LOG_FW_SLOT = 0x03, 1288 NVME_LOG_CHANGED_NS = 0x04, 1289 NVME_LOG_CMD_EFFECTS = 0x05, 1290 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1291 NVME_LOG_TELEMETRY_HOST = 0x07, 1292 NVME_LOG_TELEMETRY_CTRL = 0x08, 1293 NVME_LOG_ENDURANCE_GROUP = 0x09, 1294 NVME_LOG_ANA = 0x0c, 1295 NVME_LOG_FEATURES = 0x12, 1296 NVME_LOG_RMI = 0x16, 1297 NVME_LOG_DISC = 0x70, 1298 NVME_LOG_RESERVATION = 0x80, 1299 NVME_FWACT_REPL = (0 << 3), 1300 NVME_FWACT_REPL_ACTV = (1 << 3), 1301 NVME_FWACT_ACTV = (2 << 3), 1302 }; 1303 1304 struct nvme_supported_log { 1305 __le32 lids[256]; 1306 }; 1307 1308 enum { 1309 NVME_LIDS_LSUPP = 1 << 0, 1310 }; 1311 1312 struct nvme_supported_features_log { 1313 __le32 fis[256]; 1314 }; 1315 1316 enum { 1317 NVME_FIS_FSUPP = 1 << 0, 1318 NVME_FIS_NSCPE = 1 << 20, 1319 NVME_FIS_CSCPE = 1 << 21, 1320 }; 1321 1322 /* NVMe Namespace Write Protect State */ 1323 enum { 1324 NVME_NS_NO_WRITE_PROTECT = 0, 1325 NVME_NS_WRITE_PROTECT, 1326 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 1327 NVME_NS_WRITE_PROTECT_PERMANENT, 1328 }; 1329 1330 #define NVME_MAX_CHANGED_NAMESPACES 1024 1331 1332 struct nvme_identify { 1333 __u8 opcode; 1334 __u8 flags; 1335 __u16 command_id; 1336 __le32 nsid; 1337 __u64 rsvd2[2]; 1338 union nvme_data_ptr dptr; 1339 __u8 cns; 1340 __u8 rsvd3; 1341 __le16 ctrlid; 1342 __le16 cnssid; 1343 __u8 rsvd11; 1344 __u8 csi; 1345 __u32 rsvd12[4]; 1346 }; 1347 1348 #define NVME_IDENTIFY_DATA_SIZE 4096 1349 1350 struct nvme_features { 1351 __u8 opcode; 1352 __u8 flags; 1353 __u16 command_id; 1354 __le32 nsid; 1355 __u64 rsvd2[2]; 1356 union nvme_data_ptr dptr; 1357 __le32 fid; 1358 __le32 dword11; 1359 __le32 dword12; 1360 __le32 dword13; 1361 __le32 dword14; 1362 __le32 dword15; 1363 }; 1364 1365 struct nvme_host_mem_buf_desc { 1366 __le64 addr; 1367 __le32 size; 1368 __u32 rsvd; 1369 }; 1370 1371 struct nvme_create_cq { 1372 __u8 opcode; 1373 __u8 flags; 1374 __u16 command_id; 1375 __u32 rsvd1[5]; 1376 __le64 prp1; 1377 __u64 rsvd8; 1378 __le16 cqid; 1379 __le16 qsize; 1380 __le16 cq_flags; 1381 __le16 irq_vector; 1382 __u32 rsvd12[4]; 1383 }; 1384 1385 struct nvme_create_sq { 1386 __u8 opcode; 1387 __u8 flags; 1388 __u16 command_id; 1389 __u32 rsvd1[5]; 1390 __le64 prp1; 1391 __u64 rsvd8; 1392 __le16 sqid; 1393 __le16 qsize; 1394 __le16 sq_flags; 1395 __le16 cqid; 1396 __u32 rsvd12[4]; 1397 }; 1398 1399 struct nvme_delete_queue { 1400 __u8 opcode; 1401 __u8 flags; 1402 __u16 command_id; 1403 __u32 rsvd1[9]; 1404 __le16 qid; 1405 __u16 rsvd10; 1406 __u32 rsvd11[5]; 1407 }; 1408 1409 struct nvme_abort_cmd { 1410 __u8 opcode; 1411 __u8 flags; 1412 __u16 command_id; 1413 __u32 rsvd1[9]; 1414 __le16 sqid; 1415 __u16 cid; 1416 __u32 rsvd11[5]; 1417 }; 1418 1419 struct nvme_download_firmware { 1420 __u8 opcode; 1421 __u8 flags; 1422 __u16 command_id; 1423 __u32 rsvd1[5]; 1424 union nvme_data_ptr dptr; 1425 __le32 numd; 1426 __le32 offset; 1427 __u32 rsvd12[4]; 1428 }; 1429 1430 struct nvme_format_cmd { 1431 __u8 opcode; 1432 __u8 flags; 1433 __u16 command_id; 1434 __le32 nsid; 1435 __u64 rsvd2[4]; 1436 __le32 cdw10; 1437 __u32 rsvd11[5]; 1438 }; 1439 1440 struct nvme_get_log_page_command { 1441 __u8 opcode; 1442 __u8 flags; 1443 __u16 command_id; 1444 __le32 nsid; 1445 __u64 rsvd2[2]; 1446 union nvme_data_ptr dptr; 1447 __u8 lid; 1448 __u8 lsp; /* upper 4 bits reserved */ 1449 __le16 numdl; 1450 __le16 numdu; 1451 __le16 lsi; 1452 union { 1453 struct { 1454 __le32 lpol; 1455 __le32 lpou; 1456 }; 1457 __le64 lpo; 1458 }; 1459 __u8 rsvd14[3]; 1460 __u8 csi; 1461 __u32 rsvd15; 1462 }; 1463 1464 struct nvme_directive_cmd { 1465 __u8 opcode; 1466 __u8 flags; 1467 __u16 command_id; 1468 __le32 nsid; 1469 __u64 rsvd2[2]; 1470 union nvme_data_ptr dptr; 1471 __le32 numd; 1472 __u8 doper; 1473 __u8 dtype; 1474 __le16 dspec; 1475 __u8 endir; 1476 __u8 tdtype; 1477 __u16 rsvd15; 1478 1479 __u32 rsvd16[3]; 1480 }; 1481 1482 /* 1483 * Fabrics subcommands. 1484 */ 1485 enum nvmf_fabrics_opcode { 1486 nvme_fabrics_command = 0x7f, 1487 }; 1488 1489 enum nvmf_capsule_command { 1490 nvme_fabrics_type_property_set = 0x00, 1491 nvme_fabrics_type_connect = 0x01, 1492 nvme_fabrics_type_property_get = 0x04, 1493 nvme_fabrics_type_auth_send = 0x05, 1494 nvme_fabrics_type_auth_receive = 0x06, 1495 }; 1496 1497 #define nvme_fabrics_type_name(type) { type, #type } 1498 #define show_fabrics_type_name(type) \ 1499 __print_symbolic(type, \ 1500 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1501 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1502 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \ 1503 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \ 1504 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive)) 1505 1506 /* 1507 * If not fabrics command, fctype will be ignored. 1508 */ 1509 #define show_opcode_name(qid, opcode, fctype) \ 1510 ((opcode) == nvme_fabrics_command ? \ 1511 show_fabrics_type_name(fctype) : \ 1512 ((qid) ? \ 1513 show_nvm_opcode_name(opcode) : \ 1514 show_admin_opcode_name(opcode))) 1515 1516 struct nvmf_common_command { 1517 __u8 opcode; 1518 __u8 resv1; 1519 __u16 command_id; 1520 __u8 fctype; 1521 __u8 resv2[35]; 1522 __u8 ts[24]; 1523 }; 1524 1525 /* 1526 * The legal cntlid range a NVMe Target will provide. 1527 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1528 * Devices based on earlier specs did not have the subsystem concept; 1529 * therefore, those devices had their cntlid value set to 0 as a result. 1530 */ 1531 #define NVME_CNTLID_MIN 1 1532 #define NVME_CNTLID_MAX 0xffef 1533 #define NVME_CNTLID_DYNAMIC 0xffff 1534 1535 #define MAX_DISC_LOGS 255 1536 1537 /* Discovery log page entry flags (EFLAGS): */ 1538 enum { 1539 NVME_DISC_EFLAGS_EPCSD = (1 << 1), 1540 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0), 1541 }; 1542 1543 /* Discovery log page entry */ 1544 struct nvmf_disc_rsp_page_entry { 1545 __u8 trtype; 1546 __u8 adrfam; 1547 __u8 subtype; 1548 __u8 treq; 1549 __le16 portid; 1550 __le16 cntlid; 1551 __le16 asqsz; 1552 __le16 eflags; 1553 __u8 resv10[20]; 1554 char trsvcid[NVMF_TRSVCID_SIZE]; 1555 __u8 resv64[192]; 1556 char subnqn[NVMF_NQN_FIELD_LEN]; 1557 char traddr[NVMF_TRADDR_SIZE]; 1558 union tsas { 1559 char common[NVMF_TSAS_SIZE]; 1560 struct rdma { 1561 __u8 qptype; 1562 __u8 prtype; 1563 __u8 cms; 1564 __u8 resv3[5]; 1565 __u16 pkey; 1566 __u8 resv10[246]; 1567 } rdma; 1568 struct tcp { 1569 __u8 sectype; 1570 } tcp; 1571 } tsas; 1572 }; 1573 1574 /* Discovery log page header */ 1575 struct nvmf_disc_rsp_page_hdr { 1576 __le64 genctr; 1577 __le64 numrec; 1578 __le16 recfmt; 1579 __u8 resv14[1006]; 1580 struct nvmf_disc_rsp_page_entry entries[]; 1581 }; 1582 1583 enum { 1584 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1585 }; 1586 1587 struct nvmf_connect_command { 1588 __u8 opcode; 1589 __u8 resv1; 1590 __u16 command_id; 1591 __u8 fctype; 1592 __u8 resv2[19]; 1593 union nvme_data_ptr dptr; 1594 __le16 recfmt; 1595 __le16 qid; 1596 __le16 sqsize; 1597 __u8 cattr; 1598 __u8 resv3; 1599 __le32 kato; 1600 __u8 resv4[12]; 1601 }; 1602 1603 enum { 1604 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18), 1605 NVME_CONNECT_AUTHREQ_ATR = (1U << 17), 1606 }; 1607 1608 struct nvmf_connect_data { 1609 uuid_t hostid; 1610 __le16 cntlid; 1611 char resv4[238]; 1612 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1613 char hostnqn[NVMF_NQN_FIELD_LEN]; 1614 char resv5[256]; 1615 }; 1616 1617 struct nvmf_property_set_command { 1618 __u8 opcode; 1619 __u8 resv1; 1620 __u16 command_id; 1621 __u8 fctype; 1622 __u8 resv2[35]; 1623 __u8 attrib; 1624 __u8 resv3[3]; 1625 __le32 offset; 1626 __le64 value; 1627 __u8 resv4[8]; 1628 }; 1629 1630 struct nvmf_property_get_command { 1631 __u8 opcode; 1632 __u8 resv1; 1633 __u16 command_id; 1634 __u8 fctype; 1635 __u8 resv2[35]; 1636 __u8 attrib; 1637 __u8 resv3[3]; 1638 __le32 offset; 1639 __u8 resv4[16]; 1640 }; 1641 1642 struct nvmf_auth_common_command { 1643 __u8 opcode; 1644 __u8 resv1; 1645 __u16 command_id; 1646 __u8 fctype; 1647 __u8 resv2[19]; 1648 union nvme_data_ptr dptr; 1649 __u8 resv3; 1650 __u8 spsp0; 1651 __u8 spsp1; 1652 __u8 secp; 1653 __le32 al_tl; 1654 __u8 resv4[16]; 1655 }; 1656 1657 struct nvmf_auth_send_command { 1658 __u8 opcode; 1659 __u8 resv1; 1660 __u16 command_id; 1661 __u8 fctype; 1662 __u8 resv2[19]; 1663 union nvme_data_ptr dptr; 1664 __u8 resv3; 1665 __u8 spsp0; 1666 __u8 spsp1; 1667 __u8 secp; 1668 __le32 tl; 1669 __u8 resv4[16]; 1670 }; 1671 1672 struct nvmf_auth_receive_command { 1673 __u8 opcode; 1674 __u8 resv1; 1675 __u16 command_id; 1676 __u8 fctype; 1677 __u8 resv2[19]; 1678 union nvme_data_ptr dptr; 1679 __u8 resv3; 1680 __u8 spsp0; 1681 __u8 spsp1; 1682 __u8 secp; 1683 __le32 al; 1684 __u8 resv4[16]; 1685 }; 1686 1687 /* Value for secp */ 1688 enum { 1689 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9, 1690 }; 1691 1692 /* Defined value for auth_type */ 1693 enum { 1694 NVME_AUTH_COMMON_MESSAGES = 0x00, 1695 NVME_AUTH_DHCHAP_MESSAGES = 0x01, 1696 }; 1697 1698 /* Defined messages for auth_id */ 1699 enum { 1700 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00, 1701 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01, 1702 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02, 1703 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03, 1704 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04, 1705 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0, 1706 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1, 1707 }; 1708 1709 struct nvmf_auth_dhchap_protocol_descriptor { 1710 __u8 authid; 1711 __u8 rsvd; 1712 __u8 halen; 1713 __u8 dhlen; 1714 __u8 idlist[60]; 1715 }; 1716 1717 enum { 1718 NVME_AUTH_DHCHAP_AUTH_ID = 0x01, 1719 }; 1720 1721 /* Defined hash functions for DH-HMAC-CHAP authentication */ 1722 enum { 1723 NVME_AUTH_HASH_SHA256 = 0x01, 1724 NVME_AUTH_HASH_SHA384 = 0x02, 1725 NVME_AUTH_HASH_SHA512 = 0x03, 1726 NVME_AUTH_HASH_INVALID = 0xff, 1727 }; 1728 1729 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */ 1730 enum { 1731 NVME_AUTH_DHGROUP_NULL = 0x00, 1732 NVME_AUTH_DHGROUP_2048 = 0x01, 1733 NVME_AUTH_DHGROUP_3072 = 0x02, 1734 NVME_AUTH_DHGROUP_4096 = 0x03, 1735 NVME_AUTH_DHGROUP_6144 = 0x04, 1736 NVME_AUTH_DHGROUP_8192 = 0x05, 1737 NVME_AUTH_DHGROUP_INVALID = 0xff, 1738 }; 1739 1740 union nvmf_auth_protocol { 1741 struct nvmf_auth_dhchap_protocol_descriptor dhchap; 1742 }; 1743 1744 struct nvmf_auth_dhchap_negotiate_data { 1745 __u8 auth_type; 1746 __u8 auth_id; 1747 __le16 rsvd; 1748 __le16 t_id; 1749 __u8 sc_c; 1750 __u8 napd; 1751 union nvmf_auth_protocol auth_protocol[]; 1752 }; 1753 1754 struct nvmf_auth_dhchap_challenge_data { 1755 __u8 auth_type; 1756 __u8 auth_id; 1757 __u16 rsvd1; 1758 __le16 t_id; 1759 __u8 hl; 1760 __u8 rsvd2; 1761 __u8 hashid; 1762 __u8 dhgid; 1763 __le16 dhvlen; 1764 __le32 seqnum; 1765 /* 'hl' bytes of challenge value */ 1766 __u8 cval[]; 1767 /* followed by 'dhvlen' bytes of DH value */ 1768 }; 1769 1770 struct nvmf_auth_dhchap_reply_data { 1771 __u8 auth_type; 1772 __u8 auth_id; 1773 __le16 rsvd1; 1774 __le16 t_id; 1775 __u8 hl; 1776 __u8 rsvd2; 1777 __u8 cvalid; 1778 __u8 rsvd3; 1779 __le16 dhvlen; 1780 __le32 seqnum; 1781 /* 'hl' bytes of response data */ 1782 __u8 rval[]; 1783 /* followed by 'hl' bytes of Challenge value */ 1784 /* followed by 'dhvlen' bytes of DH value */ 1785 }; 1786 1787 enum { 1788 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0), 1789 }; 1790 1791 struct nvmf_auth_dhchap_success1_data { 1792 __u8 auth_type; 1793 __u8 auth_id; 1794 __le16 rsvd1; 1795 __le16 t_id; 1796 __u8 hl; 1797 __u8 rsvd2; 1798 __u8 rvalid; 1799 __u8 rsvd3[7]; 1800 /* 'hl' bytes of response value */ 1801 __u8 rval[]; 1802 }; 1803 1804 struct nvmf_auth_dhchap_success2_data { 1805 __u8 auth_type; 1806 __u8 auth_id; 1807 __le16 rsvd1; 1808 __le16 t_id; 1809 __u8 rsvd2[10]; 1810 }; 1811 1812 struct nvmf_auth_dhchap_failure_data { 1813 __u8 auth_type; 1814 __u8 auth_id; 1815 __le16 rsvd1; 1816 __le16 t_id; 1817 __u8 rescode; 1818 __u8 rescode_exp; 1819 }; 1820 1821 enum { 1822 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01, 1823 }; 1824 1825 enum { 1826 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01, 1827 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02, 1828 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03, 1829 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04, 1830 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05, 1831 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06, 1832 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07, 1833 }; 1834 1835 1836 struct nvme_dbbuf { 1837 __u8 opcode; 1838 __u8 flags; 1839 __u16 command_id; 1840 __u32 rsvd1[5]; 1841 __le64 prp1; 1842 __le64 prp2; 1843 __u32 rsvd12[6]; 1844 }; 1845 1846 struct streams_directive_params { 1847 __le16 msl; 1848 __le16 nssa; 1849 __le16 nsso; 1850 __u8 rsvd[10]; 1851 __le32 sws; 1852 __le16 sgs; 1853 __le16 nsa; 1854 __le16 nso; 1855 __u8 rsvd2[6]; 1856 }; 1857 1858 struct nvme_command { 1859 union { 1860 struct nvme_common_command common; 1861 struct nvme_rw_command rw; 1862 struct nvme_identify identify; 1863 struct nvme_features features; 1864 struct nvme_create_cq create_cq; 1865 struct nvme_create_sq create_sq; 1866 struct nvme_delete_queue delete_queue; 1867 struct nvme_download_firmware dlfw; 1868 struct nvme_format_cmd format; 1869 struct nvme_dsm_cmd dsm; 1870 struct nvme_write_zeroes_cmd write_zeroes; 1871 struct nvme_zone_mgmt_send_cmd zms; 1872 struct nvme_zone_mgmt_recv_cmd zmr; 1873 struct nvme_abort_cmd abort; 1874 struct nvme_get_log_page_command get_log_page; 1875 struct nvmf_common_command fabrics; 1876 struct nvmf_connect_command connect; 1877 struct nvmf_property_set_command prop_set; 1878 struct nvmf_property_get_command prop_get; 1879 struct nvmf_auth_common_command auth_common; 1880 struct nvmf_auth_send_command auth_send; 1881 struct nvmf_auth_receive_command auth_receive; 1882 struct nvme_dbbuf dbbuf; 1883 struct nvme_directive_cmd directive; 1884 }; 1885 }; 1886 1887 static inline bool nvme_is_fabrics(const struct nvme_command *cmd) 1888 { 1889 return cmd->common.opcode == nvme_fabrics_command; 1890 } 1891 1892 struct nvme_error_slot { 1893 __le64 error_count; 1894 __le16 sqid; 1895 __le16 cmdid; 1896 __le16 status_field; 1897 __le16 param_error_location; 1898 __le64 lba; 1899 __le32 nsid; 1900 __u8 vs; 1901 __u8 resv[3]; 1902 __le64 cs; 1903 __u8 resv2[24]; 1904 }; 1905 1906 static inline bool nvme_is_write(const struct nvme_command *cmd) 1907 { 1908 /* 1909 * What a mess... 1910 * 1911 * Why can't we simply have a Fabrics In and Fabrics out command? 1912 */ 1913 if (unlikely(nvme_is_fabrics(cmd))) 1914 return cmd->fabrics.fctype & 1; 1915 return cmd->common.opcode & 1; 1916 } 1917 1918 enum { 1919 /* 1920 * Generic Command Status: 1921 */ 1922 NVME_SCT_GENERIC = 0x0, 1923 NVME_SC_SUCCESS = 0x0, 1924 NVME_SC_INVALID_OPCODE = 0x1, 1925 NVME_SC_INVALID_FIELD = 0x2, 1926 NVME_SC_CMDID_CONFLICT = 0x3, 1927 NVME_SC_DATA_XFER_ERROR = 0x4, 1928 NVME_SC_POWER_LOSS = 0x5, 1929 NVME_SC_INTERNAL = 0x6, 1930 NVME_SC_ABORT_REQ = 0x7, 1931 NVME_SC_ABORT_QUEUE = 0x8, 1932 NVME_SC_FUSED_FAIL = 0x9, 1933 NVME_SC_FUSED_MISSING = 0xa, 1934 NVME_SC_INVALID_NS = 0xb, 1935 NVME_SC_CMD_SEQ_ERROR = 0xc, 1936 NVME_SC_SGL_INVALID_LAST = 0xd, 1937 NVME_SC_SGL_INVALID_COUNT = 0xe, 1938 NVME_SC_SGL_INVALID_DATA = 0xf, 1939 NVME_SC_SGL_INVALID_METADATA = 0x10, 1940 NVME_SC_SGL_INVALID_TYPE = 0x11, 1941 NVME_SC_CMB_INVALID_USE = 0x12, 1942 NVME_SC_PRP_INVALID_OFFSET = 0x13, 1943 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, 1944 NVME_SC_OP_DENIED = 0x15, 1945 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1946 NVME_SC_RESERVED = 0x17, 1947 NVME_SC_HOST_ID_INCONSIST = 0x18, 1948 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, 1949 NVME_SC_KA_TIMEOUT_INVALID = 0x1A, 1950 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, 1951 NVME_SC_SANITIZE_FAILED = 0x1C, 1952 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, 1953 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, 1954 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, 1955 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1956 NVME_SC_CMD_INTERRUPTED = 0x21, 1957 NVME_SC_TRANSIENT_TR_ERR = 0x22, 1958 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24, 1959 NVME_SC_INVALID_IO_CMD_SET = 0x2C, 1960 1961 NVME_SC_LBA_RANGE = 0x80, 1962 NVME_SC_CAP_EXCEEDED = 0x81, 1963 NVME_SC_NS_NOT_READY = 0x82, 1964 NVME_SC_RESERVATION_CONFLICT = 0x83, 1965 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 1966 1967 /* 1968 * Command Specific Status: 1969 */ 1970 NVME_SCT_COMMAND_SPECIFIC = 0x100, 1971 NVME_SC_CQ_INVALID = 0x100, 1972 NVME_SC_QID_INVALID = 0x101, 1973 NVME_SC_QUEUE_SIZE = 0x102, 1974 NVME_SC_ABORT_LIMIT = 0x103, 1975 NVME_SC_ABORT_MISSING = 0x104, 1976 NVME_SC_ASYNC_LIMIT = 0x105, 1977 NVME_SC_FIRMWARE_SLOT = 0x106, 1978 NVME_SC_FIRMWARE_IMAGE = 0x107, 1979 NVME_SC_INVALID_VECTOR = 0x108, 1980 NVME_SC_INVALID_LOG_PAGE = 0x109, 1981 NVME_SC_INVALID_FORMAT = 0x10a, 1982 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1983 NVME_SC_INVALID_QUEUE = 0x10c, 1984 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1985 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1986 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1987 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1988 NVME_SC_FW_NEEDS_RESET = 0x111, 1989 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1990 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1991 NVME_SC_OVERLAPPING_RANGE = 0x114, 1992 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1993 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1994 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1995 NVME_SC_NS_IS_PRIVATE = 0x119, 1996 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1997 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1998 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1999 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, 2000 NVME_SC_BP_WRITE_PROHIBITED = 0x11e, 2001 NVME_SC_CTRL_ID_INVALID = 0x11f, 2002 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, 2003 NVME_SC_CTRL_RES_NUM_INVALID = 0x121, 2004 NVME_SC_RES_ID_INVALID = 0x122, 2005 NVME_SC_PMR_SAN_PROHIBITED = 0x123, 2006 NVME_SC_ANA_GROUP_ID_INVALID = 0x124, 2007 NVME_SC_ANA_ATTACH_FAILED = 0x125, 2008 2009 /* 2010 * I/O Command Set Specific - NVM commands: 2011 */ 2012 NVME_SC_BAD_ATTRIBUTES = 0x180, 2013 NVME_SC_INVALID_PI = 0x181, 2014 NVME_SC_READ_ONLY = 0x182, 2015 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 2016 2017 /* 2018 * I/O Command Set Specific - Fabrics commands: 2019 */ 2020 NVME_SC_CONNECT_FORMAT = 0x180, 2021 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 2022 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 2023 NVME_SC_CONNECT_RESTART_DISC = 0x183, 2024 NVME_SC_CONNECT_INVALID_HOST = 0x184, 2025 2026 NVME_SC_DISCOVERY_RESTART = 0x190, 2027 NVME_SC_AUTH_REQUIRED = 0x191, 2028 2029 /* 2030 * I/O Command Set Specific - Zoned commands: 2031 */ 2032 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, 2033 NVME_SC_ZONE_FULL = 0x1b9, 2034 NVME_SC_ZONE_READ_ONLY = 0x1ba, 2035 NVME_SC_ZONE_OFFLINE = 0x1bb, 2036 NVME_SC_ZONE_INVALID_WRITE = 0x1bc, 2037 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, 2038 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, 2039 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, 2040 2041 /* 2042 * Media and Data Integrity Errors: 2043 */ 2044 NVME_SCT_MEDIA_ERROR = 0x200, 2045 NVME_SC_WRITE_FAULT = 0x280, 2046 NVME_SC_READ_ERROR = 0x281, 2047 NVME_SC_GUARD_CHECK = 0x282, 2048 NVME_SC_APPTAG_CHECK = 0x283, 2049 NVME_SC_REFTAG_CHECK = 0x284, 2050 NVME_SC_COMPARE_FAILED = 0x285, 2051 NVME_SC_ACCESS_DENIED = 0x286, 2052 NVME_SC_UNWRITTEN_BLOCK = 0x287, 2053 2054 /* 2055 * Path-related Errors: 2056 */ 2057 NVME_SCT_PATH = 0x300, 2058 NVME_SC_INTERNAL_PATH_ERROR = 0x300, 2059 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 2060 NVME_SC_ANA_INACCESSIBLE = 0x302, 2061 NVME_SC_ANA_TRANSITION = 0x303, 2062 NVME_SC_CTRL_PATH_ERROR = 0x360, 2063 NVME_SC_HOST_PATH_ERROR = 0x370, 2064 NVME_SC_HOST_ABORTED_CMD = 0x371, 2065 2066 NVME_SC_MASK = 0x00ff, /* Status Code */ 2067 NVME_SCT_MASK = 0x0700, /* Status Code Type */ 2068 NVME_SCT_SC_MASK = NVME_SCT_MASK | NVME_SC_MASK, 2069 2070 NVME_STATUS_CRD = 0x1800, /* Command Retry Delayed */ 2071 NVME_STATUS_MORE = 0x2000, 2072 NVME_STATUS_DNR = 0x4000, /* Do Not Retry */ 2073 }; 2074 2075 #define NVME_SCT(status) ((status) >> 8 & 7) 2076 2077 struct nvme_completion { 2078 /* 2079 * Used by Admin and Fabrics commands to return data: 2080 */ 2081 union nvme_result { 2082 __le16 u16; 2083 __le32 u32; 2084 __le64 u64; 2085 } result; 2086 __le16 sq_head; /* how much of this queue may be reclaimed */ 2087 __le16 sq_id; /* submission queue that generated this entry */ 2088 __u16 command_id; /* of the command which completed */ 2089 __le16 status; /* did the command fail, and if so, why? */ 2090 }; 2091 2092 #define NVME_VS(major, minor, tertiary) \ 2093 (((major) << 16) | ((minor) << 8) | (tertiary)) 2094 2095 #define NVME_MAJOR(ver) ((ver) >> 16) 2096 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 2097 #define NVME_TERTIARY(ver) ((ver) & 0xff) 2098 2099 enum { 2100 NVME_AEN_RESV_LOG_PAGE_AVALIABLE = 0x00, 2101 }; 2102 2103 enum { 2104 NVME_PR_LOG_EMPTY_LOG_PAGE = 0x00, 2105 NVME_PR_LOG_REGISTRATION_PREEMPTED = 0x01, 2106 NVME_PR_LOG_RESERVATION_RELEASED = 0x02, 2107 NVME_PR_LOG_RESERVATOIN_PREEMPTED = 0x03, 2108 }; 2109 2110 enum { 2111 NVME_PR_NOTIFY_BIT_REG_PREEMPTED = 1, 2112 NVME_PR_NOTIFY_BIT_RESV_RELEASED = 2, 2113 NVME_PR_NOTIFY_BIT_RESV_PREEMPTED = 3, 2114 }; 2115 2116 struct nvme_pr_log { 2117 __le64 count; 2118 __u8 type; 2119 __u8 nr_pages; 2120 __u8 rsvd1[2]; 2121 __le32 nsid; 2122 __u8 rsvd2[48]; 2123 }; 2124 2125 struct nvmet_pr_register_data { 2126 __le64 crkey; 2127 __le64 nrkey; 2128 }; 2129 2130 struct nvmet_pr_acquire_data { 2131 __le64 crkey; 2132 __le64 prkey; 2133 }; 2134 2135 struct nvmet_pr_release_data { 2136 __le64 crkey; 2137 }; 2138 2139 enum nvme_pr_capabilities { 2140 NVME_PR_SUPPORT_PTPL = 1, 2141 NVME_PR_SUPPORT_WRITE_EXCLUSIVE = 1 << 1, 2142 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS = 1 << 2, 2143 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY = 1 << 3, 2144 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY = 1 << 4, 2145 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS = 1 << 5, 2146 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS = 1 << 6, 2147 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF = 1 << 7, 2148 }; 2149 2150 enum nvme_pr_register_action { 2151 NVME_PR_REGISTER_ACT_REG = 0, 2152 NVME_PR_REGISTER_ACT_UNREG = 1, 2153 NVME_PR_REGISTER_ACT_REPLACE = 1 << 1, 2154 }; 2155 2156 enum nvme_pr_acquire_action { 2157 NVME_PR_ACQUIRE_ACT_ACQUIRE = 0, 2158 NVME_PR_ACQUIRE_ACT_PREEMPT = 1, 2159 NVME_PR_ACQUIRE_ACT_PREEMPT_AND_ABORT = 1 << 1, 2160 }; 2161 2162 enum nvme_pr_release_action { 2163 NVME_PR_RELEASE_ACT_RELEASE = 0, 2164 NVME_PR_RELEASE_ACT_CLEAR = 1, 2165 }; 2166 2167 #endif /* _LINUX_NVME_H */ 2168