1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/types.h> 11 #include <linux/uuid.h> 12 13 /* NQN names in commands fields specified one size */ 14 #define NVMF_NQN_FIELD_LEN 256 15 16 /* However the max length of a qualified name is another size */ 17 #define NVMF_NQN_SIZE 223 18 19 #define NVMF_TRSVCID_SIZE 32 20 #define NVMF_TRADDR_SIZE 256 21 #define NVMF_TSAS_SIZE 256 22 23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 24 25 #define NVME_RDMA_IP_PORT 4420 26 27 #define NVME_NSID_ALL 0xffffffff 28 29 enum nvme_subsys_type { 30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */ 31 NVME_NQN_NVME = 2, /* NVME type target subsystem */ 32 }; 33 34 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 35 enum { 36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 41 }; 42 43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 44 enum { 45 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 46 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 47 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 48 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 49 NVMF_TRTYPE_MAX, 50 }; 51 52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 53 enum { 54 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 55 NVMF_TREQ_REQUIRED = 1, /* Required */ 56 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 57 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 59 60 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 61 }; 62 63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 64 * RDMA_QPTYPE field 65 */ 66 enum { 67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 69 }; 70 71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 72 * RDMA_QPTYPE field 73 */ 74 enum { 75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 80 }; 81 82 /* RDMA Connection Management Service Type codes for Discovery Log Page 83 * entry TSAS RDMA_CMS field 84 */ 85 enum { 86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 87 }; 88 89 #define NVME_AQ_DEPTH 32 90 #define NVME_NR_AEN_COMMANDS 1 91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 92 93 /* 94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 95 * NVM-Express 1.2 specification, section 4.1.2. 96 */ 97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 98 99 enum { 100 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 101 NVME_REG_VS = 0x0008, /* Version */ 102 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 103 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 104 NVME_REG_CC = 0x0014, /* Controller Configuration */ 105 NVME_REG_CSTS = 0x001c, /* Controller Status */ 106 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 107 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 108 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 109 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 110 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 111 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 112 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 113 }; 114 115 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 116 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 117 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 118 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 119 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 120 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 121 122 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 123 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 124 125 enum { 126 NVME_CMBSZ_SQS = 1 << 0, 127 NVME_CMBSZ_CQS = 1 << 1, 128 NVME_CMBSZ_LISTS = 1 << 2, 129 NVME_CMBSZ_RDS = 1 << 3, 130 NVME_CMBSZ_WDS = 1 << 4, 131 132 NVME_CMBSZ_SZ_SHIFT = 12, 133 NVME_CMBSZ_SZ_MASK = 0xfffff, 134 135 NVME_CMBSZ_SZU_SHIFT = 8, 136 NVME_CMBSZ_SZU_MASK = 0xf, 137 }; 138 139 /* 140 * Submission and Completion Queue Entry Sizes for the NVM command set. 141 * (In bytes and specified as a power of two (2^n)). 142 */ 143 #define NVME_NVM_IOSQES 6 144 #define NVME_NVM_IOCQES 4 145 146 enum { 147 NVME_CC_ENABLE = 1 << 0, 148 NVME_CC_CSS_NVM = 0 << 4, 149 NVME_CC_EN_SHIFT = 0, 150 NVME_CC_CSS_SHIFT = 4, 151 NVME_CC_MPS_SHIFT = 7, 152 NVME_CC_AMS_SHIFT = 11, 153 NVME_CC_SHN_SHIFT = 14, 154 NVME_CC_IOSQES_SHIFT = 16, 155 NVME_CC_IOCQES_SHIFT = 20, 156 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 157 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 158 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 159 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 160 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 161 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 162 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 163 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 164 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 165 NVME_CSTS_RDY = 1 << 0, 166 NVME_CSTS_CFS = 1 << 1, 167 NVME_CSTS_NSSRO = 1 << 4, 168 NVME_CSTS_PP = 1 << 5, 169 NVME_CSTS_SHST_NORMAL = 0 << 2, 170 NVME_CSTS_SHST_OCCUR = 1 << 2, 171 NVME_CSTS_SHST_CMPLT = 2 << 2, 172 NVME_CSTS_SHST_MASK = 3 << 2, 173 }; 174 175 struct nvme_id_power_state { 176 __le16 max_power; /* centiwatts */ 177 __u8 rsvd2; 178 __u8 flags; 179 __le32 entry_lat; /* microseconds */ 180 __le32 exit_lat; /* microseconds */ 181 __u8 read_tput; 182 __u8 read_lat; 183 __u8 write_tput; 184 __u8 write_lat; 185 __le16 idle_power; 186 __u8 idle_scale; 187 __u8 rsvd19; 188 __le16 active_power; 189 __u8 active_work_scale; 190 __u8 rsvd23[9]; 191 }; 192 193 enum { 194 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 195 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 196 }; 197 198 enum nvme_ctrl_attr { 199 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 200 NVME_CTRL_ATTR_TBKAS = (1 << 6), 201 }; 202 203 struct nvme_id_ctrl { 204 __le16 vid; 205 __le16 ssvid; 206 char sn[20]; 207 char mn[40]; 208 char fr[8]; 209 __u8 rab; 210 __u8 ieee[3]; 211 __u8 cmic; 212 __u8 mdts; 213 __le16 cntlid; 214 __le32 ver; 215 __le32 rtd3r; 216 __le32 rtd3e; 217 __le32 oaes; 218 __le32 ctratt; 219 __u8 rsvd100[28]; 220 __le16 crdt1; 221 __le16 crdt2; 222 __le16 crdt3; 223 __u8 rsvd134[122]; 224 __le16 oacs; 225 __u8 acl; 226 __u8 aerl; 227 __u8 frmw; 228 __u8 lpa; 229 __u8 elpe; 230 __u8 npss; 231 __u8 avscc; 232 __u8 apsta; 233 __le16 wctemp; 234 __le16 cctemp; 235 __le16 mtfa; 236 __le32 hmpre; 237 __le32 hmmin; 238 __u8 tnvmcap[16]; 239 __u8 unvmcap[16]; 240 __le32 rpmbs; 241 __le16 edstt; 242 __u8 dsto; 243 __u8 fwug; 244 __le16 kas; 245 __le16 hctma; 246 __le16 mntmt; 247 __le16 mxtmt; 248 __le32 sanicap; 249 __le32 hmminds; 250 __le16 hmmaxd; 251 __u8 rsvd338[4]; 252 __u8 anatt; 253 __u8 anacap; 254 __le32 anagrpmax; 255 __le32 nanagrpid; 256 __u8 rsvd352[160]; 257 __u8 sqes; 258 __u8 cqes; 259 __le16 maxcmd; 260 __le32 nn; 261 __le16 oncs; 262 __le16 fuses; 263 __u8 fna; 264 __u8 vwc; 265 __le16 awun; 266 __le16 awupf; 267 __u8 nvscc; 268 __u8 nwpc; 269 __le16 acwu; 270 __u8 rsvd534[2]; 271 __le32 sgls; 272 __le32 mnan; 273 __u8 rsvd544[224]; 274 char subnqn[256]; 275 __u8 rsvd1024[768]; 276 __le32 ioccsz; 277 __le32 iorcsz; 278 __le16 icdoff; 279 __u8 ctrattr; 280 __u8 msdbd; 281 __u8 rsvd1804[244]; 282 struct nvme_id_power_state psd[32]; 283 __u8 vs[1024]; 284 }; 285 286 enum { 287 NVME_CTRL_ONCS_COMPARE = 1 << 0, 288 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 289 NVME_CTRL_ONCS_DSM = 1 << 2, 290 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 291 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 292 NVME_CTRL_VWC_PRESENT = 1 << 0, 293 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 294 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 295 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 296 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 297 }; 298 299 struct nvme_lbaf { 300 __le16 ms; 301 __u8 ds; 302 __u8 rp; 303 }; 304 305 struct nvme_id_ns { 306 __le64 nsze; 307 __le64 ncap; 308 __le64 nuse; 309 __u8 nsfeat; 310 __u8 nlbaf; 311 __u8 flbas; 312 __u8 mc; 313 __u8 dpc; 314 __u8 dps; 315 __u8 nmic; 316 __u8 rescap; 317 __u8 fpi; 318 __u8 rsvd33; 319 __le16 nawun; 320 __le16 nawupf; 321 __le16 nacwu; 322 __le16 nabsn; 323 __le16 nabo; 324 __le16 nabspf; 325 __le16 noiob; 326 __u8 nvmcap[16]; 327 __u8 rsvd64[28]; 328 __le32 anagrpid; 329 __u8 rsvd96[3]; 330 __u8 nsattr; 331 __u8 rsvd100[4]; 332 __u8 nguid[16]; 333 __u8 eui64[8]; 334 struct nvme_lbaf lbaf[16]; 335 __u8 rsvd192[192]; 336 __u8 vs[3712]; 337 }; 338 339 enum { 340 NVME_ID_CNS_NS = 0x00, 341 NVME_ID_CNS_CTRL = 0x01, 342 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 343 NVME_ID_CNS_NS_DESC_LIST = 0x03, 344 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 345 NVME_ID_CNS_NS_PRESENT = 0x11, 346 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 347 NVME_ID_CNS_CTRL_LIST = 0x13, 348 }; 349 350 enum { 351 NVME_DIR_IDENTIFY = 0x00, 352 NVME_DIR_STREAMS = 0x01, 353 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 354 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 355 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 356 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 357 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 358 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 359 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 360 NVME_DIR_ENDIR = 0x01, 361 }; 362 363 enum { 364 NVME_NS_FEAT_THIN = 1 << 0, 365 NVME_NS_FLBAS_LBA_MASK = 0xf, 366 NVME_NS_FLBAS_META_EXT = 0x10, 367 NVME_LBAF_RP_BEST = 0, 368 NVME_LBAF_RP_BETTER = 1, 369 NVME_LBAF_RP_GOOD = 2, 370 NVME_LBAF_RP_DEGRADED = 3, 371 NVME_NS_DPC_PI_LAST = 1 << 4, 372 NVME_NS_DPC_PI_FIRST = 1 << 3, 373 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 374 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 375 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 376 NVME_NS_DPS_PI_FIRST = 1 << 3, 377 NVME_NS_DPS_PI_MASK = 0x7, 378 NVME_NS_DPS_PI_TYPE1 = 1, 379 NVME_NS_DPS_PI_TYPE2 = 2, 380 NVME_NS_DPS_PI_TYPE3 = 3, 381 }; 382 383 struct nvme_ns_id_desc { 384 __u8 nidt; 385 __u8 nidl; 386 __le16 reserved; 387 }; 388 389 #define NVME_NIDT_EUI64_LEN 8 390 #define NVME_NIDT_NGUID_LEN 16 391 #define NVME_NIDT_UUID_LEN 16 392 393 enum { 394 NVME_NIDT_EUI64 = 0x01, 395 NVME_NIDT_NGUID = 0x02, 396 NVME_NIDT_UUID = 0x03, 397 }; 398 399 struct nvme_smart_log { 400 __u8 critical_warning; 401 __u8 temperature[2]; 402 __u8 avail_spare; 403 __u8 spare_thresh; 404 __u8 percent_used; 405 __u8 rsvd6[26]; 406 __u8 data_units_read[16]; 407 __u8 data_units_written[16]; 408 __u8 host_reads[16]; 409 __u8 host_writes[16]; 410 __u8 ctrl_busy_time[16]; 411 __u8 power_cycles[16]; 412 __u8 power_on_hours[16]; 413 __u8 unsafe_shutdowns[16]; 414 __u8 media_errors[16]; 415 __u8 num_err_log_entries[16]; 416 __le32 warning_temp_time; 417 __le32 critical_comp_time; 418 __le16 temp_sensor[8]; 419 __u8 rsvd216[296]; 420 }; 421 422 struct nvme_fw_slot_info_log { 423 __u8 afi; 424 __u8 rsvd1[7]; 425 __le64 frs[7]; 426 __u8 rsvd64[448]; 427 }; 428 429 enum { 430 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 431 NVME_CMD_EFFECTS_LBCC = 1 << 1, 432 NVME_CMD_EFFECTS_NCC = 1 << 2, 433 NVME_CMD_EFFECTS_NIC = 1 << 3, 434 NVME_CMD_EFFECTS_CCC = 1 << 4, 435 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, 436 }; 437 438 struct nvme_effects_log { 439 __le32 acs[256]; 440 __le32 iocs[256]; 441 __u8 resv[2048]; 442 }; 443 444 enum nvme_ana_state { 445 NVME_ANA_OPTIMIZED = 0x01, 446 NVME_ANA_NONOPTIMIZED = 0x02, 447 NVME_ANA_INACCESSIBLE = 0x03, 448 NVME_ANA_PERSISTENT_LOSS = 0x04, 449 NVME_ANA_CHANGE = 0x0f, 450 }; 451 452 struct nvme_ana_group_desc { 453 __le32 grpid; 454 __le32 nnsids; 455 __le64 chgcnt; 456 __u8 state; 457 __u8 rsvd17[15]; 458 __le32 nsids[]; 459 }; 460 461 /* flag for the log specific field of the ANA log */ 462 #define NVME_ANA_LOG_RGO (1 << 0) 463 464 struct nvme_ana_rsp_hdr { 465 __le64 chgcnt; 466 __le16 ngrps; 467 __le16 rsvd10[3]; 468 }; 469 470 enum { 471 NVME_SMART_CRIT_SPARE = 1 << 0, 472 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 473 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 474 NVME_SMART_CRIT_MEDIA = 1 << 3, 475 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 476 }; 477 478 enum { 479 NVME_AER_ERROR = 0, 480 NVME_AER_SMART = 1, 481 NVME_AER_NOTICE = 2, 482 NVME_AER_CSS = 6, 483 NVME_AER_VS = 7, 484 }; 485 486 enum { 487 NVME_AER_NOTICE_NS_CHANGED = 0x00, 488 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 489 NVME_AER_NOTICE_ANA = 0x03, 490 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 491 }; 492 493 enum { 494 NVME_AEN_BIT_NS_ATTR = 8, 495 NVME_AEN_BIT_FW_ACT = 9, 496 NVME_AEN_BIT_ANA_CHANGE = 11, 497 NVME_AEN_BIT_DISC_CHANGE = 31, 498 }; 499 500 enum { 501 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 502 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 503 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 504 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 505 }; 506 507 struct nvme_lba_range_type { 508 __u8 type; 509 __u8 attributes; 510 __u8 rsvd2[14]; 511 __u64 slba; 512 __u64 nlb; 513 __u8 guid[16]; 514 __u8 rsvd48[16]; 515 }; 516 517 enum { 518 NVME_LBART_TYPE_FS = 0x01, 519 NVME_LBART_TYPE_RAID = 0x02, 520 NVME_LBART_TYPE_CACHE = 0x03, 521 NVME_LBART_TYPE_SWAP = 0x04, 522 523 NVME_LBART_ATTRIB_TEMP = 1 << 0, 524 NVME_LBART_ATTRIB_HIDE = 1 << 1, 525 }; 526 527 struct nvme_reservation_status { 528 __le32 gen; 529 __u8 rtype; 530 __u8 regctl[2]; 531 __u8 resv5[2]; 532 __u8 ptpls; 533 __u8 resv10[13]; 534 struct { 535 __le16 cntlid; 536 __u8 rcsts; 537 __u8 resv3[5]; 538 __le64 hostid; 539 __le64 rkey; 540 } regctl_ds[]; 541 }; 542 543 enum nvme_async_event_type { 544 NVME_AER_TYPE_ERROR = 0, 545 NVME_AER_TYPE_SMART = 1, 546 NVME_AER_TYPE_NOTICE = 2, 547 }; 548 549 /* I/O commands */ 550 551 enum nvme_opcode { 552 nvme_cmd_flush = 0x00, 553 nvme_cmd_write = 0x01, 554 nvme_cmd_read = 0x02, 555 nvme_cmd_write_uncor = 0x04, 556 nvme_cmd_compare = 0x05, 557 nvme_cmd_write_zeroes = 0x08, 558 nvme_cmd_dsm = 0x09, 559 nvme_cmd_resv_register = 0x0d, 560 nvme_cmd_resv_report = 0x0e, 561 nvme_cmd_resv_acquire = 0x11, 562 nvme_cmd_resv_release = 0x15, 563 }; 564 565 /* 566 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 567 * 568 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 569 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 570 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 571 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 572 * request subtype 573 */ 574 enum { 575 NVME_SGL_FMT_ADDRESS = 0x00, 576 NVME_SGL_FMT_OFFSET = 0x01, 577 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 578 NVME_SGL_FMT_INVALIDATE = 0x0f, 579 }; 580 581 /* 582 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 583 * 584 * For struct nvme_sgl_desc: 585 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 586 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 587 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 588 * 589 * For struct nvme_keyed_sgl_desc: 590 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 591 * 592 * Transport-specific SGL types: 593 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 594 */ 595 enum { 596 NVME_SGL_FMT_DATA_DESC = 0x00, 597 NVME_SGL_FMT_SEG_DESC = 0x02, 598 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 599 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 600 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 601 }; 602 603 struct nvme_sgl_desc { 604 __le64 addr; 605 __le32 length; 606 __u8 rsvd[3]; 607 __u8 type; 608 }; 609 610 struct nvme_keyed_sgl_desc { 611 __le64 addr; 612 __u8 length[3]; 613 __u8 key[4]; 614 __u8 type; 615 }; 616 617 union nvme_data_ptr { 618 struct { 619 __le64 prp1; 620 __le64 prp2; 621 }; 622 struct nvme_sgl_desc sgl; 623 struct nvme_keyed_sgl_desc ksgl; 624 }; 625 626 /* 627 * Lowest two bits of our flags field (FUSE field in the spec): 628 * 629 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 630 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 631 * 632 * Highest two bits in our flags field (PSDT field in the spec): 633 * 634 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 635 * If used, MPTR contains addr of single physical buffer (byte aligned). 636 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 637 * If used, MPTR contains an address of an SGL segment containing 638 * exactly 1 SGL descriptor (qword aligned). 639 */ 640 enum { 641 NVME_CMD_FUSE_FIRST = (1 << 0), 642 NVME_CMD_FUSE_SECOND = (1 << 1), 643 644 NVME_CMD_SGL_METABUF = (1 << 6), 645 NVME_CMD_SGL_METASEG = (1 << 7), 646 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 647 }; 648 649 struct nvme_common_command { 650 __u8 opcode; 651 __u8 flags; 652 __u16 command_id; 653 __le32 nsid; 654 __le32 cdw2[2]; 655 __le64 metadata; 656 union nvme_data_ptr dptr; 657 __le32 cdw10; 658 __le32 cdw11; 659 __le32 cdw12; 660 __le32 cdw13; 661 __le32 cdw14; 662 __le32 cdw15; 663 }; 664 665 struct nvme_rw_command { 666 __u8 opcode; 667 __u8 flags; 668 __u16 command_id; 669 __le32 nsid; 670 __u64 rsvd2; 671 __le64 metadata; 672 union nvme_data_ptr dptr; 673 __le64 slba; 674 __le16 length; 675 __le16 control; 676 __le32 dsmgmt; 677 __le32 reftag; 678 __le16 apptag; 679 __le16 appmask; 680 }; 681 682 enum { 683 NVME_RW_LR = 1 << 15, 684 NVME_RW_FUA = 1 << 14, 685 NVME_RW_DSM_FREQ_UNSPEC = 0, 686 NVME_RW_DSM_FREQ_TYPICAL = 1, 687 NVME_RW_DSM_FREQ_RARE = 2, 688 NVME_RW_DSM_FREQ_READS = 3, 689 NVME_RW_DSM_FREQ_WRITES = 4, 690 NVME_RW_DSM_FREQ_RW = 5, 691 NVME_RW_DSM_FREQ_ONCE = 6, 692 NVME_RW_DSM_FREQ_PREFETCH = 7, 693 NVME_RW_DSM_FREQ_TEMP = 8, 694 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 695 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 696 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 697 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 698 NVME_RW_DSM_SEQ_REQ = 1 << 6, 699 NVME_RW_DSM_COMPRESSED = 1 << 7, 700 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 701 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 702 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 703 NVME_RW_PRINFO_PRACT = 1 << 13, 704 NVME_RW_DTYPE_STREAMS = 1 << 4, 705 }; 706 707 struct nvme_dsm_cmd { 708 __u8 opcode; 709 __u8 flags; 710 __u16 command_id; 711 __le32 nsid; 712 __u64 rsvd2[2]; 713 union nvme_data_ptr dptr; 714 __le32 nr; 715 __le32 attributes; 716 __u32 rsvd12[4]; 717 }; 718 719 enum { 720 NVME_DSMGMT_IDR = 1 << 0, 721 NVME_DSMGMT_IDW = 1 << 1, 722 NVME_DSMGMT_AD = 1 << 2, 723 }; 724 725 #define NVME_DSM_MAX_RANGES 256 726 727 struct nvme_dsm_range { 728 __le32 cattr; 729 __le32 nlb; 730 __le64 slba; 731 }; 732 733 struct nvme_write_zeroes_cmd { 734 __u8 opcode; 735 __u8 flags; 736 __u16 command_id; 737 __le32 nsid; 738 __u64 rsvd2; 739 __le64 metadata; 740 union nvme_data_ptr dptr; 741 __le64 slba; 742 __le16 length; 743 __le16 control; 744 __le32 dsmgmt; 745 __le32 reftag; 746 __le16 apptag; 747 __le16 appmask; 748 }; 749 750 /* Features */ 751 752 struct nvme_feat_auto_pst { 753 __le64 entries[32]; 754 }; 755 756 enum { 757 NVME_HOST_MEM_ENABLE = (1 << 0), 758 NVME_HOST_MEM_RETURN = (1 << 1), 759 }; 760 761 struct nvme_feat_host_behavior { 762 __u8 acre; 763 __u8 resv1[511]; 764 }; 765 766 enum { 767 NVME_ENABLE_ACRE = 1, 768 }; 769 770 /* Admin commands */ 771 772 enum nvme_admin_opcode { 773 nvme_admin_delete_sq = 0x00, 774 nvme_admin_create_sq = 0x01, 775 nvme_admin_get_log_page = 0x02, 776 nvme_admin_delete_cq = 0x04, 777 nvme_admin_create_cq = 0x05, 778 nvme_admin_identify = 0x06, 779 nvme_admin_abort_cmd = 0x08, 780 nvme_admin_set_features = 0x09, 781 nvme_admin_get_features = 0x0a, 782 nvme_admin_async_event = 0x0c, 783 nvme_admin_ns_mgmt = 0x0d, 784 nvme_admin_activate_fw = 0x10, 785 nvme_admin_download_fw = 0x11, 786 nvme_admin_ns_attach = 0x15, 787 nvme_admin_keep_alive = 0x18, 788 nvme_admin_directive_send = 0x19, 789 nvme_admin_directive_recv = 0x1a, 790 nvme_admin_dbbuf = 0x7C, 791 nvme_admin_format_nvm = 0x80, 792 nvme_admin_security_send = 0x81, 793 nvme_admin_security_recv = 0x82, 794 nvme_admin_sanitize_nvm = 0x84, 795 }; 796 797 enum { 798 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 799 NVME_CQ_IRQ_ENABLED = (1 << 1), 800 NVME_SQ_PRIO_URGENT = (0 << 1), 801 NVME_SQ_PRIO_HIGH = (1 << 1), 802 NVME_SQ_PRIO_MEDIUM = (2 << 1), 803 NVME_SQ_PRIO_LOW = (3 << 1), 804 NVME_FEAT_ARBITRATION = 0x01, 805 NVME_FEAT_POWER_MGMT = 0x02, 806 NVME_FEAT_LBA_RANGE = 0x03, 807 NVME_FEAT_TEMP_THRESH = 0x04, 808 NVME_FEAT_ERR_RECOVERY = 0x05, 809 NVME_FEAT_VOLATILE_WC = 0x06, 810 NVME_FEAT_NUM_QUEUES = 0x07, 811 NVME_FEAT_IRQ_COALESCE = 0x08, 812 NVME_FEAT_IRQ_CONFIG = 0x09, 813 NVME_FEAT_WRITE_ATOMIC = 0x0a, 814 NVME_FEAT_ASYNC_EVENT = 0x0b, 815 NVME_FEAT_AUTO_PST = 0x0c, 816 NVME_FEAT_HOST_MEM_BUF = 0x0d, 817 NVME_FEAT_TIMESTAMP = 0x0e, 818 NVME_FEAT_KATO = 0x0f, 819 NVME_FEAT_HCTM = 0x10, 820 NVME_FEAT_NOPSC = 0x11, 821 NVME_FEAT_RRL = 0x12, 822 NVME_FEAT_PLM_CONFIG = 0x13, 823 NVME_FEAT_PLM_WINDOW = 0x14, 824 NVME_FEAT_HOST_BEHAVIOR = 0x16, 825 NVME_FEAT_SW_PROGRESS = 0x80, 826 NVME_FEAT_HOST_ID = 0x81, 827 NVME_FEAT_RESV_MASK = 0x82, 828 NVME_FEAT_RESV_PERSIST = 0x83, 829 NVME_FEAT_WRITE_PROTECT = 0x84, 830 NVME_LOG_ERROR = 0x01, 831 NVME_LOG_SMART = 0x02, 832 NVME_LOG_FW_SLOT = 0x03, 833 NVME_LOG_CHANGED_NS = 0x04, 834 NVME_LOG_CMD_EFFECTS = 0x05, 835 NVME_LOG_ANA = 0x0c, 836 NVME_LOG_DISC = 0x70, 837 NVME_LOG_RESERVATION = 0x80, 838 NVME_FWACT_REPL = (0 << 3), 839 NVME_FWACT_REPL_ACTV = (1 << 3), 840 NVME_FWACT_ACTV = (2 << 3), 841 }; 842 843 /* NVMe Namespace Write Protect State */ 844 enum { 845 NVME_NS_NO_WRITE_PROTECT = 0, 846 NVME_NS_WRITE_PROTECT, 847 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 848 NVME_NS_WRITE_PROTECT_PERMANENT, 849 }; 850 851 #define NVME_MAX_CHANGED_NAMESPACES 1024 852 853 struct nvme_identify { 854 __u8 opcode; 855 __u8 flags; 856 __u16 command_id; 857 __le32 nsid; 858 __u64 rsvd2[2]; 859 union nvme_data_ptr dptr; 860 __u8 cns; 861 __u8 rsvd3; 862 __le16 ctrlid; 863 __u32 rsvd11[5]; 864 }; 865 866 #define NVME_IDENTIFY_DATA_SIZE 4096 867 868 struct nvme_features { 869 __u8 opcode; 870 __u8 flags; 871 __u16 command_id; 872 __le32 nsid; 873 __u64 rsvd2[2]; 874 union nvme_data_ptr dptr; 875 __le32 fid; 876 __le32 dword11; 877 __le32 dword12; 878 __le32 dword13; 879 __le32 dword14; 880 __le32 dword15; 881 }; 882 883 struct nvme_host_mem_buf_desc { 884 __le64 addr; 885 __le32 size; 886 __u32 rsvd; 887 }; 888 889 struct nvme_create_cq { 890 __u8 opcode; 891 __u8 flags; 892 __u16 command_id; 893 __u32 rsvd1[5]; 894 __le64 prp1; 895 __u64 rsvd8; 896 __le16 cqid; 897 __le16 qsize; 898 __le16 cq_flags; 899 __le16 irq_vector; 900 __u32 rsvd12[4]; 901 }; 902 903 struct nvme_create_sq { 904 __u8 opcode; 905 __u8 flags; 906 __u16 command_id; 907 __u32 rsvd1[5]; 908 __le64 prp1; 909 __u64 rsvd8; 910 __le16 sqid; 911 __le16 qsize; 912 __le16 sq_flags; 913 __le16 cqid; 914 __u32 rsvd12[4]; 915 }; 916 917 struct nvme_delete_queue { 918 __u8 opcode; 919 __u8 flags; 920 __u16 command_id; 921 __u32 rsvd1[9]; 922 __le16 qid; 923 __u16 rsvd10; 924 __u32 rsvd11[5]; 925 }; 926 927 struct nvme_abort_cmd { 928 __u8 opcode; 929 __u8 flags; 930 __u16 command_id; 931 __u32 rsvd1[9]; 932 __le16 sqid; 933 __u16 cid; 934 __u32 rsvd11[5]; 935 }; 936 937 struct nvme_download_firmware { 938 __u8 opcode; 939 __u8 flags; 940 __u16 command_id; 941 __u32 rsvd1[5]; 942 union nvme_data_ptr dptr; 943 __le32 numd; 944 __le32 offset; 945 __u32 rsvd12[4]; 946 }; 947 948 struct nvme_format_cmd { 949 __u8 opcode; 950 __u8 flags; 951 __u16 command_id; 952 __le32 nsid; 953 __u64 rsvd2[4]; 954 __le32 cdw10; 955 __u32 rsvd11[5]; 956 }; 957 958 struct nvme_get_log_page_command { 959 __u8 opcode; 960 __u8 flags; 961 __u16 command_id; 962 __le32 nsid; 963 __u64 rsvd2[2]; 964 union nvme_data_ptr dptr; 965 __u8 lid; 966 __u8 lsp; /* upper 4 bits reserved */ 967 __le16 numdl; 968 __le16 numdu; 969 __u16 rsvd11; 970 union { 971 struct { 972 __le32 lpol; 973 __le32 lpou; 974 }; 975 __le64 lpo; 976 }; 977 __u32 rsvd14[2]; 978 }; 979 980 struct nvme_directive_cmd { 981 __u8 opcode; 982 __u8 flags; 983 __u16 command_id; 984 __le32 nsid; 985 __u64 rsvd2[2]; 986 union nvme_data_ptr dptr; 987 __le32 numd; 988 __u8 doper; 989 __u8 dtype; 990 __le16 dspec; 991 __u8 endir; 992 __u8 tdtype; 993 __u16 rsvd15; 994 995 __u32 rsvd16[3]; 996 }; 997 998 /* 999 * Fabrics subcommands. 1000 */ 1001 enum nvmf_fabrics_opcode { 1002 nvme_fabrics_command = 0x7f, 1003 }; 1004 1005 enum nvmf_capsule_command { 1006 nvme_fabrics_type_property_set = 0x00, 1007 nvme_fabrics_type_connect = 0x01, 1008 nvme_fabrics_type_property_get = 0x04, 1009 }; 1010 1011 struct nvmf_common_command { 1012 __u8 opcode; 1013 __u8 resv1; 1014 __u16 command_id; 1015 __u8 fctype; 1016 __u8 resv2[35]; 1017 __u8 ts[24]; 1018 }; 1019 1020 /* 1021 * The legal cntlid range a NVMe Target will provide. 1022 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1023 * Devices based on earlier specs did not have the subsystem concept; 1024 * therefore, those devices had their cntlid value set to 0 as a result. 1025 */ 1026 #define NVME_CNTLID_MIN 1 1027 #define NVME_CNTLID_MAX 0xffef 1028 #define NVME_CNTLID_DYNAMIC 0xffff 1029 1030 #define MAX_DISC_LOGS 255 1031 1032 /* Discovery log page entry */ 1033 struct nvmf_disc_rsp_page_entry { 1034 __u8 trtype; 1035 __u8 adrfam; 1036 __u8 subtype; 1037 __u8 treq; 1038 __le16 portid; 1039 __le16 cntlid; 1040 __le16 asqsz; 1041 __u8 resv8[22]; 1042 char trsvcid[NVMF_TRSVCID_SIZE]; 1043 __u8 resv64[192]; 1044 char subnqn[NVMF_NQN_FIELD_LEN]; 1045 char traddr[NVMF_TRADDR_SIZE]; 1046 union tsas { 1047 char common[NVMF_TSAS_SIZE]; 1048 struct rdma { 1049 __u8 qptype; 1050 __u8 prtype; 1051 __u8 cms; 1052 __u8 resv3[5]; 1053 __u16 pkey; 1054 __u8 resv10[246]; 1055 } rdma; 1056 } tsas; 1057 }; 1058 1059 /* Discovery log page header */ 1060 struct nvmf_disc_rsp_page_hdr { 1061 __le64 genctr; 1062 __le64 numrec; 1063 __le16 recfmt; 1064 __u8 resv14[1006]; 1065 struct nvmf_disc_rsp_page_entry entries[0]; 1066 }; 1067 1068 enum { 1069 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1070 }; 1071 1072 struct nvmf_connect_command { 1073 __u8 opcode; 1074 __u8 resv1; 1075 __u16 command_id; 1076 __u8 fctype; 1077 __u8 resv2[19]; 1078 union nvme_data_ptr dptr; 1079 __le16 recfmt; 1080 __le16 qid; 1081 __le16 sqsize; 1082 __u8 cattr; 1083 __u8 resv3; 1084 __le32 kato; 1085 __u8 resv4[12]; 1086 }; 1087 1088 struct nvmf_connect_data { 1089 uuid_t hostid; 1090 __le16 cntlid; 1091 char resv4[238]; 1092 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1093 char hostnqn[NVMF_NQN_FIELD_LEN]; 1094 char resv5[256]; 1095 }; 1096 1097 struct nvmf_property_set_command { 1098 __u8 opcode; 1099 __u8 resv1; 1100 __u16 command_id; 1101 __u8 fctype; 1102 __u8 resv2[35]; 1103 __u8 attrib; 1104 __u8 resv3[3]; 1105 __le32 offset; 1106 __le64 value; 1107 __u8 resv4[8]; 1108 }; 1109 1110 struct nvmf_property_get_command { 1111 __u8 opcode; 1112 __u8 resv1; 1113 __u16 command_id; 1114 __u8 fctype; 1115 __u8 resv2[35]; 1116 __u8 attrib; 1117 __u8 resv3[3]; 1118 __le32 offset; 1119 __u8 resv4[16]; 1120 }; 1121 1122 struct nvme_dbbuf { 1123 __u8 opcode; 1124 __u8 flags; 1125 __u16 command_id; 1126 __u32 rsvd1[5]; 1127 __le64 prp1; 1128 __le64 prp2; 1129 __u32 rsvd12[6]; 1130 }; 1131 1132 struct streams_directive_params { 1133 __le16 msl; 1134 __le16 nssa; 1135 __le16 nsso; 1136 __u8 rsvd[10]; 1137 __le32 sws; 1138 __le16 sgs; 1139 __le16 nsa; 1140 __le16 nso; 1141 __u8 rsvd2[6]; 1142 }; 1143 1144 struct nvme_command { 1145 union { 1146 struct nvme_common_command common; 1147 struct nvme_rw_command rw; 1148 struct nvme_identify identify; 1149 struct nvme_features features; 1150 struct nvme_create_cq create_cq; 1151 struct nvme_create_sq create_sq; 1152 struct nvme_delete_queue delete_queue; 1153 struct nvme_download_firmware dlfw; 1154 struct nvme_format_cmd format; 1155 struct nvme_dsm_cmd dsm; 1156 struct nvme_write_zeroes_cmd write_zeroes; 1157 struct nvme_abort_cmd abort; 1158 struct nvme_get_log_page_command get_log_page; 1159 struct nvmf_common_command fabrics; 1160 struct nvmf_connect_command connect; 1161 struct nvmf_property_set_command prop_set; 1162 struct nvmf_property_get_command prop_get; 1163 struct nvme_dbbuf dbbuf; 1164 struct nvme_directive_cmd directive; 1165 }; 1166 }; 1167 1168 struct nvme_error_slot { 1169 __le64 error_count; 1170 __le16 sqid; 1171 __le16 cmdid; 1172 __le16 status_field; 1173 __le16 param_error_location; 1174 __le64 lba; 1175 __le32 nsid; 1176 __u8 vs; 1177 __u8 resv[3]; 1178 __le64 cs; 1179 __u8 resv2[24]; 1180 }; 1181 1182 static inline bool nvme_is_write(struct nvme_command *cmd) 1183 { 1184 /* 1185 * What a mess... 1186 * 1187 * Why can't we simply have a Fabrics In and Fabrics out command? 1188 */ 1189 if (unlikely(cmd->common.opcode == nvme_fabrics_command)) 1190 return cmd->fabrics.fctype & 1; 1191 return cmd->common.opcode & 1; 1192 } 1193 1194 enum { 1195 /* 1196 * Generic Command Status: 1197 */ 1198 NVME_SC_SUCCESS = 0x0, 1199 NVME_SC_INVALID_OPCODE = 0x1, 1200 NVME_SC_INVALID_FIELD = 0x2, 1201 NVME_SC_CMDID_CONFLICT = 0x3, 1202 NVME_SC_DATA_XFER_ERROR = 0x4, 1203 NVME_SC_POWER_LOSS = 0x5, 1204 NVME_SC_INTERNAL = 0x6, 1205 NVME_SC_ABORT_REQ = 0x7, 1206 NVME_SC_ABORT_QUEUE = 0x8, 1207 NVME_SC_FUSED_FAIL = 0x9, 1208 NVME_SC_FUSED_MISSING = 0xa, 1209 NVME_SC_INVALID_NS = 0xb, 1210 NVME_SC_CMD_SEQ_ERROR = 0xc, 1211 NVME_SC_SGL_INVALID_LAST = 0xd, 1212 NVME_SC_SGL_INVALID_COUNT = 0xe, 1213 NVME_SC_SGL_INVALID_DATA = 0xf, 1214 NVME_SC_SGL_INVALID_METADATA = 0x10, 1215 NVME_SC_SGL_INVALID_TYPE = 0x11, 1216 1217 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1218 NVME_SC_SGL_INVALID_SUBTYPE = 0x17, 1219 1220 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1221 1222 NVME_SC_LBA_RANGE = 0x80, 1223 NVME_SC_CAP_EXCEEDED = 0x81, 1224 NVME_SC_NS_NOT_READY = 0x82, 1225 NVME_SC_RESERVATION_CONFLICT = 0x83, 1226 1227 /* 1228 * Command Specific Status: 1229 */ 1230 NVME_SC_CQ_INVALID = 0x100, 1231 NVME_SC_QID_INVALID = 0x101, 1232 NVME_SC_QUEUE_SIZE = 0x102, 1233 NVME_SC_ABORT_LIMIT = 0x103, 1234 NVME_SC_ABORT_MISSING = 0x104, 1235 NVME_SC_ASYNC_LIMIT = 0x105, 1236 NVME_SC_FIRMWARE_SLOT = 0x106, 1237 NVME_SC_FIRMWARE_IMAGE = 0x107, 1238 NVME_SC_INVALID_VECTOR = 0x108, 1239 NVME_SC_INVALID_LOG_PAGE = 0x109, 1240 NVME_SC_INVALID_FORMAT = 0x10a, 1241 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1242 NVME_SC_INVALID_QUEUE = 0x10c, 1243 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1244 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1245 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1246 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1247 NVME_SC_FW_NEEDS_RESET = 0x111, 1248 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1249 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1250 NVME_SC_OVERLAPPING_RANGE = 0x114, 1251 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1252 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1253 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1254 NVME_SC_NS_IS_PRIVATE = 0x119, 1255 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1256 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1257 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1258 1259 /* 1260 * I/O Command Set Specific - NVM commands: 1261 */ 1262 NVME_SC_BAD_ATTRIBUTES = 0x180, 1263 NVME_SC_INVALID_PI = 0x181, 1264 NVME_SC_READ_ONLY = 0x182, 1265 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1266 1267 /* 1268 * I/O Command Set Specific - Fabrics commands: 1269 */ 1270 NVME_SC_CONNECT_FORMAT = 0x180, 1271 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1272 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1273 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1274 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1275 1276 NVME_SC_DISCOVERY_RESTART = 0x190, 1277 NVME_SC_AUTH_REQUIRED = 0x191, 1278 1279 /* 1280 * Media and Data Integrity Errors: 1281 */ 1282 NVME_SC_WRITE_FAULT = 0x280, 1283 NVME_SC_READ_ERROR = 0x281, 1284 NVME_SC_GUARD_CHECK = 0x282, 1285 NVME_SC_APPTAG_CHECK = 0x283, 1286 NVME_SC_REFTAG_CHECK = 0x284, 1287 NVME_SC_COMPARE_FAILED = 0x285, 1288 NVME_SC_ACCESS_DENIED = 0x286, 1289 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1290 1291 /* 1292 * Path-related Errors: 1293 */ 1294 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1295 NVME_SC_ANA_INACCESSIBLE = 0x302, 1296 NVME_SC_ANA_TRANSITION = 0x303, 1297 NVME_SC_HOST_PATH_ERROR = 0x370, 1298 1299 NVME_SC_CRD = 0x1800, 1300 NVME_SC_DNR = 0x4000, 1301 }; 1302 1303 struct nvme_completion { 1304 /* 1305 * Used by Admin and Fabrics commands to return data: 1306 */ 1307 union nvme_result { 1308 __le16 u16; 1309 __le32 u32; 1310 __le64 u64; 1311 } result; 1312 __le16 sq_head; /* how much of this queue may be reclaimed */ 1313 __le16 sq_id; /* submission queue that generated this entry */ 1314 __u16 command_id; /* of the command which completed */ 1315 __le16 status; /* did the command fail, and if so, why? */ 1316 }; 1317 1318 #define NVME_VS(major, minor, tertiary) \ 1319 (((major) << 16) | ((minor) << 8) | (tertiary)) 1320 1321 #define NVME_MAJOR(ver) ((ver) >> 16) 1322 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 1323 #define NVME_TERTIARY(ver) ((ver) & 0xff) 1324 1325 #endif /* _LINUX_NVME_H */ 1326