1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <[email protected]> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #include <linux/mutex.h> 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/nand.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/spi-mem.h> 18 19 /** 20 * Standard SPI NAND flash operations 21 */ 22 23 #define SPINAND_RESET_OP \ 24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 25 SPI_MEM_OP_NO_ADDR, \ 26 SPI_MEM_OP_NO_DUMMY, \ 27 SPI_MEM_OP_NO_DATA) 28 29 #define SPINAND_WR_EN_DIS_OP(enable) \ 30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 31 SPI_MEM_OP_NO_ADDR, \ 32 SPI_MEM_OP_NO_DUMMY, \ 33 SPI_MEM_OP_NO_DATA) 34 35 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 37 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 38 SPI_MEM_OP_DUMMY(ndummy, 1), \ 39 SPI_MEM_OP_DATA_IN(len, buf, 1)) 40 41 #define SPINAND_SET_FEATURE_OP(reg, valptr) \ 42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 43 SPI_MEM_OP_ADDR(1, reg, 1), \ 44 SPI_MEM_OP_NO_DUMMY, \ 45 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 46 47 #define SPINAND_GET_FEATURE_OP(reg, valptr) \ 48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 49 SPI_MEM_OP_ADDR(1, reg, 1), \ 50 SPI_MEM_OP_NO_DUMMY, \ 51 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 52 53 #define SPINAND_BLK_ERASE_OP(addr) \ 54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 55 SPI_MEM_OP_ADDR(3, addr, 1), \ 56 SPI_MEM_OP_NO_DUMMY, \ 57 SPI_MEM_OP_NO_DATA) 58 59 #define SPINAND_PAGE_READ_OP(addr) \ 60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 61 SPI_MEM_OP_ADDR(3, addr, 1), \ 62 SPI_MEM_OP_NO_DUMMY, \ 63 SPI_MEM_OP_NO_DATA) 64 65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(addr, ndummy, buf, len, ...) \ 66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 67 SPI_MEM_OP_ADDR(2, addr, 1), \ 68 SPI_MEM_OP_DUMMY(ndummy, 1), \ 69 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 70 __VA_OPT__(SPI_MEM_OP_MAX_FREQ(__VA_ARGS__))) 71 72 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(addr, ndummy, buf, len) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(addr, ndummy, buf, len) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 80 SPI_MEM_OP_ADDR(3, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 1)) 83 84 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP_3A(addr, ndummy, buf, len) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 86 SPI_MEM_OP_ADDR(3, addr, 1), \ 87 SPI_MEM_OP_DUMMY(ndummy, 1), \ 88 SPI_MEM_OP_DATA_IN(len, buf, 1)) 89 90 #define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \ 91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \ 92 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 93 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 94 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \ 95 SPI_MEM_OP_MAX_FREQ(freq)) 96 97 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 98 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 99 SPI_MEM_OP_ADDR(2, addr, 1), \ 100 SPI_MEM_OP_DUMMY(ndummy, 1), \ 101 SPI_MEM_OP_DATA_IN(len, buf, 2)) 102 103 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ 104 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 105 SPI_MEM_OP_ADDR(3, addr, 1), \ 106 SPI_MEM_OP_DUMMY(ndummy, 1), \ 107 SPI_MEM_OP_DATA_IN(len, buf, 2)) 108 109 #define SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(addr, ndummy, buf, len, freq) \ 110 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \ 111 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 112 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 113 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 114 SPI_MEM_OP_MAX_FREQ(freq)) 115 116 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 117 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 118 SPI_MEM_OP_ADDR(2, addr, 1), \ 119 SPI_MEM_OP_DUMMY(ndummy, 1), \ 120 SPI_MEM_OP_DATA_IN(len, buf, 4)) 121 122 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ 123 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 124 SPI_MEM_OP_ADDR(3, addr, 1), \ 125 SPI_MEM_OP_DUMMY(ndummy, 1), \ 126 SPI_MEM_OP_DATA_IN(len, buf, 4)) 127 128 #define SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(addr, ndummy, buf, len, freq) \ 129 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \ 130 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 131 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 132 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 133 SPI_MEM_OP_MAX_FREQ(freq)) 134 135 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 136 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 137 SPI_MEM_OP_ADDR(2, addr, 2), \ 138 SPI_MEM_OP_DUMMY(ndummy, 2), \ 139 SPI_MEM_OP_DATA_IN(len, buf, 2)) 140 141 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ 142 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 143 SPI_MEM_OP_ADDR(3, addr, 2), \ 144 SPI_MEM_OP_DUMMY(ndummy, 2), \ 145 SPI_MEM_OP_DATA_IN(len, buf, 2)) 146 147 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(addr, ndummy, buf, len, freq) \ 148 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \ 149 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \ 150 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \ 151 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 152 SPI_MEM_OP_MAX_FREQ(freq)) 153 154 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 155 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 156 SPI_MEM_OP_ADDR(2, addr, 4), \ 157 SPI_MEM_OP_DUMMY(ndummy, 4), \ 158 SPI_MEM_OP_DATA_IN(len, buf, 4)) 159 160 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ 161 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 162 SPI_MEM_OP_ADDR(3, addr, 4), \ 163 SPI_MEM_OP_DUMMY(ndummy, 4), \ 164 SPI_MEM_OP_DATA_IN(len, buf, 4)) 165 166 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(addr, ndummy, buf, len, freq) \ 167 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \ 168 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \ 169 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \ 170 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 171 SPI_MEM_OP_MAX_FREQ(freq)) 172 173 #define SPINAND_PROG_EXEC_OP(addr) \ 174 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 175 SPI_MEM_OP_ADDR(3, addr, 1), \ 176 SPI_MEM_OP_NO_DUMMY, \ 177 SPI_MEM_OP_NO_DATA) 178 179 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 180 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 181 SPI_MEM_OP_ADDR(2, addr, 1), \ 182 SPI_MEM_OP_NO_DUMMY, \ 183 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 184 185 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 186 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 187 SPI_MEM_OP_ADDR(2, addr, 1), \ 188 SPI_MEM_OP_NO_DUMMY, \ 189 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 190 191 /** 192 * Standard SPI NAND flash commands 193 */ 194 #define SPINAND_CMD_PROG_LOAD_X4 0x32 195 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 196 197 /* feature register */ 198 #define REG_BLOCK_LOCK 0xa0 199 #define BL_ALL_UNLOCKED 0x00 200 201 /* configuration register */ 202 #define REG_CFG 0xb0 203 #define CFG_OTP_ENABLE BIT(6) 204 #define CFG_ECC_ENABLE BIT(4) 205 #define CFG_QUAD_ENABLE BIT(0) 206 207 /* status register */ 208 #define REG_STATUS 0xc0 209 #define STATUS_BUSY BIT(0) 210 #define STATUS_ERASE_FAILED BIT(2) 211 #define STATUS_PROG_FAILED BIT(3) 212 #define STATUS_ECC_MASK GENMASK(5, 4) 213 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 214 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 215 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 216 217 struct spinand_op; 218 struct spinand_device; 219 220 #define SPINAND_MAX_ID_LEN 5 221 /* 222 * For erase, write and read operation, we got the following timings : 223 * tBERS (erase) 1ms to 4ms 224 * tPROG 300us to 400us 225 * tREAD 25us to 100us 226 * In order to minimize latency, the min value is divided by 4 for the 227 * initial delay, and dividing by 20 for the poll delay. 228 * For reset, 5us/10us/500us if the device is respectively 229 * reading/programming/erasing when the RESET occurs. Since we always 230 * issue a RESET when the device is IDLE, 5us is selected for both initial 231 * and poll delay. 232 */ 233 #define SPINAND_READ_INITIAL_DELAY_US 6 234 #define SPINAND_READ_POLL_DELAY_US 5 235 #define SPINAND_RESET_INITIAL_DELAY_US 5 236 #define SPINAND_RESET_POLL_DELAY_US 5 237 #define SPINAND_WRITE_INITIAL_DELAY_US 75 238 #define SPINAND_WRITE_POLL_DELAY_US 15 239 #define SPINAND_ERASE_INITIAL_DELAY_US 250 240 #define SPINAND_ERASE_POLL_DELAY_US 50 241 242 #define SPINAND_WAITRDY_TIMEOUT_MS 400 243 244 /** 245 * struct spinand_id - SPI NAND id structure 246 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 247 * be extended if required 248 * @len: ID length 249 */ 250 struct spinand_id { 251 u8 data[SPINAND_MAX_ID_LEN]; 252 int len; 253 }; 254 255 enum spinand_readid_method { 256 SPINAND_READID_METHOD_OPCODE, 257 SPINAND_READID_METHOD_OPCODE_ADDR, 258 SPINAND_READID_METHOD_OPCODE_DUMMY, 259 }; 260 261 /** 262 * struct spinand_devid - SPI NAND device id structure 263 * @id: device id of current chip 264 * @len: number of bytes in device id 265 * @method: method to read chip id 266 * There are 3 possible variants: 267 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 268 * after read_id opcode. 269 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 270 * read_id opcode + 1-byte address. 271 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 272 * read_id opcode + 1 dummy byte. 273 */ 274 struct spinand_devid { 275 const u8 *id; 276 const u8 len; 277 const enum spinand_readid_method method; 278 }; 279 280 /** 281 * struct manufacurer_ops - SPI NAND manufacturer specific operations 282 * @init: initialize a SPI NAND device 283 * @cleanup: cleanup a SPI NAND device 284 * 285 * Each SPI NAND manufacturer driver should implement this interface so that 286 * NAND chips coming from this vendor can be initialized properly. 287 */ 288 struct spinand_manufacturer_ops { 289 int (*init)(struct spinand_device *spinand); 290 void (*cleanup)(struct spinand_device *spinand); 291 }; 292 293 /** 294 * struct spinand_manufacturer - SPI NAND manufacturer instance 295 * @id: manufacturer ID 296 * @name: manufacturer name 297 * @devid_len: number of bytes in device ID 298 * @chips: supported SPI NANDs under current manufacturer 299 * @nchips: number of SPI NANDs available in chips array 300 * @ops: manufacturer operations 301 */ 302 struct spinand_manufacturer { 303 u8 id; 304 char *name; 305 const struct spinand_info *chips; 306 const size_t nchips; 307 const struct spinand_manufacturer_ops *ops; 308 }; 309 310 /* SPI NAND manufacturers */ 311 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; 312 extern const struct spinand_manufacturer ato_spinand_manufacturer; 313 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; 314 extern const struct spinand_manufacturer foresee_spinand_manufacturer; 315 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 316 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 317 extern const struct spinand_manufacturer micron_spinand_manufacturer; 318 extern const struct spinand_manufacturer paragon_spinand_manufacturer; 319 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer; 320 extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 321 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 322 extern const struct spinand_manufacturer xtx_spinand_manufacturer; 323 324 /** 325 * struct spinand_op_variants - SPI NAND operation variants 326 * @ops: the list of variants for a given operation 327 * @nops: the number of variants 328 * 329 * Some operations like read-from-cache/write-to-cache have several variants 330 * depending on the number of IO lines you use to transfer data or address 331 * cycles. This structure is a way to describe the different variants supported 332 * by a chip and let the core pick the best one based on the SPI mem controller 333 * capabilities. 334 */ 335 struct spinand_op_variants { 336 const struct spi_mem_op *ops; 337 unsigned int nops; 338 }; 339 340 #define SPINAND_OP_VARIANTS(name, ...) \ 341 const struct spinand_op_variants name = { \ 342 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 343 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 344 sizeof(struct spi_mem_op), \ 345 } 346 347 /** 348 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 349 * chip 350 * @get_status: get the ECC status. Should return a positive number encoding 351 * the number of corrected bitflips if correction was possible or 352 * -EBADMSG if there are uncorrectable errors. I can also return 353 * other negative error codes if the error is not caused by 354 * uncorrectable bitflips 355 * @ooblayout: the OOB layout used by the on-die ECC implementation 356 */ 357 struct spinand_ecc_info { 358 int (*get_status)(struct spinand_device *spinand, u8 status); 359 const struct mtd_ooblayout_ops *ooblayout; 360 }; 361 362 #define SPINAND_HAS_QE_BIT BIT(0) 363 #define SPINAND_HAS_CR_FEAT_BIT BIT(1) 364 #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) 365 #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) 366 #define SPINAND_NO_RAW_ACCESS BIT(4) 367 368 /** 369 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure 370 * @status: status of the last wait operation that will be used in case 371 * ->get_status() is not populated by the spinand device. 372 */ 373 struct spinand_ondie_ecc_conf { 374 u8 status; 375 }; 376 377 /** 378 * struct spinand_info - Structure used to describe SPI NAND chips 379 * @model: model name 380 * @devid: device ID 381 * @flags: OR-ing of the SPINAND_XXX flags 382 * @memorg: memory organization 383 * @eccreq: ECC requirements 384 * @eccinfo: on-die ECC info 385 * @op_variants: operations variants 386 * @op_variants.read_cache: variants of the read-cache operation 387 * @op_variants.write_cache: variants of the write-cache operation 388 * @op_variants.update_cache: variants of the update-cache operation 389 * @select_target: function used to select a target/die. Required only for 390 * multi-die chips 391 * @set_cont_read: enable/disable continuous cached reads 392 * 393 * Each SPI NAND manufacturer driver should have a spinand_info table 394 * describing all the chips supported by the driver. 395 */ 396 struct spinand_info { 397 const char *model; 398 struct spinand_devid devid; 399 u32 flags; 400 struct nand_memory_organization memorg; 401 struct nand_ecc_props eccreq; 402 struct spinand_ecc_info eccinfo; 403 struct { 404 const struct spinand_op_variants *read_cache; 405 const struct spinand_op_variants *write_cache; 406 const struct spinand_op_variants *update_cache; 407 } op_variants; 408 int (*select_target)(struct spinand_device *spinand, 409 unsigned int target); 410 int (*set_cont_read)(struct spinand_device *spinand, 411 bool enable); 412 }; 413 414 #define SPINAND_ID(__method, ...) \ 415 { \ 416 .id = (const u8[]){ __VA_ARGS__ }, \ 417 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 418 .method = __method, \ 419 } 420 421 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 422 { \ 423 .read_cache = __read, \ 424 .write_cache = __write, \ 425 .update_cache = __update, \ 426 } 427 428 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 429 .eccinfo = { \ 430 .ooblayout = __ooblayout, \ 431 .get_status = __get_status, \ 432 } 433 434 #define SPINAND_SELECT_TARGET(__func) \ 435 .select_target = __func, 436 437 #define SPINAND_CONT_READ(__set_cont_read) \ 438 .set_cont_read = __set_cont_read, 439 440 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 441 __flags, ...) \ 442 { \ 443 .model = __model, \ 444 .devid = __id, \ 445 .memorg = __memorg, \ 446 .eccreq = __eccreq, \ 447 .op_variants = __op_variants, \ 448 .flags = __flags, \ 449 __VA_ARGS__ \ 450 } 451 452 struct spinand_dirmap { 453 struct spi_mem_dirmap_desc *wdesc; 454 struct spi_mem_dirmap_desc *rdesc; 455 struct spi_mem_dirmap_desc *wdesc_ecc; 456 struct spi_mem_dirmap_desc *rdesc_ecc; 457 }; 458 459 /** 460 * struct spinand_device - SPI NAND device instance 461 * @base: NAND device instance 462 * @spimem: pointer to the SPI mem object 463 * @lock: lock used to serialize accesses to the NAND 464 * @id: NAND ID as returned by READ_ID 465 * @flags: NAND flags 466 * @op_templates: various SPI mem op templates 467 * @op_templates.read_cache: read cache op template 468 * @op_templates.write_cache: write cache op template 469 * @op_templates.update_cache: update cache op template 470 * @select_target: select a specific target/die. Usually called before sending 471 * a command addressing a page or an eraseblock embedded in 472 * this die. Only required if your chip exposes several dies 473 * @cur_target: currently selected target/die 474 * @eccinfo: on-die ECC information 475 * @cfg_cache: config register cache. One entry per die 476 * @databuf: bounce buffer for data 477 * @oobbuf: bounce buffer for OOB data 478 * @scratchbuf: buffer used for everything but page accesses. This is needed 479 * because the spi-mem interface explicitly requests that buffers 480 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 481 * the stack 482 * @manufacturer: SPI NAND manufacturer information 483 * @cont_read_possible: Field filled by the core once the whole system 484 * configuration is known to tell whether continuous reads are 485 * suitable to use or not in general with this chip/configuration. 486 * A per-transfer check must of course be done to ensure it is 487 * actually relevant to enable this feature. 488 * @set_cont_read: Enable/disable the continuous read feature 489 * @priv: manufacturer private data 490 */ 491 struct spinand_device { 492 struct nand_device base; 493 struct spi_mem *spimem; 494 struct mutex lock; 495 struct spinand_id id; 496 u32 flags; 497 498 struct { 499 const struct spi_mem_op *read_cache; 500 const struct spi_mem_op *write_cache; 501 const struct spi_mem_op *update_cache; 502 } op_templates; 503 504 struct spinand_dirmap *dirmaps; 505 506 int (*select_target)(struct spinand_device *spinand, 507 unsigned int target); 508 unsigned int cur_target; 509 510 struct spinand_ecc_info eccinfo; 511 512 u8 *cfg_cache; 513 u8 *databuf; 514 u8 *oobbuf; 515 u8 *scratchbuf; 516 const struct spinand_manufacturer *manufacturer; 517 void *priv; 518 519 bool cont_read_possible; 520 int (*set_cont_read)(struct spinand_device *spinand, 521 bool enable); 522 }; 523 524 /** 525 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 526 * @mtd: MTD instance 527 * 528 * Return: the SPI NAND device attached to @mtd. 529 */ 530 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 531 { 532 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 533 } 534 535 /** 536 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 537 * @spinand: SPI NAND device 538 * 539 * Return: the MTD device embedded in @spinand. 540 */ 541 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 542 { 543 return nanddev_to_mtd(&spinand->base); 544 } 545 546 /** 547 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 548 * @nand: NAND object 549 * 550 * Return: the SPI NAND device embedding @nand. 551 */ 552 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 553 { 554 return container_of(nand, struct spinand_device, base); 555 } 556 557 /** 558 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 559 * @spinand: SPI NAND device 560 * 561 * Return: the NAND device embedded in @spinand. 562 */ 563 static inline struct nand_device * 564 spinand_to_nand(struct spinand_device *spinand) 565 { 566 return &spinand->base; 567 } 568 569 /** 570 * spinand_set_of_node - Attach a DT node to a SPI NAND device 571 * @spinand: SPI NAND device 572 * @np: DT node 573 * 574 * Attach a DT node to a SPI NAND device. 575 */ 576 static inline void spinand_set_of_node(struct spinand_device *spinand, 577 struct device_node *np) 578 { 579 nanddev_set_of_node(&spinand->base, np); 580 } 581 582 int spinand_match_and_init(struct spinand_device *spinand, 583 const struct spinand_info *table, 584 unsigned int table_size, 585 enum spinand_readid_method rdid_method); 586 587 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 588 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val); 589 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 590 591 #endif /* __LINUX_MTD_SPINAND_H */ 592