1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LINUX_MTD_SPI_NOR_H 7 #define __LINUX_MTD_SPI_NOR_H 8 9 #include <linux/bitops.h> 10 #include <linux/mtd/cfi.h> 11 #include <linux/mtd/mtd.h> 12 13 /* 14 * Manufacturer IDs 15 * 16 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 17 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 18 */ 19 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 20 #define SNOR_MFR_GIGADEVICE 0xc8 21 #define SNOR_MFR_INTEL CFI_MFR_INTEL 22 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ 23 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ 24 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 25 #define SNOR_MFR_SPANSION CFI_MFR_AMD 26 #define SNOR_MFR_SST CFI_MFR_SST 27 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 28 29 /* 30 * Note on opcode nomenclature: some opcodes have a format like 31 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 32 * of I/O lines used for the opcode, address, and data (respectively). The 33 * FUNCTION has an optional suffix of '4', to represent an opcode which 34 * requires a 4-byte (32-bit) address. 35 */ 36 37 /* Flash opcodes. */ 38 #define SPINOR_OP_WREN 0x06 /* Write enable */ 39 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 40 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 41 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ 42 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ 43 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 44 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 45 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ 46 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ 47 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ 48 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ 49 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ 50 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ 51 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 52 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ 53 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ 54 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ 55 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ 56 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 57 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 58 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 59 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 60 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 61 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 62 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ 63 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 64 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 65 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 66 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 67 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 68 69 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 70 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ 71 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ 72 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ 73 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ 74 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ 75 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ 76 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ 77 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ 78 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 79 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ 80 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ 81 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ 82 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ 83 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ 84 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ 85 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 86 87 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ 88 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 89 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 90 #define SPINOR_OP_READ_1_4_4_DTR 0xed 91 92 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 93 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 94 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 95 96 /* Used for SST flashes only. */ 97 #define SPINOR_OP_BP 0x02 /* Byte program */ 98 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 99 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 100 101 /* Used for S3AN flashes only */ 102 #define SPINOR_OP_XSE 0x50 /* Sector erase */ 103 #define SPINOR_OP_XPP 0x82 /* Page program */ 104 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ 105 106 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 107 #define XSR_RDY BIT(7) /* Ready */ 108 109 110 /* Used for Macronix and Winbond flashes. */ 111 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 112 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 113 114 /* Used for Spansion flashes only. */ 115 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 116 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 117 118 /* Used for Micron flashes only. */ 119 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 120 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 121 122 /* Status Register bits. */ 123 #define SR_WIP BIT(0) /* Write in progress */ 124 #define SR_WEL BIT(1) /* Write enable latch */ 125 /* meaning of other SR_* bits may differ between vendors */ 126 #define SR_BP0 BIT(2) /* Block protect 0 */ 127 #define SR_BP1 BIT(3) /* Block protect 1 */ 128 #define SR_BP2 BIT(4) /* Block protect 2 */ 129 #define SR_TB BIT(5) /* Top/Bottom protect */ 130 #define SR_SRWD BIT(7) /* SR write protect */ 131 /* Spansion/Cypress specific status bits */ 132 #define SR_E_ERR BIT(5) 133 #define SR_P_ERR BIT(6) 134 135 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 136 137 /* Enhanced Volatile Configuration Register bits */ 138 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 139 140 /* Flag Status Register bits */ 141 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 142 #define FSR_E_ERR BIT(5) /* Erase operation status */ 143 #define FSR_P_ERR BIT(4) /* Program operation status */ 144 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 145 146 /* Configuration Register bits. */ 147 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 148 149 /* Status Register 2 bits. */ 150 #define SR2_QUAD_EN_BIT7 BIT(7) 151 152 /* Supported SPI protocols */ 153 #define SNOR_PROTO_INST_MASK GENMASK(23, 16) 154 #define SNOR_PROTO_INST_SHIFT 16 155 #define SNOR_PROTO_INST(_nbits) \ 156 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ 157 SNOR_PROTO_INST_MASK) 158 159 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 160 #define SNOR_PROTO_ADDR_SHIFT 8 161 #define SNOR_PROTO_ADDR(_nbits) \ 162 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ 163 SNOR_PROTO_ADDR_MASK) 164 165 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 166 #define SNOR_PROTO_DATA_SHIFT 0 167 #define SNOR_PROTO_DATA(_nbits) \ 168 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ 169 SNOR_PROTO_DATA_MASK) 170 171 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ 172 173 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ 174 (SNOR_PROTO_INST(_inst_nbits) | \ 175 SNOR_PROTO_ADDR(_addr_nbits) | \ 176 SNOR_PROTO_DATA(_data_nbits)) 177 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ 178 (SNOR_PROTO_IS_DTR | \ 179 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) 180 181 enum spi_nor_protocol { 182 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), 183 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), 184 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), 185 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), 186 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), 187 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), 188 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), 189 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), 190 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), 191 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), 192 193 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), 194 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), 195 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), 196 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), 197 }; 198 199 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) 200 { 201 return !!(proto & SNOR_PROTO_IS_DTR); 202 } 203 204 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) 205 { 206 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> 207 SNOR_PROTO_INST_SHIFT; 208 } 209 210 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) 211 { 212 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> 213 SNOR_PROTO_ADDR_SHIFT; 214 } 215 216 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) 217 { 218 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> 219 SNOR_PROTO_DATA_SHIFT; 220 } 221 222 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) 223 { 224 return spi_nor_get_protocol_data_nbits(proto); 225 } 226 227 #define SPI_NOR_MAX_CMD_SIZE 8 228 enum spi_nor_ops { 229 SPI_NOR_OPS_READ = 0, 230 SPI_NOR_OPS_WRITE, 231 SPI_NOR_OPS_ERASE, 232 SPI_NOR_OPS_LOCK, 233 SPI_NOR_OPS_UNLOCK, 234 }; 235 236 enum spi_nor_option_flags { 237 SNOR_F_USE_FSR = BIT(0), 238 SNOR_F_HAS_SR_TB = BIT(1), 239 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 240 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), 241 SNOR_F_READY_XSR_RDY = BIT(4), 242 SNOR_F_USE_CLSR = BIT(5), 243 SNOR_F_BROKEN_RESET = BIT(6), 244 SNOR_F_4B_OPCODES = BIT(7), 245 SNOR_F_HAS_4BAIT = BIT(8), 246 }; 247 248 /** 249 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type 250 * @size: the size of the sector/block erased by the erase type. 251 * JEDEC JESD216B imposes erase sizes to be a power of 2. 252 * @size_shift: @size is a power of 2, the shift is stored in 253 * @size_shift. 254 * @size_mask: the size mask based on @size_shift. 255 * @opcode: the SPI command op code to erase the sector/block. 256 * @idx: Erase Type index as sorted in the Basic Flash Parameter 257 * Table. It will be used to synchronize the supported 258 * Erase Types with the ones identified in the SFDP 259 * optional tables. 260 */ 261 struct spi_nor_erase_type { 262 u32 size; 263 u32 size_shift; 264 u32 size_mask; 265 u8 opcode; 266 u8 idx; 267 }; 268 269 /** 270 * struct spi_nor_erase_command - Used for non-uniform erases 271 * The structure is used to describe a list of erase commands to be executed 272 * once we validate that the erase can be performed. The elements in the list 273 * are run-length encoded. 274 * @list: for inclusion into the list of erase commands. 275 * @count: how many times the same erase command should be 276 * consecutively used. 277 * @size: the size of the sector/block erased by the command. 278 * @opcode: the SPI command op code to erase the sector/block. 279 */ 280 struct spi_nor_erase_command { 281 struct list_head list; 282 u32 count; 283 u32 size; 284 u8 opcode; 285 }; 286 287 /** 288 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region 289 * @offset: the offset in the data array of erase region start. 290 * LSB bits are used as a bitmask encoding flags to 291 * determine if this region is overlaid, if this region is 292 * the last in the SPI NOR flash memory and to indicate 293 * all the supported erase commands inside this region. 294 * The erase types are sorted in ascending order with the 295 * smallest Erase Type size being at BIT(0). 296 * @size: the size of the region in bytes. 297 */ 298 struct spi_nor_erase_region { 299 u64 offset; 300 u64 size; 301 }; 302 303 #define SNOR_ERASE_TYPE_MAX 4 304 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) 305 306 #define SNOR_LAST_REGION BIT(4) 307 #define SNOR_OVERLAID_REGION BIT(5) 308 309 #define SNOR_ERASE_FLAGS_MAX 6 310 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) 311 312 /** 313 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map 314 * @regions: array of erase regions. The regions are consecutive in 315 * address space. Walking through the regions is done 316 * incrementally. 317 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform 318 * sector size (legacy implementation). 319 * @erase_type: an array of erase types shared by all the regions. 320 * The erase types are sorted in ascending order, with the 321 * smallest Erase Type size being the first member in the 322 * erase_type array. 323 * @uniform_erase_type: bitmask encoding erase types that can erase the 324 * entire memory. This member is completed at init by 325 * uniform and non-uniform SPI NOR flash memories if they 326 * support at least one erase type that can erase the 327 * entire memory. 328 */ 329 struct spi_nor_erase_map { 330 struct spi_nor_erase_region *regions; 331 struct spi_nor_erase_region uniform_region; 332 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; 333 u8 uniform_erase_type; 334 }; 335 336 /** 337 * struct flash_info - Forward declaration of a structure used internally by 338 * spi_nor_scan() 339 */ 340 struct flash_info; 341 342 /** 343 * struct spi_nor - Structure for defining a the SPI NOR layer 344 * @mtd: point to a mtd_info structure 345 * @lock: the lock for the read/write/erase/lock/unlock operations 346 * @dev: point to a spi device, or a spi nor controller device. 347 * @info: spi-nor part JDEC MFR id and other info 348 * @page_size: the page size of the SPI NOR 349 * @addr_width: number of address bytes 350 * @erase_opcode: the opcode for erasing a sector 351 * @read_opcode: the read opcode 352 * @read_dummy: the dummy needed by the read operation 353 * @program_opcode: the program opcode 354 * @sst_write_second: used by the SST write operation 355 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 356 * @read_proto: the SPI protocol for read operations 357 * @write_proto: the SPI protocol for write operations 358 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations 359 * @cmd_buf: used by the write_reg 360 * @erase_map: the erase map of the SPI NOR 361 * @prepare: [OPTIONAL] do some preparations for the 362 * read/write/erase/lock/unlock operations 363 * @unprepare: [OPTIONAL] do some post work after the 364 * read/write/erase/lock/unlock operations 365 * @read_reg: [DRIVER-SPECIFIC] read out the register 366 * @write_reg: [DRIVER-SPECIFIC] write data to the register 367 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 368 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 369 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 370 * at the offset @offs; if not provided by the driver, 371 * spi-nor will send the erase opcode via write_reg() 372 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 373 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 374 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 375 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode 376 * completely locked 377 * @priv: the private data 378 */ 379 struct spi_nor { 380 struct mtd_info mtd; 381 struct mutex lock; 382 struct device *dev; 383 const struct flash_info *info; 384 u32 page_size; 385 u8 addr_width; 386 u8 erase_opcode; 387 u8 read_opcode; 388 u8 read_dummy; 389 u8 program_opcode; 390 enum spi_nor_protocol read_proto; 391 enum spi_nor_protocol write_proto; 392 enum spi_nor_protocol reg_proto; 393 bool sst_write_second; 394 u32 flags; 395 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 396 struct spi_nor_erase_map erase_map; 397 398 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 399 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 400 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 401 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 402 403 ssize_t (*read)(struct spi_nor *nor, loff_t from, 404 size_t len, u_char *read_buf); 405 ssize_t (*write)(struct spi_nor *nor, loff_t to, 406 size_t len, const u_char *write_buf); 407 int (*erase)(struct spi_nor *nor, loff_t offs); 408 409 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 410 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 411 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 412 int (*quad_enable)(struct spi_nor *nor); 413 414 void *priv; 415 }; 416 417 static u64 __maybe_unused 418 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 419 { 420 return region->offset & SNOR_LAST_REGION; 421 } 422 423 static u64 __maybe_unused 424 spi_nor_region_end(const struct spi_nor_erase_region *region) 425 { 426 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 427 } 428 429 static void __maybe_unused 430 spi_nor_region_mark_end(struct spi_nor_erase_region *region) 431 { 432 region->offset |= SNOR_LAST_REGION; 433 } 434 435 static void __maybe_unused 436 spi_nor_region_mark_overlay(struct spi_nor_erase_region *region) 437 { 438 region->offset |= SNOR_OVERLAID_REGION; 439 } 440 441 static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor) 442 { 443 return !!nor->erase_map.uniform_erase_type; 444 } 445 446 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 447 struct device_node *np) 448 { 449 mtd_set_of_node(&nor->mtd, np); 450 } 451 452 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) 453 { 454 return mtd_get_of_node(&nor->mtd); 455 } 456 457 /** 458 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies 459 * supported by the SPI controller (bus master). 460 * @mask: the bitmask listing all the supported hw capabilies 461 */ 462 struct spi_nor_hwcaps { 463 u32 mask; 464 }; 465 466 /* 467 *(Fast) Read capabilities. 468 * MUST be ordered by priority: the higher bit position, the higher priority. 469 * As a matter of performances, it is relevant to use Octal SPI protocols first, 470 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly 471 * (Slow) Read. 472 */ 473 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) 474 #define SNOR_HWCAPS_READ BIT(0) 475 #define SNOR_HWCAPS_READ_FAST BIT(1) 476 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) 477 478 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) 479 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) 480 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) 481 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) 482 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) 483 484 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) 485 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) 486 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) 487 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) 488 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) 489 490 #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11) 491 #define SNOR_HWCAPS_READ_1_1_8 BIT(11) 492 #define SNOR_HWCAPS_READ_1_8_8 BIT(12) 493 #define SNOR_HWCAPS_READ_8_8_8 BIT(13) 494 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) 495 496 /* 497 * Page Program capabilities. 498 * MUST be ordered by priority: the higher bit position, the higher priority. 499 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the 500 * legacy SPI 1-1-1 protocol. 501 * Note that Dual Page Programs are not supported because there is no existing 502 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory 503 * implements such commands. 504 */ 505 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) 506 #define SNOR_HWCAPS_PP BIT(16) 507 508 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) 509 #define SNOR_HWCAPS_PP_1_1_4 BIT(17) 510 #define SNOR_HWCAPS_PP_1_4_4 BIT(18) 511 #define SNOR_HWCAPS_PP_4_4_4 BIT(19) 512 513 #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20) 514 #define SNOR_HWCAPS_PP_1_1_8 BIT(20) 515 #define SNOR_HWCAPS_PP_1_8_8 BIT(21) 516 #define SNOR_HWCAPS_PP_8_8_8 BIT(22) 517 518 /** 519 * spi_nor_scan() - scan the SPI NOR 520 * @nor: the spi_nor structure 521 * @name: the chip type name 522 * @hwcaps: the hardware capabilities supported by the controller driver 523 * 524 * The drivers can use this fuction to scan the SPI NOR. 525 * In the scanning, it will try to get all the necessary information to 526 * fill the mtd_info{} and the spi_nor{}. 527 * 528 * The chip type name can be provided through the @name parameter. 529 * 530 * Return: 0 for success, others for failure. 531 */ 532 int spi_nor_scan(struct spi_nor *nor, const char *name, 533 const struct spi_nor_hwcaps *hwcaps); 534 535 /** 536 * spi_nor_restore_addr_mode() - restore the status of SPI NOR 537 * @nor: the spi_nor structure 538 */ 539 void spi_nor_restore(struct spi_nor *nor); 540 541 #endif 542