1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __LINUX_MTD_SPI_NOR_H 11 #define __LINUX_MTD_SPI_NOR_H 12 13 #include <linux/bitops.h> 14 #include <linux/mtd/cfi.h> 15 #include <linux/mtd/mtd.h> 16 17 /* 18 * Manufacturer IDs 19 * 20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 21 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 22 */ 23 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 24 #define SNOR_MFR_GIGADEVICE 0xc8 25 #define SNOR_MFR_INTEL CFI_MFR_INTEL 26 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ 27 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 28 #define SNOR_MFR_SPANSION CFI_MFR_AMD 29 #define SNOR_MFR_SST CFI_MFR_SST 30 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 31 32 /* 33 * Note on opcode nomenclature: some opcodes have a format like 34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 35 * of I/O lines used for the opcode, address, and data (respectively). The 36 * FUNCTION has an optional suffix of '4', to represent an opcode which 37 * requires a 4-byte (32-bit) address. 38 */ 39 40 /* Flash opcodes. */ 41 #define SPINOR_OP_WREN 0x06 /* Write enable */ 42 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 43 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 44 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ 45 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ 46 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 47 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ 49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ 50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ 51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ 52 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 53 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ 54 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ 55 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 56 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 57 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 58 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 59 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 60 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 61 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ 62 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 63 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 64 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 65 66 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 67 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ 68 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ 69 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ 70 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ 71 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ 72 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ 73 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 74 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ 75 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ 76 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ 77 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ 78 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 79 80 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ 81 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 82 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 83 #define SPINOR_OP_READ_1_4_4_DTR 0xed 84 85 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 86 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 87 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 88 89 /* Used for SST flashes only. */ 90 #define SPINOR_OP_BP 0x02 /* Byte program */ 91 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 92 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 93 94 /* Used for S3AN flashes only */ 95 #define SPINOR_OP_XSE 0x50 /* Sector erase */ 96 #define SPINOR_OP_XPP 0x82 /* Page program */ 97 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ 98 99 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 100 #define XSR_RDY BIT(7) /* Ready */ 101 102 103 /* Used for Macronix and Winbond flashes. */ 104 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 105 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 106 107 /* Used for Spansion flashes only. */ 108 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 109 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 110 111 /* Used for Micron flashes only. */ 112 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 113 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 114 115 /* Status Register bits. */ 116 #define SR_WIP BIT(0) /* Write in progress */ 117 #define SR_WEL BIT(1) /* Write enable latch */ 118 /* meaning of other SR_* bits may differ between vendors */ 119 #define SR_BP0 BIT(2) /* Block protect 0 */ 120 #define SR_BP1 BIT(3) /* Block protect 1 */ 121 #define SR_BP2 BIT(4) /* Block protect 2 */ 122 #define SR_TB BIT(5) /* Top/Bottom protect */ 123 #define SR_SRWD BIT(7) /* SR write protect */ 124 /* Spansion/Cypress specific status bits */ 125 #define SR_E_ERR BIT(5) 126 #define SR_P_ERR BIT(6) 127 128 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 129 130 /* Enhanced Volatile Configuration Register bits */ 131 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 132 133 /* Flag Status Register bits */ 134 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 135 #define FSR_E_ERR BIT(5) /* Erase operation status */ 136 #define FSR_P_ERR BIT(4) /* Program operation status */ 137 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 138 139 /* Configuration Register bits. */ 140 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 141 142 /* Status Register 2 bits. */ 143 #define SR2_QUAD_EN_BIT7 BIT(7) 144 145 /* Supported SPI protocols */ 146 #define SNOR_PROTO_INST_MASK GENMASK(23, 16) 147 #define SNOR_PROTO_INST_SHIFT 16 148 #define SNOR_PROTO_INST(_nbits) \ 149 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ 150 SNOR_PROTO_INST_MASK) 151 152 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 153 #define SNOR_PROTO_ADDR_SHIFT 8 154 #define SNOR_PROTO_ADDR(_nbits) \ 155 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ 156 SNOR_PROTO_ADDR_MASK) 157 158 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 159 #define SNOR_PROTO_DATA_SHIFT 0 160 #define SNOR_PROTO_DATA(_nbits) \ 161 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ 162 SNOR_PROTO_DATA_MASK) 163 164 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ 165 166 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ 167 (SNOR_PROTO_INST(_inst_nbits) | \ 168 SNOR_PROTO_ADDR(_addr_nbits) | \ 169 SNOR_PROTO_DATA(_data_nbits)) 170 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ 171 (SNOR_PROTO_IS_DTR | \ 172 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) 173 174 enum spi_nor_protocol { 175 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), 176 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), 177 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), 178 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), 179 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), 180 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), 181 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), 182 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), 183 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), 184 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), 185 186 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), 187 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), 188 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), 189 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), 190 }; 191 192 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) 193 { 194 return !!(proto & SNOR_PROTO_IS_DTR); 195 } 196 197 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) 198 { 199 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> 200 SNOR_PROTO_INST_SHIFT; 201 } 202 203 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) 204 { 205 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> 206 SNOR_PROTO_ADDR_SHIFT; 207 } 208 209 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) 210 { 211 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> 212 SNOR_PROTO_DATA_SHIFT; 213 } 214 215 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) 216 { 217 return spi_nor_get_protocol_data_nbits(proto); 218 } 219 220 #define SPI_NOR_MAX_CMD_SIZE 8 221 enum spi_nor_ops { 222 SPI_NOR_OPS_READ = 0, 223 SPI_NOR_OPS_WRITE, 224 SPI_NOR_OPS_ERASE, 225 SPI_NOR_OPS_LOCK, 226 SPI_NOR_OPS_UNLOCK, 227 }; 228 229 enum spi_nor_option_flags { 230 SNOR_F_USE_FSR = BIT(0), 231 SNOR_F_HAS_SR_TB = BIT(1), 232 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 233 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), 234 SNOR_F_READY_XSR_RDY = BIT(4), 235 SNOR_F_USE_CLSR = BIT(5), 236 }; 237 238 /** 239 * struct flash_info - Forward declaration of a structure used internally by 240 * spi_nor_scan() 241 */ 242 struct flash_info; 243 244 /** 245 * struct spi_nor - Structure for defining a the SPI NOR layer 246 * @mtd: point to a mtd_info structure 247 * @lock: the lock for the read/write/erase/lock/unlock operations 248 * @dev: point to a spi device, or a spi nor controller device. 249 * @info: spi-nor part JDEC MFR id and other info 250 * @page_size: the page size of the SPI NOR 251 * @addr_width: number of address bytes 252 * @erase_opcode: the opcode for erasing a sector 253 * @read_opcode: the read opcode 254 * @read_dummy: the dummy needed by the read operation 255 * @program_opcode: the program opcode 256 * @sst_write_second: used by the SST write operation 257 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 258 * @read_proto: the SPI protocol for read operations 259 * @write_proto: the SPI protocol for write operations 260 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations 261 * @cmd_buf: used by the write_reg 262 * @prepare: [OPTIONAL] do some preparations for the 263 * read/write/erase/lock/unlock operations 264 * @unprepare: [OPTIONAL] do some post work after the 265 * read/write/erase/lock/unlock operations 266 * @read_reg: [DRIVER-SPECIFIC] read out the register 267 * @write_reg: [DRIVER-SPECIFIC] write data to the register 268 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 269 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 270 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 271 * at the offset @offs; if not provided by the driver, 272 * spi-nor will send the erase opcode via write_reg() 273 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 274 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 275 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 276 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode 277 * completely locked 278 * @priv: the private data 279 */ 280 struct spi_nor { 281 struct mtd_info mtd; 282 struct mutex lock; 283 struct device *dev; 284 const struct flash_info *info; 285 u32 page_size; 286 u8 addr_width; 287 u8 erase_opcode; 288 u8 read_opcode; 289 u8 read_dummy; 290 u8 program_opcode; 291 enum spi_nor_protocol read_proto; 292 enum spi_nor_protocol write_proto; 293 enum spi_nor_protocol reg_proto; 294 bool sst_write_second; 295 u32 flags; 296 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 297 298 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 299 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 300 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 301 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 302 303 ssize_t (*read)(struct spi_nor *nor, loff_t from, 304 size_t len, u_char *read_buf); 305 ssize_t (*write)(struct spi_nor *nor, loff_t to, 306 size_t len, const u_char *write_buf); 307 int (*erase)(struct spi_nor *nor, loff_t offs); 308 309 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 310 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 311 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 312 int (*quad_enable)(struct spi_nor *nor); 313 314 void *priv; 315 }; 316 317 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 318 struct device_node *np) 319 { 320 mtd_set_of_node(&nor->mtd, np); 321 } 322 323 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) 324 { 325 return mtd_get_of_node(&nor->mtd); 326 } 327 328 /** 329 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies 330 * supported by the SPI controller (bus master). 331 * @mask: the bitmask listing all the supported hw capabilies 332 */ 333 struct spi_nor_hwcaps { 334 u32 mask; 335 }; 336 337 /* 338 *(Fast) Read capabilities. 339 * MUST be ordered by priority: the higher bit position, the higher priority. 340 * As a matter of performances, it is relevant to use Octo SPI protocols first, 341 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly 342 * (Slow) Read. 343 */ 344 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) 345 #define SNOR_HWCAPS_READ BIT(0) 346 #define SNOR_HWCAPS_READ_FAST BIT(1) 347 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) 348 349 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) 350 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) 351 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) 352 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) 353 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) 354 355 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) 356 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) 357 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) 358 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) 359 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) 360 361 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) 362 #define SNOR_HWCAPS_READ_1_1_8 BIT(11) 363 #define SNOR_HWCAPS_READ_1_8_8 BIT(12) 364 #define SNOR_HWCAPS_READ_8_8_8 BIT(13) 365 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) 366 367 /* 368 * Page Program capabilities. 369 * MUST be ordered by priority: the higher bit position, the higher priority. 370 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the 371 * legacy SPI 1-1-1 protocol. 372 * Note that Dual Page Programs are not supported because there is no existing 373 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory 374 * implements such commands. 375 */ 376 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) 377 #define SNOR_HWCAPS_PP BIT(16) 378 379 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) 380 #define SNOR_HWCAPS_PP_1_1_4 BIT(17) 381 #define SNOR_HWCAPS_PP_1_4_4 BIT(18) 382 #define SNOR_HWCAPS_PP_4_4_4 BIT(19) 383 384 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) 385 #define SNOR_HWCAPS_PP_1_1_8 BIT(20) 386 #define SNOR_HWCAPS_PP_1_8_8 BIT(21) 387 #define SNOR_HWCAPS_PP_8_8_8 BIT(22) 388 389 /** 390 * spi_nor_scan() - scan the SPI NOR 391 * @nor: the spi_nor structure 392 * @name: the chip type name 393 * @hwcaps: the hardware capabilities supported by the controller driver 394 * 395 * The drivers can use this fuction to scan the SPI NOR. 396 * In the scanning, it will try to get all the necessary information to 397 * fill the mtd_info{} and the spi_nor{}. 398 * 399 * The chip type name can be provided through the @name parameter. 400 * 401 * Return: 0 for success, others for failure. 402 */ 403 int spi_nor_scan(struct spi_nor *nor, const char *name, 404 const struct spi_nor_hwcaps *hwcaps); 405 406 /** 407 * spi_nor_restore_addr_mode() - restore the status of SPI NOR 408 * @nor: the spi_nor structure 409 */ 410 void spi_nor_restore(struct spi_nor *nor); 411 412 #endif 413