1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __LINUX_MTD_SPI_NOR_H 11 #define __LINUX_MTD_SPI_NOR_H 12 13 #include <linux/bitops.h> 14 #include <linux/mtd/cfi.h> 15 #include <linux/mtd/mtd.h> 16 17 /* 18 * Manufacturer IDs 19 * 20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 21 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 22 */ 23 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 24 #define SNOR_MFR_GIGADEVICE 0xc8 25 #define SNOR_MFR_INTEL CFI_MFR_INTEL 26 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ 27 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 28 #define SNOR_MFR_SPANSION CFI_MFR_AMD 29 #define SNOR_MFR_SST CFI_MFR_SST 30 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 31 32 /* 33 * Note on opcode nomenclature: some opcodes have a format like 34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 35 * of I/O lines used for the opcode, address, and data (respectively). The 36 * FUNCTION has an optional suffix of '4', to represent an opcode which 37 * requires a 4-byte (32-bit) address. 38 */ 39 40 /* Flash opcodes. */ 41 #define SPINOR_OP_WREN 0x06 /* Write enable */ 42 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 43 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 44 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 45 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 46 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ 47 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ 48 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 49 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 50 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 51 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 52 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 53 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 54 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 55 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 56 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 57 58 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 59 #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ 60 #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ 61 #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ 62 #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ 63 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 64 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 65 66 /* Used for SST flashes only. */ 67 #define SPINOR_OP_BP 0x02 /* Byte program */ 68 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 69 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 70 71 /* Used for Macronix and Winbond flashes. */ 72 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 73 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 74 75 /* Used for Spansion flashes only. */ 76 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 77 78 /* Used for Micron flashes only. */ 79 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 80 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 81 82 /* Status Register bits. */ 83 #define SR_WIP BIT(0) /* Write in progress */ 84 #define SR_WEL BIT(1) /* Write enable latch */ 85 /* meaning of other SR_* bits may differ between vendors */ 86 #define SR_BP0 BIT(2) /* Block protect 0 */ 87 #define SR_BP1 BIT(3) /* Block protect 1 */ 88 #define SR_BP2 BIT(4) /* Block protect 2 */ 89 #define SR_TB BIT(5) /* Top/Bottom protect */ 90 #define SR_SRWD BIT(7) /* SR write protect */ 91 92 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 93 94 /* Enhanced Volatile Configuration Register bits */ 95 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 96 97 /* Flag Status Register bits */ 98 #define FSR_READY BIT(7) 99 100 /* Configuration Register bits. */ 101 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 102 103 enum read_mode { 104 SPI_NOR_NORMAL = 0, 105 SPI_NOR_FAST, 106 SPI_NOR_DUAL, 107 SPI_NOR_QUAD, 108 }; 109 110 #define SPI_NOR_MAX_CMD_SIZE 8 111 enum spi_nor_ops { 112 SPI_NOR_OPS_READ = 0, 113 SPI_NOR_OPS_WRITE, 114 SPI_NOR_OPS_ERASE, 115 SPI_NOR_OPS_LOCK, 116 SPI_NOR_OPS_UNLOCK, 117 }; 118 119 enum spi_nor_option_flags { 120 SNOR_F_USE_FSR = BIT(0), 121 SNOR_F_HAS_SR_TB = BIT(1), 122 }; 123 124 /** 125 * struct spi_nor - Structure for defining a the SPI NOR layer 126 * @mtd: point to a mtd_info structure 127 * @lock: the lock for the read/write/erase/lock/unlock operations 128 * @dev: point to a spi device, or a spi nor controller device. 129 * @page_size: the page size of the SPI NOR 130 * @addr_width: number of address bytes 131 * @erase_opcode: the opcode for erasing a sector 132 * @read_opcode: the read opcode 133 * @read_dummy: the dummy needed by the read operation 134 * @program_opcode: the program opcode 135 * @flash_read: the mode of the read 136 * @sst_write_second: used by the SST write operation 137 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 138 * @cmd_buf: used by the write_reg 139 * @prepare: [OPTIONAL] do some preparations for the 140 * read/write/erase/lock/unlock operations 141 * @unprepare: [OPTIONAL] do some post work after the 142 * read/write/erase/lock/unlock operations 143 * @read_reg: [DRIVER-SPECIFIC] read out the register 144 * @write_reg: [DRIVER-SPECIFIC] write data to the register 145 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 146 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 147 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 148 * at the offset @offs; if not provided by the driver, 149 * spi-nor will send the erase opcode via write_reg() 150 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 151 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 152 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 153 * completely locked 154 * @priv: the private data 155 */ 156 struct spi_nor { 157 struct mtd_info mtd; 158 struct mutex lock; 159 struct device *dev; 160 u32 page_size; 161 u8 addr_width; 162 u8 erase_opcode; 163 u8 read_opcode; 164 u8 read_dummy; 165 u8 program_opcode; 166 enum read_mode flash_read; 167 bool sst_write_second; 168 u32 flags; 169 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 170 171 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 172 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 173 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 174 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 175 176 ssize_t (*read)(struct spi_nor *nor, loff_t from, 177 size_t len, u_char *read_buf); 178 ssize_t (*write)(struct spi_nor *nor, loff_t to, 179 size_t len, const u_char *write_buf); 180 int (*erase)(struct spi_nor *nor, loff_t offs); 181 182 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 183 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 184 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 185 186 void *priv; 187 }; 188 189 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 190 struct device_node *np) 191 { 192 mtd_set_of_node(&nor->mtd, np); 193 } 194 195 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) 196 { 197 return mtd_get_of_node(&nor->mtd); 198 } 199 200 /** 201 * spi_nor_scan() - scan the SPI NOR 202 * @nor: the spi_nor structure 203 * @name: the chip type name 204 * @mode: the read mode supported by the driver 205 * 206 * The drivers can use this fuction to scan the SPI NOR. 207 * In the scanning, it will try to get all the necessary information to 208 * fill the mtd_info{} and the spi_nor{}. 209 * 210 * The chip type name can be provided through the @name parameter. 211 * 212 * Return: 0 for success, others for failure. 213 */ 214 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode); 215 216 #endif 217