1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/flashchip.h> 21 #include <linux/mtd/bbm.h> 22 #include <linux/mtd/jedec.h> 23 #include <linux/mtd/onfi.h> 24 #include <linux/mutex.h> 25 #include <linux/of.h> 26 #include <linux/types.h> 27 28 struct nand_chip; 29 30 /* The maximum number of NAND chips in an array */ 31 #define NAND_MAX_CHIPS 8 32 33 /* 34 * Constants for hardware specific CLE/ALE/NCE function 35 * 36 * These are bits which can be or'ed to set/clear multiple 37 * bits in one go. 38 */ 39 /* Select the chip by setting nCE to low */ 40 #define NAND_NCE 0x01 41 /* Select the command latch by setting CLE to high */ 42 #define NAND_CLE 0x02 43 /* Select the address latch by setting ALE to high */ 44 #define NAND_ALE 0x04 45 46 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 47 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 48 #define NAND_CTRL_CHANGE 0x80 49 50 /* 51 * Standard NAND flash commands 52 */ 53 #define NAND_CMD_READ0 0 54 #define NAND_CMD_READ1 1 55 #define NAND_CMD_RNDOUT 5 56 #define NAND_CMD_PAGEPROG 0x10 57 #define NAND_CMD_READOOB 0x50 58 #define NAND_CMD_ERASE1 0x60 59 #define NAND_CMD_STATUS 0x70 60 #define NAND_CMD_SEQIN 0x80 61 #define NAND_CMD_RNDIN 0x85 62 #define NAND_CMD_READID 0x90 63 #define NAND_CMD_ERASE2 0xd0 64 #define NAND_CMD_PARAM 0xec 65 #define NAND_CMD_GET_FEATURES 0xee 66 #define NAND_CMD_SET_FEATURES 0xef 67 #define NAND_CMD_RESET 0xff 68 69 /* Extended commands for large page devices */ 70 #define NAND_CMD_READSTART 0x30 71 #define NAND_CMD_RNDOUTSTART 0xE0 72 #define NAND_CMD_CACHEDPROG 0x15 73 74 #define NAND_CMD_NONE -1 75 76 /* Status bits */ 77 #define NAND_STATUS_FAIL 0x01 78 #define NAND_STATUS_FAIL_N1 0x02 79 #define NAND_STATUS_TRUE_READY 0x20 80 #define NAND_STATUS_READY 0x40 81 #define NAND_STATUS_WP 0x80 82 83 #define NAND_DATA_IFACE_CHECK_ONLY -1 84 85 /* 86 * Constants for ECC_MODES 87 */ 88 typedef enum { 89 NAND_ECC_NONE, 90 NAND_ECC_SOFT, 91 NAND_ECC_HW, 92 NAND_ECC_HW_SYNDROME, 93 NAND_ECC_HW_OOB_FIRST, 94 NAND_ECC_ON_DIE, 95 } nand_ecc_modes_t; 96 97 enum nand_ecc_algo { 98 NAND_ECC_UNKNOWN, 99 NAND_ECC_HAMMING, 100 NAND_ECC_BCH, 101 NAND_ECC_RS, 102 }; 103 104 /* 105 * Constants for Hardware ECC 106 */ 107 /* Reset Hardware ECC for read */ 108 #define NAND_ECC_READ 0 109 /* Reset Hardware ECC for write */ 110 #define NAND_ECC_WRITE 1 111 /* Enable Hardware ECC before syndrome is read back from flash */ 112 #define NAND_ECC_READSYN 2 113 114 /* 115 * Enable generic NAND 'page erased' check. This check is only done when 116 * ecc.correct() returns -EBADMSG. 117 * Set this flag if your implementation does not fix bitflips in erased 118 * pages and you want to rely on the default implementation. 119 */ 120 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 121 #define NAND_ECC_MAXIMIZE BIT(1) 122 123 /* 124 * When using software implementation of Hamming, we can specify which byte 125 * ordering should be used. 126 */ 127 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 128 129 /* 130 * Option constants for bizarre disfunctionality and real 131 * features. 132 */ 133 /* Buswidth is 16 bit */ 134 #define NAND_BUSWIDTH_16 0x00000002 135 /* Chip has cache program function */ 136 #define NAND_CACHEPRG 0x00000008 137 /* 138 * Chip requires ready check on read (for auto-incremented sequential read). 139 * True only for small page devices; large page devices do not support 140 * autoincrement. 141 */ 142 #define NAND_NEED_READRDY 0x00000100 143 144 /* Chip does not allow subpage writes */ 145 #define NAND_NO_SUBPAGE_WRITE 0x00000200 146 147 /* Device is one of 'new' xD cards that expose fake nand command set */ 148 #define NAND_BROKEN_XD 0x00000400 149 150 /* Device behaves just like nand, but is readonly */ 151 #define NAND_ROM 0x00000800 152 153 /* Device supports subpage reads */ 154 #define NAND_SUBPAGE_READ 0x00001000 155 156 /* 157 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 158 * patterns. 159 */ 160 #define NAND_NEED_SCRAMBLING 0x00002000 161 162 /* Device needs 3rd row address cycle */ 163 #define NAND_ROW_ADDR_3 0x00004000 164 165 /* Options valid for Samsung large page devices */ 166 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 167 168 /* Macros to identify the above */ 169 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 170 171 /* Non chip related options */ 172 /* This option skips the bbt scan during initialization. */ 173 #define NAND_SKIP_BBTSCAN 0x00010000 174 /* Chip may not exist, so silence any errors in scan */ 175 #define NAND_SCAN_SILENT_NODEV 0x00040000 176 /* 177 * Autodetect nand buswidth with readid/onfi. 178 * This suppose the driver will configure the hardware in 8 bits mode 179 * when calling nand_scan_ident, and update its configuration 180 * before calling nand_scan_tail. 181 */ 182 #define NAND_BUSWIDTH_AUTO 0x00080000 183 /* 184 * This option could be defined by controller drivers to protect against 185 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 186 */ 187 #define NAND_USE_BOUNCE_BUFFER 0x00100000 188 189 /* 190 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 191 * on the default ->cmdfunc() implementation, you may want to let the core 192 * handle the tCCS delay which is required when a column change (RNDIN or 193 * RNDOUT) is requested. 194 * If your controller already takes care of this delay, you don't need to set 195 * this flag. 196 */ 197 #define NAND_WAIT_TCCS 0x00200000 198 199 /* 200 * Whether the NAND chip is a boot medium. Drivers might use this information 201 * to select ECC algorithms supported by the boot ROM or similar restrictions. 202 */ 203 #define NAND_IS_BOOT_MEDIUM 0x00400000 204 205 /* 206 * Do not try to tweak the timings at runtime. This is needed when the 207 * controller initializes the timings on itself or when it relies on 208 * configuration done by the bootloader. 209 */ 210 #define NAND_KEEP_TIMINGS 0x00800000 211 212 /* Cell info constants */ 213 #define NAND_CI_CHIPNR_MSK 0x03 214 #define NAND_CI_CELLTYPE_MSK 0x0C 215 #define NAND_CI_CELLTYPE_SHIFT 2 216 217 /** 218 * struct nand_parameters - NAND generic parameters from the parameter page 219 * @model: Model name 220 * @supports_set_get_features: The NAND chip supports setting/getting features 221 * @set_feature_list: Bitmap of features that can be set 222 * @get_feature_list: Bitmap of features that can be get 223 * @onfi: ONFI specific parameters 224 */ 225 struct nand_parameters { 226 /* Generic parameters */ 227 const char *model; 228 bool supports_set_get_features; 229 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 230 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 231 232 /* ONFI parameters */ 233 struct onfi_params *onfi; 234 }; 235 236 /* The maximum expected count of bytes in the NAND ID sequence */ 237 #define NAND_MAX_ID_LEN 8 238 239 /** 240 * struct nand_id - NAND id structure 241 * @data: buffer containing the id bytes. 242 * @len: ID length. 243 */ 244 struct nand_id { 245 u8 data[NAND_MAX_ID_LEN]; 246 int len; 247 }; 248 249 /** 250 * struct nand_ecc_step_info - ECC step information of ECC engine 251 * @stepsize: data bytes per ECC step 252 * @strengths: array of supported strengths 253 * @nstrengths: number of supported strengths 254 */ 255 struct nand_ecc_step_info { 256 int stepsize; 257 const int *strengths; 258 int nstrengths; 259 }; 260 261 /** 262 * struct nand_ecc_caps - capability of ECC engine 263 * @stepinfos: array of ECC step information 264 * @nstepinfos: number of ECC step information 265 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 266 */ 267 struct nand_ecc_caps { 268 const struct nand_ecc_step_info *stepinfos; 269 int nstepinfos; 270 int (*calc_ecc_bytes)(int step_size, int strength); 271 }; 272 273 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 274 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 275 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 276 static const struct nand_ecc_step_info __name##_stepinfo = { \ 277 .stepsize = __step, \ 278 .strengths = __name##_strengths, \ 279 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 280 }; \ 281 static const struct nand_ecc_caps __name = { \ 282 .stepinfos = &__name##_stepinfo, \ 283 .nstepinfos = 1, \ 284 .calc_ecc_bytes = __calc, \ 285 } 286 287 /** 288 * struct nand_ecc_ctrl - Control structure for ECC 289 * @mode: ECC mode 290 * @algo: ECC algorithm 291 * @steps: number of ECC steps per page 292 * @size: data bytes per ECC step 293 * @bytes: ECC bytes per step 294 * @strength: max number of correctible bits per ECC step 295 * @total: total number of ECC bytes per page 296 * @prepad: padding information for syndrome based ECC generators 297 * @postpad: padding information for syndrome based ECC generators 298 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 299 * @priv: pointer to private ECC control data 300 * @calc_buf: buffer for calculated ECC, size is oobsize. 301 * @code_buf: buffer for ECC read from flash, size is oobsize. 302 * @hwctl: function to control hardware ECC generator. Must only 303 * be provided if an hardware ECC is available 304 * @calculate: function for ECC calculation or readback from ECC hardware 305 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 306 * Should return a positive number representing the number of 307 * corrected bitflips, -EBADMSG if the number of bitflips exceed 308 * ECC strength, or any other error code if the error is not 309 * directly related to correction. 310 * If -EBADMSG is returned the input buffers should be left 311 * untouched. 312 * @read_page_raw: function to read a raw page without ECC. This function 313 * should hide the specific layout used by the ECC 314 * controller and always return contiguous in-band and 315 * out-of-band data even if they're not stored 316 * contiguously on the NAND chip (e.g. 317 * NAND_ECC_HW_SYNDROME interleaves in-band and 318 * out-of-band data). 319 * @write_page_raw: function to write a raw page without ECC. This function 320 * should hide the specific layout used by the ECC 321 * controller and consider the passed data as contiguous 322 * in-band and out-of-band data. ECC controller is 323 * responsible for doing the appropriate transformations 324 * to adapt to its specific layout (e.g. 325 * NAND_ECC_HW_SYNDROME interleaves in-band and 326 * out-of-band data). 327 * @read_page: function to read a page according to the ECC generator 328 * requirements; returns maximum number of bitflips corrected in 329 * any single ECC step, -EIO hw error 330 * @read_subpage: function to read parts of the page covered by ECC; 331 * returns same as read_page() 332 * @write_subpage: function to write parts of the page covered by ECC. 333 * @write_page: function to write a page according to the ECC generator 334 * requirements. 335 * @write_oob_raw: function to write chip OOB data without ECC 336 * @read_oob_raw: function to read chip OOB data without ECC 337 * @read_oob: function to read chip OOB data 338 * @write_oob: function to write chip OOB data 339 */ 340 struct nand_ecc_ctrl { 341 nand_ecc_modes_t mode; 342 enum nand_ecc_algo algo; 343 int steps; 344 int size; 345 int bytes; 346 int total; 347 int strength; 348 int prepad; 349 int postpad; 350 unsigned int options; 351 void *priv; 352 u8 *calc_buf; 353 u8 *code_buf; 354 void (*hwctl)(struct nand_chip *chip, int mode); 355 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 356 uint8_t *ecc_code); 357 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 358 uint8_t *calc_ecc); 359 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 360 int oob_required, int page); 361 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 362 int oob_required, int page); 363 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 364 int oob_required, int page); 365 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 366 uint32_t len, uint8_t *buf, int page); 367 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 368 uint32_t data_len, const uint8_t *data_buf, 369 int oob_required, int page); 370 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 371 int oob_required, int page); 372 int (*write_oob_raw)(struct nand_chip *chip, int page); 373 int (*read_oob_raw)(struct nand_chip *chip, int page); 374 int (*read_oob)(struct nand_chip *chip, int page); 375 int (*write_oob)(struct nand_chip *chip, int page); 376 }; 377 378 /** 379 * struct nand_sdr_timings - SDR NAND chip timings 380 * 381 * This struct defines the timing requirements of a SDR NAND chip. 382 * These information can be found in every NAND datasheets and the timings 383 * meaning are described in the ONFI specifications: 384 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 385 * Parameters) 386 * 387 * All these timings are expressed in picoseconds. 388 * 389 * @tBERS_max: Block erase time 390 * @tCCS_min: Change column setup time 391 * @tPROG_max: Page program time 392 * @tR_max: Page read time 393 * @tALH_min: ALE hold time 394 * @tADL_min: ALE to data loading time 395 * @tALS_min: ALE setup time 396 * @tAR_min: ALE to RE# delay 397 * @tCEA_max: CE# access time 398 * @tCEH_min: CE# high hold time 399 * @tCH_min: CE# hold time 400 * @tCHZ_max: CE# high to output hi-Z 401 * @tCLH_min: CLE hold time 402 * @tCLR_min: CLE to RE# delay 403 * @tCLS_min: CLE setup time 404 * @tCOH_min: CE# high to output hold 405 * @tCS_min: CE# setup time 406 * @tDH_min: Data hold time 407 * @tDS_min: Data setup time 408 * @tFEAT_max: Busy time for Set Features and Get Features 409 * @tIR_min: Output hi-Z to RE# low 410 * @tITC_max: Interface and Timing Mode Change time 411 * @tRC_min: RE# cycle time 412 * @tREA_max: RE# access time 413 * @tREH_min: RE# high hold time 414 * @tRHOH_min: RE# high to output hold 415 * @tRHW_min: RE# high to WE# low 416 * @tRHZ_max: RE# high to output hi-Z 417 * @tRLOH_min: RE# low to output hold 418 * @tRP_min: RE# pulse width 419 * @tRR_min: Ready to RE# low (data only) 420 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 421 * rising edge of R/B#. 422 * @tWB_max: WE# high to SR[6] low 423 * @tWC_min: WE# cycle time 424 * @tWH_min: WE# high hold time 425 * @tWHR_min: WE# high to RE# low 426 * @tWP_min: WE# pulse width 427 * @tWW_min: WP# transition to WE# low 428 */ 429 struct nand_sdr_timings { 430 u64 tBERS_max; 431 u32 tCCS_min; 432 u64 tPROG_max; 433 u64 tR_max; 434 u32 tALH_min; 435 u32 tADL_min; 436 u32 tALS_min; 437 u32 tAR_min; 438 u32 tCEA_max; 439 u32 tCEH_min; 440 u32 tCH_min; 441 u32 tCHZ_max; 442 u32 tCLH_min; 443 u32 tCLR_min; 444 u32 tCLS_min; 445 u32 tCOH_min; 446 u32 tCS_min; 447 u32 tDH_min; 448 u32 tDS_min; 449 u32 tFEAT_max; 450 u32 tIR_min; 451 u32 tITC_max; 452 u32 tRC_min; 453 u32 tREA_max; 454 u32 tREH_min; 455 u32 tRHOH_min; 456 u32 tRHW_min; 457 u32 tRHZ_max; 458 u32 tRLOH_min; 459 u32 tRP_min; 460 u32 tRR_min; 461 u64 tRST_max; 462 u32 tWB_max; 463 u32 tWC_min; 464 u32 tWH_min; 465 u32 tWHR_min; 466 u32 tWP_min; 467 u32 tWW_min; 468 }; 469 470 /** 471 * enum nand_data_interface_type - NAND interface timing type 472 * @NAND_SDR_IFACE: Single Data Rate interface 473 */ 474 enum nand_data_interface_type { 475 NAND_SDR_IFACE, 476 }; 477 478 /** 479 * struct nand_data_interface - NAND interface timing 480 * @type: type of the timing 481 * @timings: The timing, type according to @type 482 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 483 */ 484 struct nand_data_interface { 485 enum nand_data_interface_type type; 486 union { 487 struct nand_sdr_timings sdr; 488 } timings; 489 }; 490 491 /** 492 * nand_get_sdr_timings - get SDR timing from data interface 493 * @conf: The data interface 494 */ 495 static inline const struct nand_sdr_timings * 496 nand_get_sdr_timings(const struct nand_data_interface *conf) 497 { 498 if (conf->type != NAND_SDR_IFACE) 499 return ERR_PTR(-EINVAL); 500 501 return &conf->timings.sdr; 502 } 503 504 /** 505 * struct nand_op_cmd_instr - Definition of a command instruction 506 * @opcode: the command to issue in one cycle 507 */ 508 struct nand_op_cmd_instr { 509 u8 opcode; 510 }; 511 512 /** 513 * struct nand_op_addr_instr - Definition of an address instruction 514 * @naddrs: length of the @addrs array 515 * @addrs: array containing the address cycles to issue 516 */ 517 struct nand_op_addr_instr { 518 unsigned int naddrs; 519 const u8 *addrs; 520 }; 521 522 /** 523 * struct nand_op_data_instr - Definition of a data instruction 524 * @len: number of data bytes to move 525 * @buf: buffer to fill 526 * @buf.in: buffer to fill when reading from the NAND chip 527 * @buf.out: buffer to read from when writing to the NAND chip 528 * @force_8bit: force 8-bit access 529 * 530 * Please note that "in" and "out" are inverted from the ONFI specification 531 * and are from the controller perspective, so a "in" is a read from the NAND 532 * chip while a "out" is a write to the NAND chip. 533 */ 534 struct nand_op_data_instr { 535 unsigned int len; 536 union { 537 void *in; 538 const void *out; 539 } buf; 540 bool force_8bit; 541 }; 542 543 /** 544 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 545 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 546 */ 547 struct nand_op_waitrdy_instr { 548 unsigned int timeout_ms; 549 }; 550 551 /** 552 * enum nand_op_instr_type - Definition of all instruction types 553 * @NAND_OP_CMD_INSTR: command instruction 554 * @NAND_OP_ADDR_INSTR: address instruction 555 * @NAND_OP_DATA_IN_INSTR: data in instruction 556 * @NAND_OP_DATA_OUT_INSTR: data out instruction 557 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 558 */ 559 enum nand_op_instr_type { 560 NAND_OP_CMD_INSTR, 561 NAND_OP_ADDR_INSTR, 562 NAND_OP_DATA_IN_INSTR, 563 NAND_OP_DATA_OUT_INSTR, 564 NAND_OP_WAITRDY_INSTR, 565 }; 566 567 /** 568 * struct nand_op_instr - Instruction object 569 * @type: the instruction type 570 * @ctx: extra data associated to the instruction. You'll have to use the 571 * appropriate element depending on @type 572 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 573 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 574 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 575 * or %NAND_OP_DATA_OUT_INSTR 576 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 577 * @delay_ns: delay the controller should apply after the instruction has been 578 * issued on the bus. Most modern controllers have internal timings 579 * control logic, and in this case, the controller driver can ignore 580 * this field. 581 */ 582 struct nand_op_instr { 583 enum nand_op_instr_type type; 584 union { 585 struct nand_op_cmd_instr cmd; 586 struct nand_op_addr_instr addr; 587 struct nand_op_data_instr data; 588 struct nand_op_waitrdy_instr waitrdy; 589 } ctx; 590 unsigned int delay_ns; 591 }; 592 593 /* 594 * Special handling must be done for the WAITRDY timeout parameter as it usually 595 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 596 * tBERS (during an erase) which all of them are u64 values that cannot be 597 * divided by usual kernel macros and must be handled with the special 598 * DIV_ROUND_UP_ULL() macro. 599 * 600 * Cast to type of dividend is needed here to guarantee that the result won't 601 * be an unsigned long long when the dividend is an unsigned long (or smaller), 602 * which is what the compiler does when it sees ternary operator with 2 603 * different return types (picks the largest type to make sure there's no 604 * loss). 605 */ 606 #define __DIVIDE(dividend, divisor) ({ \ 607 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 608 DIV_ROUND_UP(dividend, divisor) : \ 609 DIV_ROUND_UP_ULL(dividend, divisor)); \ 610 }) 611 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 612 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 613 614 #define NAND_OP_CMD(id, ns) \ 615 { \ 616 .type = NAND_OP_CMD_INSTR, \ 617 .ctx.cmd.opcode = id, \ 618 .delay_ns = ns, \ 619 } 620 621 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 622 { \ 623 .type = NAND_OP_ADDR_INSTR, \ 624 .ctx.addr = { \ 625 .naddrs = ncycles, \ 626 .addrs = cycles, \ 627 }, \ 628 .delay_ns = ns, \ 629 } 630 631 #define NAND_OP_DATA_IN(l, b, ns) \ 632 { \ 633 .type = NAND_OP_DATA_IN_INSTR, \ 634 .ctx.data = { \ 635 .len = l, \ 636 .buf.in = b, \ 637 .force_8bit = false, \ 638 }, \ 639 .delay_ns = ns, \ 640 } 641 642 #define NAND_OP_DATA_OUT(l, b, ns) \ 643 { \ 644 .type = NAND_OP_DATA_OUT_INSTR, \ 645 .ctx.data = { \ 646 .len = l, \ 647 .buf.out = b, \ 648 .force_8bit = false, \ 649 }, \ 650 .delay_ns = ns, \ 651 } 652 653 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 654 { \ 655 .type = NAND_OP_DATA_IN_INSTR, \ 656 .ctx.data = { \ 657 .len = l, \ 658 .buf.in = b, \ 659 .force_8bit = true, \ 660 }, \ 661 .delay_ns = ns, \ 662 } 663 664 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 665 { \ 666 .type = NAND_OP_DATA_OUT_INSTR, \ 667 .ctx.data = { \ 668 .len = l, \ 669 .buf.out = b, \ 670 .force_8bit = true, \ 671 }, \ 672 .delay_ns = ns, \ 673 } 674 675 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 676 { \ 677 .type = NAND_OP_WAITRDY_INSTR, \ 678 .ctx.waitrdy.timeout_ms = tout_ms, \ 679 .delay_ns = ns, \ 680 } 681 682 /** 683 * struct nand_subop - a sub operation 684 * @instrs: array of instructions 685 * @ninstrs: length of the @instrs array 686 * @first_instr_start_off: offset to start from for the first instruction 687 * of the sub-operation 688 * @last_instr_end_off: offset to end at (excluded) for the last instruction 689 * of the sub-operation 690 * 691 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 692 * address instructions. 693 * 694 * When an operation cannot be handled as is by the NAND controller, it will 695 * be split by the parser into sub-operations which will be passed to the 696 * controller driver. 697 */ 698 struct nand_subop { 699 const struct nand_op_instr *instrs; 700 unsigned int ninstrs; 701 unsigned int first_instr_start_off; 702 unsigned int last_instr_end_off; 703 }; 704 705 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 706 unsigned int op_id); 707 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 708 unsigned int op_id); 709 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 710 unsigned int op_id); 711 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 712 unsigned int op_id); 713 714 /** 715 * struct nand_op_parser_addr_constraints - Constraints for address instructions 716 * @maxcycles: maximum number of address cycles the controller can issue in a 717 * single step 718 */ 719 struct nand_op_parser_addr_constraints { 720 unsigned int maxcycles; 721 }; 722 723 /** 724 * struct nand_op_parser_data_constraints - Constraints for data instructions 725 * @maxlen: maximum data length that the controller can handle in a single step 726 */ 727 struct nand_op_parser_data_constraints { 728 unsigned int maxlen; 729 }; 730 731 /** 732 * struct nand_op_parser_pattern_elem - One element of a pattern 733 * @type: the instructuction type 734 * @optional: whether this element of the pattern is optional or mandatory 735 * @ctx: address or data constraint 736 * @ctx.addr: address constraint (number of cycles) 737 * @ctx.data: data constraint (data length) 738 */ 739 struct nand_op_parser_pattern_elem { 740 enum nand_op_instr_type type; 741 bool optional; 742 union { 743 struct nand_op_parser_addr_constraints addr; 744 struct nand_op_parser_data_constraints data; 745 } ctx; 746 }; 747 748 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 749 { \ 750 .type = NAND_OP_CMD_INSTR, \ 751 .optional = _opt, \ 752 } 753 754 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 755 { \ 756 .type = NAND_OP_ADDR_INSTR, \ 757 .optional = _opt, \ 758 .ctx.addr.maxcycles = _maxcycles, \ 759 } 760 761 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 762 { \ 763 .type = NAND_OP_DATA_IN_INSTR, \ 764 .optional = _opt, \ 765 .ctx.data.maxlen = _maxlen, \ 766 } 767 768 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 769 { \ 770 .type = NAND_OP_DATA_OUT_INSTR, \ 771 .optional = _opt, \ 772 .ctx.data.maxlen = _maxlen, \ 773 } 774 775 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 776 { \ 777 .type = NAND_OP_WAITRDY_INSTR, \ 778 .optional = _opt, \ 779 } 780 781 /** 782 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 783 * @elems: array of pattern elements 784 * @nelems: number of pattern elements in @elems array 785 * @exec: the function that will issue a sub-operation 786 * 787 * A pattern is a list of elements, each element reprensenting one instruction 788 * with its constraints. The pattern itself is used by the core to match NAND 789 * chip operation with NAND controller operations. 790 * Once a match between a NAND controller operation pattern and a NAND chip 791 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 792 * hook is called so that the controller driver can issue the operation on the 793 * bus. 794 * 795 * Controller drivers should declare as many patterns as they support and pass 796 * this list of patterns (created with the help of the following macro) to 797 * the nand_op_parser_exec_op() helper. 798 */ 799 struct nand_op_parser_pattern { 800 const struct nand_op_parser_pattern_elem *elems; 801 unsigned int nelems; 802 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 803 }; 804 805 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 806 { \ 807 .exec = _exec, \ 808 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 809 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 810 sizeof(struct nand_op_parser_pattern_elem), \ 811 } 812 813 /** 814 * struct nand_op_parser - NAND controller operation parser descriptor 815 * @patterns: array of supported patterns 816 * @npatterns: length of the @patterns array 817 * 818 * The parser descriptor is just an array of supported patterns which will be 819 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 820 * NAND operation (or tries to determine if a specific operation is supported). 821 * 822 * It is worth mentioning that patterns will be tested in their declaration 823 * order, and the first match will be taken, so it's important to order patterns 824 * appropriately so that simple/inefficient patterns are placed at the end of 825 * the list. Usually, this is where you put single instruction patterns. 826 */ 827 struct nand_op_parser { 828 const struct nand_op_parser_pattern *patterns; 829 unsigned int npatterns; 830 }; 831 832 #define NAND_OP_PARSER(...) \ 833 { \ 834 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 835 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 836 sizeof(struct nand_op_parser_pattern), \ 837 } 838 839 /** 840 * struct nand_operation - NAND operation descriptor 841 * @cs: the CS line to select for this NAND operation 842 * @instrs: array of instructions to execute 843 * @ninstrs: length of the @instrs array 844 * 845 * The actual operation structure that will be passed to chip->exec_op(). 846 */ 847 struct nand_operation { 848 unsigned int cs; 849 const struct nand_op_instr *instrs; 850 unsigned int ninstrs; 851 }; 852 853 #define NAND_OPERATION(_cs, _instrs) \ 854 { \ 855 .cs = _cs, \ 856 .instrs = _instrs, \ 857 .ninstrs = ARRAY_SIZE(_instrs), \ 858 } 859 860 int nand_op_parser_exec_op(struct nand_chip *chip, 861 const struct nand_op_parser *parser, 862 const struct nand_operation *op, bool check_only); 863 /** 864 * struct nand_controller_ops - Controller operations 865 * 866 * @attach_chip: this method is called after the NAND detection phase after 867 * flash ID and MTD fields such as erase size, page size and OOB 868 * size have been set up. ECC requirements are available if 869 * provided by the NAND chip or device tree. Typically used to 870 * choose the appropriate ECC configuration and allocate 871 * associated resources. 872 * This hook is optional. 873 * @detach_chip: free all resources allocated/claimed in 874 * nand_controller_ops->attach_chip(). 875 * This hook is optional. 876 * @exec_op: controller specific method to execute NAND operations. 877 * This method replaces chip->legacy.cmdfunc(), 878 * chip->legacy.{read,write}_{buf,byte,word}(), 879 * chip->legacy.dev_ready() and chip->legacy.waifunc(). 880 * @setup_data_interface: setup the data interface and timing. If 881 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 882 * means the configuration should not be applied but 883 * only checked. 884 * This hook is optional. 885 */ 886 struct nand_controller_ops { 887 int (*attach_chip)(struct nand_chip *chip); 888 void (*detach_chip)(struct nand_chip *chip); 889 int (*exec_op)(struct nand_chip *chip, 890 const struct nand_operation *op, 891 bool check_only); 892 int (*setup_data_interface)(struct nand_chip *chip, int chipnr, 893 const struct nand_data_interface *conf); 894 }; 895 896 /** 897 * struct nand_controller - Structure used to describe a NAND controller 898 * 899 * @lock: lock used to serialize accesses to the NAND controller 900 * @ops: NAND controller operations. 901 */ 902 struct nand_controller { 903 struct mutex lock; 904 const struct nand_controller_ops *ops; 905 }; 906 907 static inline void nand_controller_init(struct nand_controller *nfc) 908 { 909 mutex_init(&nfc->lock); 910 } 911 912 /** 913 * struct nand_legacy - NAND chip legacy fields/hooks 914 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 915 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 916 * @select_chip: select/deselect a specific target/die 917 * @read_byte: read one byte from the chip 918 * @write_byte: write a single byte to the chip on the low 8 I/O lines 919 * @write_buf: write data from the buffer to the chip 920 * @read_buf: read data from the chip into the buffer 921 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 922 * to write command and address 923 * @cmdfunc: hardware specific function for writing commands to the chip. 924 * @dev_ready: hardware specific function for accessing device ready/busy line. 925 * If set to NULL no access to ready/busy is available and the 926 * ready/busy information is read from the chip status register. 927 * @waitfunc: hardware specific function for wait on ready. 928 * @block_bad: check if a block is bad, using OOB markers 929 * @block_markbad: mark a block bad 930 * @set_features: set the NAND chip features 931 * @get_features: get the NAND chip features 932 * @chip_delay: chip dependent delay for transferring data from array to read 933 * regs (tR). 934 * @dummy_controller: dummy controller implementation for drivers that can 935 * only control a single chip 936 * 937 * If you look at this structure you're already wrong. These fields/hooks are 938 * all deprecated. 939 */ 940 struct nand_legacy { 941 void __iomem *IO_ADDR_R; 942 void __iomem *IO_ADDR_W; 943 void (*select_chip)(struct nand_chip *chip, int cs); 944 u8 (*read_byte)(struct nand_chip *chip); 945 void (*write_byte)(struct nand_chip *chip, u8 byte); 946 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 947 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 948 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 949 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 950 int page_addr); 951 int (*dev_ready)(struct nand_chip *chip); 952 int (*waitfunc)(struct nand_chip *chip); 953 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 954 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 955 int (*set_features)(struct nand_chip *chip, int feature_addr, 956 u8 *subfeature_para); 957 int (*get_features)(struct nand_chip *chip, int feature_addr, 958 u8 *subfeature_para); 959 int chip_delay; 960 struct nand_controller dummy_controller; 961 }; 962 963 /** 964 * struct nand_chip - NAND Private Flash Chip Data 965 * @mtd: MTD device registered to the MTD framework 966 * @legacy: All legacy fields/hooks. If you develop a new driver, 967 * don't even try to use any of these fields/hooks, and if 968 * you're modifying an existing driver that is using those 969 * fields/hooks, you should consider reworking the driver 970 * avoid using them. 971 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 972 * setting the read-retry mode. Mostly needed for MLC NAND. 973 * @ecc: [BOARDSPECIFIC] ECC control structure 974 * @buf_align: minimum buffer alignment required by a platform 975 * @oob_poi: "poison value buffer," used for laying out OOB data 976 * before writing 977 * @page_shift: [INTERN] number of address bits in a page (column 978 * address bits). 979 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 980 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 981 * @chip_shift: [INTERN] number of address bits in one chip 982 * @options: [BOARDSPECIFIC] various chip options. They can partly 983 * be set to inform nand_scan about special functionality. 984 * See the defines for further explanation. 985 * @bbt_options: [INTERN] bad block specific options. All options used 986 * here must come from bbm.h. By default, these options 987 * will be copied to the appropriate nand_bbt_descr's. 988 * @badblockpos: [INTERN] position of the bad block marker in the oob 989 * area. 990 * @badblockbits: [INTERN] minimum number of set bits in a good block's 991 * bad block marker position; i.e., BBM == 11110111b is 992 * not bad when badblockbits == 7 993 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 994 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 995 * Minimum amount of bit errors per @ecc_step_ds guaranteed 996 * to be correctable. If unknown, set to zero. 997 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 998 * also from the datasheet. It is the recommended ECC step 999 * size, if known; if unknown, set to zero. 1000 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1001 * set to the actually used ONFI mode if the chip is 1002 * ONFI compliant or deduced from the datasheet if 1003 * the NAND chip is not ONFI compliant. 1004 * @numchips: [INTERN] number of physical chips 1005 * @chipsize: [INTERN] the size of one chip for multichip arrays 1006 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1007 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1008 * @pagebuf: [INTERN] holds the pagenumber which is currently in 1009 * data_buf. 1010 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 1011 * currently in data_buf. 1012 * @subpagesize: [INTERN] holds the subpagesize 1013 * @id: [INTERN] holds NAND ID 1014 * @parameters: [INTERN] holds generic parameters under an easily 1015 * readable form. 1016 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 1017 * this nand device will encounter their life times. 1018 * @blocks_per_die: [INTERN] The number of PEBs in a die 1019 * @data_interface: [INTERN] NAND interface timing information 1020 * @cur_cs: currently selected target. -1 means no target selected, 1021 * otherwise we should always have cur_cs >= 0 && 1022 * cur_cs < numchips. NAND Controller drivers should not 1023 * modify this value, but they're allowed to read it. 1024 * @read_retries: [INTERN] the number of read retry modes supported 1025 * @lock: lock protecting the suspended field. Also used to 1026 * serialize accesses to the NAND device. 1027 * @suspended: set to 1 when the device is suspended, 0 when it's not. 1028 * @bbt: [INTERN] bad block table pointer 1029 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1030 * lookup. 1031 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1032 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1033 * bad block scan. 1034 * @controller: [REPLACEABLE] a pointer to a hardware controller 1035 * structure which is shared among multiple independent 1036 * devices. 1037 * @priv: [OPTIONAL] pointer to private chip data 1038 * @manufacturer: [INTERN] Contains manufacturer information 1039 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1040 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1041 */ 1042 1043 struct nand_chip { 1044 struct mtd_info mtd; 1045 1046 struct nand_legacy legacy; 1047 1048 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1049 1050 unsigned int options; 1051 unsigned int bbt_options; 1052 1053 int page_shift; 1054 int phys_erase_shift; 1055 int bbt_erase_shift; 1056 int chip_shift; 1057 int numchips; 1058 uint64_t chipsize; 1059 int pagemask; 1060 u8 *data_buf; 1061 int pagebuf; 1062 unsigned int pagebuf_bitflips; 1063 int subpagesize; 1064 uint8_t bits_per_cell; 1065 uint16_t ecc_strength_ds; 1066 uint16_t ecc_step_ds; 1067 int onfi_timing_mode_default; 1068 int badblockpos; 1069 int badblockbits; 1070 1071 struct nand_id id; 1072 struct nand_parameters parameters; 1073 u16 max_bb_per_die; 1074 u32 blocks_per_die; 1075 1076 struct nand_data_interface data_interface; 1077 1078 int cur_cs; 1079 1080 int read_retries; 1081 1082 struct mutex lock; 1083 unsigned int suspended : 1; 1084 1085 uint8_t *oob_poi; 1086 struct nand_controller *controller; 1087 1088 struct nand_ecc_ctrl ecc; 1089 unsigned long buf_align; 1090 1091 uint8_t *bbt; 1092 struct nand_bbt_descr *bbt_td; 1093 struct nand_bbt_descr *bbt_md; 1094 1095 struct nand_bbt_descr *badblock_pattern; 1096 1097 void *priv; 1098 1099 struct { 1100 const struct nand_manufacturer *desc; 1101 void *priv; 1102 } manufacturer; 1103 }; 1104 1105 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1106 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1107 1108 static inline void nand_set_flash_node(struct nand_chip *chip, 1109 struct device_node *np) 1110 { 1111 mtd_set_of_node(&chip->mtd, np); 1112 } 1113 1114 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1115 { 1116 return mtd_get_of_node(&chip->mtd); 1117 } 1118 1119 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1120 { 1121 return container_of(mtd, struct nand_chip, mtd); 1122 } 1123 1124 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1125 { 1126 return &chip->mtd; 1127 } 1128 1129 static inline void *nand_get_controller_data(struct nand_chip *chip) 1130 { 1131 return chip->priv; 1132 } 1133 1134 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1135 { 1136 chip->priv = priv; 1137 } 1138 1139 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1140 void *priv) 1141 { 1142 chip->manufacturer.priv = priv; 1143 } 1144 1145 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1146 { 1147 return chip->manufacturer.priv; 1148 } 1149 1150 /* 1151 * A helper for defining older NAND chips where the second ID byte fully 1152 * defined the chip, including the geometry (chip size, eraseblock size, page 1153 * size). All these chips have 512 bytes NAND page size. 1154 */ 1155 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1156 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1157 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1158 1159 /* 1160 * A helper for defining newer chips which report their page size and 1161 * eraseblock size via the extended ID bytes. 1162 * 1163 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1164 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1165 * device ID now only represented a particular total chip size (and voltage, 1166 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1167 * using the same device ID. 1168 */ 1169 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1170 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1171 .options = (opts) } 1172 1173 #define NAND_ECC_INFO(_strength, _step) \ 1174 { .strength_ds = (_strength), .step_ds = (_step) } 1175 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1176 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1177 1178 /** 1179 * struct nand_flash_dev - NAND Flash Device ID Structure 1180 * @name: a human-readable name of the NAND chip 1181 * @dev_id: the device ID (the second byte of the full chip ID array) 1182 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1183 * memory address as @id[0]) 1184 * @dev_id: device ID part of the full chip ID array (refers the same memory 1185 * address as @id[1]) 1186 * @id: full device ID array 1187 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1188 * well as the eraseblock size) is determined from the extended NAND 1189 * chip ID array) 1190 * @chipsize: total chip size in MiB 1191 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1192 * @options: stores various chip bit options 1193 * @id_len: The valid length of the @id. 1194 * @oobsize: OOB size 1195 * @ecc: ECC correctability and step information from the datasheet. 1196 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1197 * @ecc_strength_ds in nand_chip{}. 1198 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1199 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1200 * For example, the "4bit ECC for each 512Byte" can be set with 1201 * NAND_ECC_INFO(4, 512). 1202 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1203 * reset. Should be deduced from timings described 1204 * in the datasheet. 1205 * 1206 */ 1207 struct nand_flash_dev { 1208 char *name; 1209 union { 1210 struct { 1211 uint8_t mfr_id; 1212 uint8_t dev_id; 1213 }; 1214 uint8_t id[NAND_MAX_ID_LEN]; 1215 }; 1216 unsigned int pagesize; 1217 unsigned int chipsize; 1218 unsigned int erasesize; 1219 unsigned int options; 1220 uint16_t id_len; 1221 uint16_t oobsize; 1222 struct { 1223 uint16_t strength_ds; 1224 uint16_t step_ds; 1225 } ecc; 1226 int onfi_timing_mode_default; 1227 }; 1228 1229 int nand_create_bbt(struct nand_chip *chip); 1230 1231 /* 1232 * Check if it is a SLC nand. 1233 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1234 * We do not distinguish the MLC and TLC now. 1235 */ 1236 static inline bool nand_is_slc(struct nand_chip *chip) 1237 { 1238 WARN(chip->bits_per_cell == 0, 1239 "chip->bits_per_cell is used uninitialized\n"); 1240 return chip->bits_per_cell == 1; 1241 } 1242 1243 /** 1244 * Check if the opcode's address should be sent only on the lower 8 bits 1245 * @command: opcode to check 1246 */ 1247 static inline int nand_opcode_8bits(unsigned int command) 1248 { 1249 switch (command) { 1250 case NAND_CMD_READID: 1251 case NAND_CMD_PARAM: 1252 case NAND_CMD_GET_FEATURES: 1253 case NAND_CMD_SET_FEATURES: 1254 return 1; 1255 default: 1256 break; 1257 } 1258 return 0; 1259 } 1260 1261 int nand_check_erased_ecc_chunk(void *data, int datalen, 1262 void *ecc, int ecclen, 1263 void *extraoob, int extraooblen, 1264 int threshold); 1265 1266 int nand_ecc_choose_conf(struct nand_chip *chip, 1267 const struct nand_ecc_caps *caps, int oobavail); 1268 1269 /* Default write_oob implementation */ 1270 int nand_write_oob_std(struct nand_chip *chip, int page); 1271 1272 /* Default read_oob implementation */ 1273 int nand_read_oob_std(struct nand_chip *chip, int page); 1274 1275 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1276 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1277 u8 *subfeature_param); 1278 1279 /* Default read_page_raw implementation */ 1280 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1281 int page); 1282 1283 /* Default write_page_raw implementation */ 1284 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1285 int oob_required, int page); 1286 1287 /* Reset and initialize a NAND device */ 1288 int nand_reset(struct nand_chip *chip, int chipnr); 1289 1290 /* NAND operation helpers */ 1291 int nand_reset_op(struct nand_chip *chip); 1292 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1293 unsigned int len); 1294 int nand_status_op(struct nand_chip *chip, u8 *status); 1295 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1296 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1297 unsigned int offset_in_page, void *buf, unsigned int len); 1298 int nand_change_read_column_op(struct nand_chip *chip, 1299 unsigned int offset_in_page, void *buf, 1300 unsigned int len, bool force_8bit); 1301 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1302 unsigned int offset_in_page, void *buf, unsigned int len); 1303 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1304 unsigned int offset_in_page, const void *buf, 1305 unsigned int len); 1306 int nand_prog_page_end_op(struct nand_chip *chip); 1307 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1308 unsigned int offset_in_page, const void *buf, 1309 unsigned int len); 1310 int nand_change_write_column_op(struct nand_chip *chip, 1311 unsigned int offset_in_page, const void *buf, 1312 unsigned int len, bool force_8bit); 1313 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1314 bool force_8bit); 1315 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1316 unsigned int len, bool force_8bit); 1317 1318 /* Scan and identify a NAND device */ 1319 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1320 struct nand_flash_dev *ids); 1321 1322 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1323 { 1324 return nand_scan_with_ids(chip, max_chips, NULL); 1325 } 1326 1327 /* Internal helper for board drivers which need to override command function */ 1328 void nand_wait_ready(struct nand_chip *chip); 1329 1330 /* 1331 * Free resources held by the NAND device, must be called on error after a 1332 * sucessful nand_scan(). 1333 */ 1334 void nand_cleanup(struct nand_chip *chip); 1335 /* Unregister the MTD device and calls nand_cleanup() */ 1336 void nand_release(struct nand_chip *chip); 1337 1338 /* 1339 * External helper for controller drivers that have to implement the WAITRDY 1340 * instruction and have no physical pin to check it. 1341 */ 1342 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1343 struct gpio_desc; 1344 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 1345 unsigned long timeout_ms); 1346 1347 /* Select/deselect a NAND target. */ 1348 void nand_select_target(struct nand_chip *chip, unsigned int cs); 1349 void nand_deselect_target(struct nand_chip *chip); 1350 1351 #endif /* __LINUX_MTD_RAWNAND_H */ 1352