1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/wait.h> 20 #include <linux/spinlock.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/flashchip.h> 23 #include <linux/mtd/bbm.h> 24 25 struct mtd_info; 26 struct nand_flash_dev; 27 struct device_node; 28 29 /* Scan and identify a NAND device */ 30 int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Unregister the MTD device and free resources held by the NAND device */ 40 void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 void nand_wait_ready(struct mtd_info *mtd); 44 45 /* The maximum number of NAND chips in an array */ 46 #define NAND_MAX_CHIPS 8 47 48 /* 49 * Constants for hardware specific CLE/ALE/NCE function 50 * 51 * These are bits which can be or'ed to set/clear multiple 52 * bits in one go. 53 */ 54 /* Select the chip by setting nCE to low */ 55 #define NAND_NCE 0x01 56 /* Select the command latch by setting CLE to high */ 57 #define NAND_CLE 0x02 58 /* Select the address latch by setting ALE to high */ 59 #define NAND_ALE 0x04 60 61 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 62 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 63 #define NAND_CTRL_CHANGE 0x80 64 65 /* 66 * Standard NAND flash commands 67 */ 68 #define NAND_CMD_READ0 0 69 #define NAND_CMD_READ1 1 70 #define NAND_CMD_RNDOUT 5 71 #define NAND_CMD_PAGEPROG 0x10 72 #define NAND_CMD_READOOB 0x50 73 #define NAND_CMD_ERASE1 0x60 74 #define NAND_CMD_STATUS 0x70 75 #define NAND_CMD_SEQIN 0x80 76 #define NAND_CMD_RNDIN 0x85 77 #define NAND_CMD_READID 0x90 78 #define NAND_CMD_ERASE2 0xd0 79 #define NAND_CMD_PARAM 0xec 80 #define NAND_CMD_GET_FEATURES 0xee 81 #define NAND_CMD_SET_FEATURES 0xef 82 #define NAND_CMD_RESET 0xff 83 84 /* Extended commands for large page devices */ 85 #define NAND_CMD_READSTART 0x30 86 #define NAND_CMD_RNDOUTSTART 0xE0 87 #define NAND_CMD_CACHEDPROG 0x15 88 89 #define NAND_CMD_NONE -1 90 91 /* Status bits */ 92 #define NAND_STATUS_FAIL 0x01 93 #define NAND_STATUS_FAIL_N1 0x02 94 #define NAND_STATUS_TRUE_READY 0x20 95 #define NAND_STATUS_READY 0x40 96 #define NAND_STATUS_WP 0x80 97 98 #define NAND_DATA_IFACE_CHECK_ONLY -1 99 100 /* 101 * Constants for ECC_MODES 102 */ 103 typedef enum { 104 NAND_ECC_NONE, 105 NAND_ECC_SOFT, 106 NAND_ECC_HW, 107 NAND_ECC_HW_SYNDROME, 108 NAND_ECC_HW_OOB_FIRST, 109 NAND_ECC_ON_DIE, 110 } nand_ecc_modes_t; 111 112 enum nand_ecc_algo { 113 NAND_ECC_UNKNOWN, 114 NAND_ECC_HAMMING, 115 NAND_ECC_BCH, 116 }; 117 118 /* 119 * Constants for Hardware ECC 120 */ 121 /* Reset Hardware ECC for read */ 122 #define NAND_ECC_READ 0 123 /* Reset Hardware ECC for write */ 124 #define NAND_ECC_WRITE 1 125 /* Enable Hardware ECC before syndrome is read back from flash */ 126 #define NAND_ECC_READSYN 2 127 128 /* 129 * Enable generic NAND 'page erased' check. This check is only done when 130 * ecc.correct() returns -EBADMSG. 131 * Set this flag if your implementation does not fix bitflips in erased 132 * pages and you want to rely on the default implementation. 133 */ 134 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 135 #define NAND_ECC_MAXIMIZE BIT(1) 136 /* 137 * If your controller already sends the required NAND commands when 138 * reading or writing a page, then the framework is not supposed to 139 * send READ0 and SEQIN/PAGEPROG respectively. 140 */ 141 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 142 143 /* Bit mask for flags passed to do_nand_read_ecc */ 144 #define NAND_GET_DEVICE 0x80 145 146 147 /* 148 * Option constants for bizarre disfunctionality and real 149 * features. 150 */ 151 /* Buswidth is 16 bit */ 152 #define NAND_BUSWIDTH_16 0x00000002 153 /* Chip has cache program function */ 154 #define NAND_CACHEPRG 0x00000008 155 /* 156 * Chip requires ready check on read (for auto-incremented sequential read). 157 * True only for small page devices; large page devices do not support 158 * autoincrement. 159 */ 160 #define NAND_NEED_READRDY 0x00000100 161 162 /* Chip does not allow subpage writes */ 163 #define NAND_NO_SUBPAGE_WRITE 0x00000200 164 165 /* Device is one of 'new' xD cards that expose fake nand command set */ 166 #define NAND_BROKEN_XD 0x00000400 167 168 /* Device behaves just like nand, but is readonly */ 169 #define NAND_ROM 0x00000800 170 171 /* Device supports subpage reads */ 172 #define NAND_SUBPAGE_READ 0x00001000 173 174 /* 175 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 176 * patterns. 177 */ 178 #define NAND_NEED_SCRAMBLING 0x00002000 179 180 /* Device needs 3rd row address cycle */ 181 #define NAND_ROW_ADDR_3 0x00004000 182 183 /* Options valid for Samsung large page devices */ 184 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 185 186 /* Macros to identify the above */ 187 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 188 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 189 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 190 191 /* Non chip related options */ 192 /* This option skips the bbt scan during initialization. */ 193 #define NAND_SKIP_BBTSCAN 0x00010000 194 /* 195 * This option is defined if the board driver allocates its own buffers 196 * (e.g. because it needs them DMA-coherent). 197 */ 198 #define NAND_OWN_BUFFERS 0x00020000 199 /* Chip may not exist, so silence any errors in scan */ 200 #define NAND_SCAN_SILENT_NODEV 0x00040000 201 /* 202 * Autodetect nand buswidth with readid/onfi. 203 * This suppose the driver will configure the hardware in 8 bits mode 204 * when calling nand_scan_ident, and update its configuration 205 * before calling nand_scan_tail. 206 */ 207 #define NAND_BUSWIDTH_AUTO 0x00080000 208 /* 209 * This option could be defined by controller drivers to protect against 210 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 211 */ 212 #define NAND_USE_BOUNCE_BUFFER 0x00100000 213 214 /* 215 * In case your controller is implementing ->cmd_ctrl() and is relying on the 216 * default ->cmdfunc() implementation, you may want to let the core handle the 217 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is 218 * requested. 219 * If your controller already takes care of this delay, you don't need to set 220 * this flag. 221 */ 222 #define NAND_WAIT_TCCS 0x00200000 223 224 /* Options set by nand scan */ 225 /* Nand scan has allocated controller struct */ 226 #define NAND_CONTROLLER_ALLOC 0x80000000 227 228 /* Cell info constants */ 229 #define NAND_CI_CHIPNR_MSK 0x03 230 #define NAND_CI_CELLTYPE_MSK 0x0C 231 #define NAND_CI_CELLTYPE_SHIFT 2 232 233 /* Keep gcc happy */ 234 struct nand_chip; 235 236 /* ONFI features */ 237 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 238 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 239 240 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 241 #define ONFI_TIMING_MODE_0 (1 << 0) 242 #define ONFI_TIMING_MODE_1 (1 << 1) 243 #define ONFI_TIMING_MODE_2 (1 << 2) 244 #define ONFI_TIMING_MODE_3 (1 << 3) 245 #define ONFI_TIMING_MODE_4 (1 << 4) 246 #define ONFI_TIMING_MODE_5 (1 << 5) 247 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 248 249 /* ONFI feature address */ 250 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 251 252 /* Vendor-specific feature address (Micron) */ 253 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 254 #define ONFI_FEATURE_ON_DIE_ECC 0x90 255 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) 256 257 /* ONFI subfeature parameters length */ 258 #define ONFI_SUBFEATURE_PARAM_LEN 4 259 260 /* ONFI optional commands SET/GET FEATURES supported? */ 261 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 262 263 struct nand_onfi_params { 264 /* rev info and features block */ 265 /* 'O' 'N' 'F' 'I' */ 266 u8 sig[4]; 267 __le16 revision; 268 __le16 features; 269 __le16 opt_cmd; 270 u8 reserved0[2]; 271 __le16 ext_param_page_length; /* since ONFI 2.1 */ 272 u8 num_of_param_pages; /* since ONFI 2.1 */ 273 u8 reserved1[17]; 274 275 /* manufacturer information block */ 276 char manufacturer[12]; 277 char model[20]; 278 u8 jedec_id; 279 __le16 date_code; 280 u8 reserved2[13]; 281 282 /* memory organization block */ 283 __le32 byte_per_page; 284 __le16 spare_bytes_per_page; 285 __le32 data_bytes_per_ppage; 286 __le16 spare_bytes_per_ppage; 287 __le32 pages_per_block; 288 __le32 blocks_per_lun; 289 u8 lun_count; 290 u8 addr_cycles; 291 u8 bits_per_cell; 292 __le16 bb_per_lun; 293 __le16 block_endurance; 294 u8 guaranteed_good_blocks; 295 __le16 guaranteed_block_endurance; 296 u8 programs_per_page; 297 u8 ppage_attr; 298 u8 ecc_bits; 299 u8 interleaved_bits; 300 u8 interleaved_ops; 301 u8 reserved3[13]; 302 303 /* electrical parameter block */ 304 u8 io_pin_capacitance_max; 305 __le16 async_timing_mode; 306 __le16 program_cache_timing_mode; 307 __le16 t_prog; 308 __le16 t_bers; 309 __le16 t_r; 310 __le16 t_ccs; 311 __le16 src_sync_timing_mode; 312 u8 src_ssync_features; 313 __le16 clk_pin_capacitance_typ; 314 __le16 io_pin_capacitance_typ; 315 __le16 input_pin_capacitance_typ; 316 u8 input_pin_capacitance_max; 317 u8 driver_strength_support; 318 __le16 t_int_r; 319 __le16 t_adl; 320 u8 reserved4[8]; 321 322 /* vendor */ 323 __le16 vendor_revision; 324 u8 vendor[88]; 325 326 __le16 crc; 327 } __packed; 328 329 #define ONFI_CRC_BASE 0x4F4E 330 331 /* Extended ECC information Block Definition (since ONFI 2.1) */ 332 struct onfi_ext_ecc_info { 333 u8 ecc_bits; 334 u8 codeword_size; 335 __le16 bb_per_lun; 336 __le16 block_endurance; 337 u8 reserved[2]; 338 } __packed; 339 340 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 341 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 342 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 343 struct onfi_ext_section { 344 u8 type; 345 u8 length; 346 } __packed; 347 348 #define ONFI_EXT_SECTION_MAX 8 349 350 /* Extended Parameter Page Definition (since ONFI 2.1) */ 351 struct onfi_ext_param_page { 352 __le16 crc; 353 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 354 u8 reserved0[10]; 355 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 356 357 /* 358 * The actual size of the Extended Parameter Page is in 359 * @ext_param_page_length of nand_onfi_params{}. 360 * The following are the variable length sections. 361 * So we do not add any fields below. Please see the ONFI spec. 362 */ 363 } __packed; 364 365 struct jedec_ecc_info { 366 u8 ecc_bits; 367 u8 codeword_size; 368 __le16 bb_per_lun; 369 __le16 block_endurance; 370 u8 reserved[2]; 371 } __packed; 372 373 /* JEDEC features */ 374 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 375 376 struct nand_jedec_params { 377 /* rev info and features block */ 378 /* 'J' 'E' 'S' 'D' */ 379 u8 sig[4]; 380 __le16 revision; 381 __le16 features; 382 u8 opt_cmd[3]; 383 __le16 sec_cmd; 384 u8 num_of_param_pages; 385 u8 reserved0[18]; 386 387 /* manufacturer information block */ 388 char manufacturer[12]; 389 char model[20]; 390 u8 jedec_id[6]; 391 u8 reserved1[10]; 392 393 /* memory organization block */ 394 __le32 byte_per_page; 395 __le16 spare_bytes_per_page; 396 u8 reserved2[6]; 397 __le32 pages_per_block; 398 __le32 blocks_per_lun; 399 u8 lun_count; 400 u8 addr_cycles; 401 u8 bits_per_cell; 402 u8 programs_per_page; 403 u8 multi_plane_addr; 404 u8 multi_plane_op_attr; 405 u8 reserved3[38]; 406 407 /* electrical parameter block */ 408 __le16 async_sdr_speed_grade; 409 __le16 toggle_ddr_speed_grade; 410 __le16 sync_ddr_speed_grade; 411 u8 async_sdr_features; 412 u8 toggle_ddr_features; 413 u8 sync_ddr_features; 414 __le16 t_prog; 415 __le16 t_bers; 416 __le16 t_r; 417 __le16 t_r_multi_plane; 418 __le16 t_ccs; 419 __le16 io_pin_capacitance_typ; 420 __le16 input_pin_capacitance_typ; 421 __le16 clk_pin_capacitance_typ; 422 u8 driver_strength_support; 423 __le16 t_adl; 424 u8 reserved4[36]; 425 426 /* ECC and endurance block */ 427 u8 guaranteed_good_blocks; 428 __le16 guaranteed_block_endurance; 429 struct jedec_ecc_info ecc_info[4]; 430 u8 reserved5[29]; 431 432 /* reserved */ 433 u8 reserved6[148]; 434 435 /* vendor */ 436 __le16 vendor_rev_num; 437 u8 reserved7[88]; 438 439 /* CRC for Parameter Page */ 440 __le16 crc; 441 } __packed; 442 443 /* The maximum expected count of bytes in the NAND ID sequence */ 444 #define NAND_MAX_ID_LEN 8 445 446 /** 447 * struct nand_id - NAND id structure 448 * @data: buffer containing the id bytes. 449 * @len: ID length. 450 */ 451 struct nand_id { 452 u8 data[NAND_MAX_ID_LEN]; 453 int len; 454 }; 455 456 /** 457 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 458 * @lock: protection lock 459 * @active: the mtd device which holds the controller currently 460 * @wq: wait queue to sleep on if a NAND operation is in 461 * progress used instead of the per chip wait queue 462 * when a hw controller is available. 463 */ 464 struct nand_hw_control { 465 spinlock_t lock; 466 struct nand_chip *active; 467 wait_queue_head_t wq; 468 }; 469 470 static inline void nand_hw_control_init(struct nand_hw_control *nfc) 471 { 472 nfc->active = NULL; 473 spin_lock_init(&nfc->lock); 474 init_waitqueue_head(&nfc->wq); 475 } 476 477 /** 478 * struct nand_ecc_step_info - ECC step information of ECC engine 479 * @stepsize: data bytes per ECC step 480 * @strengths: array of supported strengths 481 * @nstrengths: number of supported strengths 482 */ 483 struct nand_ecc_step_info { 484 int stepsize; 485 const int *strengths; 486 int nstrengths; 487 }; 488 489 /** 490 * struct nand_ecc_caps - capability of ECC engine 491 * @stepinfos: array of ECC step information 492 * @nstepinfos: number of ECC step information 493 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 494 */ 495 struct nand_ecc_caps { 496 const struct nand_ecc_step_info *stepinfos; 497 int nstepinfos; 498 int (*calc_ecc_bytes)(int step_size, int strength); 499 }; 500 501 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 502 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 503 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 504 static const struct nand_ecc_step_info __name##_stepinfo = { \ 505 .stepsize = __step, \ 506 .strengths = __name##_strengths, \ 507 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 508 }; \ 509 static const struct nand_ecc_caps __name = { \ 510 .stepinfos = &__name##_stepinfo, \ 511 .nstepinfos = 1, \ 512 .calc_ecc_bytes = __calc, \ 513 } 514 515 /** 516 * struct nand_ecc_ctrl - Control structure for ECC 517 * @mode: ECC mode 518 * @algo: ECC algorithm 519 * @steps: number of ECC steps per page 520 * @size: data bytes per ECC step 521 * @bytes: ECC bytes per step 522 * @strength: max number of correctible bits per ECC step 523 * @total: total number of ECC bytes per page 524 * @prepad: padding information for syndrome based ECC generators 525 * @postpad: padding information for syndrome based ECC generators 526 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 527 * @priv: pointer to private ECC control data 528 * @hwctl: function to control hardware ECC generator. Must only 529 * be provided if an hardware ECC is available 530 * @calculate: function for ECC calculation or readback from ECC hardware 531 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 532 * Should return a positive number representing the number of 533 * corrected bitflips, -EBADMSG if the number of bitflips exceed 534 * ECC strength, or any other error code if the error is not 535 * directly related to correction. 536 * If -EBADMSG is returned the input buffers should be left 537 * untouched. 538 * @read_page_raw: function to read a raw page without ECC. This function 539 * should hide the specific layout used by the ECC 540 * controller and always return contiguous in-band and 541 * out-of-band data even if they're not stored 542 * contiguously on the NAND chip (e.g. 543 * NAND_ECC_HW_SYNDROME interleaves in-band and 544 * out-of-band data). 545 * @write_page_raw: function to write a raw page without ECC. This function 546 * should hide the specific layout used by the ECC 547 * controller and consider the passed data as contiguous 548 * in-band and out-of-band data. ECC controller is 549 * responsible for doing the appropriate transformations 550 * to adapt to its specific layout (e.g. 551 * NAND_ECC_HW_SYNDROME interleaves in-band and 552 * out-of-band data). 553 * @read_page: function to read a page according to the ECC generator 554 * requirements; returns maximum number of bitflips corrected in 555 * any single ECC step, -EIO hw error 556 * @read_subpage: function to read parts of the page covered by ECC; 557 * returns same as read_page() 558 * @write_subpage: function to write parts of the page covered by ECC. 559 * @write_page: function to write a page according to the ECC generator 560 * requirements. 561 * @write_oob_raw: function to write chip OOB data without ECC 562 * @read_oob_raw: function to read chip OOB data without ECC 563 * @read_oob: function to read chip OOB data 564 * @write_oob: function to write chip OOB data 565 */ 566 struct nand_ecc_ctrl { 567 nand_ecc_modes_t mode; 568 enum nand_ecc_algo algo; 569 int steps; 570 int size; 571 int bytes; 572 int total; 573 int strength; 574 int prepad; 575 int postpad; 576 unsigned int options; 577 void *priv; 578 void (*hwctl)(struct mtd_info *mtd, int mode); 579 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 580 uint8_t *ecc_code); 581 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 582 uint8_t *calc_ecc); 583 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 584 uint8_t *buf, int oob_required, int page); 585 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 586 const uint8_t *buf, int oob_required, int page); 587 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 588 uint8_t *buf, int oob_required, int page); 589 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 590 uint32_t offs, uint32_t len, uint8_t *buf, int page); 591 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 592 uint32_t offset, uint32_t data_len, 593 const uint8_t *data_buf, int oob_required, int page); 594 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 595 const uint8_t *buf, int oob_required, int page); 596 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 597 int page); 598 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 599 int page); 600 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 601 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 602 int page); 603 }; 604 605 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 606 { 607 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 608 } 609 610 /** 611 * struct nand_buffers - buffer structure for read/write 612 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 613 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 614 * @databuf: buffer pointer for data, size is (page size + oobsize). 615 * 616 * Do not change the order of buffers. databuf and oobrbuf must be in 617 * consecutive order. 618 */ 619 struct nand_buffers { 620 uint8_t *ecccalc; 621 uint8_t *ecccode; 622 uint8_t *databuf; 623 }; 624 625 /** 626 * struct nand_sdr_timings - SDR NAND chip timings 627 * 628 * This struct defines the timing requirements of a SDR NAND chip. 629 * These information can be found in every NAND datasheets and the timings 630 * meaning are described in the ONFI specifications: 631 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 632 * Parameters) 633 * 634 * All these timings are expressed in picoseconds. 635 * 636 * @tBERS_max: Block erase time 637 * @tCCS_min: Change column setup time 638 * @tPROG_max: Page program time 639 * @tR_max: Page read time 640 * @tALH_min: ALE hold time 641 * @tADL_min: ALE to data loading time 642 * @tALS_min: ALE setup time 643 * @tAR_min: ALE to RE# delay 644 * @tCEA_max: CE# access time 645 * @tCEH_min: CE# high hold time 646 * @tCH_min: CE# hold time 647 * @tCHZ_max: CE# high to output hi-Z 648 * @tCLH_min: CLE hold time 649 * @tCLR_min: CLE to RE# delay 650 * @tCLS_min: CLE setup time 651 * @tCOH_min: CE# high to output hold 652 * @tCS_min: CE# setup time 653 * @tDH_min: Data hold time 654 * @tDS_min: Data setup time 655 * @tFEAT_max: Busy time for Set Features and Get Features 656 * @tIR_min: Output hi-Z to RE# low 657 * @tITC_max: Interface and Timing Mode Change time 658 * @tRC_min: RE# cycle time 659 * @tREA_max: RE# access time 660 * @tREH_min: RE# high hold time 661 * @tRHOH_min: RE# high to output hold 662 * @tRHW_min: RE# high to WE# low 663 * @tRHZ_max: RE# high to output hi-Z 664 * @tRLOH_min: RE# low to output hold 665 * @tRP_min: RE# pulse width 666 * @tRR_min: Ready to RE# low (data only) 667 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 668 * rising edge of R/B#. 669 * @tWB_max: WE# high to SR[6] low 670 * @tWC_min: WE# cycle time 671 * @tWH_min: WE# high hold time 672 * @tWHR_min: WE# high to RE# low 673 * @tWP_min: WE# pulse width 674 * @tWW_min: WP# transition to WE# low 675 */ 676 struct nand_sdr_timings { 677 u64 tBERS_max; 678 u32 tCCS_min; 679 u64 tPROG_max; 680 u64 tR_max; 681 u32 tALH_min; 682 u32 tADL_min; 683 u32 tALS_min; 684 u32 tAR_min; 685 u32 tCEA_max; 686 u32 tCEH_min; 687 u32 tCH_min; 688 u32 tCHZ_max; 689 u32 tCLH_min; 690 u32 tCLR_min; 691 u32 tCLS_min; 692 u32 tCOH_min; 693 u32 tCS_min; 694 u32 tDH_min; 695 u32 tDS_min; 696 u32 tFEAT_max; 697 u32 tIR_min; 698 u32 tITC_max; 699 u32 tRC_min; 700 u32 tREA_max; 701 u32 tREH_min; 702 u32 tRHOH_min; 703 u32 tRHW_min; 704 u32 tRHZ_max; 705 u32 tRLOH_min; 706 u32 tRP_min; 707 u32 tRR_min; 708 u64 tRST_max; 709 u32 tWB_max; 710 u32 tWC_min; 711 u32 tWH_min; 712 u32 tWHR_min; 713 u32 tWP_min; 714 u32 tWW_min; 715 }; 716 717 /** 718 * enum nand_data_interface_type - NAND interface timing type 719 * @NAND_SDR_IFACE: Single Data Rate interface 720 */ 721 enum nand_data_interface_type { 722 NAND_SDR_IFACE, 723 }; 724 725 /** 726 * struct nand_data_interface - NAND interface timing 727 * @type: type of the timing 728 * @timings: The timing, type according to @type 729 */ 730 struct nand_data_interface { 731 enum nand_data_interface_type type; 732 union { 733 struct nand_sdr_timings sdr; 734 } timings; 735 }; 736 737 /** 738 * nand_get_sdr_timings - get SDR timing from data interface 739 * @conf: The data interface 740 */ 741 static inline const struct nand_sdr_timings * 742 nand_get_sdr_timings(const struct nand_data_interface *conf) 743 { 744 if (conf->type != NAND_SDR_IFACE) 745 return ERR_PTR(-EINVAL); 746 747 return &conf->timings.sdr; 748 } 749 750 /** 751 * struct nand_manufacturer_ops - NAND Manufacturer operations 752 * @detect: detect the NAND memory organization and capabilities 753 * @init: initialize all vendor specific fields (like the ->read_retry() 754 * implementation) if any. 755 * @cleanup: the ->init() function may have allocated resources, ->cleanup() 756 * is here to let vendor specific code release those resources. 757 */ 758 struct nand_manufacturer_ops { 759 void (*detect)(struct nand_chip *chip); 760 int (*init)(struct nand_chip *chip); 761 void (*cleanup)(struct nand_chip *chip); 762 }; 763 764 /** 765 * struct nand_chip - NAND Private Flash Chip Data 766 * @mtd: MTD device registered to the MTD framework 767 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 768 * flash device 769 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 770 * flash device. 771 * @read_byte: [REPLACEABLE] read one byte from the chip 772 * @read_word: [REPLACEABLE] read one word from the chip 773 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 774 * low 8 I/O lines 775 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 776 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 777 * @select_chip: [REPLACEABLE] select chip nr 778 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 779 * @block_markbad: [REPLACEABLE] mark a block bad 780 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 781 * ALE/CLE/nCE. Also used to write command and address 782 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 783 * device ready/busy line. If set to NULL no access to 784 * ready/busy is available and the ready/busy information 785 * is read from the chip status register. 786 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 787 * commands to the chip. 788 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 789 * ready. 790 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 791 * setting the read-retry mode. Mostly needed for MLC NAND. 792 * @ecc: [BOARDSPECIFIC] ECC control structure 793 * @buffers: buffer structure for read/write 794 * @buf_align: minimum buffer alignment required by a platform 795 * @hwcontrol: platform-specific hardware control structure 796 * @erase: [REPLACEABLE] erase function 797 * @scan_bbt: [REPLACEABLE] function to scan bad block table 798 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 799 * data from array to read regs (tR). 800 * @state: [INTERN] the current state of the NAND device 801 * @oob_poi: "poison value buffer," used for laying out OOB data 802 * before writing 803 * @page_shift: [INTERN] number of address bits in a page (column 804 * address bits). 805 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 806 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 807 * @chip_shift: [INTERN] number of address bits in one chip 808 * @options: [BOARDSPECIFIC] various chip options. They can partly 809 * be set to inform nand_scan about special functionality. 810 * See the defines for further explanation. 811 * @bbt_options: [INTERN] bad block specific options. All options used 812 * here must come from bbm.h. By default, these options 813 * will be copied to the appropriate nand_bbt_descr's. 814 * @badblockpos: [INTERN] position of the bad block marker in the oob 815 * area. 816 * @badblockbits: [INTERN] minimum number of set bits in a good block's 817 * bad block marker position; i.e., BBM == 11110111b is 818 * not bad when badblockbits == 7 819 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 820 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 821 * Minimum amount of bit errors per @ecc_step_ds guaranteed 822 * to be correctable. If unknown, set to zero. 823 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 824 * also from the datasheet. It is the recommended ECC step 825 * size, if known; if unknown, set to zero. 826 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 827 * set to the actually used ONFI mode if the chip is 828 * ONFI compliant or deduced from the datasheet if 829 * the NAND chip is not ONFI compliant. 830 * @numchips: [INTERN] number of physical chips 831 * @chipsize: [INTERN] the size of one chip for multichip arrays 832 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 833 * @pagebuf: [INTERN] holds the pagenumber which is currently in 834 * data_buf. 835 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 836 * currently in data_buf. 837 * @subpagesize: [INTERN] holds the subpagesize 838 * @id: [INTERN] holds NAND ID 839 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 840 * non 0 if ONFI supported. 841 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 842 * non 0 if JEDEC supported. 843 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 844 * supported, 0 otherwise. 845 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 846 * supported, 0 otherwise. 847 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 848 * this nand device will encounter their life times. 849 * @blocks_per_die: [INTERN] The number of PEBs in a die 850 * @data_interface: [INTERN] NAND interface timing information 851 * @read_retries: [INTERN] the number of read retry modes supported 852 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 853 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 854 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 855 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 856 * means the configuration should not be applied but 857 * only checked. 858 * @bbt: [INTERN] bad block table pointer 859 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 860 * lookup. 861 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 862 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 863 * bad block scan. 864 * @controller: [REPLACEABLE] a pointer to a hardware controller 865 * structure which is shared among multiple independent 866 * devices. 867 * @priv: [OPTIONAL] pointer to private chip data 868 * @manufacturer: [INTERN] Contains manufacturer information 869 */ 870 871 struct nand_chip { 872 struct mtd_info mtd; 873 void __iomem *IO_ADDR_R; 874 void __iomem *IO_ADDR_W; 875 876 uint8_t (*read_byte)(struct mtd_info *mtd); 877 u16 (*read_word)(struct mtd_info *mtd); 878 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 879 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 880 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 881 void (*select_chip)(struct mtd_info *mtd, int chip); 882 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 883 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 884 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 885 int (*dev_ready)(struct mtd_info *mtd); 886 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 887 int page_addr); 888 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 889 int (*erase)(struct mtd_info *mtd, int page); 890 int (*scan_bbt)(struct mtd_info *mtd); 891 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 892 int feature_addr, uint8_t *subfeature_para); 893 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 894 int feature_addr, uint8_t *subfeature_para); 895 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 896 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 897 const struct nand_data_interface *conf); 898 899 900 int chip_delay; 901 unsigned int options; 902 unsigned int bbt_options; 903 904 int page_shift; 905 int phys_erase_shift; 906 int bbt_erase_shift; 907 int chip_shift; 908 int numchips; 909 uint64_t chipsize; 910 int pagemask; 911 int pagebuf; 912 unsigned int pagebuf_bitflips; 913 int subpagesize; 914 uint8_t bits_per_cell; 915 uint16_t ecc_strength_ds; 916 uint16_t ecc_step_ds; 917 int onfi_timing_mode_default; 918 int badblockpos; 919 int badblockbits; 920 921 struct nand_id id; 922 int onfi_version; 923 int jedec_version; 924 union { 925 struct nand_onfi_params onfi_params; 926 struct nand_jedec_params jedec_params; 927 }; 928 u16 max_bb_per_die; 929 u32 blocks_per_die; 930 931 struct nand_data_interface *data_interface; 932 933 int read_retries; 934 935 flstate_t state; 936 937 uint8_t *oob_poi; 938 struct nand_hw_control *controller; 939 940 struct nand_ecc_ctrl ecc; 941 struct nand_buffers *buffers; 942 unsigned long buf_align; 943 struct nand_hw_control hwcontrol; 944 945 uint8_t *bbt; 946 struct nand_bbt_descr *bbt_td; 947 struct nand_bbt_descr *bbt_md; 948 949 struct nand_bbt_descr *badblock_pattern; 950 951 void *priv; 952 953 struct { 954 const struct nand_manufacturer *desc; 955 void *priv; 956 } manufacturer; 957 }; 958 959 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 960 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 961 962 static inline void nand_set_flash_node(struct nand_chip *chip, 963 struct device_node *np) 964 { 965 mtd_set_of_node(&chip->mtd, np); 966 } 967 968 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 969 { 970 return mtd_get_of_node(&chip->mtd); 971 } 972 973 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 974 { 975 return container_of(mtd, struct nand_chip, mtd); 976 } 977 978 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 979 { 980 return &chip->mtd; 981 } 982 983 static inline void *nand_get_controller_data(struct nand_chip *chip) 984 { 985 return chip->priv; 986 } 987 988 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 989 { 990 chip->priv = priv; 991 } 992 993 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 994 void *priv) 995 { 996 chip->manufacturer.priv = priv; 997 } 998 999 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1000 { 1001 return chip->manufacturer.priv; 1002 } 1003 1004 /* 1005 * NAND Flash Manufacturer ID Codes 1006 */ 1007 #define NAND_MFR_TOSHIBA 0x98 1008 #define NAND_MFR_ESMT 0xc8 1009 #define NAND_MFR_SAMSUNG 0xec 1010 #define NAND_MFR_FUJITSU 0x04 1011 #define NAND_MFR_NATIONAL 0x8f 1012 #define NAND_MFR_RENESAS 0x07 1013 #define NAND_MFR_STMICRO 0x20 1014 #define NAND_MFR_HYNIX 0xad 1015 #define NAND_MFR_MICRON 0x2c 1016 #define NAND_MFR_AMD 0x01 1017 #define NAND_MFR_MACRONIX 0xc2 1018 #define NAND_MFR_EON 0x92 1019 #define NAND_MFR_SANDISK 0x45 1020 #define NAND_MFR_INTEL 0x89 1021 #define NAND_MFR_ATO 0x9b 1022 #define NAND_MFR_WINBOND 0xef 1023 1024 1025 /* 1026 * A helper for defining older NAND chips where the second ID byte fully 1027 * defined the chip, including the geometry (chip size, eraseblock size, page 1028 * size). All these chips have 512 bytes NAND page size. 1029 */ 1030 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1031 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1032 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1033 1034 /* 1035 * A helper for defining newer chips which report their page size and 1036 * eraseblock size via the extended ID bytes. 1037 * 1038 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1039 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1040 * device ID now only represented a particular total chip size (and voltage, 1041 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1042 * using the same device ID. 1043 */ 1044 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1045 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1046 .options = (opts) } 1047 1048 #define NAND_ECC_INFO(_strength, _step) \ 1049 { .strength_ds = (_strength), .step_ds = (_step) } 1050 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1051 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1052 1053 /** 1054 * struct nand_flash_dev - NAND Flash Device ID Structure 1055 * @name: a human-readable name of the NAND chip 1056 * @dev_id: the device ID (the second byte of the full chip ID array) 1057 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1058 * memory address as @id[0]) 1059 * @dev_id: device ID part of the full chip ID array (refers the same memory 1060 * address as @id[1]) 1061 * @id: full device ID array 1062 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1063 * well as the eraseblock size) is determined from the extended NAND 1064 * chip ID array) 1065 * @chipsize: total chip size in MiB 1066 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1067 * @options: stores various chip bit options 1068 * @id_len: The valid length of the @id. 1069 * @oobsize: OOB size 1070 * @ecc: ECC correctability and step information from the datasheet. 1071 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1072 * @ecc_strength_ds in nand_chip{}. 1073 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1074 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1075 * For example, the "4bit ECC for each 512Byte" can be set with 1076 * NAND_ECC_INFO(4, 512). 1077 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1078 * reset. Should be deduced from timings described 1079 * in the datasheet. 1080 * 1081 */ 1082 struct nand_flash_dev { 1083 char *name; 1084 union { 1085 struct { 1086 uint8_t mfr_id; 1087 uint8_t dev_id; 1088 }; 1089 uint8_t id[NAND_MAX_ID_LEN]; 1090 }; 1091 unsigned int pagesize; 1092 unsigned int chipsize; 1093 unsigned int erasesize; 1094 unsigned int options; 1095 uint16_t id_len; 1096 uint16_t oobsize; 1097 struct { 1098 uint16_t strength_ds; 1099 uint16_t step_ds; 1100 } ecc; 1101 int onfi_timing_mode_default; 1102 }; 1103 1104 /** 1105 * struct nand_manufacturer - NAND Flash Manufacturer structure 1106 * @name: Manufacturer name 1107 * @id: manufacturer ID code of device. 1108 * @ops: manufacturer operations 1109 */ 1110 struct nand_manufacturer { 1111 int id; 1112 char *name; 1113 const struct nand_manufacturer_ops *ops; 1114 }; 1115 1116 const struct nand_manufacturer *nand_get_manufacturer(u8 id); 1117 1118 static inline const char * 1119 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 1120 { 1121 return manufacturer ? manufacturer->name : "Unknown"; 1122 } 1123 1124 extern struct nand_flash_dev nand_flash_ids[]; 1125 1126 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 1127 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; 1128 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; 1129 extern const struct nand_manufacturer_ops micron_nand_manuf_ops; 1130 extern const struct nand_manufacturer_ops amd_nand_manuf_ops; 1131 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; 1132 1133 int nand_default_bbt(struct mtd_info *mtd); 1134 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1135 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1136 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1137 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1138 int allowbbt); 1139 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1140 size_t *retlen, uint8_t *buf); 1141 1142 /** 1143 * struct platform_nand_chip - chip level device structure 1144 * @nr_chips: max. number of chips to scan for 1145 * @chip_offset: chip number offset 1146 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1147 * @partitions: mtd partition list 1148 * @chip_delay: R/B delay value in us 1149 * @options: Option flags, e.g. 16bit buswidth 1150 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1151 * @part_probe_types: NULL-terminated array of probe types 1152 */ 1153 struct platform_nand_chip { 1154 int nr_chips; 1155 int chip_offset; 1156 int nr_partitions; 1157 struct mtd_partition *partitions; 1158 int chip_delay; 1159 unsigned int options; 1160 unsigned int bbt_options; 1161 const char **part_probe_types; 1162 }; 1163 1164 /* Keep gcc happy */ 1165 struct platform_device; 1166 1167 /** 1168 * struct platform_nand_ctrl - controller level device structure 1169 * @probe: platform specific function to probe/setup hardware 1170 * @remove: platform specific function to remove/teardown hardware 1171 * @hwcontrol: platform specific hardware control structure 1172 * @dev_ready: platform specific function to read ready/busy pin 1173 * @select_chip: platform specific chip select function 1174 * @cmd_ctrl: platform specific function for controlling 1175 * ALE/CLE/nCE. Also used to write command and address 1176 * @write_buf: platform specific function for write buffer 1177 * @read_buf: platform specific function for read buffer 1178 * @read_byte: platform specific function to read one byte from chip 1179 * @priv: private data to transport driver specific settings 1180 * 1181 * All fields are optional and depend on the hardware driver requirements 1182 */ 1183 struct platform_nand_ctrl { 1184 int (*probe)(struct platform_device *pdev); 1185 void (*remove)(struct platform_device *pdev); 1186 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1187 int (*dev_ready)(struct mtd_info *mtd); 1188 void (*select_chip)(struct mtd_info *mtd, int chip); 1189 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1190 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1191 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1192 unsigned char (*read_byte)(struct mtd_info *mtd); 1193 void *priv; 1194 }; 1195 1196 /** 1197 * struct platform_nand_data - container structure for platform-specific data 1198 * @chip: chip level chip structure 1199 * @ctrl: controller level device structure 1200 */ 1201 struct platform_nand_data { 1202 struct platform_nand_chip chip; 1203 struct platform_nand_ctrl ctrl; 1204 }; 1205 1206 /* return the supported features. */ 1207 static inline int onfi_feature(struct nand_chip *chip) 1208 { 1209 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1210 } 1211 1212 /* return the supported asynchronous timing mode. */ 1213 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1214 { 1215 if (!chip->onfi_version) 1216 return ONFI_TIMING_MODE_UNKNOWN; 1217 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1218 } 1219 1220 /* return the supported synchronous timing mode. */ 1221 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1222 { 1223 if (!chip->onfi_version) 1224 return ONFI_TIMING_MODE_UNKNOWN; 1225 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1226 } 1227 1228 int onfi_init_data_interface(struct nand_chip *chip, 1229 struct nand_data_interface *iface, 1230 enum nand_data_interface_type type, 1231 int timing_mode); 1232 1233 /* 1234 * Check if it is a SLC nand. 1235 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1236 * We do not distinguish the MLC and TLC now. 1237 */ 1238 static inline bool nand_is_slc(struct nand_chip *chip) 1239 { 1240 WARN(chip->bits_per_cell == 0, 1241 "chip->bits_per_cell is used uninitialized\n"); 1242 return chip->bits_per_cell == 1; 1243 } 1244 1245 /** 1246 * Check if the opcode's address should be sent only on the lower 8 bits 1247 * @command: opcode to check 1248 */ 1249 static inline int nand_opcode_8bits(unsigned int command) 1250 { 1251 switch (command) { 1252 case NAND_CMD_READID: 1253 case NAND_CMD_PARAM: 1254 case NAND_CMD_GET_FEATURES: 1255 case NAND_CMD_SET_FEATURES: 1256 return 1; 1257 default: 1258 break; 1259 } 1260 return 0; 1261 } 1262 1263 /* return the supported JEDEC features. */ 1264 static inline int jedec_feature(struct nand_chip *chip) 1265 { 1266 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1267 : 0; 1268 } 1269 1270 /* get timing characteristics from ONFI timing mode. */ 1271 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1272 /* get data interface from ONFI timing mode 0, used after reset. */ 1273 const struct nand_data_interface *nand_get_default_data_interface(void); 1274 1275 int nand_check_erased_ecc_chunk(void *data, int datalen, 1276 void *ecc, int ecclen, 1277 void *extraoob, int extraooblen, 1278 int threshold); 1279 1280 int nand_check_ecc_caps(struct nand_chip *chip, 1281 const struct nand_ecc_caps *caps, int oobavail); 1282 1283 int nand_match_ecc_req(struct nand_chip *chip, 1284 const struct nand_ecc_caps *caps, int oobavail); 1285 1286 int nand_maximize_ecc(struct nand_chip *chip, 1287 const struct nand_ecc_caps *caps, int oobavail); 1288 1289 /* Default write_oob implementation */ 1290 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1291 1292 /* Default write_oob syndrome implementation */ 1293 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1294 int page); 1295 1296 /* Default read_oob implementation */ 1297 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1298 1299 /* Default read_oob syndrome implementation */ 1300 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1301 int page); 1302 1303 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1304 int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, 1305 struct nand_chip *chip, int addr, 1306 u8 *subfeature_param); 1307 1308 /* Default read_page_raw implementation */ 1309 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1310 uint8_t *buf, int oob_required, int page); 1311 1312 /* Default write_page_raw implementation */ 1313 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1314 const uint8_t *buf, int oob_required, int page); 1315 1316 /* Reset and initialize a NAND device */ 1317 int nand_reset(struct nand_chip *chip, int chipnr); 1318 1319 /* Free resources held by the NAND device */ 1320 void nand_cleanup(struct nand_chip *chip); 1321 1322 /* Default extended ID decoding function */ 1323 void nand_decode_ext_id(struct nand_chip *chip); 1324 #endif /* __LINUX_MTD_RAWNAND_H */ 1325