1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/wait.h> 20 #include <linux/spinlock.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/flashchip.h> 23 #include <linux/mtd/bbm.h> 24 #include <linux/types.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Unregister the MTD device and free resources held by the NAND device */ 41 void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 void nand_wait_ready(struct mtd_info *mtd); 45 46 /* The maximum number of NAND chips in an array */ 47 #define NAND_MAX_CHIPS 8 48 49 /* 50 * Constants for hardware specific CLE/ALE/NCE function 51 * 52 * These are bits which can be or'ed to set/clear multiple 53 * bits in one go. 54 */ 55 /* Select the chip by setting nCE to low */ 56 #define NAND_NCE 0x01 57 /* Select the command latch by setting CLE to high */ 58 #define NAND_CLE 0x02 59 /* Select the address latch by setting ALE to high */ 60 #define NAND_ALE 0x04 61 62 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 63 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 64 #define NAND_CTRL_CHANGE 0x80 65 66 /* 67 * Standard NAND flash commands 68 */ 69 #define NAND_CMD_READ0 0 70 #define NAND_CMD_READ1 1 71 #define NAND_CMD_RNDOUT 5 72 #define NAND_CMD_PAGEPROG 0x10 73 #define NAND_CMD_READOOB 0x50 74 #define NAND_CMD_ERASE1 0x60 75 #define NAND_CMD_STATUS 0x70 76 #define NAND_CMD_SEQIN 0x80 77 #define NAND_CMD_RNDIN 0x85 78 #define NAND_CMD_READID 0x90 79 #define NAND_CMD_ERASE2 0xd0 80 #define NAND_CMD_PARAM 0xec 81 #define NAND_CMD_GET_FEATURES 0xee 82 #define NAND_CMD_SET_FEATURES 0xef 83 #define NAND_CMD_RESET 0xff 84 85 /* Extended commands for large page devices */ 86 #define NAND_CMD_READSTART 0x30 87 #define NAND_CMD_RNDOUTSTART 0xE0 88 #define NAND_CMD_CACHEDPROG 0x15 89 90 #define NAND_CMD_NONE -1 91 92 /* Status bits */ 93 #define NAND_STATUS_FAIL 0x01 94 #define NAND_STATUS_FAIL_N1 0x02 95 #define NAND_STATUS_TRUE_READY 0x20 96 #define NAND_STATUS_READY 0x40 97 #define NAND_STATUS_WP 0x80 98 99 #define NAND_DATA_IFACE_CHECK_ONLY -1 100 101 /* 102 * Constants for ECC_MODES 103 */ 104 typedef enum { 105 NAND_ECC_NONE, 106 NAND_ECC_SOFT, 107 NAND_ECC_HW, 108 NAND_ECC_HW_SYNDROME, 109 NAND_ECC_HW_OOB_FIRST, 110 NAND_ECC_ON_DIE, 111 } nand_ecc_modes_t; 112 113 enum nand_ecc_algo { 114 NAND_ECC_UNKNOWN, 115 NAND_ECC_HAMMING, 116 NAND_ECC_BCH, 117 }; 118 119 /* 120 * Constants for Hardware ECC 121 */ 122 /* Reset Hardware ECC for read */ 123 #define NAND_ECC_READ 0 124 /* Reset Hardware ECC for write */ 125 #define NAND_ECC_WRITE 1 126 /* Enable Hardware ECC before syndrome is read back from flash */ 127 #define NAND_ECC_READSYN 2 128 129 /* 130 * Enable generic NAND 'page erased' check. This check is only done when 131 * ecc.correct() returns -EBADMSG. 132 * Set this flag if your implementation does not fix bitflips in erased 133 * pages and you want to rely on the default implementation. 134 */ 135 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 136 #define NAND_ECC_MAXIMIZE BIT(1) 137 138 /* Bit mask for flags passed to do_nand_read_ecc */ 139 #define NAND_GET_DEVICE 0x80 140 141 142 /* 143 * Option constants for bizarre disfunctionality and real 144 * features. 145 */ 146 /* Buswidth is 16 bit */ 147 #define NAND_BUSWIDTH_16 0x00000002 148 /* Chip has cache program function */ 149 #define NAND_CACHEPRG 0x00000008 150 /* 151 * Chip requires ready check on read (for auto-incremented sequential read). 152 * True only for small page devices; large page devices do not support 153 * autoincrement. 154 */ 155 #define NAND_NEED_READRDY 0x00000100 156 157 /* Chip does not allow subpage writes */ 158 #define NAND_NO_SUBPAGE_WRITE 0x00000200 159 160 /* Device is one of 'new' xD cards that expose fake nand command set */ 161 #define NAND_BROKEN_XD 0x00000400 162 163 /* Device behaves just like nand, but is readonly */ 164 #define NAND_ROM 0x00000800 165 166 /* Device supports subpage reads */ 167 #define NAND_SUBPAGE_READ 0x00001000 168 169 /* 170 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 171 * patterns. 172 */ 173 #define NAND_NEED_SCRAMBLING 0x00002000 174 175 /* Device needs 3rd row address cycle */ 176 #define NAND_ROW_ADDR_3 0x00004000 177 178 /* Options valid for Samsung large page devices */ 179 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 180 181 /* Macros to identify the above */ 182 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 183 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 184 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 185 186 /* Non chip related options */ 187 /* This option skips the bbt scan during initialization. */ 188 #define NAND_SKIP_BBTSCAN 0x00010000 189 /* Chip may not exist, so silence any errors in scan */ 190 #define NAND_SCAN_SILENT_NODEV 0x00040000 191 /* 192 * Autodetect nand buswidth with readid/onfi. 193 * This suppose the driver will configure the hardware in 8 bits mode 194 * when calling nand_scan_ident, and update its configuration 195 * before calling nand_scan_tail. 196 */ 197 #define NAND_BUSWIDTH_AUTO 0x00080000 198 /* 199 * This option could be defined by controller drivers to protect against 200 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 201 */ 202 #define NAND_USE_BOUNCE_BUFFER 0x00100000 203 204 /* 205 * In case your controller is implementing ->cmd_ctrl() and is relying on the 206 * default ->cmdfunc() implementation, you may want to let the core handle the 207 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is 208 * requested. 209 * If your controller already takes care of this delay, you don't need to set 210 * this flag. 211 */ 212 #define NAND_WAIT_TCCS 0x00200000 213 214 /* Options set by nand scan */ 215 /* Nand scan has allocated controller struct */ 216 #define NAND_CONTROLLER_ALLOC 0x80000000 217 218 /* Cell info constants */ 219 #define NAND_CI_CHIPNR_MSK 0x03 220 #define NAND_CI_CELLTYPE_MSK 0x0C 221 #define NAND_CI_CELLTYPE_SHIFT 2 222 223 /* Keep gcc happy */ 224 struct nand_chip; 225 226 /* ONFI features */ 227 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 228 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 229 230 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 231 #define ONFI_TIMING_MODE_0 (1 << 0) 232 #define ONFI_TIMING_MODE_1 (1 << 1) 233 #define ONFI_TIMING_MODE_2 (1 << 2) 234 #define ONFI_TIMING_MODE_3 (1 << 3) 235 #define ONFI_TIMING_MODE_4 (1 << 4) 236 #define ONFI_TIMING_MODE_5 (1 << 5) 237 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 238 239 /* ONFI feature number/address */ 240 #define ONFI_FEATURE_NUMBER 256 241 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 242 243 /* Vendor-specific feature address (Micron) */ 244 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 245 #define ONFI_FEATURE_ON_DIE_ECC 0x90 246 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) 247 248 /* ONFI subfeature parameters length */ 249 #define ONFI_SUBFEATURE_PARAM_LEN 4 250 251 /* ONFI optional commands SET/GET FEATURES supported? */ 252 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 253 254 struct nand_onfi_params { 255 /* rev info and features block */ 256 /* 'O' 'N' 'F' 'I' */ 257 u8 sig[4]; 258 __le16 revision; 259 __le16 features; 260 __le16 opt_cmd; 261 u8 reserved0[2]; 262 __le16 ext_param_page_length; /* since ONFI 2.1 */ 263 u8 num_of_param_pages; /* since ONFI 2.1 */ 264 u8 reserved1[17]; 265 266 /* manufacturer information block */ 267 char manufacturer[12]; 268 char model[20]; 269 u8 jedec_id; 270 __le16 date_code; 271 u8 reserved2[13]; 272 273 /* memory organization block */ 274 __le32 byte_per_page; 275 __le16 spare_bytes_per_page; 276 __le32 data_bytes_per_ppage; 277 __le16 spare_bytes_per_ppage; 278 __le32 pages_per_block; 279 __le32 blocks_per_lun; 280 u8 lun_count; 281 u8 addr_cycles; 282 u8 bits_per_cell; 283 __le16 bb_per_lun; 284 __le16 block_endurance; 285 u8 guaranteed_good_blocks; 286 __le16 guaranteed_block_endurance; 287 u8 programs_per_page; 288 u8 ppage_attr; 289 u8 ecc_bits; 290 u8 interleaved_bits; 291 u8 interleaved_ops; 292 u8 reserved3[13]; 293 294 /* electrical parameter block */ 295 u8 io_pin_capacitance_max; 296 __le16 async_timing_mode; 297 __le16 program_cache_timing_mode; 298 __le16 t_prog; 299 __le16 t_bers; 300 __le16 t_r; 301 __le16 t_ccs; 302 __le16 src_sync_timing_mode; 303 u8 src_ssync_features; 304 __le16 clk_pin_capacitance_typ; 305 __le16 io_pin_capacitance_typ; 306 __le16 input_pin_capacitance_typ; 307 u8 input_pin_capacitance_max; 308 u8 driver_strength_support; 309 __le16 t_int_r; 310 __le16 t_adl; 311 u8 reserved4[8]; 312 313 /* vendor */ 314 __le16 vendor_revision; 315 u8 vendor[88]; 316 317 __le16 crc; 318 } __packed; 319 320 #define ONFI_CRC_BASE 0x4F4E 321 322 /* Extended ECC information Block Definition (since ONFI 2.1) */ 323 struct onfi_ext_ecc_info { 324 u8 ecc_bits; 325 u8 codeword_size; 326 __le16 bb_per_lun; 327 __le16 block_endurance; 328 u8 reserved[2]; 329 } __packed; 330 331 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 332 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 333 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 334 struct onfi_ext_section { 335 u8 type; 336 u8 length; 337 } __packed; 338 339 #define ONFI_EXT_SECTION_MAX 8 340 341 /* Extended Parameter Page Definition (since ONFI 2.1) */ 342 struct onfi_ext_param_page { 343 __le16 crc; 344 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 345 u8 reserved0[10]; 346 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 347 348 /* 349 * The actual size of the Extended Parameter Page is in 350 * @ext_param_page_length of nand_onfi_params{}. 351 * The following are the variable length sections. 352 * So we do not add any fields below. Please see the ONFI spec. 353 */ 354 } __packed; 355 356 struct jedec_ecc_info { 357 u8 ecc_bits; 358 u8 codeword_size; 359 __le16 bb_per_lun; 360 __le16 block_endurance; 361 u8 reserved[2]; 362 } __packed; 363 364 /* JEDEC features */ 365 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 366 367 struct nand_jedec_params { 368 /* rev info and features block */ 369 /* 'J' 'E' 'S' 'D' */ 370 u8 sig[4]; 371 __le16 revision; 372 __le16 features; 373 u8 opt_cmd[3]; 374 __le16 sec_cmd; 375 u8 num_of_param_pages; 376 u8 reserved0[18]; 377 378 /* manufacturer information block */ 379 char manufacturer[12]; 380 char model[20]; 381 u8 jedec_id[6]; 382 u8 reserved1[10]; 383 384 /* memory organization block */ 385 __le32 byte_per_page; 386 __le16 spare_bytes_per_page; 387 u8 reserved2[6]; 388 __le32 pages_per_block; 389 __le32 blocks_per_lun; 390 u8 lun_count; 391 u8 addr_cycles; 392 u8 bits_per_cell; 393 u8 programs_per_page; 394 u8 multi_plane_addr; 395 u8 multi_plane_op_attr; 396 u8 reserved3[38]; 397 398 /* electrical parameter block */ 399 __le16 async_sdr_speed_grade; 400 __le16 toggle_ddr_speed_grade; 401 __le16 sync_ddr_speed_grade; 402 u8 async_sdr_features; 403 u8 toggle_ddr_features; 404 u8 sync_ddr_features; 405 __le16 t_prog; 406 __le16 t_bers; 407 __le16 t_r; 408 __le16 t_r_multi_plane; 409 __le16 t_ccs; 410 __le16 io_pin_capacitance_typ; 411 __le16 input_pin_capacitance_typ; 412 __le16 clk_pin_capacitance_typ; 413 u8 driver_strength_support; 414 __le16 t_adl; 415 u8 reserved4[36]; 416 417 /* ECC and endurance block */ 418 u8 guaranteed_good_blocks; 419 __le16 guaranteed_block_endurance; 420 struct jedec_ecc_info ecc_info[4]; 421 u8 reserved5[29]; 422 423 /* reserved */ 424 u8 reserved6[148]; 425 426 /* vendor */ 427 __le16 vendor_rev_num; 428 u8 reserved7[88]; 429 430 /* CRC for Parameter Page */ 431 __le16 crc; 432 } __packed; 433 434 /** 435 * struct onfi_params - ONFI specific parameters that will be reused 436 * @version: ONFI version (BCD encoded), 0 if ONFI is not supported 437 * @tPROG: Page program time 438 * @tBERS: Block erase time 439 * @tR: Page read time 440 * @tCCS: Change column setup time 441 * @async_timing_mode: Supported asynchronous timing mode 442 * @vendor_revision: Vendor specific revision number 443 * @vendor: Vendor specific data 444 */ 445 struct onfi_params { 446 int version; 447 u16 tPROG; 448 u16 tBERS; 449 u16 tR; 450 u16 tCCS; 451 u16 async_timing_mode; 452 u16 vendor_revision; 453 u8 vendor[88]; 454 }; 455 456 /** 457 * struct nand_parameters - NAND generic parameters from the parameter page 458 * @model: Model name 459 * @supports_set_get_features: The NAND chip supports setting/getting features 460 * @set_feature_list: Bitmap of features that can be set 461 * @get_feature_list: Bitmap of features that can be get 462 * @onfi: ONFI specific parameters 463 */ 464 struct nand_parameters { 465 /* Generic parameters */ 466 char model[100]; 467 bool supports_set_get_features; 468 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 469 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 470 471 /* ONFI parameters */ 472 struct onfi_params onfi; 473 }; 474 475 /* The maximum expected count of bytes in the NAND ID sequence */ 476 #define NAND_MAX_ID_LEN 8 477 478 /** 479 * struct nand_id - NAND id structure 480 * @data: buffer containing the id bytes. 481 * @len: ID length. 482 */ 483 struct nand_id { 484 u8 data[NAND_MAX_ID_LEN]; 485 int len; 486 }; 487 488 /** 489 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 490 * @lock: protection lock 491 * @active: the mtd device which holds the controller currently 492 * @wq: wait queue to sleep on if a NAND operation is in 493 * progress used instead of the per chip wait queue 494 * when a hw controller is available. 495 */ 496 struct nand_hw_control { 497 spinlock_t lock; 498 struct nand_chip *active; 499 wait_queue_head_t wq; 500 }; 501 502 static inline void nand_hw_control_init(struct nand_hw_control *nfc) 503 { 504 nfc->active = NULL; 505 spin_lock_init(&nfc->lock); 506 init_waitqueue_head(&nfc->wq); 507 } 508 509 /** 510 * struct nand_ecc_step_info - ECC step information of ECC engine 511 * @stepsize: data bytes per ECC step 512 * @strengths: array of supported strengths 513 * @nstrengths: number of supported strengths 514 */ 515 struct nand_ecc_step_info { 516 int stepsize; 517 const int *strengths; 518 int nstrengths; 519 }; 520 521 /** 522 * struct nand_ecc_caps - capability of ECC engine 523 * @stepinfos: array of ECC step information 524 * @nstepinfos: number of ECC step information 525 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 526 */ 527 struct nand_ecc_caps { 528 const struct nand_ecc_step_info *stepinfos; 529 int nstepinfos; 530 int (*calc_ecc_bytes)(int step_size, int strength); 531 }; 532 533 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 534 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 535 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 536 static const struct nand_ecc_step_info __name##_stepinfo = { \ 537 .stepsize = __step, \ 538 .strengths = __name##_strengths, \ 539 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 540 }; \ 541 static const struct nand_ecc_caps __name = { \ 542 .stepinfos = &__name##_stepinfo, \ 543 .nstepinfos = 1, \ 544 .calc_ecc_bytes = __calc, \ 545 } 546 547 /** 548 * struct nand_ecc_ctrl - Control structure for ECC 549 * @mode: ECC mode 550 * @algo: ECC algorithm 551 * @steps: number of ECC steps per page 552 * @size: data bytes per ECC step 553 * @bytes: ECC bytes per step 554 * @strength: max number of correctible bits per ECC step 555 * @total: total number of ECC bytes per page 556 * @prepad: padding information for syndrome based ECC generators 557 * @postpad: padding information for syndrome based ECC generators 558 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 559 * @priv: pointer to private ECC control data 560 * @calc_buf: buffer for calculated ECC, size is oobsize. 561 * @code_buf: buffer for ECC read from flash, size is oobsize. 562 * @hwctl: function to control hardware ECC generator. Must only 563 * be provided if an hardware ECC is available 564 * @calculate: function for ECC calculation or readback from ECC hardware 565 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 566 * Should return a positive number representing the number of 567 * corrected bitflips, -EBADMSG if the number of bitflips exceed 568 * ECC strength, or any other error code if the error is not 569 * directly related to correction. 570 * If -EBADMSG is returned the input buffers should be left 571 * untouched. 572 * @read_page_raw: function to read a raw page without ECC. This function 573 * should hide the specific layout used by the ECC 574 * controller and always return contiguous in-band and 575 * out-of-band data even if they're not stored 576 * contiguously on the NAND chip (e.g. 577 * NAND_ECC_HW_SYNDROME interleaves in-band and 578 * out-of-band data). 579 * @write_page_raw: function to write a raw page without ECC. This function 580 * should hide the specific layout used by the ECC 581 * controller and consider the passed data as contiguous 582 * in-band and out-of-band data. ECC controller is 583 * responsible for doing the appropriate transformations 584 * to adapt to its specific layout (e.g. 585 * NAND_ECC_HW_SYNDROME interleaves in-band and 586 * out-of-band data). 587 * @read_page: function to read a page according to the ECC generator 588 * requirements; returns maximum number of bitflips corrected in 589 * any single ECC step, -EIO hw error 590 * @read_subpage: function to read parts of the page covered by ECC; 591 * returns same as read_page() 592 * @write_subpage: function to write parts of the page covered by ECC. 593 * @write_page: function to write a page according to the ECC generator 594 * requirements. 595 * @write_oob_raw: function to write chip OOB data without ECC 596 * @read_oob_raw: function to read chip OOB data without ECC 597 * @read_oob: function to read chip OOB data 598 * @write_oob: function to write chip OOB data 599 */ 600 struct nand_ecc_ctrl { 601 nand_ecc_modes_t mode; 602 enum nand_ecc_algo algo; 603 int steps; 604 int size; 605 int bytes; 606 int total; 607 int strength; 608 int prepad; 609 int postpad; 610 unsigned int options; 611 void *priv; 612 u8 *calc_buf; 613 u8 *code_buf; 614 void (*hwctl)(struct mtd_info *mtd, int mode); 615 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 616 uint8_t *ecc_code); 617 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 618 uint8_t *calc_ecc); 619 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 620 uint8_t *buf, int oob_required, int page); 621 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 622 const uint8_t *buf, int oob_required, int page); 623 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 624 uint8_t *buf, int oob_required, int page); 625 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 626 uint32_t offs, uint32_t len, uint8_t *buf, int page); 627 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 628 uint32_t offset, uint32_t data_len, 629 const uint8_t *data_buf, int oob_required, int page); 630 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 631 const uint8_t *buf, int oob_required, int page); 632 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 633 int page); 634 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 635 int page); 636 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 637 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 638 int page); 639 }; 640 641 /** 642 * struct nand_sdr_timings - SDR NAND chip timings 643 * 644 * This struct defines the timing requirements of a SDR NAND chip. 645 * These information can be found in every NAND datasheets and the timings 646 * meaning are described in the ONFI specifications: 647 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 648 * Parameters) 649 * 650 * All these timings are expressed in picoseconds. 651 * 652 * @tBERS_max: Block erase time 653 * @tCCS_min: Change column setup time 654 * @tPROG_max: Page program time 655 * @tR_max: Page read time 656 * @tALH_min: ALE hold time 657 * @tADL_min: ALE to data loading time 658 * @tALS_min: ALE setup time 659 * @tAR_min: ALE to RE# delay 660 * @tCEA_max: CE# access time 661 * @tCEH_min: CE# high hold time 662 * @tCH_min: CE# hold time 663 * @tCHZ_max: CE# high to output hi-Z 664 * @tCLH_min: CLE hold time 665 * @tCLR_min: CLE to RE# delay 666 * @tCLS_min: CLE setup time 667 * @tCOH_min: CE# high to output hold 668 * @tCS_min: CE# setup time 669 * @tDH_min: Data hold time 670 * @tDS_min: Data setup time 671 * @tFEAT_max: Busy time for Set Features and Get Features 672 * @tIR_min: Output hi-Z to RE# low 673 * @tITC_max: Interface and Timing Mode Change time 674 * @tRC_min: RE# cycle time 675 * @tREA_max: RE# access time 676 * @tREH_min: RE# high hold time 677 * @tRHOH_min: RE# high to output hold 678 * @tRHW_min: RE# high to WE# low 679 * @tRHZ_max: RE# high to output hi-Z 680 * @tRLOH_min: RE# low to output hold 681 * @tRP_min: RE# pulse width 682 * @tRR_min: Ready to RE# low (data only) 683 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 684 * rising edge of R/B#. 685 * @tWB_max: WE# high to SR[6] low 686 * @tWC_min: WE# cycle time 687 * @tWH_min: WE# high hold time 688 * @tWHR_min: WE# high to RE# low 689 * @tWP_min: WE# pulse width 690 * @tWW_min: WP# transition to WE# low 691 */ 692 struct nand_sdr_timings { 693 u64 tBERS_max; 694 u32 tCCS_min; 695 u64 tPROG_max; 696 u64 tR_max; 697 u32 tALH_min; 698 u32 tADL_min; 699 u32 tALS_min; 700 u32 tAR_min; 701 u32 tCEA_max; 702 u32 tCEH_min; 703 u32 tCH_min; 704 u32 tCHZ_max; 705 u32 tCLH_min; 706 u32 tCLR_min; 707 u32 tCLS_min; 708 u32 tCOH_min; 709 u32 tCS_min; 710 u32 tDH_min; 711 u32 tDS_min; 712 u32 tFEAT_max; 713 u32 tIR_min; 714 u32 tITC_max; 715 u32 tRC_min; 716 u32 tREA_max; 717 u32 tREH_min; 718 u32 tRHOH_min; 719 u32 tRHW_min; 720 u32 tRHZ_max; 721 u32 tRLOH_min; 722 u32 tRP_min; 723 u32 tRR_min; 724 u64 tRST_max; 725 u32 tWB_max; 726 u32 tWC_min; 727 u32 tWH_min; 728 u32 tWHR_min; 729 u32 tWP_min; 730 u32 tWW_min; 731 }; 732 733 /** 734 * enum nand_data_interface_type - NAND interface timing type 735 * @NAND_SDR_IFACE: Single Data Rate interface 736 */ 737 enum nand_data_interface_type { 738 NAND_SDR_IFACE, 739 }; 740 741 /** 742 * struct nand_data_interface - NAND interface timing 743 * @type: type of the timing 744 * @timings: The timing, type according to @type 745 */ 746 struct nand_data_interface { 747 enum nand_data_interface_type type; 748 union { 749 struct nand_sdr_timings sdr; 750 } timings; 751 }; 752 753 /** 754 * nand_get_sdr_timings - get SDR timing from data interface 755 * @conf: The data interface 756 */ 757 static inline const struct nand_sdr_timings * 758 nand_get_sdr_timings(const struct nand_data_interface *conf) 759 { 760 if (conf->type != NAND_SDR_IFACE) 761 return ERR_PTR(-EINVAL); 762 763 return &conf->timings.sdr; 764 } 765 766 /** 767 * struct nand_manufacturer_ops - NAND Manufacturer operations 768 * @detect: detect the NAND memory organization and capabilities 769 * @init: initialize all vendor specific fields (like the ->read_retry() 770 * implementation) if any. 771 * @cleanup: the ->init() function may have allocated resources, ->cleanup() 772 * is here to let vendor specific code release those resources. 773 */ 774 struct nand_manufacturer_ops { 775 void (*detect)(struct nand_chip *chip); 776 int (*init)(struct nand_chip *chip); 777 void (*cleanup)(struct nand_chip *chip); 778 }; 779 780 /** 781 * struct nand_op_cmd_instr - Definition of a command instruction 782 * @opcode: the command to issue in one cycle 783 */ 784 struct nand_op_cmd_instr { 785 u8 opcode; 786 }; 787 788 /** 789 * struct nand_op_addr_instr - Definition of an address instruction 790 * @naddrs: length of the @addrs array 791 * @addrs: array containing the address cycles to issue 792 */ 793 struct nand_op_addr_instr { 794 unsigned int naddrs; 795 const u8 *addrs; 796 }; 797 798 /** 799 * struct nand_op_data_instr - Definition of a data instruction 800 * @len: number of data bytes to move 801 * @in: buffer to fill when reading from the NAND chip 802 * @out: buffer to read from when writing to the NAND chip 803 * @force_8bit: force 8-bit access 804 * 805 * Please note that "in" and "out" are inverted from the ONFI specification 806 * and are from the controller perspective, so a "in" is a read from the NAND 807 * chip while a "out" is a write to the NAND chip. 808 */ 809 struct nand_op_data_instr { 810 unsigned int len; 811 union { 812 void *in; 813 const void *out; 814 } buf; 815 bool force_8bit; 816 }; 817 818 /** 819 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 820 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 821 */ 822 struct nand_op_waitrdy_instr { 823 unsigned int timeout_ms; 824 }; 825 826 /** 827 * enum nand_op_instr_type - Definition of all instruction types 828 * @NAND_OP_CMD_INSTR: command instruction 829 * @NAND_OP_ADDR_INSTR: address instruction 830 * @NAND_OP_DATA_IN_INSTR: data in instruction 831 * @NAND_OP_DATA_OUT_INSTR: data out instruction 832 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 833 */ 834 enum nand_op_instr_type { 835 NAND_OP_CMD_INSTR, 836 NAND_OP_ADDR_INSTR, 837 NAND_OP_DATA_IN_INSTR, 838 NAND_OP_DATA_OUT_INSTR, 839 NAND_OP_WAITRDY_INSTR, 840 }; 841 842 /** 843 * struct nand_op_instr - Instruction object 844 * @type: the instruction type 845 * @cmd/@addr/@data/@waitrdy: extra data associated to the instruction. 846 * You'll have to use the appropriate element 847 * depending on @type 848 * @delay_ns: delay the controller should apply after the instruction has been 849 * issued on the bus. Most modern controllers have internal timings 850 * control logic, and in this case, the controller driver can ignore 851 * this field. 852 */ 853 struct nand_op_instr { 854 enum nand_op_instr_type type; 855 union { 856 struct nand_op_cmd_instr cmd; 857 struct nand_op_addr_instr addr; 858 struct nand_op_data_instr data; 859 struct nand_op_waitrdy_instr waitrdy; 860 } ctx; 861 unsigned int delay_ns; 862 }; 863 864 /* 865 * Special handling must be done for the WAITRDY timeout parameter as it usually 866 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 867 * tBERS (during an erase) which all of them are u64 values that cannot be 868 * divided by usual kernel macros and must be handled with the special 869 * DIV_ROUND_UP_ULL() macro. 870 */ 871 #define __DIVIDE(dividend, divisor) ({ \ 872 sizeof(dividend) == sizeof(u32) ? \ 873 DIV_ROUND_UP(dividend, divisor) : \ 874 DIV_ROUND_UP_ULL(dividend, divisor); \ 875 }) 876 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 877 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 878 879 #define NAND_OP_CMD(id, ns) \ 880 { \ 881 .type = NAND_OP_CMD_INSTR, \ 882 .ctx.cmd.opcode = id, \ 883 .delay_ns = ns, \ 884 } 885 886 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 887 { \ 888 .type = NAND_OP_ADDR_INSTR, \ 889 .ctx.addr = { \ 890 .naddrs = ncycles, \ 891 .addrs = cycles, \ 892 }, \ 893 .delay_ns = ns, \ 894 } 895 896 #define NAND_OP_DATA_IN(l, b, ns) \ 897 { \ 898 .type = NAND_OP_DATA_IN_INSTR, \ 899 .ctx.data = { \ 900 .len = l, \ 901 .buf.in = b, \ 902 .force_8bit = false, \ 903 }, \ 904 .delay_ns = ns, \ 905 } 906 907 #define NAND_OP_DATA_OUT(l, b, ns) \ 908 { \ 909 .type = NAND_OP_DATA_OUT_INSTR, \ 910 .ctx.data = { \ 911 .len = l, \ 912 .buf.out = b, \ 913 .force_8bit = false, \ 914 }, \ 915 .delay_ns = ns, \ 916 } 917 918 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 919 { \ 920 .type = NAND_OP_DATA_IN_INSTR, \ 921 .ctx.data = { \ 922 .len = l, \ 923 .buf.in = b, \ 924 .force_8bit = true, \ 925 }, \ 926 .delay_ns = ns, \ 927 } 928 929 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 930 { \ 931 .type = NAND_OP_DATA_OUT_INSTR, \ 932 .ctx.data = { \ 933 .len = l, \ 934 .buf.out = b, \ 935 .force_8bit = true, \ 936 }, \ 937 .delay_ns = ns, \ 938 } 939 940 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 941 { \ 942 .type = NAND_OP_WAITRDY_INSTR, \ 943 .ctx.waitrdy.timeout_ms = tout_ms, \ 944 .delay_ns = ns, \ 945 } 946 947 /** 948 * struct nand_subop - a sub operation 949 * @instrs: array of instructions 950 * @ninstrs: length of the @instrs array 951 * @first_instr_start_off: offset to start from for the first instruction 952 * of the sub-operation 953 * @last_instr_end_off: offset to end at (excluded) for the last instruction 954 * of the sub-operation 955 * 956 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 957 * address instructions. 958 * 959 * When an operation cannot be handled as is by the NAND controller, it will 960 * be split by the parser into sub-operations which will be passed to the 961 * controller driver. 962 */ 963 struct nand_subop { 964 const struct nand_op_instr *instrs; 965 unsigned int ninstrs; 966 unsigned int first_instr_start_off; 967 unsigned int last_instr_end_off; 968 }; 969 970 int nand_subop_get_addr_start_off(const struct nand_subop *subop, 971 unsigned int op_id); 972 int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 973 unsigned int op_id); 974 int nand_subop_get_data_start_off(const struct nand_subop *subop, 975 unsigned int op_id); 976 int nand_subop_get_data_len(const struct nand_subop *subop, 977 unsigned int op_id); 978 979 /** 980 * struct nand_op_parser_addr_constraints - Constraints for address instructions 981 * @maxcycles: maximum number of address cycles the controller can issue in a 982 * single step 983 */ 984 struct nand_op_parser_addr_constraints { 985 unsigned int maxcycles; 986 }; 987 988 /** 989 * struct nand_op_parser_data_constraints - Constraints for data instructions 990 * @maxlen: maximum data length that the controller can handle in a single step 991 */ 992 struct nand_op_parser_data_constraints { 993 unsigned int maxlen; 994 }; 995 996 /** 997 * struct nand_op_parser_pattern_elem - One element of a pattern 998 * @type: the instructuction type 999 * @optional: whether this element of the pattern is optional or mandatory 1000 * @addr/@data: address or data constraint (number of cycles or data length) 1001 */ 1002 struct nand_op_parser_pattern_elem { 1003 enum nand_op_instr_type type; 1004 bool optional; 1005 union { 1006 struct nand_op_parser_addr_constraints addr; 1007 struct nand_op_parser_data_constraints data; 1008 } ctx; 1009 }; 1010 1011 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 1012 { \ 1013 .type = NAND_OP_CMD_INSTR, \ 1014 .optional = _opt, \ 1015 } 1016 1017 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 1018 { \ 1019 .type = NAND_OP_ADDR_INSTR, \ 1020 .optional = _opt, \ 1021 .ctx.addr.maxcycles = _maxcycles, \ 1022 } 1023 1024 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 1025 { \ 1026 .type = NAND_OP_DATA_IN_INSTR, \ 1027 .optional = _opt, \ 1028 .ctx.data.maxlen = _maxlen, \ 1029 } 1030 1031 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 1032 { \ 1033 .type = NAND_OP_DATA_OUT_INSTR, \ 1034 .optional = _opt, \ 1035 .ctx.data.maxlen = _maxlen, \ 1036 } 1037 1038 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 1039 { \ 1040 .type = NAND_OP_WAITRDY_INSTR, \ 1041 .optional = _opt, \ 1042 } 1043 1044 /** 1045 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 1046 * @elems: array of pattern elements 1047 * @nelems: number of pattern elements in @elems array 1048 * @exec: the function that will issue a sub-operation 1049 * 1050 * A pattern is a list of elements, each element reprensenting one instruction 1051 * with its constraints. The pattern itself is used by the core to match NAND 1052 * chip operation with NAND controller operations. 1053 * Once a match between a NAND controller operation pattern and a NAND chip 1054 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 1055 * hook is called so that the controller driver can issue the operation on the 1056 * bus. 1057 * 1058 * Controller drivers should declare as many patterns as they support and pass 1059 * this list of patterns (created with the help of the following macro) to 1060 * the nand_op_parser_exec_op() helper. 1061 */ 1062 struct nand_op_parser_pattern { 1063 const struct nand_op_parser_pattern_elem *elems; 1064 unsigned int nelems; 1065 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 1066 }; 1067 1068 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 1069 { \ 1070 .exec = _exec, \ 1071 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 1072 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 1073 sizeof(struct nand_op_parser_pattern_elem), \ 1074 } 1075 1076 /** 1077 * struct nand_op_parser - NAND controller operation parser descriptor 1078 * @patterns: array of supported patterns 1079 * @npatterns: length of the @patterns array 1080 * 1081 * The parser descriptor is just an array of supported patterns which will be 1082 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 1083 * NAND operation (or tries to determine if a specific operation is supported). 1084 * 1085 * It is worth mentioning that patterns will be tested in their declaration 1086 * order, and the first match will be taken, so it's important to order patterns 1087 * appropriately so that simple/inefficient patterns are placed at the end of 1088 * the list. Usually, this is where you put single instruction patterns. 1089 */ 1090 struct nand_op_parser { 1091 const struct nand_op_parser_pattern *patterns; 1092 unsigned int npatterns; 1093 }; 1094 1095 #define NAND_OP_PARSER(...) \ 1096 { \ 1097 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 1098 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 1099 sizeof(struct nand_op_parser_pattern), \ 1100 } 1101 1102 /** 1103 * struct nand_operation - NAND operation descriptor 1104 * @instrs: array of instructions to execute 1105 * @ninstrs: length of the @instrs array 1106 * 1107 * The actual operation structure that will be passed to chip->exec_op(). 1108 */ 1109 struct nand_operation { 1110 const struct nand_op_instr *instrs; 1111 unsigned int ninstrs; 1112 }; 1113 1114 #define NAND_OPERATION(_instrs) \ 1115 { \ 1116 .instrs = _instrs, \ 1117 .ninstrs = ARRAY_SIZE(_instrs), \ 1118 } 1119 1120 int nand_op_parser_exec_op(struct nand_chip *chip, 1121 const struct nand_op_parser *parser, 1122 const struct nand_operation *op, bool check_only); 1123 1124 /** 1125 * struct nand_chip - NAND Private Flash Chip Data 1126 * @mtd: MTD device registered to the MTD framework 1127 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 1128 * flash device 1129 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 1130 * flash device. 1131 * @read_byte: [REPLACEABLE] read one byte from the chip 1132 * @read_word: [REPLACEABLE] read one word from the chip 1133 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 1134 * low 8 I/O lines 1135 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 1136 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 1137 * @select_chip: [REPLACEABLE] select chip nr 1138 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 1139 * @block_markbad: [REPLACEABLE] mark a block bad 1140 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 1141 * ALE/CLE/nCE. Also used to write command and address 1142 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 1143 * device ready/busy line. If set to NULL no access to 1144 * ready/busy is available and the ready/busy information 1145 * is read from the chip status register. 1146 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 1147 * commands to the chip. 1148 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 1149 * ready. 1150 * @exec_op: controller specific method to execute NAND operations. 1151 * This method replaces ->cmdfunc(), 1152 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and 1153 * ->waifunc(). 1154 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 1155 * setting the read-retry mode. Mostly needed for MLC NAND. 1156 * @ecc: [BOARDSPECIFIC] ECC control structure 1157 * @buf_align: minimum buffer alignment required by a platform 1158 * @hwcontrol: platform-specific hardware control structure 1159 * @erase: [REPLACEABLE] erase function 1160 * @scan_bbt: [REPLACEABLE] function to scan bad block table 1161 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 1162 * data from array to read regs (tR). 1163 * @state: [INTERN] the current state of the NAND device 1164 * @oob_poi: "poison value buffer," used for laying out OOB data 1165 * before writing 1166 * @page_shift: [INTERN] number of address bits in a page (column 1167 * address bits). 1168 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 1169 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 1170 * @chip_shift: [INTERN] number of address bits in one chip 1171 * @options: [BOARDSPECIFIC] various chip options. They can partly 1172 * be set to inform nand_scan about special functionality. 1173 * See the defines for further explanation. 1174 * @bbt_options: [INTERN] bad block specific options. All options used 1175 * here must come from bbm.h. By default, these options 1176 * will be copied to the appropriate nand_bbt_descr's. 1177 * @badblockpos: [INTERN] position of the bad block marker in the oob 1178 * area. 1179 * @badblockbits: [INTERN] minimum number of set bits in a good block's 1180 * bad block marker position; i.e., BBM == 11110111b is 1181 * not bad when badblockbits == 7 1182 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 1183 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 1184 * Minimum amount of bit errors per @ecc_step_ds guaranteed 1185 * to be correctable. If unknown, set to zero. 1186 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 1187 * also from the datasheet. It is the recommended ECC step 1188 * size, if known; if unknown, set to zero. 1189 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1190 * set to the actually used ONFI mode if the chip is 1191 * ONFI compliant or deduced from the datasheet if 1192 * the NAND chip is not ONFI compliant. 1193 * @numchips: [INTERN] number of physical chips 1194 * @chipsize: [INTERN] the size of one chip for multichip arrays 1195 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1196 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1197 * @pagebuf: [INTERN] holds the pagenumber which is currently in 1198 * data_buf. 1199 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 1200 * currently in data_buf. 1201 * @subpagesize: [INTERN] holds the subpagesize 1202 * @id: [INTERN] holds NAND ID 1203 * @parameters: [INTERN] holds generic parameters under an easily 1204 * readable form. 1205 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 1206 * this nand device will encounter their life times. 1207 * @blocks_per_die: [INTERN] The number of PEBs in a die 1208 * @data_interface: [INTERN] NAND interface timing information 1209 * @read_retries: [INTERN] the number of read retry modes supported 1210 * @set_features: [REPLACEABLE] set the NAND chip features 1211 * @get_features: [REPLACEABLE] get the NAND chip features 1212 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 1213 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 1214 * means the configuration should not be applied but 1215 * only checked. 1216 * @bbt: [INTERN] bad block table pointer 1217 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1218 * lookup. 1219 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1220 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1221 * bad block scan. 1222 * @controller: [REPLACEABLE] a pointer to a hardware controller 1223 * structure which is shared among multiple independent 1224 * devices. 1225 * @priv: [OPTIONAL] pointer to private chip data 1226 * @manufacturer: [INTERN] Contains manufacturer information 1227 */ 1228 1229 struct nand_chip { 1230 struct mtd_info mtd; 1231 void __iomem *IO_ADDR_R; 1232 void __iomem *IO_ADDR_W; 1233 1234 uint8_t (*read_byte)(struct mtd_info *mtd); 1235 u16 (*read_word)(struct mtd_info *mtd); 1236 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 1237 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1238 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1239 void (*select_chip)(struct mtd_info *mtd, int chip); 1240 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 1241 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 1242 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1243 int (*dev_ready)(struct mtd_info *mtd); 1244 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 1245 int page_addr); 1246 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 1247 int (*exec_op)(struct nand_chip *chip, 1248 const struct nand_operation *op, 1249 bool check_only); 1250 int (*erase)(struct mtd_info *mtd, int page); 1251 int (*scan_bbt)(struct mtd_info *mtd); 1252 int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip, 1253 int feature_addr, uint8_t *subfeature_para); 1254 int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip, 1255 int feature_addr, uint8_t *subfeature_para); 1256 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 1257 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 1258 const struct nand_data_interface *conf); 1259 1260 int chip_delay; 1261 unsigned int options; 1262 unsigned int bbt_options; 1263 1264 int page_shift; 1265 int phys_erase_shift; 1266 int bbt_erase_shift; 1267 int chip_shift; 1268 int numchips; 1269 uint64_t chipsize; 1270 int pagemask; 1271 u8 *data_buf; 1272 int pagebuf; 1273 unsigned int pagebuf_bitflips; 1274 int subpagesize; 1275 uint8_t bits_per_cell; 1276 uint16_t ecc_strength_ds; 1277 uint16_t ecc_step_ds; 1278 int onfi_timing_mode_default; 1279 int badblockpos; 1280 int badblockbits; 1281 1282 struct nand_id id; 1283 struct nand_parameters parameters; 1284 u16 max_bb_per_die; 1285 u32 blocks_per_die; 1286 1287 struct nand_data_interface data_interface; 1288 1289 int read_retries; 1290 1291 flstate_t state; 1292 1293 uint8_t *oob_poi; 1294 struct nand_hw_control *controller; 1295 1296 struct nand_ecc_ctrl ecc; 1297 unsigned long buf_align; 1298 struct nand_hw_control hwcontrol; 1299 1300 uint8_t *bbt; 1301 struct nand_bbt_descr *bbt_td; 1302 struct nand_bbt_descr *bbt_md; 1303 1304 struct nand_bbt_descr *badblock_pattern; 1305 1306 void *priv; 1307 1308 struct { 1309 const struct nand_manufacturer *desc; 1310 void *priv; 1311 } manufacturer; 1312 }; 1313 1314 static inline int nand_exec_op(struct nand_chip *chip, 1315 const struct nand_operation *op) 1316 { 1317 if (!chip->exec_op) 1318 return -ENOTSUPP; 1319 1320 return chip->exec_op(chip, op, false); 1321 } 1322 1323 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1324 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1325 1326 static inline void nand_set_flash_node(struct nand_chip *chip, 1327 struct device_node *np) 1328 { 1329 mtd_set_of_node(&chip->mtd, np); 1330 } 1331 1332 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1333 { 1334 return mtd_get_of_node(&chip->mtd); 1335 } 1336 1337 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1338 { 1339 return container_of(mtd, struct nand_chip, mtd); 1340 } 1341 1342 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1343 { 1344 return &chip->mtd; 1345 } 1346 1347 static inline void *nand_get_controller_data(struct nand_chip *chip) 1348 { 1349 return chip->priv; 1350 } 1351 1352 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1353 { 1354 chip->priv = priv; 1355 } 1356 1357 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1358 void *priv) 1359 { 1360 chip->manufacturer.priv = priv; 1361 } 1362 1363 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1364 { 1365 return chip->manufacturer.priv; 1366 } 1367 1368 /* 1369 * NAND Flash Manufacturer ID Codes 1370 */ 1371 #define NAND_MFR_TOSHIBA 0x98 1372 #define NAND_MFR_ESMT 0xc8 1373 #define NAND_MFR_SAMSUNG 0xec 1374 #define NAND_MFR_FUJITSU 0x04 1375 #define NAND_MFR_NATIONAL 0x8f 1376 #define NAND_MFR_RENESAS 0x07 1377 #define NAND_MFR_STMICRO 0x20 1378 #define NAND_MFR_HYNIX 0xad 1379 #define NAND_MFR_MICRON 0x2c 1380 #define NAND_MFR_AMD 0x01 1381 #define NAND_MFR_MACRONIX 0xc2 1382 #define NAND_MFR_EON 0x92 1383 #define NAND_MFR_SANDISK 0x45 1384 #define NAND_MFR_INTEL 0x89 1385 #define NAND_MFR_ATO 0x9b 1386 #define NAND_MFR_WINBOND 0xef 1387 1388 1389 /* 1390 * A helper for defining older NAND chips where the second ID byte fully 1391 * defined the chip, including the geometry (chip size, eraseblock size, page 1392 * size). All these chips have 512 bytes NAND page size. 1393 */ 1394 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1395 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1396 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1397 1398 /* 1399 * A helper for defining newer chips which report their page size and 1400 * eraseblock size via the extended ID bytes. 1401 * 1402 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1403 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1404 * device ID now only represented a particular total chip size (and voltage, 1405 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1406 * using the same device ID. 1407 */ 1408 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1409 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1410 .options = (opts) } 1411 1412 #define NAND_ECC_INFO(_strength, _step) \ 1413 { .strength_ds = (_strength), .step_ds = (_step) } 1414 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1415 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1416 1417 /** 1418 * struct nand_flash_dev - NAND Flash Device ID Structure 1419 * @name: a human-readable name of the NAND chip 1420 * @dev_id: the device ID (the second byte of the full chip ID array) 1421 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1422 * memory address as @id[0]) 1423 * @dev_id: device ID part of the full chip ID array (refers the same memory 1424 * address as @id[1]) 1425 * @id: full device ID array 1426 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1427 * well as the eraseblock size) is determined from the extended NAND 1428 * chip ID array) 1429 * @chipsize: total chip size in MiB 1430 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1431 * @options: stores various chip bit options 1432 * @id_len: The valid length of the @id. 1433 * @oobsize: OOB size 1434 * @ecc: ECC correctability and step information from the datasheet. 1435 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1436 * @ecc_strength_ds in nand_chip{}. 1437 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1438 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1439 * For example, the "4bit ECC for each 512Byte" can be set with 1440 * NAND_ECC_INFO(4, 512). 1441 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1442 * reset. Should be deduced from timings described 1443 * in the datasheet. 1444 * 1445 */ 1446 struct nand_flash_dev { 1447 char *name; 1448 union { 1449 struct { 1450 uint8_t mfr_id; 1451 uint8_t dev_id; 1452 }; 1453 uint8_t id[NAND_MAX_ID_LEN]; 1454 }; 1455 unsigned int pagesize; 1456 unsigned int chipsize; 1457 unsigned int erasesize; 1458 unsigned int options; 1459 uint16_t id_len; 1460 uint16_t oobsize; 1461 struct { 1462 uint16_t strength_ds; 1463 uint16_t step_ds; 1464 } ecc; 1465 int onfi_timing_mode_default; 1466 }; 1467 1468 /** 1469 * struct nand_manufacturer - NAND Flash Manufacturer structure 1470 * @name: Manufacturer name 1471 * @id: manufacturer ID code of device. 1472 * @ops: manufacturer operations 1473 */ 1474 struct nand_manufacturer { 1475 int id; 1476 char *name; 1477 const struct nand_manufacturer_ops *ops; 1478 }; 1479 1480 const struct nand_manufacturer *nand_get_manufacturer(u8 id); 1481 1482 static inline const char * 1483 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 1484 { 1485 return manufacturer ? manufacturer->name : "Unknown"; 1486 } 1487 1488 extern struct nand_flash_dev nand_flash_ids[]; 1489 1490 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 1491 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; 1492 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; 1493 extern const struct nand_manufacturer_ops micron_nand_manuf_ops; 1494 extern const struct nand_manufacturer_ops amd_nand_manuf_ops; 1495 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; 1496 1497 int nand_default_bbt(struct mtd_info *mtd); 1498 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1499 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1500 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1501 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1502 int allowbbt); 1503 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1504 size_t *retlen, uint8_t *buf); 1505 1506 /** 1507 * struct platform_nand_chip - chip level device structure 1508 * @nr_chips: max. number of chips to scan for 1509 * @chip_offset: chip number offset 1510 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1511 * @partitions: mtd partition list 1512 * @chip_delay: R/B delay value in us 1513 * @options: Option flags, e.g. 16bit buswidth 1514 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1515 * @part_probe_types: NULL-terminated array of probe types 1516 */ 1517 struct platform_nand_chip { 1518 int nr_chips; 1519 int chip_offset; 1520 int nr_partitions; 1521 struct mtd_partition *partitions; 1522 int chip_delay; 1523 unsigned int options; 1524 unsigned int bbt_options; 1525 const char **part_probe_types; 1526 }; 1527 1528 /* Keep gcc happy */ 1529 struct platform_device; 1530 1531 /** 1532 * struct platform_nand_ctrl - controller level device structure 1533 * @probe: platform specific function to probe/setup hardware 1534 * @remove: platform specific function to remove/teardown hardware 1535 * @hwcontrol: platform specific hardware control structure 1536 * @dev_ready: platform specific function to read ready/busy pin 1537 * @select_chip: platform specific chip select function 1538 * @cmd_ctrl: platform specific function for controlling 1539 * ALE/CLE/nCE. Also used to write command and address 1540 * @write_buf: platform specific function for write buffer 1541 * @read_buf: platform specific function for read buffer 1542 * @read_byte: platform specific function to read one byte from chip 1543 * @priv: private data to transport driver specific settings 1544 * 1545 * All fields are optional and depend on the hardware driver requirements 1546 */ 1547 struct platform_nand_ctrl { 1548 int (*probe)(struct platform_device *pdev); 1549 void (*remove)(struct platform_device *pdev); 1550 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1551 int (*dev_ready)(struct mtd_info *mtd); 1552 void (*select_chip)(struct mtd_info *mtd, int chip); 1553 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1554 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1555 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1556 unsigned char (*read_byte)(struct mtd_info *mtd); 1557 void *priv; 1558 }; 1559 1560 /** 1561 * struct platform_nand_data - container structure for platform-specific data 1562 * @chip: chip level chip structure 1563 * @ctrl: controller level device structure 1564 */ 1565 struct platform_nand_data { 1566 struct platform_nand_chip chip; 1567 struct platform_nand_ctrl ctrl; 1568 }; 1569 1570 /* return the supported asynchronous timing mode. */ 1571 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1572 { 1573 if (!chip->parameters.onfi.version) 1574 return ONFI_TIMING_MODE_UNKNOWN; 1575 1576 return chip->parameters.onfi.async_timing_mode; 1577 } 1578 1579 int onfi_fill_data_interface(struct nand_chip *chip, 1580 enum nand_data_interface_type type, 1581 int timing_mode); 1582 1583 /* 1584 * Check if it is a SLC nand. 1585 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1586 * We do not distinguish the MLC and TLC now. 1587 */ 1588 static inline bool nand_is_slc(struct nand_chip *chip) 1589 { 1590 WARN(chip->bits_per_cell == 0, 1591 "chip->bits_per_cell is used uninitialized\n"); 1592 return chip->bits_per_cell == 1; 1593 } 1594 1595 /** 1596 * Check if the opcode's address should be sent only on the lower 8 bits 1597 * @command: opcode to check 1598 */ 1599 static inline int nand_opcode_8bits(unsigned int command) 1600 { 1601 switch (command) { 1602 case NAND_CMD_READID: 1603 case NAND_CMD_PARAM: 1604 case NAND_CMD_GET_FEATURES: 1605 case NAND_CMD_SET_FEATURES: 1606 return 1; 1607 default: 1608 break; 1609 } 1610 return 0; 1611 } 1612 1613 /* get timing characteristics from ONFI timing mode. */ 1614 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1615 1616 int nand_check_erased_ecc_chunk(void *data, int datalen, 1617 void *ecc, int ecclen, 1618 void *extraoob, int extraooblen, 1619 int threshold); 1620 1621 int nand_check_ecc_caps(struct nand_chip *chip, 1622 const struct nand_ecc_caps *caps, int oobavail); 1623 1624 int nand_match_ecc_req(struct nand_chip *chip, 1625 const struct nand_ecc_caps *caps, int oobavail); 1626 1627 int nand_maximize_ecc(struct nand_chip *chip, 1628 const struct nand_ecc_caps *caps, int oobavail); 1629 1630 /* Default write_oob implementation */ 1631 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1632 1633 /* Default write_oob syndrome implementation */ 1634 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1635 int page); 1636 1637 /* Default read_oob implementation */ 1638 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1639 1640 /* Default read_oob syndrome implementation */ 1641 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1642 int page); 1643 1644 /* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */ 1645 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param); 1646 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param); 1647 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1648 int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip, 1649 int addr, u8 *subfeature_param); 1650 1651 /* Default read_page_raw implementation */ 1652 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1653 uint8_t *buf, int oob_required, int page); 1654 1655 /* Default write_page_raw implementation */ 1656 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1657 const uint8_t *buf, int oob_required, int page); 1658 1659 /* Reset and initialize a NAND device */ 1660 int nand_reset(struct nand_chip *chip, int chipnr); 1661 1662 /* NAND operation helpers */ 1663 int nand_reset_op(struct nand_chip *chip); 1664 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1665 unsigned int len); 1666 int nand_status_op(struct nand_chip *chip, u8 *status); 1667 int nand_exit_status_op(struct nand_chip *chip); 1668 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1669 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1670 unsigned int offset_in_page, void *buf, unsigned int len); 1671 int nand_change_read_column_op(struct nand_chip *chip, 1672 unsigned int offset_in_page, void *buf, 1673 unsigned int len, bool force_8bit); 1674 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1675 unsigned int offset_in_page, void *buf, unsigned int len); 1676 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1677 unsigned int offset_in_page, const void *buf, 1678 unsigned int len); 1679 int nand_prog_page_end_op(struct nand_chip *chip); 1680 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1681 unsigned int offset_in_page, const void *buf, 1682 unsigned int len); 1683 int nand_change_write_column_op(struct nand_chip *chip, 1684 unsigned int offset_in_page, const void *buf, 1685 unsigned int len, bool force_8bit); 1686 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1687 bool force_8bit); 1688 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1689 unsigned int len, bool force_8bit); 1690 1691 /* Free resources held by the NAND device */ 1692 void nand_cleanup(struct nand_chip *chip); 1693 1694 /* Default extended ID decoding function */ 1695 void nand_decode_ext_id(struct nand_chip *chip); 1696 1697 /* 1698 * External helper for controller drivers that have to implement the WAITRDY 1699 * instruction and have no physical pin to check it. 1700 */ 1701 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1702 1703 #endif /* __LINUX_MTD_RAWNAND_H */ 1704