1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/flashchip.h> 21 #include <linux/mtd/bbm.h> 22 #include <linux/mtd/jedec.h> 23 #include <linux/mtd/nand.h> 24 #include <linux/mtd/onfi.h> 25 #include <linux/mutex.h> 26 #include <linux/of.h> 27 #include <linux/types.h> 28 29 struct nand_chip; 30 31 /* The maximum number of NAND chips in an array */ 32 #define NAND_MAX_CHIPS 8 33 34 /* 35 * Constants for hardware specific CLE/ALE/NCE function 36 * 37 * These are bits which can be or'ed to set/clear multiple 38 * bits in one go. 39 */ 40 /* Select the chip by setting nCE to low */ 41 #define NAND_NCE 0x01 42 /* Select the command latch by setting CLE to high */ 43 #define NAND_CLE 0x02 44 /* Select the address latch by setting ALE to high */ 45 #define NAND_ALE 0x04 46 47 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 48 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 49 #define NAND_CTRL_CHANGE 0x80 50 51 /* 52 * Standard NAND flash commands 53 */ 54 #define NAND_CMD_READ0 0 55 #define NAND_CMD_READ1 1 56 #define NAND_CMD_RNDOUT 5 57 #define NAND_CMD_PAGEPROG 0x10 58 #define NAND_CMD_READOOB 0x50 59 #define NAND_CMD_ERASE1 0x60 60 #define NAND_CMD_STATUS 0x70 61 #define NAND_CMD_SEQIN 0x80 62 #define NAND_CMD_RNDIN 0x85 63 #define NAND_CMD_READID 0x90 64 #define NAND_CMD_ERASE2 0xd0 65 #define NAND_CMD_PARAM 0xec 66 #define NAND_CMD_GET_FEATURES 0xee 67 #define NAND_CMD_SET_FEATURES 0xef 68 #define NAND_CMD_RESET 0xff 69 70 /* Extended commands for large page devices */ 71 #define NAND_CMD_READSTART 0x30 72 #define NAND_CMD_RNDOUTSTART 0xE0 73 #define NAND_CMD_CACHEDPROG 0x15 74 75 #define NAND_CMD_NONE -1 76 77 /* Status bits */ 78 #define NAND_STATUS_FAIL 0x01 79 #define NAND_STATUS_FAIL_N1 0x02 80 #define NAND_STATUS_TRUE_READY 0x20 81 #define NAND_STATUS_READY 0x40 82 #define NAND_STATUS_WP 0x80 83 84 #define NAND_DATA_IFACE_CHECK_ONLY -1 85 86 /* 87 * Constants for ECC_MODES 88 */ 89 typedef enum { 90 NAND_ECC_NONE, 91 NAND_ECC_SOFT, 92 NAND_ECC_HW, 93 NAND_ECC_HW_SYNDROME, 94 NAND_ECC_HW_OOB_FIRST, 95 NAND_ECC_ON_DIE, 96 } nand_ecc_modes_t; 97 98 enum nand_ecc_algo { 99 NAND_ECC_UNKNOWN, 100 NAND_ECC_HAMMING, 101 NAND_ECC_BCH, 102 NAND_ECC_RS, 103 }; 104 105 /* 106 * Constants for Hardware ECC 107 */ 108 /* Reset Hardware ECC for read */ 109 #define NAND_ECC_READ 0 110 /* Reset Hardware ECC for write */ 111 #define NAND_ECC_WRITE 1 112 /* Enable Hardware ECC before syndrome is read back from flash */ 113 #define NAND_ECC_READSYN 2 114 115 /* 116 * Enable generic NAND 'page erased' check. This check is only done when 117 * ecc.correct() returns -EBADMSG. 118 * Set this flag if your implementation does not fix bitflips in erased 119 * pages and you want to rely on the default implementation. 120 */ 121 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 122 #define NAND_ECC_MAXIMIZE BIT(1) 123 124 /* 125 * When using software implementation of Hamming, we can specify which byte 126 * ordering should be used. 127 */ 128 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 129 130 /* 131 * Option constants for bizarre disfunctionality and real 132 * features. 133 */ 134 /* Buswidth is 16 bit */ 135 #define NAND_BUSWIDTH_16 0x00000002 136 /* Chip has cache program function */ 137 #define NAND_CACHEPRG 0x00000008 138 /* 139 * Chip requires ready check on read (for auto-incremented sequential read). 140 * True only for small page devices; large page devices do not support 141 * autoincrement. 142 */ 143 #define NAND_NEED_READRDY 0x00000100 144 145 /* Chip does not allow subpage writes */ 146 #define NAND_NO_SUBPAGE_WRITE 0x00000200 147 148 /* Device is one of 'new' xD cards that expose fake nand command set */ 149 #define NAND_BROKEN_XD 0x00000400 150 151 /* Device behaves just like nand, but is readonly */ 152 #define NAND_ROM 0x00000800 153 154 /* Device supports subpage reads */ 155 #define NAND_SUBPAGE_READ 0x00001000 156 157 /* 158 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 159 * patterns. 160 */ 161 #define NAND_NEED_SCRAMBLING 0x00002000 162 163 /* Device needs 3rd row address cycle */ 164 #define NAND_ROW_ADDR_3 0x00004000 165 166 /* Options valid for Samsung large page devices */ 167 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 168 169 /* Macros to identify the above */ 170 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 171 172 /* 173 * There are different places where the manufacturer stores the factory bad 174 * block markers. 175 * 176 * Position within the block: Each of these pages needs to be checked for a 177 * bad block marking pattern. 178 */ 179 #define NAND_BBM_FIRSTPAGE 0x01000000 180 #define NAND_BBM_SECONDPAGE 0x02000000 181 #define NAND_BBM_LASTPAGE 0x04000000 182 183 /* Position within the OOB data of the page */ 184 #define NAND_BBM_POS_SMALL 5 185 #define NAND_BBM_POS_LARGE 0 186 187 /* Non chip related options */ 188 /* This option skips the bbt scan during initialization. */ 189 #define NAND_SKIP_BBTSCAN 0x00010000 190 /* Chip may not exist, so silence any errors in scan */ 191 #define NAND_SCAN_SILENT_NODEV 0x00040000 192 /* 193 * Autodetect nand buswidth with readid/onfi. 194 * This suppose the driver will configure the hardware in 8 bits mode 195 * when calling nand_scan_ident, and update its configuration 196 * before calling nand_scan_tail. 197 */ 198 #define NAND_BUSWIDTH_AUTO 0x00080000 199 /* 200 * This option could be defined by controller drivers to protect against 201 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 202 */ 203 #define NAND_USE_BOUNCE_BUFFER 0x00100000 204 205 /* 206 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 207 * on the default ->cmdfunc() implementation, you may want to let the core 208 * handle the tCCS delay which is required when a column change (RNDIN or 209 * RNDOUT) is requested. 210 * If your controller already takes care of this delay, you don't need to set 211 * this flag. 212 */ 213 #define NAND_WAIT_TCCS 0x00200000 214 215 /* 216 * Whether the NAND chip is a boot medium. Drivers might use this information 217 * to select ECC algorithms supported by the boot ROM or similar restrictions. 218 */ 219 #define NAND_IS_BOOT_MEDIUM 0x00400000 220 221 /* 222 * Do not try to tweak the timings at runtime. This is needed when the 223 * controller initializes the timings on itself or when it relies on 224 * configuration done by the bootloader. 225 */ 226 #define NAND_KEEP_TIMINGS 0x00800000 227 228 /* Cell info constants */ 229 #define NAND_CI_CHIPNR_MSK 0x03 230 #define NAND_CI_CELLTYPE_MSK 0x0C 231 #define NAND_CI_CELLTYPE_SHIFT 2 232 233 /** 234 * struct nand_parameters - NAND generic parameters from the parameter page 235 * @model: Model name 236 * @supports_set_get_features: The NAND chip supports setting/getting features 237 * @set_feature_list: Bitmap of features that can be set 238 * @get_feature_list: Bitmap of features that can be get 239 * @onfi: ONFI specific parameters 240 */ 241 struct nand_parameters { 242 /* Generic parameters */ 243 const char *model; 244 bool supports_set_get_features; 245 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 246 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 247 248 /* ONFI parameters */ 249 struct onfi_params *onfi; 250 }; 251 252 /* The maximum expected count of bytes in the NAND ID sequence */ 253 #define NAND_MAX_ID_LEN 8 254 255 /** 256 * struct nand_id - NAND id structure 257 * @data: buffer containing the id bytes. 258 * @len: ID length. 259 */ 260 struct nand_id { 261 u8 data[NAND_MAX_ID_LEN]; 262 int len; 263 }; 264 265 /** 266 * struct nand_ecc_step_info - ECC step information of ECC engine 267 * @stepsize: data bytes per ECC step 268 * @strengths: array of supported strengths 269 * @nstrengths: number of supported strengths 270 */ 271 struct nand_ecc_step_info { 272 int stepsize; 273 const int *strengths; 274 int nstrengths; 275 }; 276 277 /** 278 * struct nand_ecc_caps - capability of ECC engine 279 * @stepinfos: array of ECC step information 280 * @nstepinfos: number of ECC step information 281 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 282 */ 283 struct nand_ecc_caps { 284 const struct nand_ecc_step_info *stepinfos; 285 int nstepinfos; 286 int (*calc_ecc_bytes)(int step_size, int strength); 287 }; 288 289 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 290 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 291 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 292 static const struct nand_ecc_step_info __name##_stepinfo = { \ 293 .stepsize = __step, \ 294 .strengths = __name##_strengths, \ 295 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 296 }; \ 297 static const struct nand_ecc_caps __name = { \ 298 .stepinfos = &__name##_stepinfo, \ 299 .nstepinfos = 1, \ 300 .calc_ecc_bytes = __calc, \ 301 } 302 303 /** 304 * struct nand_ecc_ctrl - Control structure for ECC 305 * @mode: ECC mode 306 * @algo: ECC algorithm 307 * @steps: number of ECC steps per page 308 * @size: data bytes per ECC step 309 * @bytes: ECC bytes per step 310 * @strength: max number of correctible bits per ECC step 311 * @total: total number of ECC bytes per page 312 * @prepad: padding information for syndrome based ECC generators 313 * @postpad: padding information for syndrome based ECC generators 314 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 315 * @priv: pointer to private ECC control data 316 * @calc_buf: buffer for calculated ECC, size is oobsize. 317 * @code_buf: buffer for ECC read from flash, size is oobsize. 318 * @hwctl: function to control hardware ECC generator. Must only 319 * be provided if an hardware ECC is available 320 * @calculate: function for ECC calculation or readback from ECC hardware 321 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 322 * Should return a positive number representing the number of 323 * corrected bitflips, -EBADMSG if the number of bitflips exceed 324 * ECC strength, or any other error code if the error is not 325 * directly related to correction. 326 * If -EBADMSG is returned the input buffers should be left 327 * untouched. 328 * @read_page_raw: function to read a raw page without ECC. This function 329 * should hide the specific layout used by the ECC 330 * controller and always return contiguous in-band and 331 * out-of-band data even if they're not stored 332 * contiguously on the NAND chip (e.g. 333 * NAND_ECC_HW_SYNDROME interleaves in-band and 334 * out-of-band data). 335 * @write_page_raw: function to write a raw page without ECC. This function 336 * should hide the specific layout used by the ECC 337 * controller and consider the passed data as contiguous 338 * in-band and out-of-band data. ECC controller is 339 * responsible for doing the appropriate transformations 340 * to adapt to its specific layout (e.g. 341 * NAND_ECC_HW_SYNDROME interleaves in-band and 342 * out-of-band data). 343 * @read_page: function to read a page according to the ECC generator 344 * requirements; returns maximum number of bitflips corrected in 345 * any single ECC step, -EIO hw error 346 * @read_subpage: function to read parts of the page covered by ECC; 347 * returns same as read_page() 348 * @write_subpage: function to write parts of the page covered by ECC. 349 * @write_page: function to write a page according to the ECC generator 350 * requirements. 351 * @write_oob_raw: function to write chip OOB data without ECC 352 * @read_oob_raw: function to read chip OOB data without ECC 353 * @read_oob: function to read chip OOB data 354 * @write_oob: function to write chip OOB data 355 */ 356 struct nand_ecc_ctrl { 357 nand_ecc_modes_t mode; 358 enum nand_ecc_algo algo; 359 int steps; 360 int size; 361 int bytes; 362 int total; 363 int strength; 364 int prepad; 365 int postpad; 366 unsigned int options; 367 void *priv; 368 u8 *calc_buf; 369 u8 *code_buf; 370 void (*hwctl)(struct nand_chip *chip, int mode); 371 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 372 uint8_t *ecc_code); 373 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 374 uint8_t *calc_ecc); 375 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 376 int oob_required, int page); 377 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 378 int oob_required, int page); 379 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 380 int oob_required, int page); 381 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 382 uint32_t len, uint8_t *buf, int page); 383 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 384 uint32_t data_len, const uint8_t *data_buf, 385 int oob_required, int page); 386 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 387 int oob_required, int page); 388 int (*write_oob_raw)(struct nand_chip *chip, int page); 389 int (*read_oob_raw)(struct nand_chip *chip, int page); 390 int (*read_oob)(struct nand_chip *chip, int page); 391 int (*write_oob)(struct nand_chip *chip, int page); 392 }; 393 394 /** 395 * struct nand_sdr_timings - SDR NAND chip timings 396 * 397 * This struct defines the timing requirements of a SDR NAND chip. 398 * These information can be found in every NAND datasheets and the timings 399 * meaning are described in the ONFI specifications: 400 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 401 * Parameters) 402 * 403 * All these timings are expressed in picoseconds. 404 * 405 * @tBERS_max: Block erase time 406 * @tCCS_min: Change column setup time 407 * @tPROG_max: Page program time 408 * @tR_max: Page read time 409 * @tALH_min: ALE hold time 410 * @tADL_min: ALE to data loading time 411 * @tALS_min: ALE setup time 412 * @tAR_min: ALE to RE# delay 413 * @tCEA_max: CE# access time 414 * @tCEH_min: CE# high hold time 415 * @tCH_min: CE# hold time 416 * @tCHZ_max: CE# high to output hi-Z 417 * @tCLH_min: CLE hold time 418 * @tCLR_min: CLE to RE# delay 419 * @tCLS_min: CLE setup time 420 * @tCOH_min: CE# high to output hold 421 * @tCS_min: CE# setup time 422 * @tDH_min: Data hold time 423 * @tDS_min: Data setup time 424 * @tFEAT_max: Busy time for Set Features and Get Features 425 * @tIR_min: Output hi-Z to RE# low 426 * @tITC_max: Interface and Timing Mode Change time 427 * @tRC_min: RE# cycle time 428 * @tREA_max: RE# access time 429 * @tREH_min: RE# high hold time 430 * @tRHOH_min: RE# high to output hold 431 * @tRHW_min: RE# high to WE# low 432 * @tRHZ_max: RE# high to output hi-Z 433 * @tRLOH_min: RE# low to output hold 434 * @tRP_min: RE# pulse width 435 * @tRR_min: Ready to RE# low (data only) 436 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 437 * rising edge of R/B#. 438 * @tWB_max: WE# high to SR[6] low 439 * @tWC_min: WE# cycle time 440 * @tWH_min: WE# high hold time 441 * @tWHR_min: WE# high to RE# low 442 * @tWP_min: WE# pulse width 443 * @tWW_min: WP# transition to WE# low 444 */ 445 struct nand_sdr_timings { 446 u64 tBERS_max; 447 u32 tCCS_min; 448 u64 tPROG_max; 449 u64 tR_max; 450 u32 tALH_min; 451 u32 tADL_min; 452 u32 tALS_min; 453 u32 tAR_min; 454 u32 tCEA_max; 455 u32 tCEH_min; 456 u32 tCH_min; 457 u32 tCHZ_max; 458 u32 tCLH_min; 459 u32 tCLR_min; 460 u32 tCLS_min; 461 u32 tCOH_min; 462 u32 tCS_min; 463 u32 tDH_min; 464 u32 tDS_min; 465 u32 tFEAT_max; 466 u32 tIR_min; 467 u32 tITC_max; 468 u32 tRC_min; 469 u32 tREA_max; 470 u32 tREH_min; 471 u32 tRHOH_min; 472 u32 tRHW_min; 473 u32 tRHZ_max; 474 u32 tRLOH_min; 475 u32 tRP_min; 476 u32 tRR_min; 477 u64 tRST_max; 478 u32 tWB_max; 479 u32 tWC_min; 480 u32 tWH_min; 481 u32 tWHR_min; 482 u32 tWP_min; 483 u32 tWW_min; 484 }; 485 486 /** 487 * enum nand_data_interface_type - NAND interface timing type 488 * @NAND_SDR_IFACE: Single Data Rate interface 489 */ 490 enum nand_data_interface_type { 491 NAND_SDR_IFACE, 492 }; 493 494 /** 495 * struct nand_data_interface - NAND interface timing 496 * @type: type of the timing 497 * @timings: The timing, type according to @type 498 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 499 */ 500 struct nand_data_interface { 501 enum nand_data_interface_type type; 502 union { 503 struct nand_sdr_timings sdr; 504 } timings; 505 }; 506 507 /** 508 * nand_get_sdr_timings - get SDR timing from data interface 509 * @conf: The data interface 510 */ 511 static inline const struct nand_sdr_timings * 512 nand_get_sdr_timings(const struct nand_data_interface *conf) 513 { 514 if (conf->type != NAND_SDR_IFACE) 515 return ERR_PTR(-EINVAL); 516 517 return &conf->timings.sdr; 518 } 519 520 /** 521 * struct nand_op_cmd_instr - Definition of a command instruction 522 * @opcode: the command to issue in one cycle 523 */ 524 struct nand_op_cmd_instr { 525 u8 opcode; 526 }; 527 528 /** 529 * struct nand_op_addr_instr - Definition of an address instruction 530 * @naddrs: length of the @addrs array 531 * @addrs: array containing the address cycles to issue 532 */ 533 struct nand_op_addr_instr { 534 unsigned int naddrs; 535 const u8 *addrs; 536 }; 537 538 /** 539 * struct nand_op_data_instr - Definition of a data instruction 540 * @len: number of data bytes to move 541 * @buf: buffer to fill 542 * @buf.in: buffer to fill when reading from the NAND chip 543 * @buf.out: buffer to read from when writing to the NAND chip 544 * @force_8bit: force 8-bit access 545 * 546 * Please note that "in" and "out" are inverted from the ONFI specification 547 * and are from the controller perspective, so a "in" is a read from the NAND 548 * chip while a "out" is a write to the NAND chip. 549 */ 550 struct nand_op_data_instr { 551 unsigned int len; 552 union { 553 void *in; 554 const void *out; 555 } buf; 556 bool force_8bit; 557 }; 558 559 /** 560 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 561 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 562 */ 563 struct nand_op_waitrdy_instr { 564 unsigned int timeout_ms; 565 }; 566 567 /** 568 * enum nand_op_instr_type - Definition of all instruction types 569 * @NAND_OP_CMD_INSTR: command instruction 570 * @NAND_OP_ADDR_INSTR: address instruction 571 * @NAND_OP_DATA_IN_INSTR: data in instruction 572 * @NAND_OP_DATA_OUT_INSTR: data out instruction 573 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 574 */ 575 enum nand_op_instr_type { 576 NAND_OP_CMD_INSTR, 577 NAND_OP_ADDR_INSTR, 578 NAND_OP_DATA_IN_INSTR, 579 NAND_OP_DATA_OUT_INSTR, 580 NAND_OP_WAITRDY_INSTR, 581 }; 582 583 /** 584 * struct nand_op_instr - Instruction object 585 * @type: the instruction type 586 * @ctx: extra data associated to the instruction. You'll have to use the 587 * appropriate element depending on @type 588 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 589 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 590 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 591 * or %NAND_OP_DATA_OUT_INSTR 592 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 593 * @delay_ns: delay the controller should apply after the instruction has been 594 * issued on the bus. Most modern controllers have internal timings 595 * control logic, and in this case, the controller driver can ignore 596 * this field. 597 */ 598 struct nand_op_instr { 599 enum nand_op_instr_type type; 600 union { 601 struct nand_op_cmd_instr cmd; 602 struct nand_op_addr_instr addr; 603 struct nand_op_data_instr data; 604 struct nand_op_waitrdy_instr waitrdy; 605 } ctx; 606 unsigned int delay_ns; 607 }; 608 609 /* 610 * Special handling must be done for the WAITRDY timeout parameter as it usually 611 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 612 * tBERS (during an erase) which all of them are u64 values that cannot be 613 * divided by usual kernel macros and must be handled with the special 614 * DIV_ROUND_UP_ULL() macro. 615 * 616 * Cast to type of dividend is needed here to guarantee that the result won't 617 * be an unsigned long long when the dividend is an unsigned long (or smaller), 618 * which is what the compiler does when it sees ternary operator with 2 619 * different return types (picks the largest type to make sure there's no 620 * loss). 621 */ 622 #define __DIVIDE(dividend, divisor) ({ \ 623 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 624 DIV_ROUND_UP(dividend, divisor) : \ 625 DIV_ROUND_UP_ULL(dividend, divisor)); \ 626 }) 627 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 628 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 629 630 #define NAND_OP_CMD(id, ns) \ 631 { \ 632 .type = NAND_OP_CMD_INSTR, \ 633 .ctx.cmd.opcode = id, \ 634 .delay_ns = ns, \ 635 } 636 637 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 638 { \ 639 .type = NAND_OP_ADDR_INSTR, \ 640 .ctx.addr = { \ 641 .naddrs = ncycles, \ 642 .addrs = cycles, \ 643 }, \ 644 .delay_ns = ns, \ 645 } 646 647 #define NAND_OP_DATA_IN(l, b, ns) \ 648 { \ 649 .type = NAND_OP_DATA_IN_INSTR, \ 650 .ctx.data = { \ 651 .len = l, \ 652 .buf.in = b, \ 653 .force_8bit = false, \ 654 }, \ 655 .delay_ns = ns, \ 656 } 657 658 #define NAND_OP_DATA_OUT(l, b, ns) \ 659 { \ 660 .type = NAND_OP_DATA_OUT_INSTR, \ 661 .ctx.data = { \ 662 .len = l, \ 663 .buf.out = b, \ 664 .force_8bit = false, \ 665 }, \ 666 .delay_ns = ns, \ 667 } 668 669 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 670 { \ 671 .type = NAND_OP_DATA_IN_INSTR, \ 672 .ctx.data = { \ 673 .len = l, \ 674 .buf.in = b, \ 675 .force_8bit = true, \ 676 }, \ 677 .delay_ns = ns, \ 678 } 679 680 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 681 { \ 682 .type = NAND_OP_DATA_OUT_INSTR, \ 683 .ctx.data = { \ 684 .len = l, \ 685 .buf.out = b, \ 686 .force_8bit = true, \ 687 }, \ 688 .delay_ns = ns, \ 689 } 690 691 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 692 { \ 693 .type = NAND_OP_WAITRDY_INSTR, \ 694 .ctx.waitrdy.timeout_ms = tout_ms, \ 695 .delay_ns = ns, \ 696 } 697 698 /** 699 * struct nand_subop - a sub operation 700 * @instrs: array of instructions 701 * @ninstrs: length of the @instrs array 702 * @first_instr_start_off: offset to start from for the first instruction 703 * of the sub-operation 704 * @last_instr_end_off: offset to end at (excluded) for the last instruction 705 * of the sub-operation 706 * 707 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 708 * address instructions. 709 * 710 * When an operation cannot be handled as is by the NAND controller, it will 711 * be split by the parser into sub-operations which will be passed to the 712 * controller driver. 713 */ 714 struct nand_subop { 715 const struct nand_op_instr *instrs; 716 unsigned int ninstrs; 717 unsigned int first_instr_start_off; 718 unsigned int last_instr_end_off; 719 }; 720 721 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 722 unsigned int op_id); 723 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 724 unsigned int op_id); 725 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 726 unsigned int op_id); 727 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 728 unsigned int op_id); 729 730 /** 731 * struct nand_op_parser_addr_constraints - Constraints for address instructions 732 * @maxcycles: maximum number of address cycles the controller can issue in a 733 * single step 734 */ 735 struct nand_op_parser_addr_constraints { 736 unsigned int maxcycles; 737 }; 738 739 /** 740 * struct nand_op_parser_data_constraints - Constraints for data instructions 741 * @maxlen: maximum data length that the controller can handle in a single step 742 */ 743 struct nand_op_parser_data_constraints { 744 unsigned int maxlen; 745 }; 746 747 /** 748 * struct nand_op_parser_pattern_elem - One element of a pattern 749 * @type: the instructuction type 750 * @optional: whether this element of the pattern is optional or mandatory 751 * @ctx: address or data constraint 752 * @ctx.addr: address constraint (number of cycles) 753 * @ctx.data: data constraint (data length) 754 */ 755 struct nand_op_parser_pattern_elem { 756 enum nand_op_instr_type type; 757 bool optional; 758 union { 759 struct nand_op_parser_addr_constraints addr; 760 struct nand_op_parser_data_constraints data; 761 } ctx; 762 }; 763 764 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 765 { \ 766 .type = NAND_OP_CMD_INSTR, \ 767 .optional = _opt, \ 768 } 769 770 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 771 { \ 772 .type = NAND_OP_ADDR_INSTR, \ 773 .optional = _opt, \ 774 .ctx.addr.maxcycles = _maxcycles, \ 775 } 776 777 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 778 { \ 779 .type = NAND_OP_DATA_IN_INSTR, \ 780 .optional = _opt, \ 781 .ctx.data.maxlen = _maxlen, \ 782 } 783 784 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 785 { \ 786 .type = NAND_OP_DATA_OUT_INSTR, \ 787 .optional = _opt, \ 788 .ctx.data.maxlen = _maxlen, \ 789 } 790 791 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 792 { \ 793 .type = NAND_OP_WAITRDY_INSTR, \ 794 .optional = _opt, \ 795 } 796 797 /** 798 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 799 * @elems: array of pattern elements 800 * @nelems: number of pattern elements in @elems array 801 * @exec: the function that will issue a sub-operation 802 * 803 * A pattern is a list of elements, each element reprensenting one instruction 804 * with its constraints. The pattern itself is used by the core to match NAND 805 * chip operation with NAND controller operations. 806 * Once a match between a NAND controller operation pattern and a NAND chip 807 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 808 * hook is called so that the controller driver can issue the operation on the 809 * bus. 810 * 811 * Controller drivers should declare as many patterns as they support and pass 812 * this list of patterns (created with the help of the following macro) to 813 * the nand_op_parser_exec_op() helper. 814 */ 815 struct nand_op_parser_pattern { 816 const struct nand_op_parser_pattern_elem *elems; 817 unsigned int nelems; 818 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 819 }; 820 821 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 822 { \ 823 .exec = _exec, \ 824 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 825 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 826 sizeof(struct nand_op_parser_pattern_elem), \ 827 } 828 829 /** 830 * struct nand_op_parser - NAND controller operation parser descriptor 831 * @patterns: array of supported patterns 832 * @npatterns: length of the @patterns array 833 * 834 * The parser descriptor is just an array of supported patterns which will be 835 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 836 * NAND operation (or tries to determine if a specific operation is supported). 837 * 838 * It is worth mentioning that patterns will be tested in their declaration 839 * order, and the first match will be taken, so it's important to order patterns 840 * appropriately so that simple/inefficient patterns are placed at the end of 841 * the list. Usually, this is where you put single instruction patterns. 842 */ 843 struct nand_op_parser { 844 const struct nand_op_parser_pattern *patterns; 845 unsigned int npatterns; 846 }; 847 848 #define NAND_OP_PARSER(...) \ 849 { \ 850 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 851 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 852 sizeof(struct nand_op_parser_pattern), \ 853 } 854 855 /** 856 * struct nand_operation - NAND operation descriptor 857 * @cs: the CS line to select for this NAND operation 858 * @instrs: array of instructions to execute 859 * @ninstrs: length of the @instrs array 860 * 861 * The actual operation structure that will be passed to chip->exec_op(). 862 */ 863 struct nand_operation { 864 unsigned int cs; 865 const struct nand_op_instr *instrs; 866 unsigned int ninstrs; 867 }; 868 869 #define NAND_OPERATION(_cs, _instrs) \ 870 { \ 871 .cs = _cs, \ 872 .instrs = _instrs, \ 873 .ninstrs = ARRAY_SIZE(_instrs), \ 874 } 875 876 int nand_op_parser_exec_op(struct nand_chip *chip, 877 const struct nand_op_parser *parser, 878 const struct nand_operation *op, bool check_only); 879 880 /** 881 * struct nand_controller_ops - Controller operations 882 * 883 * @attach_chip: this method is called after the NAND detection phase after 884 * flash ID and MTD fields such as erase size, page size and OOB 885 * size have been set up. ECC requirements are available if 886 * provided by the NAND chip or device tree. Typically used to 887 * choose the appropriate ECC configuration and allocate 888 * associated resources. 889 * This hook is optional. 890 * @detach_chip: free all resources allocated/claimed in 891 * nand_controller_ops->attach_chip(). 892 * This hook is optional. 893 * @exec_op: controller specific method to execute NAND operations. 894 * This method replaces chip->legacy.cmdfunc(), 895 * chip->legacy.{read,write}_{buf,byte,word}(), 896 * chip->legacy.dev_ready() and chip->legacy.waifunc(). 897 * @setup_data_interface: setup the data interface and timing. If 898 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 899 * means the configuration should not be applied but 900 * only checked. 901 * This hook is optional. 902 */ 903 struct nand_controller_ops { 904 int (*attach_chip)(struct nand_chip *chip); 905 void (*detach_chip)(struct nand_chip *chip); 906 int (*exec_op)(struct nand_chip *chip, 907 const struct nand_operation *op, 908 bool check_only); 909 int (*setup_data_interface)(struct nand_chip *chip, int chipnr, 910 const struct nand_data_interface *conf); 911 }; 912 913 /** 914 * struct nand_controller - Structure used to describe a NAND controller 915 * 916 * @lock: lock used to serialize accesses to the NAND controller 917 * @ops: NAND controller operations. 918 */ 919 struct nand_controller { 920 struct mutex lock; 921 const struct nand_controller_ops *ops; 922 }; 923 924 static inline void nand_controller_init(struct nand_controller *nfc) 925 { 926 mutex_init(&nfc->lock); 927 } 928 929 /** 930 * struct nand_legacy - NAND chip legacy fields/hooks 931 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 932 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 933 * @select_chip: select/deselect a specific target/die 934 * @read_byte: read one byte from the chip 935 * @write_byte: write a single byte to the chip on the low 8 I/O lines 936 * @write_buf: write data from the buffer to the chip 937 * @read_buf: read data from the chip into the buffer 938 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 939 * to write command and address 940 * @cmdfunc: hardware specific function for writing commands to the chip. 941 * @dev_ready: hardware specific function for accessing device ready/busy line. 942 * If set to NULL no access to ready/busy is available and the 943 * ready/busy information is read from the chip status register. 944 * @waitfunc: hardware specific function for wait on ready. 945 * @block_bad: check if a block is bad, using OOB markers 946 * @block_markbad: mark a block bad 947 * @set_features: set the NAND chip features 948 * @get_features: get the NAND chip features 949 * @chip_delay: chip dependent delay for transferring data from array to read 950 * regs (tR). 951 * @dummy_controller: dummy controller implementation for drivers that can 952 * only control a single chip 953 * 954 * If you look at this structure you're already wrong. These fields/hooks are 955 * all deprecated. 956 */ 957 struct nand_legacy { 958 void __iomem *IO_ADDR_R; 959 void __iomem *IO_ADDR_W; 960 void (*select_chip)(struct nand_chip *chip, int cs); 961 u8 (*read_byte)(struct nand_chip *chip); 962 void (*write_byte)(struct nand_chip *chip, u8 byte); 963 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 964 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 965 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 966 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 967 int page_addr); 968 int (*dev_ready)(struct nand_chip *chip); 969 int (*waitfunc)(struct nand_chip *chip); 970 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 971 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 972 int (*set_features)(struct nand_chip *chip, int feature_addr, 973 u8 *subfeature_para); 974 int (*get_features)(struct nand_chip *chip, int feature_addr, 975 u8 *subfeature_para); 976 int chip_delay; 977 struct nand_controller dummy_controller; 978 }; 979 980 /** 981 * struct nand_chip - NAND Private Flash Chip Data 982 * @base: Inherit from the generic NAND device 983 * @legacy: All legacy fields/hooks. If you develop a new driver, 984 * don't even try to use any of these fields/hooks, and if 985 * you're modifying an existing driver that is using those 986 * fields/hooks, you should consider reworking the driver 987 * avoid using them. 988 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 989 * setting the read-retry mode. Mostly needed for MLC NAND. 990 * @ecc: [BOARDSPECIFIC] ECC control structure 991 * @buf_align: minimum buffer alignment required by a platform 992 * @oob_poi: "poison value buffer," used for laying out OOB data 993 * before writing 994 * @page_shift: [INTERN] number of address bits in a page (column 995 * address bits). 996 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 997 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 998 * @chip_shift: [INTERN] number of address bits in one chip 999 * @options: [BOARDSPECIFIC] various chip options. They can partly 1000 * be set to inform nand_scan about special functionality. 1001 * See the defines for further explanation. 1002 * @bbt_options: [INTERN] bad block specific options. All options used 1003 * here must come from bbm.h. By default, these options 1004 * will be copied to the appropriate nand_bbt_descr's. 1005 * @badblockpos: [INTERN] position of the bad block marker in the oob 1006 * area. 1007 * @badblockbits: [INTERN] minimum number of set bits in a good block's 1008 * bad block marker position; i.e., BBM == 11110111b is 1009 * not bad when badblockbits == 7 1010 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1011 * set to the actually used ONFI mode if the chip is 1012 * ONFI compliant or deduced from the datasheet if 1013 * the NAND chip is not ONFI compliant. 1014 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1015 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1016 * @pagecache: Structure containing page cache related fields 1017 * @pagecache.bitflips: Number of bitflips of the cached page 1018 * @pagecache.page: Page number currently in the cache. -1 means no page is 1019 * currently cached 1020 * @subpagesize: [INTERN] holds the subpagesize 1021 * @id: [INTERN] holds NAND ID 1022 * @parameters: [INTERN] holds generic parameters under an easily 1023 * readable form. 1024 * @data_interface: [INTERN] NAND interface timing information 1025 * @cur_cs: currently selected target. -1 means no target selected, 1026 * otherwise we should always have cur_cs >= 0 && 1027 * cur_cs < nanddev_ntargets(). NAND Controller drivers 1028 * should not modify this value, but they're allowed to 1029 * read it. 1030 * @read_retries: [INTERN] the number of read retry modes supported 1031 * @lock: lock protecting the suspended field. Also used to 1032 * serialize accesses to the NAND device. 1033 * @suspended: set to 1 when the device is suspended, 0 when it's not. 1034 * @bbt: [INTERN] bad block table pointer 1035 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1036 * lookup. 1037 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1038 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1039 * bad block scan. 1040 * @controller: [REPLACEABLE] a pointer to a hardware controller 1041 * structure which is shared among multiple independent 1042 * devices. 1043 * @priv: [OPTIONAL] pointer to private chip data 1044 * @manufacturer: [INTERN] Contains manufacturer information 1045 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1046 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1047 */ 1048 1049 struct nand_chip { 1050 struct nand_device base; 1051 1052 struct nand_legacy legacy; 1053 1054 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1055 1056 unsigned int options; 1057 unsigned int bbt_options; 1058 1059 int page_shift; 1060 int phys_erase_shift; 1061 int bbt_erase_shift; 1062 int chip_shift; 1063 int pagemask; 1064 u8 *data_buf; 1065 1066 struct { 1067 unsigned int bitflips; 1068 int page; 1069 } pagecache; 1070 1071 int subpagesize; 1072 int onfi_timing_mode_default; 1073 unsigned int badblockpos; 1074 int badblockbits; 1075 1076 struct nand_id id; 1077 struct nand_parameters parameters; 1078 1079 struct nand_data_interface data_interface; 1080 1081 int cur_cs; 1082 1083 int read_retries; 1084 1085 struct mutex lock; 1086 unsigned int suspended : 1; 1087 1088 uint8_t *oob_poi; 1089 struct nand_controller *controller; 1090 1091 struct nand_ecc_ctrl ecc; 1092 unsigned long buf_align; 1093 1094 uint8_t *bbt; 1095 struct nand_bbt_descr *bbt_td; 1096 struct nand_bbt_descr *bbt_md; 1097 1098 struct nand_bbt_descr *badblock_pattern; 1099 1100 void *priv; 1101 1102 struct { 1103 const struct nand_manufacturer *desc; 1104 void *priv; 1105 } manufacturer; 1106 }; 1107 1108 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1109 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1110 1111 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1112 { 1113 return container_of(mtd, struct nand_chip, base.mtd); 1114 } 1115 1116 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1117 { 1118 return &chip->base.mtd; 1119 } 1120 1121 static inline void *nand_get_controller_data(struct nand_chip *chip) 1122 { 1123 return chip->priv; 1124 } 1125 1126 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1127 { 1128 chip->priv = priv; 1129 } 1130 1131 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1132 void *priv) 1133 { 1134 chip->manufacturer.priv = priv; 1135 } 1136 1137 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1138 { 1139 return chip->manufacturer.priv; 1140 } 1141 1142 static inline void nand_set_flash_node(struct nand_chip *chip, 1143 struct device_node *np) 1144 { 1145 mtd_set_of_node(nand_to_mtd(chip), np); 1146 } 1147 1148 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1149 { 1150 return mtd_get_of_node(nand_to_mtd(chip)); 1151 } 1152 1153 /* 1154 * A helper for defining older NAND chips where the second ID byte fully 1155 * defined the chip, including the geometry (chip size, eraseblock size, page 1156 * size). All these chips have 512 bytes NAND page size. 1157 */ 1158 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1159 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1160 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1161 1162 /* 1163 * A helper for defining newer chips which report their page size and 1164 * eraseblock size via the extended ID bytes. 1165 * 1166 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1167 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1168 * device ID now only represented a particular total chip size (and voltage, 1169 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1170 * using the same device ID. 1171 */ 1172 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1173 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1174 .options = (opts) } 1175 1176 #define NAND_ECC_INFO(_strength, _step) \ 1177 { .strength_ds = (_strength), .step_ds = (_step) } 1178 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1179 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1180 1181 /** 1182 * struct nand_flash_dev - NAND Flash Device ID Structure 1183 * @name: a human-readable name of the NAND chip 1184 * @dev_id: the device ID (the second byte of the full chip ID array) 1185 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1186 * memory address as ``id[0]``) 1187 * @dev_id: device ID part of the full chip ID array (refers the same memory 1188 * address as ``id[1]``) 1189 * @id: full device ID array 1190 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1191 * well as the eraseblock size) is determined from the extended NAND 1192 * chip ID array) 1193 * @chipsize: total chip size in MiB 1194 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1195 * @options: stores various chip bit options 1196 * @id_len: The valid length of the @id. 1197 * @oobsize: OOB size 1198 * @ecc: ECC correctability and step information from the datasheet. 1199 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1200 * @ecc_strength_ds in nand_chip{}. 1201 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1202 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1203 * For example, the "4bit ECC for each 512Byte" can be set with 1204 * NAND_ECC_INFO(4, 512). 1205 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1206 * reset. Should be deduced from timings described 1207 * in the datasheet. 1208 * 1209 */ 1210 struct nand_flash_dev { 1211 char *name; 1212 union { 1213 struct { 1214 uint8_t mfr_id; 1215 uint8_t dev_id; 1216 }; 1217 uint8_t id[NAND_MAX_ID_LEN]; 1218 }; 1219 unsigned int pagesize; 1220 unsigned int chipsize; 1221 unsigned int erasesize; 1222 unsigned int options; 1223 uint16_t id_len; 1224 uint16_t oobsize; 1225 struct { 1226 uint16_t strength_ds; 1227 uint16_t step_ds; 1228 } ecc; 1229 int onfi_timing_mode_default; 1230 }; 1231 1232 int nand_create_bbt(struct nand_chip *chip); 1233 1234 /* 1235 * Check if it is a SLC nand. 1236 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1237 * We do not distinguish the MLC and TLC now. 1238 */ 1239 static inline bool nand_is_slc(struct nand_chip *chip) 1240 { 1241 WARN(nanddev_bits_per_cell(&chip->base) == 0, 1242 "chip->bits_per_cell is used uninitialized\n"); 1243 return nanddev_bits_per_cell(&chip->base) == 1; 1244 } 1245 1246 /** 1247 * Check if the opcode's address should be sent only on the lower 8 bits 1248 * @command: opcode to check 1249 */ 1250 static inline int nand_opcode_8bits(unsigned int command) 1251 { 1252 switch (command) { 1253 case NAND_CMD_READID: 1254 case NAND_CMD_PARAM: 1255 case NAND_CMD_GET_FEATURES: 1256 case NAND_CMD_SET_FEATURES: 1257 return 1; 1258 default: 1259 break; 1260 } 1261 return 0; 1262 } 1263 1264 int nand_check_erased_ecc_chunk(void *data, int datalen, 1265 void *ecc, int ecclen, 1266 void *extraoob, int extraooblen, 1267 int threshold); 1268 1269 int nand_ecc_choose_conf(struct nand_chip *chip, 1270 const struct nand_ecc_caps *caps, int oobavail); 1271 1272 /* Default write_oob implementation */ 1273 int nand_write_oob_std(struct nand_chip *chip, int page); 1274 1275 /* Default read_oob implementation */ 1276 int nand_read_oob_std(struct nand_chip *chip, int page); 1277 1278 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1279 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1280 u8 *subfeature_param); 1281 1282 /* Default read_page_raw implementation */ 1283 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1284 int page); 1285 1286 /* Default write_page_raw implementation */ 1287 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1288 int oob_required, int page); 1289 1290 /* Reset and initialize a NAND device */ 1291 int nand_reset(struct nand_chip *chip, int chipnr); 1292 1293 /* NAND operation helpers */ 1294 int nand_reset_op(struct nand_chip *chip); 1295 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1296 unsigned int len); 1297 int nand_status_op(struct nand_chip *chip, u8 *status); 1298 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1299 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1300 unsigned int offset_in_page, void *buf, unsigned int len); 1301 int nand_change_read_column_op(struct nand_chip *chip, 1302 unsigned int offset_in_page, void *buf, 1303 unsigned int len, bool force_8bit); 1304 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1305 unsigned int offset_in_page, void *buf, unsigned int len); 1306 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1307 unsigned int offset_in_page, const void *buf, 1308 unsigned int len); 1309 int nand_prog_page_end_op(struct nand_chip *chip); 1310 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1311 unsigned int offset_in_page, const void *buf, 1312 unsigned int len); 1313 int nand_change_write_column_op(struct nand_chip *chip, 1314 unsigned int offset_in_page, const void *buf, 1315 unsigned int len, bool force_8bit); 1316 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1317 bool force_8bit); 1318 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1319 unsigned int len, bool force_8bit); 1320 1321 /* Scan and identify a NAND device */ 1322 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1323 struct nand_flash_dev *ids); 1324 1325 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1326 { 1327 return nand_scan_with_ids(chip, max_chips, NULL); 1328 } 1329 1330 /* Internal helper for board drivers which need to override command function */ 1331 void nand_wait_ready(struct nand_chip *chip); 1332 1333 /* 1334 * Free resources held by the NAND device, must be called on error after a 1335 * sucessful nand_scan(). 1336 */ 1337 void nand_cleanup(struct nand_chip *chip); 1338 /* Unregister the MTD device and calls nand_cleanup() */ 1339 void nand_release(struct nand_chip *chip); 1340 1341 /* 1342 * External helper for controller drivers that have to implement the WAITRDY 1343 * instruction and have no physical pin to check it. 1344 */ 1345 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1346 struct gpio_desc; 1347 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 1348 unsigned long timeout_ms); 1349 1350 /* Select/deselect a NAND target. */ 1351 void nand_select_target(struct nand_chip *chip, unsigned int cs); 1352 void nand_deselect_target(struct nand_chip *chip); 1353 1354 /** 1355 * nand_get_data_buf() - Get the internal page buffer 1356 * @chip: NAND chip object 1357 * 1358 * Returns the pre-allocated page buffer after invalidating the cache. This 1359 * function should be used by drivers that do not want to allocate their own 1360 * bounce buffer and still need such a buffer for specific operations (most 1361 * commonly when reading OOB data only). 1362 * 1363 * Be careful to never call this function in the write/write_oob path, because 1364 * the core may have placed the data to be written out in this buffer. 1365 * 1366 * Return: pointer to the page cache buffer 1367 */ 1368 static inline void *nand_get_data_buf(struct nand_chip *chip) 1369 { 1370 chip->pagecache.page = -1; 1371 1372 return chip->data_buf; 1373 } 1374 1375 #endif /* __LINUX_MTD_RAWNAND_H */ 1376