1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/wait.h> 20 #include <linux/spinlock.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/flashchip.h> 23 #include <linux/mtd/bbm.h> 24 #include <linux/types.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 int nand_scan_with_ids(struct mtd_info *mtd, int max_chips, 32 struct nand_flash_dev *ids); 33 34 static inline int nand_scan(struct mtd_info *mtd, int max_chips) 35 { 36 return nand_scan_with_ids(mtd, max_chips, NULL); 37 } 38 39 /* 40 * Separate phases of nand_scan(), allowing board driver to intervene 41 * and override command or ECC setup according to flash type. 42 */ 43 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 44 struct nand_flash_dev *table); 45 int nand_scan_tail(struct mtd_info *mtd); 46 47 /* Unregister the MTD device and free resources held by the NAND device */ 48 void nand_release(struct mtd_info *mtd); 49 50 /* Internal helper for board drivers which need to override command function */ 51 void nand_wait_ready(struct mtd_info *mtd); 52 53 /* The maximum number of NAND chips in an array */ 54 #define NAND_MAX_CHIPS 8 55 56 /* 57 * Constants for hardware specific CLE/ALE/NCE function 58 * 59 * These are bits which can be or'ed to set/clear multiple 60 * bits in one go. 61 */ 62 /* Select the chip by setting nCE to low */ 63 #define NAND_NCE 0x01 64 /* Select the command latch by setting CLE to high */ 65 #define NAND_CLE 0x02 66 /* Select the address latch by setting ALE to high */ 67 #define NAND_ALE 0x04 68 69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 71 #define NAND_CTRL_CHANGE 0x80 72 73 /* 74 * Standard NAND flash commands 75 */ 76 #define NAND_CMD_READ0 0 77 #define NAND_CMD_READ1 1 78 #define NAND_CMD_RNDOUT 5 79 #define NAND_CMD_PAGEPROG 0x10 80 #define NAND_CMD_READOOB 0x50 81 #define NAND_CMD_ERASE1 0x60 82 #define NAND_CMD_STATUS 0x70 83 #define NAND_CMD_SEQIN 0x80 84 #define NAND_CMD_RNDIN 0x85 85 #define NAND_CMD_READID 0x90 86 #define NAND_CMD_ERASE2 0xd0 87 #define NAND_CMD_PARAM 0xec 88 #define NAND_CMD_GET_FEATURES 0xee 89 #define NAND_CMD_SET_FEATURES 0xef 90 #define NAND_CMD_RESET 0xff 91 92 /* Extended commands for large page devices */ 93 #define NAND_CMD_READSTART 0x30 94 #define NAND_CMD_RNDOUTSTART 0xE0 95 #define NAND_CMD_CACHEDPROG 0x15 96 97 #define NAND_CMD_NONE -1 98 99 /* Status bits */ 100 #define NAND_STATUS_FAIL 0x01 101 #define NAND_STATUS_FAIL_N1 0x02 102 #define NAND_STATUS_TRUE_READY 0x20 103 #define NAND_STATUS_READY 0x40 104 #define NAND_STATUS_WP 0x80 105 106 #define NAND_DATA_IFACE_CHECK_ONLY -1 107 108 /* 109 * Constants for ECC_MODES 110 */ 111 typedef enum { 112 NAND_ECC_NONE, 113 NAND_ECC_SOFT, 114 NAND_ECC_HW, 115 NAND_ECC_HW_SYNDROME, 116 NAND_ECC_HW_OOB_FIRST, 117 NAND_ECC_ON_DIE, 118 } nand_ecc_modes_t; 119 120 enum nand_ecc_algo { 121 NAND_ECC_UNKNOWN, 122 NAND_ECC_HAMMING, 123 NAND_ECC_BCH, 124 }; 125 126 /* 127 * Constants for Hardware ECC 128 */ 129 /* Reset Hardware ECC for read */ 130 #define NAND_ECC_READ 0 131 /* Reset Hardware ECC for write */ 132 #define NAND_ECC_WRITE 1 133 /* Enable Hardware ECC before syndrome is read back from flash */ 134 #define NAND_ECC_READSYN 2 135 136 /* 137 * Enable generic NAND 'page erased' check. This check is only done when 138 * ecc.correct() returns -EBADMSG. 139 * Set this flag if your implementation does not fix bitflips in erased 140 * pages and you want to rely on the default implementation. 141 */ 142 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 143 #define NAND_ECC_MAXIMIZE BIT(1) 144 145 /* Bit mask for flags passed to do_nand_read_ecc */ 146 #define NAND_GET_DEVICE 0x80 147 148 149 /* 150 * Option constants for bizarre disfunctionality and real 151 * features. 152 */ 153 /* Buswidth is 16 bit */ 154 #define NAND_BUSWIDTH_16 0x00000002 155 /* Chip has cache program function */ 156 #define NAND_CACHEPRG 0x00000008 157 /* 158 * Chip requires ready check on read (for auto-incremented sequential read). 159 * True only for small page devices; large page devices do not support 160 * autoincrement. 161 */ 162 #define NAND_NEED_READRDY 0x00000100 163 164 /* Chip does not allow subpage writes */ 165 #define NAND_NO_SUBPAGE_WRITE 0x00000200 166 167 /* Device is one of 'new' xD cards that expose fake nand command set */ 168 #define NAND_BROKEN_XD 0x00000400 169 170 /* Device behaves just like nand, but is readonly */ 171 #define NAND_ROM 0x00000800 172 173 /* Device supports subpage reads */ 174 #define NAND_SUBPAGE_READ 0x00001000 175 176 /* 177 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 178 * patterns. 179 */ 180 #define NAND_NEED_SCRAMBLING 0x00002000 181 182 /* Device needs 3rd row address cycle */ 183 #define NAND_ROW_ADDR_3 0x00004000 184 185 /* Options valid for Samsung large page devices */ 186 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 187 188 /* Macros to identify the above */ 189 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 190 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 191 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 192 193 /* Non chip related options */ 194 /* This option skips the bbt scan during initialization. */ 195 #define NAND_SKIP_BBTSCAN 0x00010000 196 /* Chip may not exist, so silence any errors in scan */ 197 #define NAND_SCAN_SILENT_NODEV 0x00040000 198 /* 199 * Autodetect nand buswidth with readid/onfi. 200 * This suppose the driver will configure the hardware in 8 bits mode 201 * when calling nand_scan_ident, and update its configuration 202 * before calling nand_scan_tail. 203 */ 204 #define NAND_BUSWIDTH_AUTO 0x00080000 205 /* 206 * This option could be defined by controller drivers to protect against 207 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 208 */ 209 #define NAND_USE_BOUNCE_BUFFER 0x00100000 210 211 /* 212 * In case your controller is implementing ->cmd_ctrl() and is relying on the 213 * default ->cmdfunc() implementation, you may want to let the core handle the 214 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is 215 * requested. 216 * If your controller already takes care of this delay, you don't need to set 217 * this flag. 218 */ 219 #define NAND_WAIT_TCCS 0x00200000 220 221 /* Options set by nand scan */ 222 /* Nand scan has allocated controller struct */ 223 #define NAND_CONTROLLER_ALLOC 0x80000000 224 225 /* Cell info constants */ 226 #define NAND_CI_CHIPNR_MSK 0x03 227 #define NAND_CI_CELLTYPE_MSK 0x0C 228 #define NAND_CI_CELLTYPE_SHIFT 2 229 230 /* Keep gcc happy */ 231 struct nand_chip; 232 233 /* ONFI features */ 234 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 235 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 236 237 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 238 #define ONFI_TIMING_MODE_0 (1 << 0) 239 #define ONFI_TIMING_MODE_1 (1 << 1) 240 #define ONFI_TIMING_MODE_2 (1 << 2) 241 #define ONFI_TIMING_MODE_3 (1 << 3) 242 #define ONFI_TIMING_MODE_4 (1 << 4) 243 #define ONFI_TIMING_MODE_5 (1 << 5) 244 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 245 246 /* ONFI feature number/address */ 247 #define ONFI_FEATURE_NUMBER 256 248 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 249 250 /* Vendor-specific feature address (Micron) */ 251 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 252 #define ONFI_FEATURE_ON_DIE_ECC 0x90 253 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) 254 255 /* ONFI subfeature parameters length */ 256 #define ONFI_SUBFEATURE_PARAM_LEN 4 257 258 /* ONFI optional commands SET/GET FEATURES supported? */ 259 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 260 261 struct nand_onfi_params { 262 /* rev info and features block */ 263 /* 'O' 'N' 'F' 'I' */ 264 u8 sig[4]; 265 __le16 revision; 266 __le16 features; 267 __le16 opt_cmd; 268 u8 reserved0[2]; 269 __le16 ext_param_page_length; /* since ONFI 2.1 */ 270 u8 num_of_param_pages; /* since ONFI 2.1 */ 271 u8 reserved1[17]; 272 273 /* manufacturer information block */ 274 char manufacturer[12]; 275 char model[20]; 276 u8 jedec_id; 277 __le16 date_code; 278 u8 reserved2[13]; 279 280 /* memory organization block */ 281 __le32 byte_per_page; 282 __le16 spare_bytes_per_page; 283 __le32 data_bytes_per_ppage; 284 __le16 spare_bytes_per_ppage; 285 __le32 pages_per_block; 286 __le32 blocks_per_lun; 287 u8 lun_count; 288 u8 addr_cycles; 289 u8 bits_per_cell; 290 __le16 bb_per_lun; 291 __le16 block_endurance; 292 u8 guaranteed_good_blocks; 293 __le16 guaranteed_block_endurance; 294 u8 programs_per_page; 295 u8 ppage_attr; 296 u8 ecc_bits; 297 u8 interleaved_bits; 298 u8 interleaved_ops; 299 u8 reserved3[13]; 300 301 /* electrical parameter block */ 302 u8 io_pin_capacitance_max; 303 __le16 async_timing_mode; 304 __le16 program_cache_timing_mode; 305 __le16 t_prog; 306 __le16 t_bers; 307 __le16 t_r; 308 __le16 t_ccs; 309 __le16 src_sync_timing_mode; 310 u8 src_ssync_features; 311 __le16 clk_pin_capacitance_typ; 312 __le16 io_pin_capacitance_typ; 313 __le16 input_pin_capacitance_typ; 314 u8 input_pin_capacitance_max; 315 u8 driver_strength_support; 316 __le16 t_int_r; 317 __le16 t_adl; 318 u8 reserved4[8]; 319 320 /* vendor */ 321 __le16 vendor_revision; 322 u8 vendor[88]; 323 324 __le16 crc; 325 } __packed; 326 327 #define ONFI_CRC_BASE 0x4F4E 328 329 /* Extended ECC information Block Definition (since ONFI 2.1) */ 330 struct onfi_ext_ecc_info { 331 u8 ecc_bits; 332 u8 codeword_size; 333 __le16 bb_per_lun; 334 __le16 block_endurance; 335 u8 reserved[2]; 336 } __packed; 337 338 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 339 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 340 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 341 struct onfi_ext_section { 342 u8 type; 343 u8 length; 344 } __packed; 345 346 #define ONFI_EXT_SECTION_MAX 8 347 348 /* Extended Parameter Page Definition (since ONFI 2.1) */ 349 struct onfi_ext_param_page { 350 __le16 crc; 351 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 352 u8 reserved0[10]; 353 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 354 355 /* 356 * The actual size of the Extended Parameter Page is in 357 * @ext_param_page_length of nand_onfi_params{}. 358 * The following are the variable length sections. 359 * So we do not add any fields below. Please see the ONFI spec. 360 */ 361 } __packed; 362 363 struct jedec_ecc_info { 364 u8 ecc_bits; 365 u8 codeword_size; 366 __le16 bb_per_lun; 367 __le16 block_endurance; 368 u8 reserved[2]; 369 } __packed; 370 371 /* JEDEC features */ 372 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 373 374 struct nand_jedec_params { 375 /* rev info and features block */ 376 /* 'J' 'E' 'S' 'D' */ 377 u8 sig[4]; 378 __le16 revision; 379 __le16 features; 380 u8 opt_cmd[3]; 381 __le16 sec_cmd; 382 u8 num_of_param_pages; 383 u8 reserved0[18]; 384 385 /* manufacturer information block */ 386 char manufacturer[12]; 387 char model[20]; 388 u8 jedec_id[6]; 389 u8 reserved1[10]; 390 391 /* memory organization block */ 392 __le32 byte_per_page; 393 __le16 spare_bytes_per_page; 394 u8 reserved2[6]; 395 __le32 pages_per_block; 396 __le32 blocks_per_lun; 397 u8 lun_count; 398 u8 addr_cycles; 399 u8 bits_per_cell; 400 u8 programs_per_page; 401 u8 multi_plane_addr; 402 u8 multi_plane_op_attr; 403 u8 reserved3[38]; 404 405 /* electrical parameter block */ 406 __le16 async_sdr_speed_grade; 407 __le16 toggle_ddr_speed_grade; 408 __le16 sync_ddr_speed_grade; 409 u8 async_sdr_features; 410 u8 toggle_ddr_features; 411 u8 sync_ddr_features; 412 __le16 t_prog; 413 __le16 t_bers; 414 __le16 t_r; 415 __le16 t_r_multi_plane; 416 __le16 t_ccs; 417 __le16 io_pin_capacitance_typ; 418 __le16 input_pin_capacitance_typ; 419 __le16 clk_pin_capacitance_typ; 420 u8 driver_strength_support; 421 __le16 t_adl; 422 u8 reserved4[36]; 423 424 /* ECC and endurance block */ 425 u8 guaranteed_good_blocks; 426 __le16 guaranteed_block_endurance; 427 struct jedec_ecc_info ecc_info[4]; 428 u8 reserved5[29]; 429 430 /* reserved */ 431 u8 reserved6[148]; 432 433 /* vendor */ 434 __le16 vendor_rev_num; 435 u8 reserved7[88]; 436 437 /* CRC for Parameter Page */ 438 __le16 crc; 439 } __packed; 440 441 /** 442 * struct onfi_params - ONFI specific parameters that will be reused 443 * @version: ONFI version (BCD encoded), 0 if ONFI is not supported 444 * @tPROG: Page program time 445 * @tBERS: Block erase time 446 * @tR: Page read time 447 * @tCCS: Change column setup time 448 * @async_timing_mode: Supported asynchronous timing mode 449 * @vendor_revision: Vendor specific revision number 450 * @vendor: Vendor specific data 451 */ 452 struct onfi_params { 453 int version; 454 u16 tPROG; 455 u16 tBERS; 456 u16 tR; 457 u16 tCCS; 458 u16 async_timing_mode; 459 u16 vendor_revision; 460 u8 vendor[88]; 461 }; 462 463 /** 464 * struct nand_parameters - NAND generic parameters from the parameter page 465 * @model: Model name 466 * @supports_set_get_features: The NAND chip supports setting/getting features 467 * @set_feature_list: Bitmap of features that can be set 468 * @get_feature_list: Bitmap of features that can be get 469 * @onfi: ONFI specific parameters 470 */ 471 struct nand_parameters { 472 /* Generic parameters */ 473 char model[100]; 474 bool supports_set_get_features; 475 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 476 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 477 478 /* ONFI parameters */ 479 struct onfi_params onfi; 480 }; 481 482 /* The maximum expected count of bytes in the NAND ID sequence */ 483 #define NAND_MAX_ID_LEN 8 484 485 /** 486 * struct nand_id - NAND id structure 487 * @data: buffer containing the id bytes. 488 * @len: ID length. 489 */ 490 struct nand_id { 491 u8 data[NAND_MAX_ID_LEN]; 492 int len; 493 }; 494 495 /** 496 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 497 * @lock: protection lock 498 * @active: the mtd device which holds the controller currently 499 * @wq: wait queue to sleep on if a NAND operation is in 500 * progress used instead of the per chip wait queue 501 * when a hw controller is available. 502 */ 503 struct nand_hw_control { 504 spinlock_t lock; 505 struct nand_chip *active; 506 wait_queue_head_t wq; 507 }; 508 509 static inline void nand_hw_control_init(struct nand_hw_control *nfc) 510 { 511 nfc->active = NULL; 512 spin_lock_init(&nfc->lock); 513 init_waitqueue_head(&nfc->wq); 514 } 515 516 /** 517 * struct nand_ecc_step_info - ECC step information of ECC engine 518 * @stepsize: data bytes per ECC step 519 * @strengths: array of supported strengths 520 * @nstrengths: number of supported strengths 521 */ 522 struct nand_ecc_step_info { 523 int stepsize; 524 const int *strengths; 525 int nstrengths; 526 }; 527 528 /** 529 * struct nand_ecc_caps - capability of ECC engine 530 * @stepinfos: array of ECC step information 531 * @nstepinfos: number of ECC step information 532 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 533 */ 534 struct nand_ecc_caps { 535 const struct nand_ecc_step_info *stepinfos; 536 int nstepinfos; 537 int (*calc_ecc_bytes)(int step_size, int strength); 538 }; 539 540 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 541 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 542 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 543 static const struct nand_ecc_step_info __name##_stepinfo = { \ 544 .stepsize = __step, \ 545 .strengths = __name##_strengths, \ 546 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 547 }; \ 548 static const struct nand_ecc_caps __name = { \ 549 .stepinfos = &__name##_stepinfo, \ 550 .nstepinfos = 1, \ 551 .calc_ecc_bytes = __calc, \ 552 } 553 554 /** 555 * struct nand_ecc_ctrl - Control structure for ECC 556 * @mode: ECC mode 557 * @algo: ECC algorithm 558 * @steps: number of ECC steps per page 559 * @size: data bytes per ECC step 560 * @bytes: ECC bytes per step 561 * @strength: max number of correctible bits per ECC step 562 * @total: total number of ECC bytes per page 563 * @prepad: padding information for syndrome based ECC generators 564 * @postpad: padding information for syndrome based ECC generators 565 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 566 * @priv: pointer to private ECC control data 567 * @calc_buf: buffer for calculated ECC, size is oobsize. 568 * @code_buf: buffer for ECC read from flash, size is oobsize. 569 * @hwctl: function to control hardware ECC generator. Must only 570 * be provided if an hardware ECC is available 571 * @calculate: function for ECC calculation or readback from ECC hardware 572 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 573 * Should return a positive number representing the number of 574 * corrected bitflips, -EBADMSG if the number of bitflips exceed 575 * ECC strength, or any other error code if the error is not 576 * directly related to correction. 577 * If -EBADMSG is returned the input buffers should be left 578 * untouched. 579 * @read_page_raw: function to read a raw page without ECC. This function 580 * should hide the specific layout used by the ECC 581 * controller and always return contiguous in-band and 582 * out-of-band data even if they're not stored 583 * contiguously on the NAND chip (e.g. 584 * NAND_ECC_HW_SYNDROME interleaves in-band and 585 * out-of-band data). 586 * @write_page_raw: function to write a raw page without ECC. This function 587 * should hide the specific layout used by the ECC 588 * controller and consider the passed data as contiguous 589 * in-band and out-of-band data. ECC controller is 590 * responsible for doing the appropriate transformations 591 * to adapt to its specific layout (e.g. 592 * NAND_ECC_HW_SYNDROME interleaves in-band and 593 * out-of-band data). 594 * @read_page: function to read a page according to the ECC generator 595 * requirements; returns maximum number of bitflips corrected in 596 * any single ECC step, -EIO hw error 597 * @read_subpage: function to read parts of the page covered by ECC; 598 * returns same as read_page() 599 * @write_subpage: function to write parts of the page covered by ECC. 600 * @write_page: function to write a page according to the ECC generator 601 * requirements. 602 * @write_oob_raw: function to write chip OOB data without ECC 603 * @read_oob_raw: function to read chip OOB data without ECC 604 * @read_oob: function to read chip OOB data 605 * @write_oob: function to write chip OOB data 606 */ 607 struct nand_ecc_ctrl { 608 nand_ecc_modes_t mode; 609 enum nand_ecc_algo algo; 610 int steps; 611 int size; 612 int bytes; 613 int total; 614 int strength; 615 int prepad; 616 int postpad; 617 unsigned int options; 618 void *priv; 619 u8 *calc_buf; 620 u8 *code_buf; 621 void (*hwctl)(struct mtd_info *mtd, int mode); 622 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 623 uint8_t *ecc_code); 624 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 625 uint8_t *calc_ecc); 626 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 627 uint8_t *buf, int oob_required, int page); 628 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 629 const uint8_t *buf, int oob_required, int page); 630 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 631 uint8_t *buf, int oob_required, int page); 632 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 633 uint32_t offs, uint32_t len, uint8_t *buf, int page); 634 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 635 uint32_t offset, uint32_t data_len, 636 const uint8_t *data_buf, int oob_required, int page); 637 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 638 const uint8_t *buf, int oob_required, int page); 639 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 640 int page); 641 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 642 int page); 643 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 644 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 645 int page); 646 }; 647 648 /** 649 * struct nand_sdr_timings - SDR NAND chip timings 650 * 651 * This struct defines the timing requirements of a SDR NAND chip. 652 * These information can be found in every NAND datasheets and the timings 653 * meaning are described in the ONFI specifications: 654 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 655 * Parameters) 656 * 657 * All these timings are expressed in picoseconds. 658 * 659 * @tBERS_max: Block erase time 660 * @tCCS_min: Change column setup time 661 * @tPROG_max: Page program time 662 * @tR_max: Page read time 663 * @tALH_min: ALE hold time 664 * @tADL_min: ALE to data loading time 665 * @tALS_min: ALE setup time 666 * @tAR_min: ALE to RE# delay 667 * @tCEA_max: CE# access time 668 * @tCEH_min: CE# high hold time 669 * @tCH_min: CE# hold time 670 * @tCHZ_max: CE# high to output hi-Z 671 * @tCLH_min: CLE hold time 672 * @tCLR_min: CLE to RE# delay 673 * @tCLS_min: CLE setup time 674 * @tCOH_min: CE# high to output hold 675 * @tCS_min: CE# setup time 676 * @tDH_min: Data hold time 677 * @tDS_min: Data setup time 678 * @tFEAT_max: Busy time for Set Features and Get Features 679 * @tIR_min: Output hi-Z to RE# low 680 * @tITC_max: Interface and Timing Mode Change time 681 * @tRC_min: RE# cycle time 682 * @tREA_max: RE# access time 683 * @tREH_min: RE# high hold time 684 * @tRHOH_min: RE# high to output hold 685 * @tRHW_min: RE# high to WE# low 686 * @tRHZ_max: RE# high to output hi-Z 687 * @tRLOH_min: RE# low to output hold 688 * @tRP_min: RE# pulse width 689 * @tRR_min: Ready to RE# low (data only) 690 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 691 * rising edge of R/B#. 692 * @tWB_max: WE# high to SR[6] low 693 * @tWC_min: WE# cycle time 694 * @tWH_min: WE# high hold time 695 * @tWHR_min: WE# high to RE# low 696 * @tWP_min: WE# pulse width 697 * @tWW_min: WP# transition to WE# low 698 */ 699 struct nand_sdr_timings { 700 u64 tBERS_max; 701 u32 tCCS_min; 702 u64 tPROG_max; 703 u64 tR_max; 704 u32 tALH_min; 705 u32 tADL_min; 706 u32 tALS_min; 707 u32 tAR_min; 708 u32 tCEA_max; 709 u32 tCEH_min; 710 u32 tCH_min; 711 u32 tCHZ_max; 712 u32 tCLH_min; 713 u32 tCLR_min; 714 u32 tCLS_min; 715 u32 tCOH_min; 716 u32 tCS_min; 717 u32 tDH_min; 718 u32 tDS_min; 719 u32 tFEAT_max; 720 u32 tIR_min; 721 u32 tITC_max; 722 u32 tRC_min; 723 u32 tREA_max; 724 u32 tREH_min; 725 u32 tRHOH_min; 726 u32 tRHW_min; 727 u32 tRHZ_max; 728 u32 tRLOH_min; 729 u32 tRP_min; 730 u32 tRR_min; 731 u64 tRST_max; 732 u32 tWB_max; 733 u32 tWC_min; 734 u32 tWH_min; 735 u32 tWHR_min; 736 u32 tWP_min; 737 u32 tWW_min; 738 }; 739 740 /** 741 * enum nand_data_interface_type - NAND interface timing type 742 * @NAND_SDR_IFACE: Single Data Rate interface 743 */ 744 enum nand_data_interface_type { 745 NAND_SDR_IFACE, 746 }; 747 748 /** 749 * struct nand_data_interface - NAND interface timing 750 * @type: type of the timing 751 * @timings: The timing, type according to @type 752 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 753 */ 754 struct nand_data_interface { 755 enum nand_data_interface_type type; 756 union { 757 struct nand_sdr_timings sdr; 758 } timings; 759 }; 760 761 /** 762 * nand_get_sdr_timings - get SDR timing from data interface 763 * @conf: The data interface 764 */ 765 static inline const struct nand_sdr_timings * 766 nand_get_sdr_timings(const struct nand_data_interface *conf) 767 { 768 if (conf->type != NAND_SDR_IFACE) 769 return ERR_PTR(-EINVAL); 770 771 return &conf->timings.sdr; 772 } 773 774 /** 775 * struct nand_manufacturer_ops - NAND Manufacturer operations 776 * @detect: detect the NAND memory organization and capabilities 777 * @init: initialize all vendor specific fields (like the ->read_retry() 778 * implementation) if any. 779 * @cleanup: the ->init() function may have allocated resources, ->cleanup() 780 * is here to let vendor specific code release those resources. 781 */ 782 struct nand_manufacturer_ops { 783 void (*detect)(struct nand_chip *chip); 784 int (*init)(struct nand_chip *chip); 785 void (*cleanup)(struct nand_chip *chip); 786 }; 787 788 /** 789 * struct nand_op_cmd_instr - Definition of a command instruction 790 * @opcode: the command to issue in one cycle 791 */ 792 struct nand_op_cmd_instr { 793 u8 opcode; 794 }; 795 796 /** 797 * struct nand_op_addr_instr - Definition of an address instruction 798 * @naddrs: length of the @addrs array 799 * @addrs: array containing the address cycles to issue 800 */ 801 struct nand_op_addr_instr { 802 unsigned int naddrs; 803 const u8 *addrs; 804 }; 805 806 /** 807 * struct nand_op_data_instr - Definition of a data instruction 808 * @len: number of data bytes to move 809 * @buf: buffer to fill 810 * @buf.in: buffer to fill when reading from the NAND chip 811 * @buf.out: buffer to read from when writing to the NAND chip 812 * @force_8bit: force 8-bit access 813 * 814 * Please note that "in" and "out" are inverted from the ONFI specification 815 * and are from the controller perspective, so a "in" is a read from the NAND 816 * chip while a "out" is a write to the NAND chip. 817 */ 818 struct nand_op_data_instr { 819 unsigned int len; 820 union { 821 void *in; 822 const void *out; 823 } buf; 824 bool force_8bit; 825 }; 826 827 /** 828 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 829 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 830 */ 831 struct nand_op_waitrdy_instr { 832 unsigned int timeout_ms; 833 }; 834 835 /** 836 * enum nand_op_instr_type - Definition of all instruction types 837 * @NAND_OP_CMD_INSTR: command instruction 838 * @NAND_OP_ADDR_INSTR: address instruction 839 * @NAND_OP_DATA_IN_INSTR: data in instruction 840 * @NAND_OP_DATA_OUT_INSTR: data out instruction 841 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 842 */ 843 enum nand_op_instr_type { 844 NAND_OP_CMD_INSTR, 845 NAND_OP_ADDR_INSTR, 846 NAND_OP_DATA_IN_INSTR, 847 NAND_OP_DATA_OUT_INSTR, 848 NAND_OP_WAITRDY_INSTR, 849 }; 850 851 /** 852 * struct nand_op_instr - Instruction object 853 * @type: the instruction type 854 * @ctx: extra data associated to the instruction. You'll have to use the 855 * appropriate element depending on @type 856 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 857 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 858 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 859 * or %NAND_OP_DATA_OUT_INSTR 860 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 861 * @delay_ns: delay the controller should apply after the instruction has been 862 * issued on the bus. Most modern controllers have internal timings 863 * control logic, and in this case, the controller driver can ignore 864 * this field. 865 */ 866 struct nand_op_instr { 867 enum nand_op_instr_type type; 868 union { 869 struct nand_op_cmd_instr cmd; 870 struct nand_op_addr_instr addr; 871 struct nand_op_data_instr data; 872 struct nand_op_waitrdy_instr waitrdy; 873 } ctx; 874 unsigned int delay_ns; 875 }; 876 877 /* 878 * Special handling must be done for the WAITRDY timeout parameter as it usually 879 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 880 * tBERS (during an erase) which all of them are u64 values that cannot be 881 * divided by usual kernel macros and must be handled with the special 882 * DIV_ROUND_UP_ULL() macro. 883 * 884 * Cast to type of dividend is needed here to guarantee that the result won't 885 * be an unsigned long long when the dividend is an unsigned long (or smaller), 886 * which is what the compiler does when it sees ternary operator with 2 887 * different return types (picks the largest type to make sure there's no 888 * loss). 889 */ 890 #define __DIVIDE(dividend, divisor) ({ \ 891 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 892 DIV_ROUND_UP(dividend, divisor) : \ 893 DIV_ROUND_UP_ULL(dividend, divisor)); \ 894 }) 895 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 896 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 897 898 #define NAND_OP_CMD(id, ns) \ 899 { \ 900 .type = NAND_OP_CMD_INSTR, \ 901 .ctx.cmd.opcode = id, \ 902 .delay_ns = ns, \ 903 } 904 905 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 906 { \ 907 .type = NAND_OP_ADDR_INSTR, \ 908 .ctx.addr = { \ 909 .naddrs = ncycles, \ 910 .addrs = cycles, \ 911 }, \ 912 .delay_ns = ns, \ 913 } 914 915 #define NAND_OP_DATA_IN(l, b, ns) \ 916 { \ 917 .type = NAND_OP_DATA_IN_INSTR, \ 918 .ctx.data = { \ 919 .len = l, \ 920 .buf.in = b, \ 921 .force_8bit = false, \ 922 }, \ 923 .delay_ns = ns, \ 924 } 925 926 #define NAND_OP_DATA_OUT(l, b, ns) \ 927 { \ 928 .type = NAND_OP_DATA_OUT_INSTR, \ 929 .ctx.data = { \ 930 .len = l, \ 931 .buf.out = b, \ 932 .force_8bit = false, \ 933 }, \ 934 .delay_ns = ns, \ 935 } 936 937 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 938 { \ 939 .type = NAND_OP_DATA_IN_INSTR, \ 940 .ctx.data = { \ 941 .len = l, \ 942 .buf.in = b, \ 943 .force_8bit = true, \ 944 }, \ 945 .delay_ns = ns, \ 946 } 947 948 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 949 { \ 950 .type = NAND_OP_DATA_OUT_INSTR, \ 951 .ctx.data = { \ 952 .len = l, \ 953 .buf.out = b, \ 954 .force_8bit = true, \ 955 }, \ 956 .delay_ns = ns, \ 957 } 958 959 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 960 { \ 961 .type = NAND_OP_WAITRDY_INSTR, \ 962 .ctx.waitrdy.timeout_ms = tout_ms, \ 963 .delay_ns = ns, \ 964 } 965 966 /** 967 * struct nand_subop - a sub operation 968 * @instrs: array of instructions 969 * @ninstrs: length of the @instrs array 970 * @first_instr_start_off: offset to start from for the first instruction 971 * of the sub-operation 972 * @last_instr_end_off: offset to end at (excluded) for the last instruction 973 * of the sub-operation 974 * 975 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 976 * address instructions. 977 * 978 * When an operation cannot be handled as is by the NAND controller, it will 979 * be split by the parser into sub-operations which will be passed to the 980 * controller driver. 981 */ 982 struct nand_subop { 983 const struct nand_op_instr *instrs; 984 unsigned int ninstrs; 985 unsigned int first_instr_start_off; 986 unsigned int last_instr_end_off; 987 }; 988 989 int nand_subop_get_addr_start_off(const struct nand_subop *subop, 990 unsigned int op_id); 991 int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 992 unsigned int op_id); 993 int nand_subop_get_data_start_off(const struct nand_subop *subop, 994 unsigned int op_id); 995 int nand_subop_get_data_len(const struct nand_subop *subop, 996 unsigned int op_id); 997 998 /** 999 * struct nand_op_parser_addr_constraints - Constraints for address instructions 1000 * @maxcycles: maximum number of address cycles the controller can issue in a 1001 * single step 1002 */ 1003 struct nand_op_parser_addr_constraints { 1004 unsigned int maxcycles; 1005 }; 1006 1007 /** 1008 * struct nand_op_parser_data_constraints - Constraints for data instructions 1009 * @maxlen: maximum data length that the controller can handle in a single step 1010 */ 1011 struct nand_op_parser_data_constraints { 1012 unsigned int maxlen; 1013 }; 1014 1015 /** 1016 * struct nand_op_parser_pattern_elem - One element of a pattern 1017 * @type: the instructuction type 1018 * @optional: whether this element of the pattern is optional or mandatory 1019 * @ctx: address or data constraint 1020 * @ctx.addr: address constraint (number of cycles) 1021 * @ctx.data: data constraint (data length) 1022 */ 1023 struct nand_op_parser_pattern_elem { 1024 enum nand_op_instr_type type; 1025 bool optional; 1026 union { 1027 struct nand_op_parser_addr_constraints addr; 1028 struct nand_op_parser_data_constraints data; 1029 } ctx; 1030 }; 1031 1032 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 1033 { \ 1034 .type = NAND_OP_CMD_INSTR, \ 1035 .optional = _opt, \ 1036 } 1037 1038 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 1039 { \ 1040 .type = NAND_OP_ADDR_INSTR, \ 1041 .optional = _opt, \ 1042 .ctx.addr.maxcycles = _maxcycles, \ 1043 } 1044 1045 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 1046 { \ 1047 .type = NAND_OP_DATA_IN_INSTR, \ 1048 .optional = _opt, \ 1049 .ctx.data.maxlen = _maxlen, \ 1050 } 1051 1052 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 1053 { \ 1054 .type = NAND_OP_DATA_OUT_INSTR, \ 1055 .optional = _opt, \ 1056 .ctx.data.maxlen = _maxlen, \ 1057 } 1058 1059 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 1060 { \ 1061 .type = NAND_OP_WAITRDY_INSTR, \ 1062 .optional = _opt, \ 1063 } 1064 1065 /** 1066 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 1067 * @elems: array of pattern elements 1068 * @nelems: number of pattern elements in @elems array 1069 * @exec: the function that will issue a sub-operation 1070 * 1071 * A pattern is a list of elements, each element reprensenting one instruction 1072 * with its constraints. The pattern itself is used by the core to match NAND 1073 * chip operation with NAND controller operations. 1074 * Once a match between a NAND controller operation pattern and a NAND chip 1075 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 1076 * hook is called so that the controller driver can issue the operation on the 1077 * bus. 1078 * 1079 * Controller drivers should declare as many patterns as they support and pass 1080 * this list of patterns (created with the help of the following macro) to 1081 * the nand_op_parser_exec_op() helper. 1082 */ 1083 struct nand_op_parser_pattern { 1084 const struct nand_op_parser_pattern_elem *elems; 1085 unsigned int nelems; 1086 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 1087 }; 1088 1089 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 1090 { \ 1091 .exec = _exec, \ 1092 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 1093 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 1094 sizeof(struct nand_op_parser_pattern_elem), \ 1095 } 1096 1097 /** 1098 * struct nand_op_parser - NAND controller operation parser descriptor 1099 * @patterns: array of supported patterns 1100 * @npatterns: length of the @patterns array 1101 * 1102 * The parser descriptor is just an array of supported patterns which will be 1103 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 1104 * NAND operation (or tries to determine if a specific operation is supported). 1105 * 1106 * It is worth mentioning that patterns will be tested in their declaration 1107 * order, and the first match will be taken, so it's important to order patterns 1108 * appropriately so that simple/inefficient patterns are placed at the end of 1109 * the list. Usually, this is where you put single instruction patterns. 1110 */ 1111 struct nand_op_parser { 1112 const struct nand_op_parser_pattern *patterns; 1113 unsigned int npatterns; 1114 }; 1115 1116 #define NAND_OP_PARSER(...) \ 1117 { \ 1118 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 1119 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 1120 sizeof(struct nand_op_parser_pattern), \ 1121 } 1122 1123 /** 1124 * struct nand_operation - NAND operation descriptor 1125 * @instrs: array of instructions to execute 1126 * @ninstrs: length of the @instrs array 1127 * 1128 * The actual operation structure that will be passed to chip->exec_op(). 1129 */ 1130 struct nand_operation { 1131 const struct nand_op_instr *instrs; 1132 unsigned int ninstrs; 1133 }; 1134 1135 #define NAND_OPERATION(_instrs) \ 1136 { \ 1137 .instrs = _instrs, \ 1138 .ninstrs = ARRAY_SIZE(_instrs), \ 1139 } 1140 1141 int nand_op_parser_exec_op(struct nand_chip *chip, 1142 const struct nand_op_parser *parser, 1143 const struct nand_operation *op, bool check_only); 1144 1145 /** 1146 * struct nand_chip - NAND Private Flash Chip Data 1147 * @mtd: MTD device registered to the MTD framework 1148 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 1149 * flash device 1150 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 1151 * flash device. 1152 * @read_byte: [REPLACEABLE] read one byte from the chip 1153 * @read_word: [REPLACEABLE] read one word from the chip 1154 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 1155 * low 8 I/O lines 1156 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 1157 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 1158 * @select_chip: [REPLACEABLE] select chip nr 1159 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 1160 * @block_markbad: [REPLACEABLE] mark a block bad 1161 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 1162 * ALE/CLE/nCE. Also used to write command and address 1163 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 1164 * device ready/busy line. If set to NULL no access to 1165 * ready/busy is available and the ready/busy information 1166 * is read from the chip status register. 1167 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 1168 * commands to the chip. 1169 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 1170 * ready. 1171 * @exec_op: controller specific method to execute NAND operations. 1172 * This method replaces ->cmdfunc(), 1173 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and 1174 * ->waifunc(). 1175 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 1176 * setting the read-retry mode. Mostly needed for MLC NAND. 1177 * @ecc: [BOARDSPECIFIC] ECC control structure 1178 * @buf_align: minimum buffer alignment required by a platform 1179 * @hwcontrol: platform-specific hardware control structure 1180 * @erase: [REPLACEABLE] erase function 1181 * @scan_bbt: [REPLACEABLE] function to scan bad block table 1182 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 1183 * data from array to read regs (tR). 1184 * @state: [INTERN] the current state of the NAND device 1185 * @oob_poi: "poison value buffer," used for laying out OOB data 1186 * before writing 1187 * @page_shift: [INTERN] number of address bits in a page (column 1188 * address bits). 1189 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 1190 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 1191 * @chip_shift: [INTERN] number of address bits in one chip 1192 * @options: [BOARDSPECIFIC] various chip options. They can partly 1193 * be set to inform nand_scan about special functionality. 1194 * See the defines for further explanation. 1195 * @bbt_options: [INTERN] bad block specific options. All options used 1196 * here must come from bbm.h. By default, these options 1197 * will be copied to the appropriate nand_bbt_descr's. 1198 * @badblockpos: [INTERN] position of the bad block marker in the oob 1199 * area. 1200 * @badblockbits: [INTERN] minimum number of set bits in a good block's 1201 * bad block marker position; i.e., BBM == 11110111b is 1202 * not bad when badblockbits == 7 1203 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 1204 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 1205 * Minimum amount of bit errors per @ecc_step_ds guaranteed 1206 * to be correctable. If unknown, set to zero. 1207 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 1208 * also from the datasheet. It is the recommended ECC step 1209 * size, if known; if unknown, set to zero. 1210 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1211 * set to the actually used ONFI mode if the chip is 1212 * ONFI compliant or deduced from the datasheet if 1213 * the NAND chip is not ONFI compliant. 1214 * @numchips: [INTERN] number of physical chips 1215 * @chipsize: [INTERN] the size of one chip for multichip arrays 1216 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1217 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1218 * @pagebuf: [INTERN] holds the pagenumber which is currently in 1219 * data_buf. 1220 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 1221 * currently in data_buf. 1222 * @subpagesize: [INTERN] holds the subpagesize 1223 * @id: [INTERN] holds NAND ID 1224 * @parameters: [INTERN] holds generic parameters under an easily 1225 * readable form. 1226 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 1227 * this nand device will encounter their life times. 1228 * @blocks_per_die: [INTERN] The number of PEBs in a die 1229 * @data_interface: [INTERN] NAND interface timing information 1230 * @read_retries: [INTERN] the number of read retry modes supported 1231 * @set_features: [REPLACEABLE] set the NAND chip features 1232 * @get_features: [REPLACEABLE] get the NAND chip features 1233 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 1234 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 1235 * means the configuration should not be applied but 1236 * only checked. 1237 * @bbt: [INTERN] bad block table pointer 1238 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1239 * lookup. 1240 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1241 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1242 * bad block scan. 1243 * @controller: [REPLACEABLE] a pointer to a hardware controller 1244 * structure which is shared among multiple independent 1245 * devices. 1246 * @priv: [OPTIONAL] pointer to private chip data 1247 * @manufacturer: [INTERN] Contains manufacturer information 1248 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1249 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1250 */ 1251 1252 struct nand_chip { 1253 struct mtd_info mtd; 1254 void __iomem *IO_ADDR_R; 1255 void __iomem *IO_ADDR_W; 1256 1257 uint8_t (*read_byte)(struct mtd_info *mtd); 1258 u16 (*read_word)(struct mtd_info *mtd); 1259 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 1260 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1261 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1262 void (*select_chip)(struct mtd_info *mtd, int chip); 1263 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 1264 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 1265 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1266 int (*dev_ready)(struct mtd_info *mtd); 1267 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 1268 int page_addr); 1269 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 1270 int (*exec_op)(struct nand_chip *chip, 1271 const struct nand_operation *op, 1272 bool check_only); 1273 int (*erase)(struct mtd_info *mtd, int page); 1274 int (*scan_bbt)(struct mtd_info *mtd); 1275 int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip, 1276 int feature_addr, uint8_t *subfeature_para); 1277 int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip, 1278 int feature_addr, uint8_t *subfeature_para); 1279 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 1280 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 1281 const struct nand_data_interface *conf); 1282 1283 int chip_delay; 1284 unsigned int options; 1285 unsigned int bbt_options; 1286 1287 int page_shift; 1288 int phys_erase_shift; 1289 int bbt_erase_shift; 1290 int chip_shift; 1291 int numchips; 1292 uint64_t chipsize; 1293 int pagemask; 1294 u8 *data_buf; 1295 int pagebuf; 1296 unsigned int pagebuf_bitflips; 1297 int subpagesize; 1298 uint8_t bits_per_cell; 1299 uint16_t ecc_strength_ds; 1300 uint16_t ecc_step_ds; 1301 int onfi_timing_mode_default; 1302 int badblockpos; 1303 int badblockbits; 1304 1305 struct nand_id id; 1306 struct nand_parameters parameters; 1307 u16 max_bb_per_die; 1308 u32 blocks_per_die; 1309 1310 struct nand_data_interface data_interface; 1311 1312 int read_retries; 1313 1314 flstate_t state; 1315 1316 uint8_t *oob_poi; 1317 struct nand_hw_control *controller; 1318 1319 struct nand_ecc_ctrl ecc; 1320 unsigned long buf_align; 1321 struct nand_hw_control hwcontrol; 1322 1323 uint8_t *bbt; 1324 struct nand_bbt_descr *bbt_td; 1325 struct nand_bbt_descr *bbt_md; 1326 1327 struct nand_bbt_descr *badblock_pattern; 1328 1329 void *priv; 1330 1331 struct { 1332 const struct nand_manufacturer *desc; 1333 void *priv; 1334 } manufacturer; 1335 }; 1336 1337 static inline int nand_exec_op(struct nand_chip *chip, 1338 const struct nand_operation *op) 1339 { 1340 if (!chip->exec_op) 1341 return -ENOTSUPP; 1342 1343 return chip->exec_op(chip, op, false); 1344 } 1345 1346 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1347 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1348 1349 static inline void nand_set_flash_node(struct nand_chip *chip, 1350 struct device_node *np) 1351 { 1352 mtd_set_of_node(&chip->mtd, np); 1353 } 1354 1355 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1356 { 1357 return mtd_get_of_node(&chip->mtd); 1358 } 1359 1360 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1361 { 1362 return container_of(mtd, struct nand_chip, mtd); 1363 } 1364 1365 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1366 { 1367 return &chip->mtd; 1368 } 1369 1370 static inline void *nand_get_controller_data(struct nand_chip *chip) 1371 { 1372 return chip->priv; 1373 } 1374 1375 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1376 { 1377 chip->priv = priv; 1378 } 1379 1380 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1381 void *priv) 1382 { 1383 chip->manufacturer.priv = priv; 1384 } 1385 1386 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1387 { 1388 return chip->manufacturer.priv; 1389 } 1390 1391 /* 1392 * NAND Flash Manufacturer ID Codes 1393 */ 1394 #define NAND_MFR_TOSHIBA 0x98 1395 #define NAND_MFR_ESMT 0xc8 1396 #define NAND_MFR_SAMSUNG 0xec 1397 #define NAND_MFR_FUJITSU 0x04 1398 #define NAND_MFR_NATIONAL 0x8f 1399 #define NAND_MFR_RENESAS 0x07 1400 #define NAND_MFR_STMICRO 0x20 1401 #define NAND_MFR_HYNIX 0xad 1402 #define NAND_MFR_MICRON 0x2c 1403 #define NAND_MFR_AMD 0x01 1404 #define NAND_MFR_MACRONIX 0xc2 1405 #define NAND_MFR_EON 0x92 1406 #define NAND_MFR_SANDISK 0x45 1407 #define NAND_MFR_INTEL 0x89 1408 #define NAND_MFR_ATO 0x9b 1409 #define NAND_MFR_WINBOND 0xef 1410 1411 1412 /* 1413 * A helper for defining older NAND chips where the second ID byte fully 1414 * defined the chip, including the geometry (chip size, eraseblock size, page 1415 * size). All these chips have 512 bytes NAND page size. 1416 */ 1417 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1418 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1419 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1420 1421 /* 1422 * A helper for defining newer chips which report their page size and 1423 * eraseblock size via the extended ID bytes. 1424 * 1425 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1426 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1427 * device ID now only represented a particular total chip size (and voltage, 1428 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1429 * using the same device ID. 1430 */ 1431 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1432 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1433 .options = (opts) } 1434 1435 #define NAND_ECC_INFO(_strength, _step) \ 1436 { .strength_ds = (_strength), .step_ds = (_step) } 1437 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1438 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1439 1440 /** 1441 * struct nand_flash_dev - NAND Flash Device ID Structure 1442 * @name: a human-readable name of the NAND chip 1443 * @dev_id: the device ID (the second byte of the full chip ID array) 1444 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1445 * memory address as @id[0]) 1446 * @dev_id: device ID part of the full chip ID array (refers the same memory 1447 * address as @id[1]) 1448 * @id: full device ID array 1449 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1450 * well as the eraseblock size) is determined from the extended NAND 1451 * chip ID array) 1452 * @chipsize: total chip size in MiB 1453 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1454 * @options: stores various chip bit options 1455 * @id_len: The valid length of the @id. 1456 * @oobsize: OOB size 1457 * @ecc: ECC correctability and step information from the datasheet. 1458 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1459 * @ecc_strength_ds in nand_chip{}. 1460 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1461 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1462 * For example, the "4bit ECC for each 512Byte" can be set with 1463 * NAND_ECC_INFO(4, 512). 1464 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1465 * reset. Should be deduced from timings described 1466 * in the datasheet. 1467 * 1468 */ 1469 struct nand_flash_dev { 1470 char *name; 1471 union { 1472 struct { 1473 uint8_t mfr_id; 1474 uint8_t dev_id; 1475 }; 1476 uint8_t id[NAND_MAX_ID_LEN]; 1477 }; 1478 unsigned int pagesize; 1479 unsigned int chipsize; 1480 unsigned int erasesize; 1481 unsigned int options; 1482 uint16_t id_len; 1483 uint16_t oobsize; 1484 struct { 1485 uint16_t strength_ds; 1486 uint16_t step_ds; 1487 } ecc; 1488 int onfi_timing_mode_default; 1489 }; 1490 1491 /** 1492 * struct nand_manufacturer - NAND Flash Manufacturer structure 1493 * @name: Manufacturer name 1494 * @id: manufacturer ID code of device. 1495 * @ops: manufacturer operations 1496 */ 1497 struct nand_manufacturer { 1498 int id; 1499 char *name; 1500 const struct nand_manufacturer_ops *ops; 1501 }; 1502 1503 const struct nand_manufacturer *nand_get_manufacturer(u8 id); 1504 1505 static inline const char * 1506 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 1507 { 1508 return manufacturer ? manufacturer->name : "Unknown"; 1509 } 1510 1511 extern struct nand_flash_dev nand_flash_ids[]; 1512 1513 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 1514 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; 1515 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; 1516 extern const struct nand_manufacturer_ops micron_nand_manuf_ops; 1517 extern const struct nand_manufacturer_ops amd_nand_manuf_ops; 1518 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; 1519 1520 int nand_default_bbt(struct mtd_info *mtd); 1521 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1522 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1523 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1524 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1525 int allowbbt); 1526 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1527 size_t *retlen, uint8_t *buf); 1528 1529 /** 1530 * struct platform_nand_chip - chip level device structure 1531 * @nr_chips: max. number of chips to scan for 1532 * @chip_offset: chip number offset 1533 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1534 * @partitions: mtd partition list 1535 * @chip_delay: R/B delay value in us 1536 * @options: Option flags, e.g. 16bit buswidth 1537 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1538 * @part_probe_types: NULL-terminated array of probe types 1539 */ 1540 struct platform_nand_chip { 1541 int nr_chips; 1542 int chip_offset; 1543 int nr_partitions; 1544 struct mtd_partition *partitions; 1545 int chip_delay; 1546 unsigned int options; 1547 unsigned int bbt_options; 1548 const char **part_probe_types; 1549 }; 1550 1551 /* Keep gcc happy */ 1552 struct platform_device; 1553 1554 /** 1555 * struct platform_nand_ctrl - controller level device structure 1556 * @probe: platform specific function to probe/setup hardware 1557 * @remove: platform specific function to remove/teardown hardware 1558 * @hwcontrol: platform specific hardware control structure 1559 * @dev_ready: platform specific function to read ready/busy pin 1560 * @select_chip: platform specific chip select function 1561 * @cmd_ctrl: platform specific function for controlling 1562 * ALE/CLE/nCE. Also used to write command and address 1563 * @write_buf: platform specific function for write buffer 1564 * @read_buf: platform specific function for read buffer 1565 * @read_byte: platform specific function to read one byte from chip 1566 * @priv: private data to transport driver specific settings 1567 * 1568 * All fields are optional and depend on the hardware driver requirements 1569 */ 1570 struct platform_nand_ctrl { 1571 int (*probe)(struct platform_device *pdev); 1572 void (*remove)(struct platform_device *pdev); 1573 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1574 int (*dev_ready)(struct mtd_info *mtd); 1575 void (*select_chip)(struct mtd_info *mtd, int chip); 1576 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1577 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1578 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1579 unsigned char (*read_byte)(struct mtd_info *mtd); 1580 void *priv; 1581 }; 1582 1583 /** 1584 * struct platform_nand_data - container structure for platform-specific data 1585 * @chip: chip level chip structure 1586 * @ctrl: controller level device structure 1587 */ 1588 struct platform_nand_data { 1589 struct platform_nand_chip chip; 1590 struct platform_nand_ctrl ctrl; 1591 }; 1592 1593 /* return the supported asynchronous timing mode. */ 1594 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1595 { 1596 if (!chip->parameters.onfi.version) 1597 return ONFI_TIMING_MODE_UNKNOWN; 1598 1599 return chip->parameters.onfi.async_timing_mode; 1600 } 1601 1602 int onfi_fill_data_interface(struct nand_chip *chip, 1603 enum nand_data_interface_type type, 1604 int timing_mode); 1605 1606 /* 1607 * Check if it is a SLC nand. 1608 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1609 * We do not distinguish the MLC and TLC now. 1610 */ 1611 static inline bool nand_is_slc(struct nand_chip *chip) 1612 { 1613 WARN(chip->bits_per_cell == 0, 1614 "chip->bits_per_cell is used uninitialized\n"); 1615 return chip->bits_per_cell == 1; 1616 } 1617 1618 /** 1619 * Check if the opcode's address should be sent only on the lower 8 bits 1620 * @command: opcode to check 1621 */ 1622 static inline int nand_opcode_8bits(unsigned int command) 1623 { 1624 switch (command) { 1625 case NAND_CMD_READID: 1626 case NAND_CMD_PARAM: 1627 case NAND_CMD_GET_FEATURES: 1628 case NAND_CMD_SET_FEATURES: 1629 return 1; 1630 default: 1631 break; 1632 } 1633 return 0; 1634 } 1635 1636 /* get timing characteristics from ONFI timing mode. */ 1637 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1638 1639 int nand_check_erased_ecc_chunk(void *data, int datalen, 1640 void *ecc, int ecclen, 1641 void *extraoob, int extraooblen, 1642 int threshold); 1643 1644 int nand_check_ecc_caps(struct nand_chip *chip, 1645 const struct nand_ecc_caps *caps, int oobavail); 1646 1647 int nand_match_ecc_req(struct nand_chip *chip, 1648 const struct nand_ecc_caps *caps, int oobavail); 1649 1650 int nand_maximize_ecc(struct nand_chip *chip, 1651 const struct nand_ecc_caps *caps, int oobavail); 1652 1653 /* Default write_oob implementation */ 1654 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1655 1656 /* Default write_oob syndrome implementation */ 1657 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1658 int page); 1659 1660 /* Default read_oob implementation */ 1661 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1662 1663 /* Default read_oob syndrome implementation */ 1664 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1665 int page); 1666 1667 /* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */ 1668 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param); 1669 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param); 1670 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1671 int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip, 1672 int addr, u8 *subfeature_param); 1673 1674 /* Default read_page_raw implementation */ 1675 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1676 uint8_t *buf, int oob_required, int page); 1677 1678 /* Default write_page_raw implementation */ 1679 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1680 const uint8_t *buf, int oob_required, int page); 1681 1682 /* Reset and initialize a NAND device */ 1683 int nand_reset(struct nand_chip *chip, int chipnr); 1684 1685 /* NAND operation helpers */ 1686 int nand_reset_op(struct nand_chip *chip); 1687 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1688 unsigned int len); 1689 int nand_status_op(struct nand_chip *chip, u8 *status); 1690 int nand_exit_status_op(struct nand_chip *chip); 1691 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1692 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1693 unsigned int offset_in_page, void *buf, unsigned int len); 1694 int nand_change_read_column_op(struct nand_chip *chip, 1695 unsigned int offset_in_page, void *buf, 1696 unsigned int len, bool force_8bit); 1697 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1698 unsigned int offset_in_page, void *buf, unsigned int len); 1699 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1700 unsigned int offset_in_page, const void *buf, 1701 unsigned int len); 1702 int nand_prog_page_end_op(struct nand_chip *chip); 1703 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1704 unsigned int offset_in_page, const void *buf, 1705 unsigned int len); 1706 int nand_change_write_column_op(struct nand_chip *chip, 1707 unsigned int offset_in_page, const void *buf, 1708 unsigned int len, bool force_8bit); 1709 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1710 bool force_8bit); 1711 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1712 unsigned int len, bool force_8bit); 1713 1714 /* Free resources held by the NAND device */ 1715 void nand_cleanup(struct nand_chip *chip); 1716 1717 /* Default extended ID decoding function */ 1718 void nand_decode_ext_id(struct nand_chip *chip); 1719 1720 /* 1721 * External helper for controller drivers that have to implement the WAITRDY 1722 * instruction and have no physical pin to check it. 1723 */ 1724 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1725 1726 #endif /* __LINUX_MTD_RAWNAND_H */ 1727