1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2000-2010 David Woodhouse <[email protected]> 4 * Steven J. Hill <[email protected]> 5 * Thomas Gleixner <[email protected]> 6 * 7 * Info: 8 * Contains standard defines and IDs for NAND flash devices 9 * 10 * Changelog: 11 * See git changelog. 12 */ 13 #ifndef __LINUX_MTD_RAWNAND_H 14 #define __LINUX_MTD_RAWNAND_H 15 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/nand.h> 18 #include <linux/mtd/flashchip.h> 19 #include <linux/mtd/bbm.h> 20 #include <linux/mtd/jedec.h> 21 #include <linux/mtd/nand.h> 22 #include <linux/mtd/onfi.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/types.h> 26 27 struct nand_chip; 28 29 /* The maximum number of NAND chips in an array */ 30 #define NAND_MAX_CHIPS 8 31 32 /* 33 * Constants for hardware specific CLE/ALE/NCE function 34 * 35 * These are bits which can be or'ed to set/clear multiple 36 * bits in one go. 37 */ 38 /* Select the chip by setting nCE to low */ 39 #define NAND_NCE 0x01 40 /* Select the command latch by setting CLE to high */ 41 #define NAND_CLE 0x02 42 /* Select the address latch by setting ALE to high */ 43 #define NAND_ALE 0x04 44 45 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 46 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 47 #define NAND_CTRL_CHANGE 0x80 48 49 /* 50 * Standard NAND flash commands 51 */ 52 #define NAND_CMD_READ0 0 53 #define NAND_CMD_READ1 1 54 #define NAND_CMD_RNDOUT 5 55 #define NAND_CMD_PAGEPROG 0x10 56 #define NAND_CMD_READOOB 0x50 57 #define NAND_CMD_ERASE1 0x60 58 #define NAND_CMD_STATUS 0x70 59 #define NAND_CMD_SEQIN 0x80 60 #define NAND_CMD_RNDIN 0x85 61 #define NAND_CMD_READID 0x90 62 #define NAND_CMD_ERASE2 0xd0 63 #define NAND_CMD_PARAM 0xec 64 #define NAND_CMD_GET_FEATURES 0xee 65 #define NAND_CMD_SET_FEATURES 0xef 66 #define NAND_CMD_RESET 0xff 67 68 /* Extended commands for large page devices */ 69 #define NAND_CMD_READSTART 0x30 70 #define NAND_CMD_RNDOUTSTART 0xE0 71 #define NAND_CMD_CACHEDPROG 0x15 72 73 #define NAND_CMD_NONE -1 74 75 /* Status bits */ 76 #define NAND_STATUS_FAIL 0x01 77 #define NAND_STATUS_FAIL_N1 0x02 78 #define NAND_STATUS_TRUE_READY 0x20 79 #define NAND_STATUS_READY 0x40 80 #define NAND_STATUS_WP 0x80 81 82 #define NAND_DATA_IFACE_CHECK_ONLY -1 83 84 /* 85 * Constants for Hardware ECC 86 */ 87 /* Reset Hardware ECC for read */ 88 #define NAND_ECC_READ 0 89 /* Reset Hardware ECC for write */ 90 #define NAND_ECC_WRITE 1 91 /* Enable Hardware ECC before syndrome is read back from flash */ 92 #define NAND_ECC_READSYN 2 93 94 /* 95 * Enable generic NAND 'page erased' check. This check is only done when 96 * ecc.correct() returns -EBADMSG. 97 * Set this flag if your implementation does not fix bitflips in erased 98 * pages and you want to rely on the default implementation. 99 */ 100 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 101 102 /* 103 * Option constants for bizarre disfunctionality and real 104 * features. 105 */ 106 107 /* Buswidth is 16 bit */ 108 #define NAND_BUSWIDTH_16 BIT(1) 109 110 /* 111 * When using software implementation of Hamming, we can specify which byte 112 * ordering should be used. 113 */ 114 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 115 116 /* Chip has cache program function */ 117 #define NAND_CACHEPRG BIT(3) 118 /* Options valid for Samsung large page devices */ 119 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 120 121 /* 122 * Chip requires ready check on read (for auto-incremented sequential read). 123 * True only for small page devices; large page devices do not support 124 * autoincrement. 125 */ 126 #define NAND_NEED_READRDY BIT(8) 127 128 /* Chip does not allow subpage writes */ 129 #define NAND_NO_SUBPAGE_WRITE BIT(9) 130 131 /* Device is one of 'new' xD cards that expose fake nand command set */ 132 #define NAND_BROKEN_XD BIT(10) 133 134 /* Device behaves just like nand, but is readonly */ 135 #define NAND_ROM BIT(11) 136 137 /* Device supports subpage reads */ 138 #define NAND_SUBPAGE_READ BIT(12) 139 /* Macros to identify the above */ 140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 141 142 /* 143 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 144 * patterns. 145 */ 146 #define NAND_NEED_SCRAMBLING BIT(13) 147 148 /* Device needs 3rd row address cycle */ 149 #define NAND_ROW_ADDR_3 BIT(14) 150 151 /* Non chip related options */ 152 /* This option skips the bbt scan during initialization. */ 153 #define NAND_SKIP_BBTSCAN BIT(16) 154 /* Chip may not exist, so silence any errors in scan */ 155 #define NAND_SCAN_SILENT_NODEV BIT(18) 156 157 /* 158 * Autodetect nand buswidth with readid/onfi. 159 * This suppose the driver will configure the hardware in 8 bits mode 160 * when calling nand_scan_ident, and update its configuration 161 * before calling nand_scan_tail. 162 */ 163 #define NAND_BUSWIDTH_AUTO BIT(19) 164 165 /* 166 * This option could be defined by controller drivers to protect against 167 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 168 */ 169 #define NAND_USES_DMA BIT(20) 170 171 /* 172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 173 * on the default ->cmdfunc() implementation, you may want to let the core 174 * handle the tCCS delay which is required when a column change (RNDIN or 175 * RNDOUT) is requested. 176 * If your controller already takes care of this delay, you don't need to set 177 * this flag. 178 */ 179 #define NAND_WAIT_TCCS BIT(21) 180 181 /* 182 * Whether the NAND chip is a boot medium. Drivers might use this information 183 * to select ECC algorithms supported by the boot ROM or similar restrictions. 184 */ 185 #define NAND_IS_BOOT_MEDIUM BIT(22) 186 187 /* 188 * Do not try to tweak the timings at runtime. This is needed when the 189 * controller initializes the timings on itself or when it relies on 190 * configuration done by the bootloader. 191 */ 192 #define NAND_KEEP_TIMINGS BIT(23) 193 194 /* 195 * There are different places where the manufacturer stores the factory bad 196 * block markers. 197 * 198 * Position within the block: Each of these pages needs to be checked for a 199 * bad block marking pattern. 200 */ 201 #define NAND_BBM_FIRSTPAGE BIT(24) 202 #define NAND_BBM_SECONDPAGE BIT(25) 203 #define NAND_BBM_LASTPAGE BIT(26) 204 205 /* 206 * Some controllers with pipelined ECC engines override the BBM marker with 207 * data or ECC bytes, thus making bad block detection through bad block marker 208 * impossible. Let's flag those chips so the core knows it shouldn't check the 209 * BBM and consider all blocks good. 210 */ 211 #define NAND_NO_BBM_QUIRK BIT(27) 212 213 /* Cell info constants */ 214 #define NAND_CI_CHIPNR_MSK 0x03 215 #define NAND_CI_CELLTYPE_MSK 0x0C 216 #define NAND_CI_CELLTYPE_SHIFT 2 217 218 /* Position within the OOB data of the page */ 219 #define NAND_BBM_POS_SMALL 5 220 #define NAND_BBM_POS_LARGE 0 221 222 /** 223 * struct nand_parameters - NAND generic parameters from the parameter page 224 * @model: Model name 225 * @supports_set_get_features: The NAND chip supports setting/getting features 226 * @set_feature_list: Bitmap of features that can be set 227 * @get_feature_list: Bitmap of features that can be get 228 * @onfi: ONFI specific parameters 229 */ 230 struct nand_parameters { 231 /* Generic parameters */ 232 const char *model; 233 bool supports_set_get_features; 234 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 235 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 236 237 /* ONFI parameters */ 238 struct onfi_params *onfi; 239 }; 240 241 /* The maximum expected count of bytes in the NAND ID sequence */ 242 #define NAND_MAX_ID_LEN 8 243 244 /** 245 * struct nand_id - NAND id structure 246 * @data: buffer containing the id bytes. 247 * @len: ID length. 248 */ 249 struct nand_id { 250 u8 data[NAND_MAX_ID_LEN]; 251 int len; 252 }; 253 254 /** 255 * struct nand_ecc_step_info - ECC step information of ECC engine 256 * @stepsize: data bytes per ECC step 257 * @strengths: array of supported strengths 258 * @nstrengths: number of supported strengths 259 */ 260 struct nand_ecc_step_info { 261 int stepsize; 262 const int *strengths; 263 int nstrengths; 264 }; 265 266 /** 267 * struct nand_ecc_caps - capability of ECC engine 268 * @stepinfos: array of ECC step information 269 * @nstepinfos: number of ECC step information 270 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 271 */ 272 struct nand_ecc_caps { 273 const struct nand_ecc_step_info *stepinfos; 274 int nstepinfos; 275 int (*calc_ecc_bytes)(int step_size, int strength); 276 }; 277 278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 279 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 280 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 281 static const struct nand_ecc_step_info __name##_stepinfo = { \ 282 .stepsize = __step, \ 283 .strengths = __name##_strengths, \ 284 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 285 }; \ 286 static const struct nand_ecc_caps __name = { \ 287 .stepinfos = &__name##_stepinfo, \ 288 .nstepinfos = 1, \ 289 .calc_ecc_bytes = __calc, \ 290 } 291 292 /** 293 * struct nand_ecc_ctrl - Control structure for ECC 294 * @engine_type: ECC engine type 295 * @placement: OOB bytes placement 296 * @algo: ECC algorithm 297 * @steps: number of ECC steps per page 298 * @size: data bytes per ECC step 299 * @bytes: ECC bytes per step 300 * @strength: max number of correctible bits per ECC step 301 * @total: total number of ECC bytes per page 302 * @prepad: padding information for syndrome based ECC generators 303 * @postpad: padding information for syndrome based ECC generators 304 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 305 * @calc_buf: buffer for calculated ECC, size is oobsize. 306 * @code_buf: buffer for ECC read from flash, size is oobsize. 307 * @hwctl: function to control hardware ECC generator. Must only 308 * be provided if an hardware ECC is available 309 * @calculate: function for ECC calculation or readback from ECC hardware 310 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 311 * Should return a positive number representing the number of 312 * corrected bitflips, -EBADMSG if the number of bitflips exceed 313 * ECC strength, or any other error code if the error is not 314 * directly related to correction. 315 * If -EBADMSG is returned the input buffers should be left 316 * untouched. 317 * @read_page_raw: function to read a raw page without ECC. This function 318 * should hide the specific layout used by the ECC 319 * controller and always return contiguous in-band and 320 * out-of-band data even if they're not stored 321 * contiguously on the NAND chip (e.g. 322 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 323 * out-of-band data). 324 * @write_page_raw: function to write a raw page without ECC. This function 325 * should hide the specific layout used by the ECC 326 * controller and consider the passed data as contiguous 327 * in-band and out-of-band data. ECC controller is 328 * responsible for doing the appropriate transformations 329 * to adapt to its specific layout (e.g. 330 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 331 * out-of-band data). 332 * @read_page: function to read a page according to the ECC generator 333 * requirements; returns maximum number of bitflips corrected in 334 * any single ECC step, -EIO hw error 335 * @read_subpage: function to read parts of the page covered by ECC; 336 * returns same as read_page() 337 * @write_subpage: function to write parts of the page covered by ECC. 338 * @write_page: function to write a page according to the ECC generator 339 * requirements. 340 * @write_oob_raw: function to write chip OOB data without ECC 341 * @read_oob_raw: function to read chip OOB data without ECC 342 * @read_oob: function to read chip OOB data 343 * @write_oob: function to write chip OOB data 344 */ 345 struct nand_ecc_ctrl { 346 enum nand_ecc_engine_type engine_type; 347 enum nand_ecc_placement placement; 348 enum nand_ecc_algo algo; 349 int steps; 350 int size; 351 int bytes; 352 int total; 353 int strength; 354 int prepad; 355 int postpad; 356 unsigned int options; 357 u8 *calc_buf; 358 u8 *code_buf; 359 void (*hwctl)(struct nand_chip *chip, int mode); 360 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 361 uint8_t *ecc_code); 362 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 363 uint8_t *calc_ecc); 364 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 365 int oob_required, int page); 366 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 367 int oob_required, int page); 368 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 369 int oob_required, int page); 370 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 371 uint32_t len, uint8_t *buf, int page); 372 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 373 uint32_t data_len, const uint8_t *data_buf, 374 int oob_required, int page); 375 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 376 int oob_required, int page); 377 int (*write_oob_raw)(struct nand_chip *chip, int page); 378 int (*read_oob_raw)(struct nand_chip *chip, int page); 379 int (*read_oob)(struct nand_chip *chip, int page); 380 int (*write_oob)(struct nand_chip *chip, int page); 381 }; 382 383 /** 384 * struct nand_sdr_timings - SDR NAND chip timings 385 * 386 * This struct defines the timing requirements of a SDR NAND chip. 387 * These information can be found in every NAND datasheets and the timings 388 * meaning are described in the ONFI specifications: 389 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 390 * Parameters) 391 * 392 * All these timings are expressed in picoseconds. 393 * 394 * @tBERS_max: Block erase time 395 * @tCCS_min: Change column setup time 396 * @tPROG_max: Page program time 397 * @tR_max: Page read time 398 * @tALH_min: ALE hold time 399 * @tADL_min: ALE to data loading time 400 * @tALS_min: ALE setup time 401 * @tAR_min: ALE to RE# delay 402 * @tCEA_max: CE# access time 403 * @tCEH_min: CE# high hold time 404 * @tCH_min: CE# hold time 405 * @tCHZ_max: CE# high to output hi-Z 406 * @tCLH_min: CLE hold time 407 * @tCLR_min: CLE to RE# delay 408 * @tCLS_min: CLE setup time 409 * @tCOH_min: CE# high to output hold 410 * @tCS_min: CE# setup time 411 * @tDH_min: Data hold time 412 * @tDS_min: Data setup time 413 * @tFEAT_max: Busy time for Set Features and Get Features 414 * @tIR_min: Output hi-Z to RE# low 415 * @tITC_max: Interface and Timing Mode Change time 416 * @tRC_min: RE# cycle time 417 * @tREA_max: RE# access time 418 * @tREH_min: RE# high hold time 419 * @tRHOH_min: RE# high to output hold 420 * @tRHW_min: RE# high to WE# low 421 * @tRHZ_max: RE# high to output hi-Z 422 * @tRLOH_min: RE# low to output hold 423 * @tRP_min: RE# pulse width 424 * @tRR_min: Ready to RE# low (data only) 425 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 426 * rising edge of R/B#. 427 * @tWB_max: WE# high to SR[6] low 428 * @tWC_min: WE# cycle time 429 * @tWH_min: WE# high hold time 430 * @tWHR_min: WE# high to RE# low 431 * @tWP_min: WE# pulse width 432 * @tWW_min: WP# transition to WE# low 433 */ 434 struct nand_sdr_timings { 435 u64 tBERS_max; 436 u32 tCCS_min; 437 u64 tPROG_max; 438 u64 tR_max; 439 u32 tALH_min; 440 u32 tADL_min; 441 u32 tALS_min; 442 u32 tAR_min; 443 u32 tCEA_max; 444 u32 tCEH_min; 445 u32 tCH_min; 446 u32 tCHZ_max; 447 u32 tCLH_min; 448 u32 tCLR_min; 449 u32 tCLS_min; 450 u32 tCOH_min; 451 u32 tCS_min; 452 u32 tDH_min; 453 u32 tDS_min; 454 u32 tFEAT_max; 455 u32 tIR_min; 456 u32 tITC_max; 457 u32 tRC_min; 458 u32 tREA_max; 459 u32 tREH_min; 460 u32 tRHOH_min; 461 u32 tRHW_min; 462 u32 tRHZ_max; 463 u32 tRLOH_min; 464 u32 tRP_min; 465 u32 tRR_min; 466 u64 tRST_max; 467 u32 tWB_max; 468 u32 tWC_min; 469 u32 tWH_min; 470 u32 tWHR_min; 471 u32 tWP_min; 472 u32 tWW_min; 473 }; 474 475 /** 476 * enum nand_interface_type - NAND interface type 477 * @NAND_SDR_IFACE: Single Data Rate interface 478 */ 479 enum nand_interface_type { 480 NAND_SDR_IFACE, 481 }; 482 483 /** 484 * struct nand_interface_config - NAND interface timing 485 * @type: type of the timing 486 * @timings: The timing information 487 * @timings.mode: Timing mode as defined in the specification 488 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 489 */ 490 struct nand_interface_config { 491 enum nand_interface_type type; 492 struct nand_timings { 493 unsigned int mode; 494 union { 495 struct nand_sdr_timings sdr; 496 }; 497 } timings; 498 }; 499 500 /** 501 * nand_get_sdr_timings - get SDR timing from data interface 502 * @conf: The data interface 503 */ 504 static inline const struct nand_sdr_timings * 505 nand_get_sdr_timings(const struct nand_interface_config *conf) 506 { 507 if (conf->type != NAND_SDR_IFACE) 508 return ERR_PTR(-EINVAL); 509 510 return &conf->timings.sdr; 511 } 512 513 /** 514 * struct nand_op_cmd_instr - Definition of a command instruction 515 * @opcode: the command to issue in one cycle 516 */ 517 struct nand_op_cmd_instr { 518 u8 opcode; 519 }; 520 521 /** 522 * struct nand_op_addr_instr - Definition of an address instruction 523 * @naddrs: length of the @addrs array 524 * @addrs: array containing the address cycles to issue 525 */ 526 struct nand_op_addr_instr { 527 unsigned int naddrs; 528 const u8 *addrs; 529 }; 530 531 /** 532 * struct nand_op_data_instr - Definition of a data instruction 533 * @len: number of data bytes to move 534 * @buf: buffer to fill 535 * @buf.in: buffer to fill when reading from the NAND chip 536 * @buf.out: buffer to read from when writing to the NAND chip 537 * @force_8bit: force 8-bit access 538 * 539 * Please note that "in" and "out" are inverted from the ONFI specification 540 * and are from the controller perspective, so a "in" is a read from the NAND 541 * chip while a "out" is a write to the NAND chip. 542 */ 543 struct nand_op_data_instr { 544 unsigned int len; 545 union { 546 void *in; 547 const void *out; 548 } buf; 549 bool force_8bit; 550 }; 551 552 /** 553 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 554 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 555 */ 556 struct nand_op_waitrdy_instr { 557 unsigned int timeout_ms; 558 }; 559 560 /** 561 * enum nand_op_instr_type - Definition of all instruction types 562 * @NAND_OP_CMD_INSTR: command instruction 563 * @NAND_OP_ADDR_INSTR: address instruction 564 * @NAND_OP_DATA_IN_INSTR: data in instruction 565 * @NAND_OP_DATA_OUT_INSTR: data out instruction 566 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 567 */ 568 enum nand_op_instr_type { 569 NAND_OP_CMD_INSTR, 570 NAND_OP_ADDR_INSTR, 571 NAND_OP_DATA_IN_INSTR, 572 NAND_OP_DATA_OUT_INSTR, 573 NAND_OP_WAITRDY_INSTR, 574 }; 575 576 /** 577 * struct nand_op_instr - Instruction object 578 * @type: the instruction type 579 * @ctx: extra data associated to the instruction. You'll have to use the 580 * appropriate element depending on @type 581 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 582 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 583 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 584 * or %NAND_OP_DATA_OUT_INSTR 585 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 586 * @delay_ns: delay the controller should apply after the instruction has been 587 * issued on the bus. Most modern controllers have internal timings 588 * control logic, and in this case, the controller driver can ignore 589 * this field. 590 */ 591 struct nand_op_instr { 592 enum nand_op_instr_type type; 593 union { 594 struct nand_op_cmd_instr cmd; 595 struct nand_op_addr_instr addr; 596 struct nand_op_data_instr data; 597 struct nand_op_waitrdy_instr waitrdy; 598 } ctx; 599 unsigned int delay_ns; 600 }; 601 602 /* 603 * Special handling must be done for the WAITRDY timeout parameter as it usually 604 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 605 * tBERS (during an erase) which all of them are u64 values that cannot be 606 * divided by usual kernel macros and must be handled with the special 607 * DIV_ROUND_UP_ULL() macro. 608 * 609 * Cast to type of dividend is needed here to guarantee that the result won't 610 * be an unsigned long long when the dividend is an unsigned long (or smaller), 611 * which is what the compiler does when it sees ternary operator with 2 612 * different return types (picks the largest type to make sure there's no 613 * loss). 614 */ 615 #define __DIVIDE(dividend, divisor) ({ \ 616 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 617 DIV_ROUND_UP(dividend, divisor) : \ 618 DIV_ROUND_UP_ULL(dividend, divisor)); \ 619 }) 620 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 621 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 622 623 #define NAND_OP_CMD(id, ns) \ 624 { \ 625 .type = NAND_OP_CMD_INSTR, \ 626 .ctx.cmd.opcode = id, \ 627 .delay_ns = ns, \ 628 } 629 630 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 631 { \ 632 .type = NAND_OP_ADDR_INSTR, \ 633 .ctx.addr = { \ 634 .naddrs = ncycles, \ 635 .addrs = cycles, \ 636 }, \ 637 .delay_ns = ns, \ 638 } 639 640 #define NAND_OP_DATA_IN(l, b, ns) \ 641 { \ 642 .type = NAND_OP_DATA_IN_INSTR, \ 643 .ctx.data = { \ 644 .len = l, \ 645 .buf.in = b, \ 646 .force_8bit = false, \ 647 }, \ 648 .delay_ns = ns, \ 649 } 650 651 #define NAND_OP_DATA_OUT(l, b, ns) \ 652 { \ 653 .type = NAND_OP_DATA_OUT_INSTR, \ 654 .ctx.data = { \ 655 .len = l, \ 656 .buf.out = b, \ 657 .force_8bit = false, \ 658 }, \ 659 .delay_ns = ns, \ 660 } 661 662 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 663 { \ 664 .type = NAND_OP_DATA_IN_INSTR, \ 665 .ctx.data = { \ 666 .len = l, \ 667 .buf.in = b, \ 668 .force_8bit = true, \ 669 }, \ 670 .delay_ns = ns, \ 671 } 672 673 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 674 { \ 675 .type = NAND_OP_DATA_OUT_INSTR, \ 676 .ctx.data = { \ 677 .len = l, \ 678 .buf.out = b, \ 679 .force_8bit = true, \ 680 }, \ 681 .delay_ns = ns, \ 682 } 683 684 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 685 { \ 686 .type = NAND_OP_WAITRDY_INSTR, \ 687 .ctx.waitrdy.timeout_ms = tout_ms, \ 688 .delay_ns = ns, \ 689 } 690 691 /** 692 * struct nand_subop - a sub operation 693 * @cs: the CS line to select for this NAND sub-operation 694 * @instrs: array of instructions 695 * @ninstrs: length of the @instrs array 696 * @first_instr_start_off: offset to start from for the first instruction 697 * of the sub-operation 698 * @last_instr_end_off: offset to end at (excluded) for the last instruction 699 * of the sub-operation 700 * 701 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 702 * address instructions. 703 * 704 * When an operation cannot be handled as is by the NAND controller, it will 705 * be split by the parser into sub-operations which will be passed to the 706 * controller driver. 707 */ 708 struct nand_subop { 709 unsigned int cs; 710 const struct nand_op_instr *instrs; 711 unsigned int ninstrs; 712 unsigned int first_instr_start_off; 713 unsigned int last_instr_end_off; 714 }; 715 716 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 717 unsigned int op_id); 718 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 719 unsigned int op_id); 720 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 721 unsigned int op_id); 722 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 723 unsigned int op_id); 724 725 /** 726 * struct nand_op_parser_addr_constraints - Constraints for address instructions 727 * @maxcycles: maximum number of address cycles the controller can issue in a 728 * single step 729 */ 730 struct nand_op_parser_addr_constraints { 731 unsigned int maxcycles; 732 }; 733 734 /** 735 * struct nand_op_parser_data_constraints - Constraints for data instructions 736 * @maxlen: maximum data length that the controller can handle in a single step 737 */ 738 struct nand_op_parser_data_constraints { 739 unsigned int maxlen; 740 }; 741 742 /** 743 * struct nand_op_parser_pattern_elem - One element of a pattern 744 * @type: the instructuction type 745 * @optional: whether this element of the pattern is optional or mandatory 746 * @ctx: address or data constraint 747 * @ctx.addr: address constraint (number of cycles) 748 * @ctx.data: data constraint (data length) 749 */ 750 struct nand_op_parser_pattern_elem { 751 enum nand_op_instr_type type; 752 bool optional; 753 union { 754 struct nand_op_parser_addr_constraints addr; 755 struct nand_op_parser_data_constraints data; 756 } ctx; 757 }; 758 759 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 760 { \ 761 .type = NAND_OP_CMD_INSTR, \ 762 .optional = _opt, \ 763 } 764 765 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 766 { \ 767 .type = NAND_OP_ADDR_INSTR, \ 768 .optional = _opt, \ 769 .ctx.addr.maxcycles = _maxcycles, \ 770 } 771 772 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 773 { \ 774 .type = NAND_OP_DATA_IN_INSTR, \ 775 .optional = _opt, \ 776 .ctx.data.maxlen = _maxlen, \ 777 } 778 779 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 780 { \ 781 .type = NAND_OP_DATA_OUT_INSTR, \ 782 .optional = _opt, \ 783 .ctx.data.maxlen = _maxlen, \ 784 } 785 786 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 787 { \ 788 .type = NAND_OP_WAITRDY_INSTR, \ 789 .optional = _opt, \ 790 } 791 792 /** 793 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 794 * @elems: array of pattern elements 795 * @nelems: number of pattern elements in @elems array 796 * @exec: the function that will issue a sub-operation 797 * 798 * A pattern is a list of elements, each element reprensenting one instruction 799 * with its constraints. The pattern itself is used by the core to match NAND 800 * chip operation with NAND controller operations. 801 * Once a match between a NAND controller operation pattern and a NAND chip 802 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 803 * hook is called so that the controller driver can issue the operation on the 804 * bus. 805 * 806 * Controller drivers should declare as many patterns as they support and pass 807 * this list of patterns (created with the help of the following macro) to 808 * the nand_op_parser_exec_op() helper. 809 */ 810 struct nand_op_parser_pattern { 811 const struct nand_op_parser_pattern_elem *elems; 812 unsigned int nelems; 813 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 814 }; 815 816 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 817 { \ 818 .exec = _exec, \ 819 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 820 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 821 sizeof(struct nand_op_parser_pattern_elem), \ 822 } 823 824 /** 825 * struct nand_op_parser - NAND controller operation parser descriptor 826 * @patterns: array of supported patterns 827 * @npatterns: length of the @patterns array 828 * 829 * The parser descriptor is just an array of supported patterns which will be 830 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 831 * NAND operation (or tries to determine if a specific operation is supported). 832 * 833 * It is worth mentioning that patterns will be tested in their declaration 834 * order, and the first match will be taken, so it's important to order patterns 835 * appropriately so that simple/inefficient patterns are placed at the end of 836 * the list. Usually, this is where you put single instruction patterns. 837 */ 838 struct nand_op_parser { 839 const struct nand_op_parser_pattern *patterns; 840 unsigned int npatterns; 841 }; 842 843 #define NAND_OP_PARSER(...) \ 844 { \ 845 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 846 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 847 sizeof(struct nand_op_parser_pattern), \ 848 } 849 850 /** 851 * struct nand_operation - NAND operation descriptor 852 * @cs: the CS line to select for this NAND operation 853 * @instrs: array of instructions to execute 854 * @ninstrs: length of the @instrs array 855 * 856 * The actual operation structure that will be passed to chip->exec_op(). 857 */ 858 struct nand_operation { 859 unsigned int cs; 860 const struct nand_op_instr *instrs; 861 unsigned int ninstrs; 862 }; 863 864 #define NAND_OPERATION(_cs, _instrs) \ 865 { \ 866 .cs = _cs, \ 867 .instrs = _instrs, \ 868 .ninstrs = ARRAY_SIZE(_instrs), \ 869 } 870 871 int nand_op_parser_exec_op(struct nand_chip *chip, 872 const struct nand_op_parser *parser, 873 const struct nand_operation *op, bool check_only); 874 875 static inline void nand_op_trace(const char *prefix, 876 const struct nand_op_instr *instr) 877 { 878 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) 879 switch (instr->type) { 880 case NAND_OP_CMD_INSTR: 881 pr_debug("%sCMD [0x%02x]\n", prefix, 882 instr->ctx.cmd.opcode); 883 break; 884 case NAND_OP_ADDR_INSTR: 885 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix, 886 instr->ctx.addr.naddrs, 887 instr->ctx.addr.naddrs < 64 ? 888 instr->ctx.addr.naddrs : 64, 889 instr->ctx.addr.addrs); 890 break; 891 case NAND_OP_DATA_IN_INSTR: 892 pr_debug("%sDATA_IN [%d B%s]\n", prefix, 893 instr->ctx.data.len, 894 instr->ctx.data.force_8bit ? 895 ", force 8-bit" : ""); 896 break; 897 case NAND_OP_DATA_OUT_INSTR: 898 pr_debug("%sDATA_OUT [%d B%s]\n", prefix, 899 instr->ctx.data.len, 900 instr->ctx.data.force_8bit ? 901 ", force 8-bit" : ""); 902 break; 903 case NAND_OP_WAITRDY_INSTR: 904 pr_debug("%sWAITRDY [max %d ms]\n", prefix, 905 instr->ctx.waitrdy.timeout_ms); 906 break; 907 } 908 #endif 909 } 910 911 /** 912 * struct nand_controller_ops - Controller operations 913 * 914 * @attach_chip: this method is called after the NAND detection phase after 915 * flash ID and MTD fields such as erase size, page size and OOB 916 * size have been set up. ECC requirements are available if 917 * provided by the NAND chip or device tree. Typically used to 918 * choose the appropriate ECC configuration and allocate 919 * associated resources. 920 * This hook is optional. 921 * @detach_chip: free all resources allocated/claimed in 922 * nand_controller_ops->attach_chip(). 923 * This hook is optional. 924 * @exec_op: controller specific method to execute NAND operations. 925 * This method replaces chip->legacy.cmdfunc(), 926 * chip->legacy.{read,write}_{buf,byte,word}(), 927 * chip->legacy.dev_ready() and chip->legacy.waifunc(). 928 * @setup_interface: setup the data interface and timing. If chipnr is set to 929 * %NAND_DATA_IFACE_CHECK_ONLY this means the configuration 930 * should not be applied but only checked. 931 * This hook is optional. 932 */ 933 struct nand_controller_ops { 934 int (*attach_chip)(struct nand_chip *chip); 935 void (*detach_chip)(struct nand_chip *chip); 936 int (*exec_op)(struct nand_chip *chip, 937 const struct nand_operation *op, 938 bool check_only); 939 int (*setup_interface)(struct nand_chip *chip, int chipnr, 940 const struct nand_interface_config *conf); 941 }; 942 943 /** 944 * struct nand_controller - Structure used to describe a NAND controller 945 * 946 * @lock: lock used to serialize accesses to the NAND controller 947 * @ops: NAND controller operations. 948 */ 949 struct nand_controller { 950 struct mutex lock; 951 const struct nand_controller_ops *ops; 952 }; 953 954 static inline void nand_controller_init(struct nand_controller *nfc) 955 { 956 mutex_init(&nfc->lock); 957 } 958 959 /** 960 * struct nand_legacy - NAND chip legacy fields/hooks 961 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 962 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 963 * @select_chip: select/deselect a specific target/die 964 * @read_byte: read one byte from the chip 965 * @write_byte: write a single byte to the chip on the low 8 I/O lines 966 * @write_buf: write data from the buffer to the chip 967 * @read_buf: read data from the chip into the buffer 968 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 969 * to write command and address 970 * @cmdfunc: hardware specific function for writing commands to the chip. 971 * @dev_ready: hardware specific function for accessing device ready/busy line. 972 * If set to NULL no access to ready/busy is available and the 973 * ready/busy information is read from the chip status register. 974 * @waitfunc: hardware specific function for wait on ready. 975 * @block_bad: check if a block is bad, using OOB markers 976 * @block_markbad: mark a block bad 977 * @set_features: set the NAND chip features 978 * @get_features: get the NAND chip features 979 * @chip_delay: chip dependent delay for transferring data from array to read 980 * regs (tR). 981 * @dummy_controller: dummy controller implementation for drivers that can 982 * only control a single chip 983 * 984 * If you look at this structure you're already wrong. These fields/hooks are 985 * all deprecated. 986 */ 987 struct nand_legacy { 988 void __iomem *IO_ADDR_R; 989 void __iomem *IO_ADDR_W; 990 void (*select_chip)(struct nand_chip *chip, int cs); 991 u8 (*read_byte)(struct nand_chip *chip); 992 void (*write_byte)(struct nand_chip *chip, u8 byte); 993 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 994 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 995 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 996 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 997 int page_addr); 998 int (*dev_ready)(struct nand_chip *chip); 999 int (*waitfunc)(struct nand_chip *chip); 1000 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 1001 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 1002 int (*set_features)(struct nand_chip *chip, int feature_addr, 1003 u8 *subfeature_para); 1004 int (*get_features)(struct nand_chip *chip, int feature_addr, 1005 u8 *subfeature_para); 1006 int chip_delay; 1007 struct nand_controller dummy_controller; 1008 }; 1009 1010 /** 1011 * struct nand_chip_ops - NAND chip operations 1012 * @suspend: Suspend operation 1013 * @resume: Resume operation 1014 * @lock_area: Lock operation 1015 * @unlock_area: Unlock operation 1016 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs) 1017 * @choose_interface_config: Choose the best interface configuration 1018 */ 1019 struct nand_chip_ops { 1020 int (*suspend)(struct nand_chip *chip); 1021 void (*resume)(struct nand_chip *chip); 1022 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1023 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1024 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1025 int (*choose_interface_config)(struct nand_chip *chip, 1026 struct nand_interface_config *iface); 1027 }; 1028 1029 /** 1030 * struct nand_manufacturer - NAND manufacturer structure 1031 * @desc: The manufacturer description 1032 * @priv: Private information for the manufacturer driver 1033 */ 1034 struct nand_manufacturer { 1035 const struct nand_manufacturer_desc *desc; 1036 void *priv; 1037 }; 1038 1039 /** 1040 * struct nand_chip - NAND Private Flash Chip Data 1041 * @base: Inherit from the generic NAND device 1042 * @id: Holds NAND ID 1043 * @parameters: Holds generic parameters under an easily readable form 1044 * @manufacturer: Manufacturer information 1045 * @ops: NAND chip operations 1046 * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try 1047 * to use any of these fields/hooks, and if you're modifying an 1048 * existing driver that is using those fields/hooks, you should 1049 * consider reworking the driver and avoid using them. 1050 * @options: Various chip options. They can partly be set to inform nand_scan 1051 * about special functionality. See the defines for further 1052 * explanation. 1053 * @current_interface_config: The currently used NAND interface configuration 1054 * @best_interface_config: The best NAND interface configuration which fits both 1055 * the NAND chip and NAND controller constraints. If 1056 * unset, the default reset interface configuration must 1057 * be used. 1058 * @bbt_erase_shift: Number of address bits in a bbt entry 1059 * @bbt_options: Bad block table specific options. All options used here must 1060 * come from bbm.h. By default, these options will be copied to 1061 * the appropriate nand_bbt_descr's. 1062 * @badblockpos: Bad block marker position in the oob area 1063 * @badblockbits: Minimum number of set bits in a good block's bad block marker 1064 * position; i.e., BBM = 11110111b is good when badblockbits = 7 1065 * @bbt_td: Bad block table descriptor for flash lookup 1066 * @bbt_md: Bad block table mirror descriptor 1067 * @badblock_pattern: Bad block scan pattern used for initial bad block scan 1068 * @bbt: Bad block table pointer 1069 * @page_shift: Number of address bits in a page (column address bits) 1070 * @phys_erase_shift: Number of address bits in a physical eraseblock 1071 * @chip_shift: Number of address bits in one chip 1072 * @pagemask: Page number mask = number of (pages / chip) - 1 1073 * @subpagesize: Holds the subpagesize 1074 * @data_buf: Buffer for data, size is (page size + oobsize) 1075 * @oob_poi: pointer on the OOB area covered by data_buf 1076 * @pagecache: Structure containing page cache related fields 1077 * @pagecache.bitflips: Number of bitflips of the cached page 1078 * @pagecache.page: Page number currently in the cache. -1 means no page is 1079 * currently cached 1080 * @buf_align: Minimum buffer alignment required by a platform 1081 * @lock: Lock protecting the suspended field. Also used to serialize accesses 1082 * to the NAND device 1083 * @suspended: Set to 1 when the device is suspended, 0 when it's not 1084 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we 1085 * should always have cur_cs >= 0 && cur_cs < nanddev_ntargets(). 1086 * NAND Controller drivers should not modify this value, but they're 1087 * allowed to read it. 1088 * @read_retries: The number of read retry modes supported 1089 * @controller: The hardware controller structure which is shared among multiple 1090 * independent devices 1091 * @ecc: The ECC controller structure 1092 * @priv: Chip private data 1093 */ 1094 struct nand_chip { 1095 struct nand_device base; 1096 struct nand_id id; 1097 struct nand_parameters parameters; 1098 struct nand_manufacturer manufacturer; 1099 struct nand_chip_ops ops; 1100 struct nand_legacy legacy; 1101 unsigned int options; 1102 1103 /* Data interface */ 1104 const struct nand_interface_config *current_interface_config; 1105 struct nand_interface_config *best_interface_config; 1106 1107 /* Bad block information */ 1108 unsigned int bbt_erase_shift; 1109 unsigned int bbt_options; 1110 unsigned int badblockpos; 1111 unsigned int badblockbits; 1112 struct nand_bbt_descr *bbt_td; 1113 struct nand_bbt_descr *bbt_md; 1114 struct nand_bbt_descr *badblock_pattern; 1115 u8 *bbt; 1116 1117 /* Device internal layout */ 1118 unsigned int page_shift; 1119 unsigned int phys_erase_shift; 1120 unsigned int chip_shift; 1121 unsigned int pagemask; 1122 unsigned int subpagesize; 1123 1124 /* Buffers */ 1125 u8 *data_buf; 1126 u8 *oob_poi; 1127 struct { 1128 unsigned int bitflips; 1129 int page; 1130 } pagecache; 1131 unsigned long buf_align; 1132 1133 /* Internals */ 1134 struct mutex lock; 1135 unsigned int suspended : 1; 1136 int cur_cs; 1137 int read_retries; 1138 1139 /* Externals */ 1140 struct nand_controller *controller; 1141 struct nand_ecc_ctrl ecc; 1142 void *priv; 1143 }; 1144 1145 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1146 { 1147 return container_of(mtd, struct nand_chip, base.mtd); 1148 } 1149 1150 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1151 { 1152 return &chip->base.mtd; 1153 } 1154 1155 static inline void *nand_get_controller_data(struct nand_chip *chip) 1156 { 1157 return chip->priv; 1158 } 1159 1160 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1161 { 1162 chip->priv = priv; 1163 } 1164 1165 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1166 void *priv) 1167 { 1168 chip->manufacturer.priv = priv; 1169 } 1170 1171 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1172 { 1173 return chip->manufacturer.priv; 1174 } 1175 1176 static inline void nand_set_flash_node(struct nand_chip *chip, 1177 struct device_node *np) 1178 { 1179 mtd_set_of_node(nand_to_mtd(chip), np); 1180 } 1181 1182 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1183 { 1184 return mtd_get_of_node(nand_to_mtd(chip)); 1185 } 1186 1187 /** 1188 * nand_get_interface_config - Retrieve the current interface configuration 1189 * of a NAND chip 1190 * @chip: The NAND chip 1191 */ 1192 static inline const struct nand_interface_config * 1193 nand_get_interface_config(struct nand_chip *chip) 1194 { 1195 return chip->current_interface_config; 1196 } 1197 1198 /* 1199 * A helper for defining older NAND chips where the second ID byte fully 1200 * defined the chip, including the geometry (chip size, eraseblock size, page 1201 * size). All these chips have 512 bytes NAND page size. 1202 */ 1203 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1204 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1205 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1206 1207 /* 1208 * A helper for defining newer chips which report their page size and 1209 * eraseblock size via the extended ID bytes. 1210 * 1211 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1212 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1213 * device ID now only represented a particular total chip size (and voltage, 1214 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1215 * using the same device ID. 1216 */ 1217 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1218 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1219 .options = (opts) } 1220 1221 #define NAND_ECC_INFO(_strength, _step) \ 1222 { .strength_ds = (_strength), .step_ds = (_step) } 1223 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1224 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1225 1226 /** 1227 * struct nand_flash_dev - NAND Flash Device ID Structure 1228 * @name: a human-readable name of the NAND chip 1229 * @dev_id: the device ID (the second byte of the full chip ID array) 1230 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same 1231 * memory address as ``id[0]``) 1232 * @dev_id: device ID part of the full chip ID array (refers the same memory 1233 * address as ``id[1]``) 1234 * @id: full device ID array 1235 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1236 * well as the eraseblock size) is determined from the extended NAND 1237 * chip ID array) 1238 * @chipsize: total chip size in MiB 1239 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1240 * @options: stores various chip bit options 1241 * @id_len: The valid length of the @id. 1242 * @oobsize: OOB size 1243 * @ecc: ECC correctability and step information from the datasheet. 1244 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1245 * @ecc_strength_ds in nand_chip{}. 1246 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1247 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1248 * For example, the "4bit ECC for each 512Byte" can be set with 1249 * NAND_ECC_INFO(4, 512). 1250 */ 1251 struct nand_flash_dev { 1252 char *name; 1253 union { 1254 struct { 1255 uint8_t mfr_id; 1256 uint8_t dev_id; 1257 }; 1258 uint8_t id[NAND_MAX_ID_LEN]; 1259 }; 1260 unsigned int pagesize; 1261 unsigned int chipsize; 1262 unsigned int erasesize; 1263 unsigned int options; 1264 uint16_t id_len; 1265 uint16_t oobsize; 1266 struct { 1267 uint16_t strength_ds; 1268 uint16_t step_ds; 1269 } ecc; 1270 }; 1271 1272 int nand_create_bbt(struct nand_chip *chip); 1273 1274 /* 1275 * Check if it is a SLC nand. 1276 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1277 * We do not distinguish the MLC and TLC now. 1278 */ 1279 static inline bool nand_is_slc(struct nand_chip *chip) 1280 { 1281 WARN(nanddev_bits_per_cell(&chip->base) == 0, 1282 "chip->bits_per_cell is used uninitialized\n"); 1283 return nanddev_bits_per_cell(&chip->base) == 1; 1284 } 1285 1286 /** 1287 * nand_opcode_8bits - Check if the opcode's address should be sent only on the 1288 * lower 8 bits 1289 * @command: opcode to check 1290 */ 1291 static inline int nand_opcode_8bits(unsigned int command) 1292 { 1293 switch (command) { 1294 case NAND_CMD_READID: 1295 case NAND_CMD_PARAM: 1296 case NAND_CMD_GET_FEATURES: 1297 case NAND_CMD_SET_FEATURES: 1298 return 1; 1299 default: 1300 break; 1301 } 1302 return 0; 1303 } 1304 1305 int rawnand_sw_hamming_init(struct nand_chip *chip); 1306 int rawnand_sw_hamming_calculate(struct nand_chip *chip, 1307 const unsigned char *buf, 1308 unsigned char *code); 1309 int rawnand_sw_hamming_correct(struct nand_chip *chip, 1310 unsigned char *buf, 1311 unsigned char *read_ecc, 1312 unsigned char *calc_ecc); 1313 void rawnand_sw_hamming_cleanup(struct nand_chip *chip); 1314 int rawnand_sw_bch_init(struct nand_chip *chip); 1315 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf, 1316 unsigned char *read_ecc, unsigned char *calc_ecc); 1317 void rawnand_sw_bch_cleanup(struct nand_chip *chip); 1318 1319 int nand_check_erased_ecc_chunk(void *data, int datalen, 1320 void *ecc, int ecclen, 1321 void *extraoob, int extraooblen, 1322 int threshold); 1323 1324 int nand_ecc_choose_conf(struct nand_chip *chip, 1325 const struct nand_ecc_caps *caps, int oobavail); 1326 1327 /* Default write_oob implementation */ 1328 int nand_write_oob_std(struct nand_chip *chip, int page); 1329 1330 /* Default read_oob implementation */ 1331 int nand_read_oob_std(struct nand_chip *chip, int page); 1332 1333 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1334 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1335 u8 *subfeature_param); 1336 1337 /* read_page_raw implementations */ 1338 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1339 int page); 1340 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf, 1341 int oob_required, int page); 1342 1343 /* write_page_raw implementations */ 1344 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1345 int oob_required, int page); 1346 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1347 int oob_required, int page); 1348 1349 /* Reset and initialize a NAND device */ 1350 int nand_reset(struct nand_chip *chip, int chipnr); 1351 1352 /* NAND operation helpers */ 1353 int nand_reset_op(struct nand_chip *chip); 1354 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1355 unsigned int len); 1356 int nand_status_op(struct nand_chip *chip, u8 *status); 1357 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1358 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1359 unsigned int offset_in_page, void *buf, unsigned int len); 1360 int nand_change_read_column_op(struct nand_chip *chip, 1361 unsigned int offset_in_page, void *buf, 1362 unsigned int len, bool force_8bit); 1363 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1364 unsigned int offset_in_page, void *buf, unsigned int len); 1365 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1366 unsigned int offset_in_page, const void *buf, 1367 unsigned int len); 1368 int nand_prog_page_end_op(struct nand_chip *chip); 1369 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1370 unsigned int offset_in_page, const void *buf, 1371 unsigned int len); 1372 int nand_change_write_column_op(struct nand_chip *chip, 1373 unsigned int offset_in_page, const void *buf, 1374 unsigned int len, bool force_8bit); 1375 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1376 bool force_8bit, bool check_only); 1377 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1378 unsigned int len, bool force_8bit); 1379 1380 /* Scan and identify a NAND device */ 1381 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1382 struct nand_flash_dev *ids); 1383 1384 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1385 { 1386 return nand_scan_with_ids(chip, max_chips, NULL); 1387 } 1388 1389 /* Internal helper for board drivers which need to override command function */ 1390 void nand_wait_ready(struct nand_chip *chip); 1391 1392 /* 1393 * Free resources held by the NAND device, must be called on error after a 1394 * sucessful nand_scan(). 1395 */ 1396 void nand_cleanup(struct nand_chip *chip); 1397 1398 /* 1399 * External helper for controller drivers that have to implement the WAITRDY 1400 * instruction and have no physical pin to check it. 1401 */ 1402 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1403 struct gpio_desc; 1404 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 1405 unsigned long timeout_ms); 1406 1407 /* Select/deselect a NAND target. */ 1408 void nand_select_target(struct nand_chip *chip, unsigned int cs); 1409 void nand_deselect_target(struct nand_chip *chip); 1410 1411 /* Bitops */ 1412 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src, 1413 unsigned int src_off, unsigned int nbits); 1414 1415 /** 1416 * nand_get_data_buf() - Get the internal page buffer 1417 * @chip: NAND chip object 1418 * 1419 * Returns the pre-allocated page buffer after invalidating the cache. This 1420 * function should be used by drivers that do not want to allocate their own 1421 * bounce buffer and still need such a buffer for specific operations (most 1422 * commonly when reading OOB data only). 1423 * 1424 * Be careful to never call this function in the write/write_oob path, because 1425 * the core may have placed the data to be written out in this buffer. 1426 * 1427 * Return: pointer to the page cache buffer 1428 */ 1429 static inline void *nand_get_data_buf(struct nand_chip *chip) 1430 { 1431 chip->pagecache.page = -1; 1432 1433 return chip->data_buf; 1434 } 1435 1436 #endif /* __LINUX_MTD_RAWNAND_H */ 1437