1 /* 2 * Copyright © 2000-2010 David Woodhouse <[email protected]> 3 * Steven J. Hill <[email protected]> 4 * Thomas Gleixner <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/wait.h> 20 #include <linux/spinlock.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/flashchip.h> 23 #include <linux/mtd/bbm.h> 24 25 struct mtd_info; 26 struct nand_flash_dev; 27 struct device_node; 28 29 /* Scan and identify a NAND device */ 30 int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Unregister the MTD device and free resources held by the NAND device */ 40 void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 void nand_wait_ready(struct mtd_info *mtd); 44 45 /* The maximum number of NAND chips in an array */ 46 #define NAND_MAX_CHIPS 8 47 48 /* 49 * Constants for hardware specific CLE/ALE/NCE function 50 * 51 * These are bits which can be or'ed to set/clear multiple 52 * bits in one go. 53 */ 54 /* Select the chip by setting nCE to low */ 55 #define NAND_NCE 0x01 56 /* Select the command latch by setting CLE to high */ 57 #define NAND_CLE 0x02 58 /* Select the address latch by setting ALE to high */ 59 #define NAND_ALE 0x04 60 61 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 62 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 63 #define NAND_CTRL_CHANGE 0x80 64 65 /* 66 * Standard NAND flash commands 67 */ 68 #define NAND_CMD_READ0 0 69 #define NAND_CMD_READ1 1 70 #define NAND_CMD_RNDOUT 5 71 #define NAND_CMD_PAGEPROG 0x10 72 #define NAND_CMD_READOOB 0x50 73 #define NAND_CMD_ERASE1 0x60 74 #define NAND_CMD_STATUS 0x70 75 #define NAND_CMD_SEQIN 0x80 76 #define NAND_CMD_RNDIN 0x85 77 #define NAND_CMD_READID 0x90 78 #define NAND_CMD_ERASE2 0xd0 79 #define NAND_CMD_PARAM 0xec 80 #define NAND_CMD_GET_FEATURES 0xee 81 #define NAND_CMD_SET_FEATURES 0xef 82 #define NAND_CMD_RESET 0xff 83 84 /* Extended commands for large page devices */ 85 #define NAND_CMD_READSTART 0x30 86 #define NAND_CMD_RNDOUTSTART 0xE0 87 #define NAND_CMD_CACHEDPROG 0x15 88 89 #define NAND_CMD_NONE -1 90 91 /* Status bits */ 92 #define NAND_STATUS_FAIL 0x01 93 #define NAND_STATUS_FAIL_N1 0x02 94 #define NAND_STATUS_TRUE_READY 0x20 95 #define NAND_STATUS_READY 0x40 96 #define NAND_STATUS_WP 0x80 97 98 #define NAND_DATA_IFACE_CHECK_ONLY -1 99 100 /* 101 * Constants for ECC_MODES 102 */ 103 typedef enum { 104 NAND_ECC_NONE, 105 NAND_ECC_SOFT, 106 NAND_ECC_HW, 107 NAND_ECC_HW_SYNDROME, 108 NAND_ECC_HW_OOB_FIRST, 109 NAND_ECC_ON_DIE, 110 } nand_ecc_modes_t; 111 112 enum nand_ecc_algo { 113 NAND_ECC_UNKNOWN, 114 NAND_ECC_HAMMING, 115 NAND_ECC_BCH, 116 }; 117 118 /* 119 * Constants for Hardware ECC 120 */ 121 /* Reset Hardware ECC for read */ 122 #define NAND_ECC_READ 0 123 /* Reset Hardware ECC for write */ 124 #define NAND_ECC_WRITE 1 125 /* Enable Hardware ECC before syndrome is read back from flash */ 126 #define NAND_ECC_READSYN 2 127 128 /* 129 * Enable generic NAND 'page erased' check. This check is only done when 130 * ecc.correct() returns -EBADMSG. 131 * Set this flag if your implementation does not fix bitflips in erased 132 * pages and you want to rely on the default implementation. 133 */ 134 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 135 #define NAND_ECC_MAXIMIZE BIT(1) 136 137 /* Bit mask for flags passed to do_nand_read_ecc */ 138 #define NAND_GET_DEVICE 0x80 139 140 141 /* 142 * Option constants for bizarre disfunctionality and real 143 * features. 144 */ 145 /* Buswidth is 16 bit */ 146 #define NAND_BUSWIDTH_16 0x00000002 147 /* Chip has cache program function */ 148 #define NAND_CACHEPRG 0x00000008 149 /* 150 * Chip requires ready check on read (for auto-incremented sequential read). 151 * True only for small page devices; large page devices do not support 152 * autoincrement. 153 */ 154 #define NAND_NEED_READRDY 0x00000100 155 156 /* Chip does not allow subpage writes */ 157 #define NAND_NO_SUBPAGE_WRITE 0x00000200 158 159 /* Device is one of 'new' xD cards that expose fake nand command set */ 160 #define NAND_BROKEN_XD 0x00000400 161 162 /* Device behaves just like nand, but is readonly */ 163 #define NAND_ROM 0x00000800 164 165 /* Device supports subpage reads */ 166 #define NAND_SUBPAGE_READ 0x00001000 167 168 /* 169 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 170 * patterns. 171 */ 172 #define NAND_NEED_SCRAMBLING 0x00002000 173 174 /* Device needs 3rd row address cycle */ 175 #define NAND_ROW_ADDR_3 0x00004000 176 177 /* Options valid for Samsung large page devices */ 178 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 179 180 /* Macros to identify the above */ 181 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 182 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 183 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 184 185 /* Non chip related options */ 186 /* This option skips the bbt scan during initialization. */ 187 #define NAND_SKIP_BBTSCAN 0x00010000 188 /* Chip may not exist, so silence any errors in scan */ 189 #define NAND_SCAN_SILENT_NODEV 0x00040000 190 /* 191 * Autodetect nand buswidth with readid/onfi. 192 * This suppose the driver will configure the hardware in 8 bits mode 193 * when calling nand_scan_ident, and update its configuration 194 * before calling nand_scan_tail. 195 */ 196 #define NAND_BUSWIDTH_AUTO 0x00080000 197 /* 198 * This option could be defined by controller drivers to protect against 199 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 200 */ 201 #define NAND_USE_BOUNCE_BUFFER 0x00100000 202 203 /* 204 * In case your controller is implementing ->cmd_ctrl() and is relying on the 205 * default ->cmdfunc() implementation, you may want to let the core handle the 206 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is 207 * requested. 208 * If your controller already takes care of this delay, you don't need to set 209 * this flag. 210 */ 211 #define NAND_WAIT_TCCS 0x00200000 212 213 /* Options set by nand scan */ 214 /* Nand scan has allocated controller struct */ 215 #define NAND_CONTROLLER_ALLOC 0x80000000 216 217 /* Cell info constants */ 218 #define NAND_CI_CHIPNR_MSK 0x03 219 #define NAND_CI_CELLTYPE_MSK 0x0C 220 #define NAND_CI_CELLTYPE_SHIFT 2 221 222 /* Keep gcc happy */ 223 struct nand_chip; 224 225 /* ONFI features */ 226 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 227 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 228 229 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 230 #define ONFI_TIMING_MODE_0 (1 << 0) 231 #define ONFI_TIMING_MODE_1 (1 << 1) 232 #define ONFI_TIMING_MODE_2 (1 << 2) 233 #define ONFI_TIMING_MODE_3 (1 << 3) 234 #define ONFI_TIMING_MODE_4 (1 << 4) 235 #define ONFI_TIMING_MODE_5 (1 << 5) 236 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 237 238 /* ONFI feature address */ 239 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 240 241 /* Vendor-specific feature address (Micron) */ 242 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 243 #define ONFI_FEATURE_ON_DIE_ECC 0x90 244 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) 245 246 /* ONFI subfeature parameters length */ 247 #define ONFI_SUBFEATURE_PARAM_LEN 4 248 249 /* ONFI optional commands SET/GET FEATURES supported? */ 250 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 251 252 struct nand_onfi_params { 253 /* rev info and features block */ 254 /* 'O' 'N' 'F' 'I' */ 255 u8 sig[4]; 256 __le16 revision; 257 __le16 features; 258 __le16 opt_cmd; 259 u8 reserved0[2]; 260 __le16 ext_param_page_length; /* since ONFI 2.1 */ 261 u8 num_of_param_pages; /* since ONFI 2.1 */ 262 u8 reserved1[17]; 263 264 /* manufacturer information block */ 265 char manufacturer[12]; 266 char model[20]; 267 u8 jedec_id; 268 __le16 date_code; 269 u8 reserved2[13]; 270 271 /* memory organization block */ 272 __le32 byte_per_page; 273 __le16 spare_bytes_per_page; 274 __le32 data_bytes_per_ppage; 275 __le16 spare_bytes_per_ppage; 276 __le32 pages_per_block; 277 __le32 blocks_per_lun; 278 u8 lun_count; 279 u8 addr_cycles; 280 u8 bits_per_cell; 281 __le16 bb_per_lun; 282 __le16 block_endurance; 283 u8 guaranteed_good_blocks; 284 __le16 guaranteed_block_endurance; 285 u8 programs_per_page; 286 u8 ppage_attr; 287 u8 ecc_bits; 288 u8 interleaved_bits; 289 u8 interleaved_ops; 290 u8 reserved3[13]; 291 292 /* electrical parameter block */ 293 u8 io_pin_capacitance_max; 294 __le16 async_timing_mode; 295 __le16 program_cache_timing_mode; 296 __le16 t_prog; 297 __le16 t_bers; 298 __le16 t_r; 299 __le16 t_ccs; 300 __le16 src_sync_timing_mode; 301 u8 src_ssync_features; 302 __le16 clk_pin_capacitance_typ; 303 __le16 io_pin_capacitance_typ; 304 __le16 input_pin_capacitance_typ; 305 u8 input_pin_capacitance_max; 306 u8 driver_strength_support; 307 __le16 t_int_r; 308 __le16 t_adl; 309 u8 reserved4[8]; 310 311 /* vendor */ 312 __le16 vendor_revision; 313 u8 vendor[88]; 314 315 __le16 crc; 316 } __packed; 317 318 #define ONFI_CRC_BASE 0x4F4E 319 320 /* Extended ECC information Block Definition (since ONFI 2.1) */ 321 struct onfi_ext_ecc_info { 322 u8 ecc_bits; 323 u8 codeword_size; 324 __le16 bb_per_lun; 325 __le16 block_endurance; 326 u8 reserved[2]; 327 } __packed; 328 329 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 330 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 331 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 332 struct onfi_ext_section { 333 u8 type; 334 u8 length; 335 } __packed; 336 337 #define ONFI_EXT_SECTION_MAX 8 338 339 /* Extended Parameter Page Definition (since ONFI 2.1) */ 340 struct onfi_ext_param_page { 341 __le16 crc; 342 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 343 u8 reserved0[10]; 344 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 345 346 /* 347 * The actual size of the Extended Parameter Page is in 348 * @ext_param_page_length of nand_onfi_params{}. 349 * The following are the variable length sections. 350 * So we do not add any fields below. Please see the ONFI spec. 351 */ 352 } __packed; 353 354 struct jedec_ecc_info { 355 u8 ecc_bits; 356 u8 codeword_size; 357 __le16 bb_per_lun; 358 __le16 block_endurance; 359 u8 reserved[2]; 360 } __packed; 361 362 /* JEDEC features */ 363 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 364 365 struct nand_jedec_params { 366 /* rev info and features block */ 367 /* 'J' 'E' 'S' 'D' */ 368 u8 sig[4]; 369 __le16 revision; 370 __le16 features; 371 u8 opt_cmd[3]; 372 __le16 sec_cmd; 373 u8 num_of_param_pages; 374 u8 reserved0[18]; 375 376 /* manufacturer information block */ 377 char manufacturer[12]; 378 char model[20]; 379 u8 jedec_id[6]; 380 u8 reserved1[10]; 381 382 /* memory organization block */ 383 __le32 byte_per_page; 384 __le16 spare_bytes_per_page; 385 u8 reserved2[6]; 386 __le32 pages_per_block; 387 __le32 blocks_per_lun; 388 u8 lun_count; 389 u8 addr_cycles; 390 u8 bits_per_cell; 391 u8 programs_per_page; 392 u8 multi_plane_addr; 393 u8 multi_plane_op_attr; 394 u8 reserved3[38]; 395 396 /* electrical parameter block */ 397 __le16 async_sdr_speed_grade; 398 __le16 toggle_ddr_speed_grade; 399 __le16 sync_ddr_speed_grade; 400 u8 async_sdr_features; 401 u8 toggle_ddr_features; 402 u8 sync_ddr_features; 403 __le16 t_prog; 404 __le16 t_bers; 405 __le16 t_r; 406 __le16 t_r_multi_plane; 407 __le16 t_ccs; 408 __le16 io_pin_capacitance_typ; 409 __le16 input_pin_capacitance_typ; 410 __le16 clk_pin_capacitance_typ; 411 u8 driver_strength_support; 412 __le16 t_adl; 413 u8 reserved4[36]; 414 415 /* ECC and endurance block */ 416 u8 guaranteed_good_blocks; 417 __le16 guaranteed_block_endurance; 418 struct jedec_ecc_info ecc_info[4]; 419 u8 reserved5[29]; 420 421 /* reserved */ 422 u8 reserved6[148]; 423 424 /* vendor */ 425 __le16 vendor_rev_num; 426 u8 reserved7[88]; 427 428 /* CRC for Parameter Page */ 429 __le16 crc; 430 } __packed; 431 432 /* The maximum expected count of bytes in the NAND ID sequence */ 433 #define NAND_MAX_ID_LEN 8 434 435 /** 436 * struct nand_id - NAND id structure 437 * @data: buffer containing the id bytes. 438 * @len: ID length. 439 */ 440 struct nand_id { 441 u8 data[NAND_MAX_ID_LEN]; 442 int len; 443 }; 444 445 /** 446 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 447 * @lock: protection lock 448 * @active: the mtd device which holds the controller currently 449 * @wq: wait queue to sleep on if a NAND operation is in 450 * progress used instead of the per chip wait queue 451 * when a hw controller is available. 452 */ 453 struct nand_hw_control { 454 spinlock_t lock; 455 struct nand_chip *active; 456 wait_queue_head_t wq; 457 }; 458 459 static inline void nand_hw_control_init(struct nand_hw_control *nfc) 460 { 461 nfc->active = NULL; 462 spin_lock_init(&nfc->lock); 463 init_waitqueue_head(&nfc->wq); 464 } 465 466 /** 467 * struct nand_ecc_step_info - ECC step information of ECC engine 468 * @stepsize: data bytes per ECC step 469 * @strengths: array of supported strengths 470 * @nstrengths: number of supported strengths 471 */ 472 struct nand_ecc_step_info { 473 int stepsize; 474 const int *strengths; 475 int nstrengths; 476 }; 477 478 /** 479 * struct nand_ecc_caps - capability of ECC engine 480 * @stepinfos: array of ECC step information 481 * @nstepinfos: number of ECC step information 482 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 483 */ 484 struct nand_ecc_caps { 485 const struct nand_ecc_step_info *stepinfos; 486 int nstepinfos; 487 int (*calc_ecc_bytes)(int step_size, int strength); 488 }; 489 490 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 491 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 492 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 493 static const struct nand_ecc_step_info __name##_stepinfo = { \ 494 .stepsize = __step, \ 495 .strengths = __name##_strengths, \ 496 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 497 }; \ 498 static const struct nand_ecc_caps __name = { \ 499 .stepinfos = &__name##_stepinfo, \ 500 .nstepinfos = 1, \ 501 .calc_ecc_bytes = __calc, \ 502 } 503 504 /** 505 * struct nand_ecc_ctrl - Control structure for ECC 506 * @mode: ECC mode 507 * @algo: ECC algorithm 508 * @steps: number of ECC steps per page 509 * @size: data bytes per ECC step 510 * @bytes: ECC bytes per step 511 * @strength: max number of correctible bits per ECC step 512 * @total: total number of ECC bytes per page 513 * @prepad: padding information for syndrome based ECC generators 514 * @postpad: padding information for syndrome based ECC generators 515 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 516 * @priv: pointer to private ECC control data 517 * @calc_buf: buffer for calculated ECC, size is oobsize. 518 * @code_buf: buffer for ECC read from flash, size is oobsize. 519 * @hwctl: function to control hardware ECC generator. Must only 520 * be provided if an hardware ECC is available 521 * @calculate: function for ECC calculation or readback from ECC hardware 522 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 523 * Should return a positive number representing the number of 524 * corrected bitflips, -EBADMSG if the number of bitflips exceed 525 * ECC strength, or any other error code if the error is not 526 * directly related to correction. 527 * If -EBADMSG is returned the input buffers should be left 528 * untouched. 529 * @read_page_raw: function to read a raw page without ECC. This function 530 * should hide the specific layout used by the ECC 531 * controller and always return contiguous in-band and 532 * out-of-band data even if they're not stored 533 * contiguously on the NAND chip (e.g. 534 * NAND_ECC_HW_SYNDROME interleaves in-band and 535 * out-of-band data). 536 * @write_page_raw: function to write a raw page without ECC. This function 537 * should hide the specific layout used by the ECC 538 * controller and consider the passed data as contiguous 539 * in-band and out-of-band data. ECC controller is 540 * responsible for doing the appropriate transformations 541 * to adapt to its specific layout (e.g. 542 * NAND_ECC_HW_SYNDROME interleaves in-band and 543 * out-of-band data). 544 * @read_page: function to read a page according to the ECC generator 545 * requirements; returns maximum number of bitflips corrected in 546 * any single ECC step, -EIO hw error 547 * @read_subpage: function to read parts of the page covered by ECC; 548 * returns same as read_page() 549 * @write_subpage: function to write parts of the page covered by ECC. 550 * @write_page: function to write a page according to the ECC generator 551 * requirements. 552 * @write_oob_raw: function to write chip OOB data without ECC 553 * @read_oob_raw: function to read chip OOB data without ECC 554 * @read_oob: function to read chip OOB data 555 * @write_oob: function to write chip OOB data 556 */ 557 struct nand_ecc_ctrl { 558 nand_ecc_modes_t mode; 559 enum nand_ecc_algo algo; 560 int steps; 561 int size; 562 int bytes; 563 int total; 564 int strength; 565 int prepad; 566 int postpad; 567 unsigned int options; 568 void *priv; 569 u8 *calc_buf; 570 u8 *code_buf; 571 void (*hwctl)(struct mtd_info *mtd, int mode); 572 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 573 uint8_t *ecc_code); 574 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 575 uint8_t *calc_ecc); 576 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 577 uint8_t *buf, int oob_required, int page); 578 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 579 const uint8_t *buf, int oob_required, int page); 580 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 581 uint8_t *buf, int oob_required, int page); 582 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 583 uint32_t offs, uint32_t len, uint8_t *buf, int page); 584 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 585 uint32_t offset, uint32_t data_len, 586 const uint8_t *data_buf, int oob_required, int page); 587 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 588 const uint8_t *buf, int oob_required, int page); 589 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 590 int page); 591 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 592 int page); 593 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 594 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 595 int page); 596 }; 597 598 /** 599 * struct nand_sdr_timings - SDR NAND chip timings 600 * 601 * This struct defines the timing requirements of a SDR NAND chip. 602 * These information can be found in every NAND datasheets and the timings 603 * meaning are described in the ONFI specifications: 604 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 605 * Parameters) 606 * 607 * All these timings are expressed in picoseconds. 608 * 609 * @tBERS_max: Block erase time 610 * @tCCS_min: Change column setup time 611 * @tPROG_max: Page program time 612 * @tR_max: Page read time 613 * @tALH_min: ALE hold time 614 * @tADL_min: ALE to data loading time 615 * @tALS_min: ALE setup time 616 * @tAR_min: ALE to RE# delay 617 * @tCEA_max: CE# access time 618 * @tCEH_min: CE# high hold time 619 * @tCH_min: CE# hold time 620 * @tCHZ_max: CE# high to output hi-Z 621 * @tCLH_min: CLE hold time 622 * @tCLR_min: CLE to RE# delay 623 * @tCLS_min: CLE setup time 624 * @tCOH_min: CE# high to output hold 625 * @tCS_min: CE# setup time 626 * @tDH_min: Data hold time 627 * @tDS_min: Data setup time 628 * @tFEAT_max: Busy time for Set Features and Get Features 629 * @tIR_min: Output hi-Z to RE# low 630 * @tITC_max: Interface and Timing Mode Change time 631 * @tRC_min: RE# cycle time 632 * @tREA_max: RE# access time 633 * @tREH_min: RE# high hold time 634 * @tRHOH_min: RE# high to output hold 635 * @tRHW_min: RE# high to WE# low 636 * @tRHZ_max: RE# high to output hi-Z 637 * @tRLOH_min: RE# low to output hold 638 * @tRP_min: RE# pulse width 639 * @tRR_min: Ready to RE# low (data only) 640 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 641 * rising edge of R/B#. 642 * @tWB_max: WE# high to SR[6] low 643 * @tWC_min: WE# cycle time 644 * @tWH_min: WE# high hold time 645 * @tWHR_min: WE# high to RE# low 646 * @tWP_min: WE# pulse width 647 * @tWW_min: WP# transition to WE# low 648 */ 649 struct nand_sdr_timings { 650 u64 tBERS_max; 651 u32 tCCS_min; 652 u64 tPROG_max; 653 u64 tR_max; 654 u32 tALH_min; 655 u32 tADL_min; 656 u32 tALS_min; 657 u32 tAR_min; 658 u32 tCEA_max; 659 u32 tCEH_min; 660 u32 tCH_min; 661 u32 tCHZ_max; 662 u32 tCLH_min; 663 u32 tCLR_min; 664 u32 tCLS_min; 665 u32 tCOH_min; 666 u32 tCS_min; 667 u32 tDH_min; 668 u32 tDS_min; 669 u32 tFEAT_max; 670 u32 tIR_min; 671 u32 tITC_max; 672 u32 tRC_min; 673 u32 tREA_max; 674 u32 tREH_min; 675 u32 tRHOH_min; 676 u32 tRHW_min; 677 u32 tRHZ_max; 678 u32 tRLOH_min; 679 u32 tRP_min; 680 u32 tRR_min; 681 u64 tRST_max; 682 u32 tWB_max; 683 u32 tWC_min; 684 u32 tWH_min; 685 u32 tWHR_min; 686 u32 tWP_min; 687 u32 tWW_min; 688 }; 689 690 /** 691 * enum nand_data_interface_type - NAND interface timing type 692 * @NAND_SDR_IFACE: Single Data Rate interface 693 */ 694 enum nand_data_interface_type { 695 NAND_SDR_IFACE, 696 }; 697 698 /** 699 * struct nand_data_interface - NAND interface timing 700 * @type: type of the timing 701 * @timings: The timing, type according to @type 702 */ 703 struct nand_data_interface { 704 enum nand_data_interface_type type; 705 union { 706 struct nand_sdr_timings sdr; 707 } timings; 708 }; 709 710 /** 711 * nand_get_sdr_timings - get SDR timing from data interface 712 * @conf: The data interface 713 */ 714 static inline const struct nand_sdr_timings * 715 nand_get_sdr_timings(const struct nand_data_interface *conf) 716 { 717 if (conf->type != NAND_SDR_IFACE) 718 return ERR_PTR(-EINVAL); 719 720 return &conf->timings.sdr; 721 } 722 723 /** 724 * struct nand_manufacturer_ops - NAND Manufacturer operations 725 * @detect: detect the NAND memory organization and capabilities 726 * @init: initialize all vendor specific fields (like the ->read_retry() 727 * implementation) if any. 728 * @cleanup: the ->init() function may have allocated resources, ->cleanup() 729 * is here to let vendor specific code release those resources. 730 */ 731 struct nand_manufacturer_ops { 732 void (*detect)(struct nand_chip *chip); 733 int (*init)(struct nand_chip *chip); 734 void (*cleanup)(struct nand_chip *chip); 735 }; 736 737 /** 738 * struct nand_op_cmd_instr - Definition of a command instruction 739 * @opcode: the command to issue in one cycle 740 */ 741 struct nand_op_cmd_instr { 742 u8 opcode; 743 }; 744 745 /** 746 * struct nand_op_addr_instr - Definition of an address instruction 747 * @naddrs: length of the @addrs array 748 * @addrs: array containing the address cycles to issue 749 */ 750 struct nand_op_addr_instr { 751 unsigned int naddrs; 752 const u8 *addrs; 753 }; 754 755 /** 756 * struct nand_op_data_instr - Definition of a data instruction 757 * @len: number of data bytes to move 758 * @in: buffer to fill when reading from the NAND chip 759 * @out: buffer to read from when writing to the NAND chip 760 * @force_8bit: force 8-bit access 761 * 762 * Please note that "in" and "out" are inverted from the ONFI specification 763 * and are from the controller perspective, so a "in" is a read from the NAND 764 * chip while a "out" is a write to the NAND chip. 765 */ 766 struct nand_op_data_instr { 767 unsigned int len; 768 union { 769 void *in; 770 const void *out; 771 } buf; 772 bool force_8bit; 773 }; 774 775 /** 776 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 777 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 778 */ 779 struct nand_op_waitrdy_instr { 780 unsigned int timeout_ms; 781 }; 782 783 /** 784 * enum nand_op_instr_type - Definition of all instruction types 785 * @NAND_OP_CMD_INSTR: command instruction 786 * @NAND_OP_ADDR_INSTR: address instruction 787 * @NAND_OP_DATA_IN_INSTR: data in instruction 788 * @NAND_OP_DATA_OUT_INSTR: data out instruction 789 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 790 */ 791 enum nand_op_instr_type { 792 NAND_OP_CMD_INSTR, 793 NAND_OP_ADDR_INSTR, 794 NAND_OP_DATA_IN_INSTR, 795 NAND_OP_DATA_OUT_INSTR, 796 NAND_OP_WAITRDY_INSTR, 797 }; 798 799 /** 800 * struct nand_op_instr - Instruction object 801 * @type: the instruction type 802 * @cmd/@addr/@data/@waitrdy: extra data associated to the instruction. 803 * You'll have to use the appropriate element 804 * depending on @type 805 * @delay_ns: delay the controller should apply after the instruction has been 806 * issued on the bus. Most modern controllers have internal timings 807 * control logic, and in this case, the controller driver can ignore 808 * this field. 809 */ 810 struct nand_op_instr { 811 enum nand_op_instr_type type; 812 union { 813 struct nand_op_cmd_instr cmd; 814 struct nand_op_addr_instr addr; 815 struct nand_op_data_instr data; 816 struct nand_op_waitrdy_instr waitrdy; 817 } ctx; 818 unsigned int delay_ns; 819 }; 820 821 /* 822 * Special handling must be done for the WAITRDY timeout parameter as it usually 823 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 824 * tBERS (during an erase) which all of them are u64 values that cannot be 825 * divided by usual kernel macros and must be handled with the special 826 * DIV_ROUND_UP_ULL() macro. 827 */ 828 #define __DIVIDE(dividend, divisor) ({ \ 829 sizeof(dividend) == sizeof(u32) ? \ 830 DIV_ROUND_UP(dividend, divisor) : \ 831 DIV_ROUND_UP_ULL(dividend, divisor); \ 832 }) 833 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 834 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 835 836 #define NAND_OP_CMD(id, ns) \ 837 { \ 838 .type = NAND_OP_CMD_INSTR, \ 839 .ctx.cmd.opcode = id, \ 840 .delay_ns = ns, \ 841 } 842 843 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 844 { \ 845 .type = NAND_OP_ADDR_INSTR, \ 846 .ctx.addr = { \ 847 .naddrs = ncycles, \ 848 .addrs = cycles, \ 849 }, \ 850 .delay_ns = ns, \ 851 } 852 853 #define NAND_OP_DATA_IN(l, b, ns) \ 854 { \ 855 .type = NAND_OP_DATA_IN_INSTR, \ 856 .ctx.data = { \ 857 .len = l, \ 858 .buf.in = b, \ 859 .force_8bit = false, \ 860 }, \ 861 .delay_ns = ns, \ 862 } 863 864 #define NAND_OP_DATA_OUT(l, b, ns) \ 865 { \ 866 .type = NAND_OP_DATA_OUT_INSTR, \ 867 .ctx.data = { \ 868 .len = l, \ 869 .buf.out = b, \ 870 .force_8bit = false, \ 871 }, \ 872 .delay_ns = ns, \ 873 } 874 875 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 876 { \ 877 .type = NAND_OP_DATA_IN_INSTR, \ 878 .ctx.data = { \ 879 .len = l, \ 880 .buf.in = b, \ 881 .force_8bit = true, \ 882 }, \ 883 .delay_ns = ns, \ 884 } 885 886 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 887 { \ 888 .type = NAND_OP_DATA_OUT_INSTR, \ 889 .ctx.data = { \ 890 .len = l, \ 891 .buf.out = b, \ 892 .force_8bit = true, \ 893 }, \ 894 .delay_ns = ns, \ 895 } 896 897 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 898 { \ 899 .type = NAND_OP_WAITRDY_INSTR, \ 900 .ctx.waitrdy.timeout_ms = tout_ms, \ 901 .delay_ns = ns, \ 902 } 903 904 /** 905 * struct nand_subop - a sub operation 906 * @instrs: array of instructions 907 * @ninstrs: length of the @instrs array 908 * @first_instr_start_off: offset to start from for the first instruction 909 * of the sub-operation 910 * @last_instr_end_off: offset to end at (excluded) for the last instruction 911 * of the sub-operation 912 * 913 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 914 * address instructions. 915 * 916 * When an operation cannot be handled as is by the NAND controller, it will 917 * be split by the parser into sub-operations which will be passed to the 918 * controller driver. 919 */ 920 struct nand_subop { 921 const struct nand_op_instr *instrs; 922 unsigned int ninstrs; 923 unsigned int first_instr_start_off; 924 unsigned int last_instr_end_off; 925 }; 926 927 int nand_subop_get_addr_start_off(const struct nand_subop *subop, 928 unsigned int op_id); 929 int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 930 unsigned int op_id); 931 int nand_subop_get_data_start_off(const struct nand_subop *subop, 932 unsigned int op_id); 933 int nand_subop_get_data_len(const struct nand_subop *subop, 934 unsigned int op_id); 935 936 /** 937 * struct nand_op_parser_addr_constraints - Constraints for address instructions 938 * @maxcycles: maximum number of address cycles the controller can issue in a 939 * single step 940 */ 941 struct nand_op_parser_addr_constraints { 942 unsigned int maxcycles; 943 }; 944 945 /** 946 * struct nand_op_parser_data_constraints - Constraints for data instructions 947 * @maxlen: maximum data length that the controller can handle in a single step 948 */ 949 struct nand_op_parser_data_constraints { 950 unsigned int maxlen; 951 }; 952 953 /** 954 * struct nand_op_parser_pattern_elem - One element of a pattern 955 * @type: the instructuction type 956 * @optional: whether this element of the pattern is optional or mandatory 957 * @addr/@data: address or data constraint (number of cycles or data length) 958 */ 959 struct nand_op_parser_pattern_elem { 960 enum nand_op_instr_type type; 961 bool optional; 962 union { 963 struct nand_op_parser_addr_constraints addr; 964 struct nand_op_parser_data_constraints data; 965 } ctx; 966 }; 967 968 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 969 { \ 970 .type = NAND_OP_CMD_INSTR, \ 971 .optional = _opt, \ 972 } 973 974 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 975 { \ 976 .type = NAND_OP_ADDR_INSTR, \ 977 .optional = _opt, \ 978 .ctx.addr.maxcycles = _maxcycles, \ 979 } 980 981 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 982 { \ 983 .type = NAND_OP_DATA_IN_INSTR, \ 984 .optional = _opt, \ 985 .ctx.data.maxlen = _maxlen, \ 986 } 987 988 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 989 { \ 990 .type = NAND_OP_DATA_OUT_INSTR, \ 991 .optional = _opt, \ 992 .ctx.data.maxlen = _maxlen, \ 993 } 994 995 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 996 { \ 997 .type = NAND_OP_WAITRDY_INSTR, \ 998 .optional = _opt, \ 999 } 1000 1001 /** 1002 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 1003 * @elems: array of pattern elements 1004 * @nelems: number of pattern elements in @elems array 1005 * @exec: the function that will issue a sub-operation 1006 * 1007 * A pattern is a list of elements, each element reprensenting one instruction 1008 * with its constraints. The pattern itself is used by the core to match NAND 1009 * chip operation with NAND controller operations. 1010 * Once a match between a NAND controller operation pattern and a NAND chip 1011 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 1012 * hook is called so that the controller driver can issue the operation on the 1013 * bus. 1014 * 1015 * Controller drivers should declare as many patterns as they support and pass 1016 * this list of patterns (created with the help of the following macro) to 1017 * the nand_op_parser_exec_op() helper. 1018 */ 1019 struct nand_op_parser_pattern { 1020 const struct nand_op_parser_pattern_elem *elems; 1021 unsigned int nelems; 1022 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 1023 }; 1024 1025 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 1026 { \ 1027 .exec = _exec, \ 1028 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 1029 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 1030 sizeof(struct nand_op_parser_pattern_elem), \ 1031 } 1032 1033 /** 1034 * struct nand_op_parser - NAND controller operation parser descriptor 1035 * @patterns: array of supported patterns 1036 * @npatterns: length of the @patterns array 1037 * 1038 * The parser descriptor is just an array of supported patterns which will be 1039 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 1040 * NAND operation (or tries to determine if a specific operation is supported). 1041 * 1042 * It is worth mentioning that patterns will be tested in their declaration 1043 * order, and the first match will be taken, so it's important to order patterns 1044 * appropriately so that simple/inefficient patterns are placed at the end of 1045 * the list. Usually, this is where you put single instruction patterns. 1046 */ 1047 struct nand_op_parser { 1048 const struct nand_op_parser_pattern *patterns; 1049 unsigned int npatterns; 1050 }; 1051 1052 #define NAND_OP_PARSER(...) \ 1053 { \ 1054 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 1055 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 1056 sizeof(struct nand_op_parser_pattern), \ 1057 } 1058 1059 /** 1060 * struct nand_operation - NAND operation descriptor 1061 * @instrs: array of instructions to execute 1062 * @ninstrs: length of the @instrs array 1063 * 1064 * The actual operation structure that will be passed to chip->exec_op(). 1065 */ 1066 struct nand_operation { 1067 const struct nand_op_instr *instrs; 1068 unsigned int ninstrs; 1069 }; 1070 1071 #define NAND_OPERATION(_instrs) \ 1072 { \ 1073 .instrs = _instrs, \ 1074 .ninstrs = ARRAY_SIZE(_instrs), \ 1075 } 1076 1077 int nand_op_parser_exec_op(struct nand_chip *chip, 1078 const struct nand_op_parser *parser, 1079 const struct nand_operation *op, bool check_only); 1080 1081 /** 1082 * struct nand_chip - NAND Private Flash Chip Data 1083 * @mtd: MTD device registered to the MTD framework 1084 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 1085 * flash device 1086 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 1087 * flash device. 1088 * @read_byte: [REPLACEABLE] read one byte from the chip 1089 * @read_word: [REPLACEABLE] read one word from the chip 1090 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 1091 * low 8 I/O lines 1092 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 1093 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 1094 * @select_chip: [REPLACEABLE] select chip nr 1095 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 1096 * @block_markbad: [REPLACEABLE] mark a block bad 1097 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 1098 * ALE/CLE/nCE. Also used to write command and address 1099 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 1100 * device ready/busy line. If set to NULL no access to 1101 * ready/busy is available and the ready/busy information 1102 * is read from the chip status register. 1103 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 1104 * commands to the chip. 1105 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 1106 * ready. 1107 * @exec_op: controller specific method to execute NAND operations. 1108 * This method replaces ->cmdfunc(), 1109 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and 1110 * ->waifunc(). 1111 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 1112 * setting the read-retry mode. Mostly needed for MLC NAND. 1113 * @ecc: [BOARDSPECIFIC] ECC control structure 1114 * @buf_align: minimum buffer alignment required by a platform 1115 * @hwcontrol: platform-specific hardware control structure 1116 * @erase: [REPLACEABLE] erase function 1117 * @scan_bbt: [REPLACEABLE] function to scan bad block table 1118 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 1119 * data from array to read regs (tR). 1120 * @state: [INTERN] the current state of the NAND device 1121 * @oob_poi: "poison value buffer," used for laying out OOB data 1122 * before writing 1123 * @page_shift: [INTERN] number of address bits in a page (column 1124 * address bits). 1125 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 1126 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 1127 * @chip_shift: [INTERN] number of address bits in one chip 1128 * @options: [BOARDSPECIFIC] various chip options. They can partly 1129 * be set to inform nand_scan about special functionality. 1130 * See the defines for further explanation. 1131 * @bbt_options: [INTERN] bad block specific options. All options used 1132 * here must come from bbm.h. By default, these options 1133 * will be copied to the appropriate nand_bbt_descr's. 1134 * @badblockpos: [INTERN] position of the bad block marker in the oob 1135 * area. 1136 * @badblockbits: [INTERN] minimum number of set bits in a good block's 1137 * bad block marker position; i.e., BBM == 11110111b is 1138 * not bad when badblockbits == 7 1139 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 1140 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 1141 * Minimum amount of bit errors per @ecc_step_ds guaranteed 1142 * to be correctable. If unknown, set to zero. 1143 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 1144 * also from the datasheet. It is the recommended ECC step 1145 * size, if known; if unknown, set to zero. 1146 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1147 * set to the actually used ONFI mode if the chip is 1148 * ONFI compliant or deduced from the datasheet if 1149 * the NAND chip is not ONFI compliant. 1150 * @numchips: [INTERN] number of physical chips 1151 * @chipsize: [INTERN] the size of one chip for multichip arrays 1152 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1153 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1154 * @pagebuf: [INTERN] holds the pagenumber which is currently in 1155 * data_buf. 1156 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 1157 * currently in data_buf. 1158 * @subpagesize: [INTERN] holds the subpagesize 1159 * @id: [INTERN] holds NAND ID 1160 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 1161 * non 0 if ONFI supported. 1162 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 1163 * non 0 if JEDEC supported. 1164 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 1165 * supported, 0 otherwise. 1166 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 1167 * supported, 0 otherwise. 1168 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 1169 * this nand device will encounter their life times. 1170 * @blocks_per_die: [INTERN] The number of PEBs in a die 1171 * @data_interface: [INTERN] NAND interface timing information 1172 * @read_retries: [INTERN] the number of read retry modes supported 1173 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 1174 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 1175 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 1176 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 1177 * means the configuration should not be applied but 1178 * only checked. 1179 * @bbt: [INTERN] bad block table pointer 1180 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1181 * lookup. 1182 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1183 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1184 * bad block scan. 1185 * @controller: [REPLACEABLE] a pointer to a hardware controller 1186 * structure which is shared among multiple independent 1187 * devices. 1188 * @priv: [OPTIONAL] pointer to private chip data 1189 * @manufacturer: [INTERN] Contains manufacturer information 1190 */ 1191 1192 struct nand_chip { 1193 struct mtd_info mtd; 1194 void __iomem *IO_ADDR_R; 1195 void __iomem *IO_ADDR_W; 1196 1197 uint8_t (*read_byte)(struct mtd_info *mtd); 1198 u16 (*read_word)(struct mtd_info *mtd); 1199 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 1200 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1201 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1202 void (*select_chip)(struct mtd_info *mtd, int chip); 1203 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 1204 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 1205 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1206 int (*dev_ready)(struct mtd_info *mtd); 1207 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 1208 int page_addr); 1209 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 1210 int (*exec_op)(struct nand_chip *chip, 1211 const struct nand_operation *op, 1212 bool check_only); 1213 int (*erase)(struct mtd_info *mtd, int page); 1214 int (*scan_bbt)(struct mtd_info *mtd); 1215 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 1216 int feature_addr, uint8_t *subfeature_para); 1217 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 1218 int feature_addr, uint8_t *subfeature_para); 1219 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 1220 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 1221 const struct nand_data_interface *conf); 1222 1223 int chip_delay; 1224 unsigned int options; 1225 unsigned int bbt_options; 1226 1227 int page_shift; 1228 int phys_erase_shift; 1229 int bbt_erase_shift; 1230 int chip_shift; 1231 int numchips; 1232 uint64_t chipsize; 1233 int pagemask; 1234 u8 *data_buf; 1235 int pagebuf; 1236 unsigned int pagebuf_bitflips; 1237 int subpagesize; 1238 uint8_t bits_per_cell; 1239 uint16_t ecc_strength_ds; 1240 uint16_t ecc_step_ds; 1241 int onfi_timing_mode_default; 1242 int badblockpos; 1243 int badblockbits; 1244 1245 struct nand_id id; 1246 int onfi_version; 1247 int jedec_version; 1248 union { 1249 struct nand_onfi_params onfi_params; 1250 struct nand_jedec_params jedec_params; 1251 }; 1252 u16 max_bb_per_die; 1253 u32 blocks_per_die; 1254 1255 struct nand_data_interface data_interface; 1256 1257 int read_retries; 1258 1259 flstate_t state; 1260 1261 uint8_t *oob_poi; 1262 struct nand_hw_control *controller; 1263 1264 struct nand_ecc_ctrl ecc; 1265 unsigned long buf_align; 1266 struct nand_hw_control hwcontrol; 1267 1268 uint8_t *bbt; 1269 struct nand_bbt_descr *bbt_td; 1270 struct nand_bbt_descr *bbt_md; 1271 1272 struct nand_bbt_descr *badblock_pattern; 1273 1274 void *priv; 1275 1276 struct { 1277 const struct nand_manufacturer *desc; 1278 void *priv; 1279 } manufacturer; 1280 }; 1281 1282 static inline int nand_exec_op(struct nand_chip *chip, 1283 const struct nand_operation *op) 1284 { 1285 if (!chip->exec_op) 1286 return -ENOTSUPP; 1287 1288 return chip->exec_op(chip, op, false); 1289 } 1290 1291 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1292 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1293 1294 static inline void nand_set_flash_node(struct nand_chip *chip, 1295 struct device_node *np) 1296 { 1297 mtd_set_of_node(&chip->mtd, np); 1298 } 1299 1300 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1301 { 1302 return mtd_get_of_node(&chip->mtd); 1303 } 1304 1305 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1306 { 1307 return container_of(mtd, struct nand_chip, mtd); 1308 } 1309 1310 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1311 { 1312 return &chip->mtd; 1313 } 1314 1315 static inline void *nand_get_controller_data(struct nand_chip *chip) 1316 { 1317 return chip->priv; 1318 } 1319 1320 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1321 { 1322 chip->priv = priv; 1323 } 1324 1325 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1326 void *priv) 1327 { 1328 chip->manufacturer.priv = priv; 1329 } 1330 1331 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1332 { 1333 return chip->manufacturer.priv; 1334 } 1335 1336 /* 1337 * NAND Flash Manufacturer ID Codes 1338 */ 1339 #define NAND_MFR_TOSHIBA 0x98 1340 #define NAND_MFR_ESMT 0xc8 1341 #define NAND_MFR_SAMSUNG 0xec 1342 #define NAND_MFR_FUJITSU 0x04 1343 #define NAND_MFR_NATIONAL 0x8f 1344 #define NAND_MFR_RENESAS 0x07 1345 #define NAND_MFR_STMICRO 0x20 1346 #define NAND_MFR_HYNIX 0xad 1347 #define NAND_MFR_MICRON 0x2c 1348 #define NAND_MFR_AMD 0x01 1349 #define NAND_MFR_MACRONIX 0xc2 1350 #define NAND_MFR_EON 0x92 1351 #define NAND_MFR_SANDISK 0x45 1352 #define NAND_MFR_INTEL 0x89 1353 #define NAND_MFR_ATO 0x9b 1354 #define NAND_MFR_WINBOND 0xef 1355 1356 1357 /* 1358 * A helper for defining older NAND chips where the second ID byte fully 1359 * defined the chip, including the geometry (chip size, eraseblock size, page 1360 * size). All these chips have 512 bytes NAND page size. 1361 */ 1362 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1363 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1364 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1365 1366 /* 1367 * A helper for defining newer chips which report their page size and 1368 * eraseblock size via the extended ID bytes. 1369 * 1370 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1371 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1372 * device ID now only represented a particular total chip size (and voltage, 1373 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1374 * using the same device ID. 1375 */ 1376 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1377 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1378 .options = (opts) } 1379 1380 #define NAND_ECC_INFO(_strength, _step) \ 1381 { .strength_ds = (_strength), .step_ds = (_step) } 1382 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1383 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1384 1385 /** 1386 * struct nand_flash_dev - NAND Flash Device ID Structure 1387 * @name: a human-readable name of the NAND chip 1388 * @dev_id: the device ID (the second byte of the full chip ID array) 1389 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1390 * memory address as @id[0]) 1391 * @dev_id: device ID part of the full chip ID array (refers the same memory 1392 * address as @id[1]) 1393 * @id: full device ID array 1394 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1395 * well as the eraseblock size) is determined from the extended NAND 1396 * chip ID array) 1397 * @chipsize: total chip size in MiB 1398 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1399 * @options: stores various chip bit options 1400 * @id_len: The valid length of the @id. 1401 * @oobsize: OOB size 1402 * @ecc: ECC correctability and step information from the datasheet. 1403 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1404 * @ecc_strength_ds in nand_chip{}. 1405 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1406 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1407 * For example, the "4bit ECC for each 512Byte" can be set with 1408 * NAND_ECC_INFO(4, 512). 1409 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1410 * reset. Should be deduced from timings described 1411 * in the datasheet. 1412 * 1413 */ 1414 struct nand_flash_dev { 1415 char *name; 1416 union { 1417 struct { 1418 uint8_t mfr_id; 1419 uint8_t dev_id; 1420 }; 1421 uint8_t id[NAND_MAX_ID_LEN]; 1422 }; 1423 unsigned int pagesize; 1424 unsigned int chipsize; 1425 unsigned int erasesize; 1426 unsigned int options; 1427 uint16_t id_len; 1428 uint16_t oobsize; 1429 struct { 1430 uint16_t strength_ds; 1431 uint16_t step_ds; 1432 } ecc; 1433 int onfi_timing_mode_default; 1434 }; 1435 1436 /** 1437 * struct nand_manufacturer - NAND Flash Manufacturer structure 1438 * @name: Manufacturer name 1439 * @id: manufacturer ID code of device. 1440 * @ops: manufacturer operations 1441 */ 1442 struct nand_manufacturer { 1443 int id; 1444 char *name; 1445 const struct nand_manufacturer_ops *ops; 1446 }; 1447 1448 const struct nand_manufacturer *nand_get_manufacturer(u8 id); 1449 1450 static inline const char * 1451 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 1452 { 1453 return manufacturer ? manufacturer->name : "Unknown"; 1454 } 1455 1456 extern struct nand_flash_dev nand_flash_ids[]; 1457 1458 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 1459 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; 1460 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; 1461 extern const struct nand_manufacturer_ops micron_nand_manuf_ops; 1462 extern const struct nand_manufacturer_ops amd_nand_manuf_ops; 1463 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; 1464 1465 int nand_default_bbt(struct mtd_info *mtd); 1466 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1467 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1468 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1469 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1470 int allowbbt); 1471 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1472 size_t *retlen, uint8_t *buf); 1473 1474 /** 1475 * struct platform_nand_chip - chip level device structure 1476 * @nr_chips: max. number of chips to scan for 1477 * @chip_offset: chip number offset 1478 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1479 * @partitions: mtd partition list 1480 * @chip_delay: R/B delay value in us 1481 * @options: Option flags, e.g. 16bit buswidth 1482 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1483 * @part_probe_types: NULL-terminated array of probe types 1484 */ 1485 struct platform_nand_chip { 1486 int nr_chips; 1487 int chip_offset; 1488 int nr_partitions; 1489 struct mtd_partition *partitions; 1490 int chip_delay; 1491 unsigned int options; 1492 unsigned int bbt_options; 1493 const char **part_probe_types; 1494 }; 1495 1496 /* Keep gcc happy */ 1497 struct platform_device; 1498 1499 /** 1500 * struct platform_nand_ctrl - controller level device structure 1501 * @probe: platform specific function to probe/setup hardware 1502 * @remove: platform specific function to remove/teardown hardware 1503 * @hwcontrol: platform specific hardware control structure 1504 * @dev_ready: platform specific function to read ready/busy pin 1505 * @select_chip: platform specific chip select function 1506 * @cmd_ctrl: platform specific function for controlling 1507 * ALE/CLE/nCE. Also used to write command and address 1508 * @write_buf: platform specific function for write buffer 1509 * @read_buf: platform specific function for read buffer 1510 * @read_byte: platform specific function to read one byte from chip 1511 * @priv: private data to transport driver specific settings 1512 * 1513 * All fields are optional and depend on the hardware driver requirements 1514 */ 1515 struct platform_nand_ctrl { 1516 int (*probe)(struct platform_device *pdev); 1517 void (*remove)(struct platform_device *pdev); 1518 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1519 int (*dev_ready)(struct mtd_info *mtd); 1520 void (*select_chip)(struct mtd_info *mtd, int chip); 1521 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1522 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1523 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1524 unsigned char (*read_byte)(struct mtd_info *mtd); 1525 void *priv; 1526 }; 1527 1528 /** 1529 * struct platform_nand_data - container structure for platform-specific data 1530 * @chip: chip level chip structure 1531 * @ctrl: controller level device structure 1532 */ 1533 struct platform_nand_data { 1534 struct platform_nand_chip chip; 1535 struct platform_nand_ctrl ctrl; 1536 }; 1537 1538 /* return the supported features. */ 1539 static inline int onfi_feature(struct nand_chip *chip) 1540 { 1541 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1542 } 1543 1544 /* return the supported asynchronous timing mode. */ 1545 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1546 { 1547 if (!chip->onfi_version) 1548 return ONFI_TIMING_MODE_UNKNOWN; 1549 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1550 } 1551 1552 /* return the supported synchronous timing mode. */ 1553 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1554 { 1555 if (!chip->onfi_version) 1556 return ONFI_TIMING_MODE_UNKNOWN; 1557 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1558 } 1559 1560 int onfi_fill_data_interface(struct nand_chip *chip, 1561 enum nand_data_interface_type type, 1562 int timing_mode); 1563 1564 /* 1565 * Check if it is a SLC nand. 1566 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1567 * We do not distinguish the MLC and TLC now. 1568 */ 1569 static inline bool nand_is_slc(struct nand_chip *chip) 1570 { 1571 WARN(chip->bits_per_cell == 0, 1572 "chip->bits_per_cell is used uninitialized\n"); 1573 return chip->bits_per_cell == 1; 1574 } 1575 1576 /** 1577 * Check if the opcode's address should be sent only on the lower 8 bits 1578 * @command: opcode to check 1579 */ 1580 static inline int nand_opcode_8bits(unsigned int command) 1581 { 1582 switch (command) { 1583 case NAND_CMD_READID: 1584 case NAND_CMD_PARAM: 1585 case NAND_CMD_GET_FEATURES: 1586 case NAND_CMD_SET_FEATURES: 1587 return 1; 1588 default: 1589 break; 1590 } 1591 return 0; 1592 } 1593 1594 /* return the supported JEDEC features. */ 1595 static inline int jedec_feature(struct nand_chip *chip) 1596 { 1597 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1598 : 0; 1599 } 1600 1601 /* get timing characteristics from ONFI timing mode. */ 1602 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1603 1604 int nand_check_erased_ecc_chunk(void *data, int datalen, 1605 void *ecc, int ecclen, 1606 void *extraoob, int extraooblen, 1607 int threshold); 1608 1609 int nand_check_ecc_caps(struct nand_chip *chip, 1610 const struct nand_ecc_caps *caps, int oobavail); 1611 1612 int nand_match_ecc_req(struct nand_chip *chip, 1613 const struct nand_ecc_caps *caps, int oobavail); 1614 1615 int nand_maximize_ecc(struct nand_chip *chip, 1616 const struct nand_ecc_caps *caps, int oobavail); 1617 1618 /* Default write_oob implementation */ 1619 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1620 1621 /* Default write_oob syndrome implementation */ 1622 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1623 int page); 1624 1625 /* Default read_oob implementation */ 1626 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1627 1628 /* Default read_oob syndrome implementation */ 1629 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1630 int page); 1631 1632 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1633 int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, 1634 struct nand_chip *chip, int addr, 1635 u8 *subfeature_param); 1636 1637 /* Default read_page_raw implementation */ 1638 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1639 uint8_t *buf, int oob_required, int page); 1640 1641 /* Default write_page_raw implementation */ 1642 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1643 const uint8_t *buf, int oob_required, int page); 1644 1645 /* Reset and initialize a NAND device */ 1646 int nand_reset(struct nand_chip *chip, int chipnr); 1647 1648 /* NAND operation helpers */ 1649 int nand_reset_op(struct nand_chip *chip); 1650 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1651 unsigned int len); 1652 int nand_status_op(struct nand_chip *chip, u8 *status); 1653 int nand_exit_status_op(struct nand_chip *chip); 1654 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1655 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1656 unsigned int offset_in_page, void *buf, unsigned int len); 1657 int nand_change_read_column_op(struct nand_chip *chip, 1658 unsigned int offset_in_page, void *buf, 1659 unsigned int len, bool force_8bit); 1660 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1661 unsigned int offset_in_page, void *buf, unsigned int len); 1662 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1663 unsigned int offset_in_page, const void *buf, 1664 unsigned int len); 1665 int nand_prog_page_end_op(struct nand_chip *chip); 1666 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1667 unsigned int offset_in_page, const void *buf, 1668 unsigned int len); 1669 int nand_change_write_column_op(struct nand_chip *chip, 1670 unsigned int offset_in_page, const void *buf, 1671 unsigned int len, bool force_8bit); 1672 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1673 bool force_8bit); 1674 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1675 unsigned int len, bool force_8bit); 1676 1677 /* Free resources held by the NAND device */ 1678 void nand_cleanup(struct nand_chip *chip); 1679 1680 /* Default extended ID decoding function */ 1681 void nand_decode_ext_id(struct nand_chip *chip); 1682 1683 /* 1684 * External helper for controller drivers that have to implement the WAITRDY 1685 * instruction and have no physical pin to check it. 1686 */ 1687 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1688 1689 #endif /* __LINUX_MTD_RAWNAND_H */ 1690