1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2000-2010 David Woodhouse <[email protected]> 4 * Steven J. Hill <[email protected]> 5 * Thomas Gleixner <[email protected]> 6 * 7 * Info: 8 * Contains standard defines and IDs for NAND flash devices 9 * 10 * Changelog: 11 * See git changelog. 12 */ 13 #ifndef __LINUX_MTD_RAWNAND_H 14 #define __LINUX_MTD_RAWNAND_H 15 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/nand.h> 18 #include <linux/mtd/flashchip.h> 19 #include <linux/mtd/bbm.h> 20 #include <linux/mtd/jedec.h> 21 #include <linux/mtd/onfi.h> 22 #include <linux/mutex.h> 23 #include <linux/of.h> 24 #include <linux/types.h> 25 26 struct nand_chip; 27 28 /* The maximum number of NAND chips in an array */ 29 #define NAND_MAX_CHIPS 8 30 31 /* 32 * Constants for hardware specific CLE/ALE/NCE function 33 * 34 * These are bits which can be or'ed to set/clear multiple 35 * bits in one go. 36 */ 37 /* Select the chip by setting nCE to low */ 38 #define NAND_NCE 0x01 39 /* Select the command latch by setting CLE to high */ 40 #define NAND_CLE 0x02 41 /* Select the address latch by setting ALE to high */ 42 #define NAND_ALE 0x04 43 44 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 45 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 46 #define NAND_CTRL_CHANGE 0x80 47 48 /* 49 * Standard NAND flash commands 50 */ 51 #define NAND_CMD_READ0 0 52 #define NAND_CMD_READ1 1 53 #define NAND_CMD_RNDOUT 5 54 #define NAND_CMD_PAGEPROG 0x10 55 #define NAND_CMD_READOOB 0x50 56 #define NAND_CMD_ERASE1 0x60 57 #define NAND_CMD_STATUS 0x70 58 #define NAND_CMD_SEQIN 0x80 59 #define NAND_CMD_RNDIN 0x85 60 #define NAND_CMD_READID 0x90 61 #define NAND_CMD_ERASE2 0xd0 62 #define NAND_CMD_PARAM 0xec 63 #define NAND_CMD_GET_FEATURES 0xee 64 #define NAND_CMD_SET_FEATURES 0xef 65 #define NAND_CMD_RESET 0xff 66 67 /* Extended commands for large page devices */ 68 #define NAND_CMD_READSTART 0x30 69 #define NAND_CMD_RNDOUTSTART 0xE0 70 #define NAND_CMD_CACHEDPROG 0x15 71 72 #define NAND_CMD_NONE -1 73 74 /* Status bits */ 75 #define NAND_STATUS_FAIL 0x01 76 #define NAND_STATUS_FAIL_N1 0x02 77 #define NAND_STATUS_TRUE_READY 0x20 78 #define NAND_STATUS_READY 0x40 79 #define NAND_STATUS_WP 0x80 80 81 #define NAND_DATA_IFACE_CHECK_ONLY -1 82 83 /* 84 * Constants for Hardware ECC 85 */ 86 /* Reset Hardware ECC for read */ 87 #define NAND_ECC_READ 0 88 /* Reset Hardware ECC for write */ 89 #define NAND_ECC_WRITE 1 90 /* Enable Hardware ECC before syndrome is read back from flash */ 91 #define NAND_ECC_READSYN 2 92 93 /* 94 * Enable generic NAND 'page erased' check. This check is only done when 95 * ecc.correct() returns -EBADMSG. 96 * Set this flag if your implementation does not fix bitflips in erased 97 * pages and you want to rely on the default implementation. 98 */ 99 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 100 101 /* 102 * Option constants for bizarre disfunctionality and real 103 * features. 104 */ 105 106 /* Buswidth is 16 bit */ 107 #define NAND_BUSWIDTH_16 BIT(1) 108 109 /* 110 * When using software implementation of Hamming, we can specify which byte 111 * ordering should be used. 112 */ 113 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 114 115 /* Chip has cache program function */ 116 #define NAND_CACHEPRG BIT(3) 117 /* Options valid for Samsung large page devices */ 118 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 119 120 /* 121 * Chip requires ready check on read (for auto-incremented sequential read). 122 * True only for small page devices; large page devices do not support 123 * autoincrement. 124 */ 125 #define NAND_NEED_READRDY BIT(8) 126 127 /* Chip does not allow subpage writes */ 128 #define NAND_NO_SUBPAGE_WRITE BIT(9) 129 130 /* Device is one of 'new' xD cards that expose fake nand command set */ 131 #define NAND_BROKEN_XD BIT(10) 132 133 /* Device behaves just like nand, but is readonly */ 134 #define NAND_ROM BIT(11) 135 136 /* Device supports subpage reads */ 137 #define NAND_SUBPAGE_READ BIT(12) 138 /* Macros to identify the above */ 139 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 140 141 /* 142 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 143 * patterns. 144 */ 145 #define NAND_NEED_SCRAMBLING BIT(13) 146 147 /* Device needs 3rd row address cycle */ 148 #define NAND_ROW_ADDR_3 BIT(14) 149 150 /* Non chip related options */ 151 /* This option skips the bbt scan during initialization. */ 152 #define NAND_SKIP_BBTSCAN BIT(16) 153 /* Chip may not exist, so silence any errors in scan */ 154 #define NAND_SCAN_SILENT_NODEV BIT(18) 155 156 /* 157 * Autodetect nand buswidth with readid/onfi. 158 * This suppose the driver will configure the hardware in 8 bits mode 159 * when calling nand_scan_ident, and update its configuration 160 * before calling nand_scan_tail. 161 */ 162 #define NAND_BUSWIDTH_AUTO BIT(19) 163 164 /* 165 * This option could be defined by controller drivers to protect against 166 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 167 */ 168 #define NAND_USES_DMA BIT(20) 169 170 /* 171 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 172 * on the default ->cmdfunc() implementation, you may want to let the core 173 * handle the tCCS delay which is required when a column change (RNDIN or 174 * RNDOUT) is requested. 175 * If your controller already takes care of this delay, you don't need to set 176 * this flag. 177 */ 178 #define NAND_WAIT_TCCS BIT(21) 179 180 /* 181 * Whether the NAND chip is a boot medium. Drivers might use this information 182 * to select ECC algorithms supported by the boot ROM or similar restrictions. 183 */ 184 #define NAND_IS_BOOT_MEDIUM BIT(22) 185 186 /* 187 * Do not try to tweak the timings at runtime. This is needed when the 188 * controller initializes the timings on itself or when it relies on 189 * configuration done by the bootloader. 190 */ 191 #define NAND_KEEP_TIMINGS BIT(23) 192 193 /* 194 * There are different places where the manufacturer stores the factory bad 195 * block markers. 196 * 197 * Position within the block: Each of these pages needs to be checked for a 198 * bad block marking pattern. 199 */ 200 #define NAND_BBM_FIRSTPAGE BIT(24) 201 #define NAND_BBM_SECONDPAGE BIT(25) 202 #define NAND_BBM_LASTPAGE BIT(26) 203 204 /* 205 * Some controllers with pipelined ECC engines override the BBM marker with 206 * data or ECC bytes, thus making bad block detection through bad block marker 207 * impossible. Let's flag those chips so the core knows it shouldn't check the 208 * BBM and consider all blocks good. 209 */ 210 #define NAND_NO_BBM_QUIRK BIT(27) 211 212 /* Cell info constants */ 213 #define NAND_CI_CHIPNR_MSK 0x03 214 #define NAND_CI_CELLTYPE_MSK 0x0C 215 #define NAND_CI_CELLTYPE_SHIFT 2 216 217 /* Position within the OOB data of the page */ 218 #define NAND_BBM_POS_SMALL 5 219 #define NAND_BBM_POS_LARGE 0 220 221 /** 222 * struct nand_parameters - NAND generic parameters from the parameter page 223 * @model: Model name 224 * @supports_set_get_features: The NAND chip supports setting/getting features 225 * @set_feature_list: Bitmap of features that can be set 226 * @get_feature_list: Bitmap of features that can be get 227 * @onfi: ONFI specific parameters 228 */ 229 struct nand_parameters { 230 /* Generic parameters */ 231 const char *model; 232 bool supports_set_get_features; 233 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 234 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 235 236 /* ONFI parameters */ 237 struct onfi_params *onfi; 238 }; 239 240 /* The maximum expected count of bytes in the NAND ID sequence */ 241 #define NAND_MAX_ID_LEN 8 242 243 /** 244 * struct nand_id - NAND id structure 245 * @data: buffer containing the id bytes. 246 * @len: ID length. 247 */ 248 struct nand_id { 249 u8 data[NAND_MAX_ID_LEN]; 250 int len; 251 }; 252 253 /** 254 * struct nand_ecc_step_info - ECC step information of ECC engine 255 * @stepsize: data bytes per ECC step 256 * @strengths: array of supported strengths 257 * @nstrengths: number of supported strengths 258 */ 259 struct nand_ecc_step_info { 260 int stepsize; 261 const int *strengths; 262 int nstrengths; 263 }; 264 265 /** 266 * struct nand_ecc_caps - capability of ECC engine 267 * @stepinfos: array of ECC step information 268 * @nstepinfos: number of ECC step information 269 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 270 */ 271 struct nand_ecc_caps { 272 const struct nand_ecc_step_info *stepinfos; 273 int nstepinfos; 274 int (*calc_ecc_bytes)(int step_size, int strength); 275 }; 276 277 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 278 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 279 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 280 static const struct nand_ecc_step_info __name##_stepinfo = { \ 281 .stepsize = __step, \ 282 .strengths = __name##_strengths, \ 283 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 284 }; \ 285 static const struct nand_ecc_caps __name = { \ 286 .stepinfos = &__name##_stepinfo, \ 287 .nstepinfos = 1, \ 288 .calc_ecc_bytes = __calc, \ 289 } 290 291 /** 292 * struct nand_ecc_ctrl - Control structure for ECC 293 * @engine_type: ECC engine type 294 * @placement: OOB bytes placement 295 * @algo: ECC algorithm 296 * @steps: number of ECC steps per page 297 * @size: data bytes per ECC step 298 * @bytes: ECC bytes per step 299 * @strength: max number of correctible bits per ECC step 300 * @total: total number of ECC bytes per page 301 * @prepad: padding information for syndrome based ECC generators 302 * @postpad: padding information for syndrome based ECC generators 303 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 304 * @calc_buf: buffer for calculated ECC, size is oobsize. 305 * @code_buf: buffer for ECC read from flash, size is oobsize. 306 * @hwctl: function to control hardware ECC generator. Must only 307 * be provided if an hardware ECC is available 308 * @calculate: function for ECC calculation or readback from ECC hardware 309 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 310 * Should return a positive number representing the number of 311 * corrected bitflips, -EBADMSG if the number of bitflips exceed 312 * ECC strength, or any other error code if the error is not 313 * directly related to correction. 314 * If -EBADMSG is returned the input buffers should be left 315 * untouched. 316 * @read_page_raw: function to read a raw page without ECC. This function 317 * should hide the specific layout used by the ECC 318 * controller and always return contiguous in-band and 319 * out-of-band data even if they're not stored 320 * contiguously on the NAND chip (e.g. 321 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 322 * out-of-band data). 323 * @write_page_raw: function to write a raw page without ECC. This function 324 * should hide the specific layout used by the ECC 325 * controller and consider the passed data as contiguous 326 * in-band and out-of-band data. ECC controller is 327 * responsible for doing the appropriate transformations 328 * to adapt to its specific layout (e.g. 329 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 330 * out-of-band data). 331 * @read_page: function to read a page according to the ECC generator 332 * requirements; returns maximum number of bitflips corrected in 333 * any single ECC step, -EIO hw error 334 * @read_subpage: function to read parts of the page covered by ECC; 335 * returns same as read_page() 336 * @write_subpage: function to write parts of the page covered by ECC. 337 * @write_page: function to write a page according to the ECC generator 338 * requirements. 339 * @write_oob_raw: function to write chip OOB data without ECC 340 * @read_oob_raw: function to read chip OOB data without ECC 341 * @read_oob: function to read chip OOB data 342 * @write_oob: function to write chip OOB data 343 */ 344 struct nand_ecc_ctrl { 345 enum nand_ecc_engine_type engine_type; 346 enum nand_ecc_placement placement; 347 enum nand_ecc_algo algo; 348 int steps; 349 int size; 350 int bytes; 351 int total; 352 int strength; 353 int prepad; 354 int postpad; 355 unsigned int options; 356 u8 *calc_buf; 357 u8 *code_buf; 358 void (*hwctl)(struct nand_chip *chip, int mode); 359 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 360 uint8_t *ecc_code); 361 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 362 uint8_t *calc_ecc); 363 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 364 int oob_required, int page); 365 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 366 int oob_required, int page); 367 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 368 int oob_required, int page); 369 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 370 uint32_t len, uint8_t *buf, int page); 371 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 372 uint32_t data_len, const uint8_t *data_buf, 373 int oob_required, int page); 374 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 375 int oob_required, int page); 376 int (*write_oob_raw)(struct nand_chip *chip, int page); 377 int (*read_oob_raw)(struct nand_chip *chip, int page); 378 int (*read_oob)(struct nand_chip *chip, int page); 379 int (*write_oob)(struct nand_chip *chip, int page); 380 }; 381 382 /** 383 * struct nand_sdr_timings - SDR NAND chip timings 384 * 385 * This struct defines the timing requirements of a SDR NAND chip. 386 * These information can be found in every NAND datasheets and the timings 387 * meaning are described in the ONFI specifications: 388 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 389 * Parameters) 390 * 391 * All these timings are expressed in picoseconds. 392 * 393 * @tBERS_max: Block erase time 394 * @tCCS_min: Change column setup time 395 * @tPROG_max: Page program time 396 * @tR_max: Page read time 397 * @tALH_min: ALE hold time 398 * @tADL_min: ALE to data loading time 399 * @tALS_min: ALE setup time 400 * @tAR_min: ALE to RE# delay 401 * @tCEA_max: CE# access time 402 * @tCEH_min: CE# high hold time 403 * @tCH_min: CE# hold time 404 * @tCHZ_max: CE# high to output hi-Z 405 * @tCLH_min: CLE hold time 406 * @tCLR_min: CLE to RE# delay 407 * @tCLS_min: CLE setup time 408 * @tCOH_min: CE# high to output hold 409 * @tCS_min: CE# setup time 410 * @tDH_min: Data hold time 411 * @tDS_min: Data setup time 412 * @tFEAT_max: Busy time for Set Features and Get Features 413 * @tIR_min: Output hi-Z to RE# low 414 * @tITC_max: Interface and Timing Mode Change time 415 * @tRC_min: RE# cycle time 416 * @tREA_max: RE# access time 417 * @tREH_min: RE# high hold time 418 * @tRHOH_min: RE# high to output hold 419 * @tRHW_min: RE# high to WE# low 420 * @tRHZ_max: RE# high to output hi-Z 421 * @tRLOH_min: RE# low to output hold 422 * @tRP_min: RE# pulse width 423 * @tRR_min: Ready to RE# low (data only) 424 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 425 * rising edge of R/B#. 426 * @tWB_max: WE# high to SR[6] low 427 * @tWC_min: WE# cycle time 428 * @tWH_min: WE# high hold time 429 * @tWHR_min: WE# high to RE# low 430 * @tWP_min: WE# pulse width 431 * @tWW_min: WP# transition to WE# low 432 */ 433 struct nand_sdr_timings { 434 u64 tBERS_max; 435 u32 tCCS_min; 436 u64 tPROG_max; 437 u64 tR_max; 438 u32 tALH_min; 439 u32 tADL_min; 440 u32 tALS_min; 441 u32 tAR_min; 442 u32 tCEA_max; 443 u32 tCEH_min; 444 u32 tCH_min; 445 u32 tCHZ_max; 446 u32 tCLH_min; 447 u32 tCLR_min; 448 u32 tCLS_min; 449 u32 tCOH_min; 450 u32 tCS_min; 451 u32 tDH_min; 452 u32 tDS_min; 453 u32 tFEAT_max; 454 u32 tIR_min; 455 u32 tITC_max; 456 u32 tRC_min; 457 u32 tREA_max; 458 u32 tREH_min; 459 u32 tRHOH_min; 460 u32 tRHW_min; 461 u32 tRHZ_max; 462 u32 tRLOH_min; 463 u32 tRP_min; 464 u32 tRR_min; 465 u64 tRST_max; 466 u32 tWB_max; 467 u32 tWC_min; 468 u32 tWH_min; 469 u32 tWHR_min; 470 u32 tWP_min; 471 u32 tWW_min; 472 }; 473 474 /** 475 * enum nand_interface_type - NAND interface type 476 * @NAND_SDR_IFACE: Single Data Rate interface 477 */ 478 enum nand_interface_type { 479 NAND_SDR_IFACE, 480 }; 481 482 /** 483 * struct nand_interface_config - NAND interface timing 484 * @type: type of the timing 485 * @timings: The timing information 486 * @timings.mode: Timing mode as defined in the specification 487 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 488 */ 489 struct nand_interface_config { 490 enum nand_interface_type type; 491 struct nand_timings { 492 unsigned int mode; 493 union { 494 struct nand_sdr_timings sdr; 495 }; 496 } timings; 497 }; 498 499 /** 500 * nand_get_sdr_timings - get SDR timing from data interface 501 * @conf: The data interface 502 */ 503 static inline const struct nand_sdr_timings * 504 nand_get_sdr_timings(const struct nand_interface_config *conf) 505 { 506 if (conf->type != NAND_SDR_IFACE) 507 return ERR_PTR(-EINVAL); 508 509 return &conf->timings.sdr; 510 } 511 512 /** 513 * struct nand_op_cmd_instr - Definition of a command instruction 514 * @opcode: the command to issue in one cycle 515 */ 516 struct nand_op_cmd_instr { 517 u8 opcode; 518 }; 519 520 /** 521 * struct nand_op_addr_instr - Definition of an address instruction 522 * @naddrs: length of the @addrs array 523 * @addrs: array containing the address cycles to issue 524 */ 525 struct nand_op_addr_instr { 526 unsigned int naddrs; 527 const u8 *addrs; 528 }; 529 530 /** 531 * struct nand_op_data_instr - Definition of a data instruction 532 * @len: number of data bytes to move 533 * @buf: buffer to fill 534 * @buf.in: buffer to fill when reading from the NAND chip 535 * @buf.out: buffer to read from when writing to the NAND chip 536 * @force_8bit: force 8-bit access 537 * 538 * Please note that "in" and "out" are inverted from the ONFI specification 539 * and are from the controller perspective, so a "in" is a read from the NAND 540 * chip while a "out" is a write to the NAND chip. 541 */ 542 struct nand_op_data_instr { 543 unsigned int len; 544 union { 545 void *in; 546 const void *out; 547 } buf; 548 bool force_8bit; 549 }; 550 551 /** 552 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 553 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 554 */ 555 struct nand_op_waitrdy_instr { 556 unsigned int timeout_ms; 557 }; 558 559 /** 560 * enum nand_op_instr_type - Definition of all instruction types 561 * @NAND_OP_CMD_INSTR: command instruction 562 * @NAND_OP_ADDR_INSTR: address instruction 563 * @NAND_OP_DATA_IN_INSTR: data in instruction 564 * @NAND_OP_DATA_OUT_INSTR: data out instruction 565 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 566 */ 567 enum nand_op_instr_type { 568 NAND_OP_CMD_INSTR, 569 NAND_OP_ADDR_INSTR, 570 NAND_OP_DATA_IN_INSTR, 571 NAND_OP_DATA_OUT_INSTR, 572 NAND_OP_WAITRDY_INSTR, 573 }; 574 575 /** 576 * struct nand_op_instr - Instruction object 577 * @type: the instruction type 578 * @ctx: extra data associated to the instruction. You'll have to use the 579 * appropriate element depending on @type 580 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 581 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 582 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 583 * or %NAND_OP_DATA_OUT_INSTR 584 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 585 * @delay_ns: delay the controller should apply after the instruction has been 586 * issued on the bus. Most modern controllers have internal timings 587 * control logic, and in this case, the controller driver can ignore 588 * this field. 589 */ 590 struct nand_op_instr { 591 enum nand_op_instr_type type; 592 union { 593 struct nand_op_cmd_instr cmd; 594 struct nand_op_addr_instr addr; 595 struct nand_op_data_instr data; 596 struct nand_op_waitrdy_instr waitrdy; 597 } ctx; 598 unsigned int delay_ns; 599 }; 600 601 /* 602 * Special handling must be done for the WAITRDY timeout parameter as it usually 603 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 604 * tBERS (during an erase) which all of them are u64 values that cannot be 605 * divided by usual kernel macros and must be handled with the special 606 * DIV_ROUND_UP_ULL() macro. 607 * 608 * Cast to type of dividend is needed here to guarantee that the result won't 609 * be an unsigned long long when the dividend is an unsigned long (or smaller), 610 * which is what the compiler does when it sees ternary operator with 2 611 * different return types (picks the largest type to make sure there's no 612 * loss). 613 */ 614 #define __DIVIDE(dividend, divisor) ({ \ 615 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 616 DIV_ROUND_UP(dividend, divisor) : \ 617 DIV_ROUND_UP_ULL(dividend, divisor)); \ 618 }) 619 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 620 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 621 622 #define NAND_OP_CMD(id, ns) \ 623 { \ 624 .type = NAND_OP_CMD_INSTR, \ 625 .ctx.cmd.opcode = id, \ 626 .delay_ns = ns, \ 627 } 628 629 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 630 { \ 631 .type = NAND_OP_ADDR_INSTR, \ 632 .ctx.addr = { \ 633 .naddrs = ncycles, \ 634 .addrs = cycles, \ 635 }, \ 636 .delay_ns = ns, \ 637 } 638 639 #define NAND_OP_DATA_IN(l, b, ns) \ 640 { \ 641 .type = NAND_OP_DATA_IN_INSTR, \ 642 .ctx.data = { \ 643 .len = l, \ 644 .buf.in = b, \ 645 .force_8bit = false, \ 646 }, \ 647 .delay_ns = ns, \ 648 } 649 650 #define NAND_OP_DATA_OUT(l, b, ns) \ 651 { \ 652 .type = NAND_OP_DATA_OUT_INSTR, \ 653 .ctx.data = { \ 654 .len = l, \ 655 .buf.out = b, \ 656 .force_8bit = false, \ 657 }, \ 658 .delay_ns = ns, \ 659 } 660 661 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 662 { \ 663 .type = NAND_OP_DATA_IN_INSTR, \ 664 .ctx.data = { \ 665 .len = l, \ 666 .buf.in = b, \ 667 .force_8bit = true, \ 668 }, \ 669 .delay_ns = ns, \ 670 } 671 672 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 673 { \ 674 .type = NAND_OP_DATA_OUT_INSTR, \ 675 .ctx.data = { \ 676 .len = l, \ 677 .buf.out = b, \ 678 .force_8bit = true, \ 679 }, \ 680 .delay_ns = ns, \ 681 } 682 683 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 684 { \ 685 .type = NAND_OP_WAITRDY_INSTR, \ 686 .ctx.waitrdy.timeout_ms = tout_ms, \ 687 .delay_ns = ns, \ 688 } 689 690 /** 691 * struct nand_subop - a sub operation 692 * @cs: the CS line to select for this NAND sub-operation 693 * @instrs: array of instructions 694 * @ninstrs: length of the @instrs array 695 * @first_instr_start_off: offset to start from for the first instruction 696 * of the sub-operation 697 * @last_instr_end_off: offset to end at (excluded) for the last instruction 698 * of the sub-operation 699 * 700 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 701 * address instructions. 702 * 703 * When an operation cannot be handled as is by the NAND controller, it will 704 * be split by the parser into sub-operations which will be passed to the 705 * controller driver. 706 */ 707 struct nand_subop { 708 unsigned int cs; 709 const struct nand_op_instr *instrs; 710 unsigned int ninstrs; 711 unsigned int first_instr_start_off; 712 unsigned int last_instr_end_off; 713 }; 714 715 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 716 unsigned int op_id); 717 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 718 unsigned int op_id); 719 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 720 unsigned int op_id); 721 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 722 unsigned int op_id); 723 724 /** 725 * struct nand_op_parser_addr_constraints - Constraints for address instructions 726 * @maxcycles: maximum number of address cycles the controller can issue in a 727 * single step 728 */ 729 struct nand_op_parser_addr_constraints { 730 unsigned int maxcycles; 731 }; 732 733 /** 734 * struct nand_op_parser_data_constraints - Constraints for data instructions 735 * @maxlen: maximum data length that the controller can handle in a single step 736 */ 737 struct nand_op_parser_data_constraints { 738 unsigned int maxlen; 739 }; 740 741 /** 742 * struct nand_op_parser_pattern_elem - One element of a pattern 743 * @type: the instructuction type 744 * @optional: whether this element of the pattern is optional or mandatory 745 * @ctx: address or data constraint 746 * @ctx.addr: address constraint (number of cycles) 747 * @ctx.data: data constraint (data length) 748 */ 749 struct nand_op_parser_pattern_elem { 750 enum nand_op_instr_type type; 751 bool optional; 752 union { 753 struct nand_op_parser_addr_constraints addr; 754 struct nand_op_parser_data_constraints data; 755 } ctx; 756 }; 757 758 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 759 { \ 760 .type = NAND_OP_CMD_INSTR, \ 761 .optional = _opt, \ 762 } 763 764 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 765 { \ 766 .type = NAND_OP_ADDR_INSTR, \ 767 .optional = _opt, \ 768 .ctx.addr.maxcycles = _maxcycles, \ 769 } 770 771 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 772 { \ 773 .type = NAND_OP_DATA_IN_INSTR, \ 774 .optional = _opt, \ 775 .ctx.data.maxlen = _maxlen, \ 776 } 777 778 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 779 { \ 780 .type = NAND_OP_DATA_OUT_INSTR, \ 781 .optional = _opt, \ 782 .ctx.data.maxlen = _maxlen, \ 783 } 784 785 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 786 { \ 787 .type = NAND_OP_WAITRDY_INSTR, \ 788 .optional = _opt, \ 789 } 790 791 /** 792 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 793 * @elems: array of pattern elements 794 * @nelems: number of pattern elements in @elems array 795 * @exec: the function that will issue a sub-operation 796 * 797 * A pattern is a list of elements, each element reprensenting one instruction 798 * with its constraints. The pattern itself is used by the core to match NAND 799 * chip operation with NAND controller operations. 800 * Once a match between a NAND controller operation pattern and a NAND chip 801 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 802 * hook is called so that the controller driver can issue the operation on the 803 * bus. 804 * 805 * Controller drivers should declare as many patterns as they support and pass 806 * this list of patterns (created with the help of the following macro) to 807 * the nand_op_parser_exec_op() helper. 808 */ 809 struct nand_op_parser_pattern { 810 const struct nand_op_parser_pattern_elem *elems; 811 unsigned int nelems; 812 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 813 }; 814 815 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 816 { \ 817 .exec = _exec, \ 818 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 819 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 820 sizeof(struct nand_op_parser_pattern_elem), \ 821 } 822 823 /** 824 * struct nand_op_parser - NAND controller operation parser descriptor 825 * @patterns: array of supported patterns 826 * @npatterns: length of the @patterns array 827 * 828 * The parser descriptor is just an array of supported patterns which will be 829 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 830 * NAND operation (or tries to determine if a specific operation is supported). 831 * 832 * It is worth mentioning that patterns will be tested in their declaration 833 * order, and the first match will be taken, so it's important to order patterns 834 * appropriately so that simple/inefficient patterns are placed at the end of 835 * the list. Usually, this is where you put single instruction patterns. 836 */ 837 struct nand_op_parser { 838 const struct nand_op_parser_pattern *patterns; 839 unsigned int npatterns; 840 }; 841 842 #define NAND_OP_PARSER(...) \ 843 { \ 844 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 845 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 846 sizeof(struct nand_op_parser_pattern), \ 847 } 848 849 /** 850 * struct nand_operation - NAND operation descriptor 851 * @cs: the CS line to select for this NAND operation 852 * @instrs: array of instructions to execute 853 * @ninstrs: length of the @instrs array 854 * 855 * The actual operation structure that will be passed to chip->exec_op(). 856 */ 857 struct nand_operation { 858 unsigned int cs; 859 const struct nand_op_instr *instrs; 860 unsigned int ninstrs; 861 }; 862 863 #define NAND_OPERATION(_cs, _instrs) \ 864 { \ 865 .cs = _cs, \ 866 .instrs = _instrs, \ 867 .ninstrs = ARRAY_SIZE(_instrs), \ 868 } 869 870 int nand_op_parser_exec_op(struct nand_chip *chip, 871 const struct nand_op_parser *parser, 872 const struct nand_operation *op, bool check_only); 873 874 static inline void nand_op_trace(const char *prefix, 875 const struct nand_op_instr *instr) 876 { 877 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) 878 switch (instr->type) { 879 case NAND_OP_CMD_INSTR: 880 pr_debug("%sCMD [0x%02x]\n", prefix, 881 instr->ctx.cmd.opcode); 882 break; 883 case NAND_OP_ADDR_INSTR: 884 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix, 885 instr->ctx.addr.naddrs, 886 instr->ctx.addr.naddrs < 64 ? 887 instr->ctx.addr.naddrs : 64, 888 instr->ctx.addr.addrs); 889 break; 890 case NAND_OP_DATA_IN_INSTR: 891 pr_debug("%sDATA_IN [%d B%s]\n", prefix, 892 instr->ctx.data.len, 893 instr->ctx.data.force_8bit ? 894 ", force 8-bit" : ""); 895 break; 896 case NAND_OP_DATA_OUT_INSTR: 897 pr_debug("%sDATA_OUT [%d B%s]\n", prefix, 898 instr->ctx.data.len, 899 instr->ctx.data.force_8bit ? 900 ", force 8-bit" : ""); 901 break; 902 case NAND_OP_WAITRDY_INSTR: 903 pr_debug("%sWAITRDY [max %d ms]\n", prefix, 904 instr->ctx.waitrdy.timeout_ms); 905 break; 906 } 907 #endif 908 } 909 910 /** 911 * struct nand_controller_ops - Controller operations 912 * 913 * @attach_chip: this method is called after the NAND detection phase after 914 * flash ID and MTD fields such as erase size, page size and OOB 915 * size have been set up. ECC requirements are available if 916 * provided by the NAND chip or device tree. Typically used to 917 * choose the appropriate ECC configuration and allocate 918 * associated resources. 919 * This hook is optional. 920 * @detach_chip: free all resources allocated/claimed in 921 * nand_controller_ops->attach_chip(). 922 * This hook is optional. 923 * @exec_op: controller specific method to execute NAND operations. 924 * This method replaces chip->legacy.cmdfunc(), 925 * chip->legacy.{read,write}_{buf,byte,word}(), 926 * chip->legacy.dev_ready() and chip->legacy.waifunc(). 927 * @setup_interface: setup the data interface and timing. If chipnr is set to 928 * %NAND_DATA_IFACE_CHECK_ONLY this means the configuration 929 * should not be applied but only checked. 930 * This hook is optional. 931 */ 932 struct nand_controller_ops { 933 int (*attach_chip)(struct nand_chip *chip); 934 void (*detach_chip)(struct nand_chip *chip); 935 int (*exec_op)(struct nand_chip *chip, 936 const struct nand_operation *op, 937 bool check_only); 938 int (*setup_interface)(struct nand_chip *chip, int chipnr, 939 const struct nand_interface_config *conf); 940 }; 941 942 /** 943 * struct nand_controller - Structure used to describe a NAND controller 944 * 945 * @lock: lock used to serialize accesses to the NAND controller 946 * @ops: NAND controller operations. 947 */ 948 struct nand_controller { 949 struct mutex lock; 950 const struct nand_controller_ops *ops; 951 }; 952 953 static inline void nand_controller_init(struct nand_controller *nfc) 954 { 955 mutex_init(&nfc->lock); 956 } 957 958 /** 959 * struct nand_legacy - NAND chip legacy fields/hooks 960 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 961 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 962 * @select_chip: select/deselect a specific target/die 963 * @read_byte: read one byte from the chip 964 * @write_byte: write a single byte to the chip on the low 8 I/O lines 965 * @write_buf: write data from the buffer to the chip 966 * @read_buf: read data from the chip into the buffer 967 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 968 * to write command and address 969 * @cmdfunc: hardware specific function for writing commands to the chip. 970 * @dev_ready: hardware specific function for accessing device ready/busy line. 971 * If set to NULL no access to ready/busy is available and the 972 * ready/busy information is read from the chip status register. 973 * @waitfunc: hardware specific function for wait on ready. 974 * @block_bad: check if a block is bad, using OOB markers 975 * @block_markbad: mark a block bad 976 * @set_features: set the NAND chip features 977 * @get_features: get the NAND chip features 978 * @chip_delay: chip dependent delay for transferring data from array to read 979 * regs (tR). 980 * @dummy_controller: dummy controller implementation for drivers that can 981 * only control a single chip 982 * 983 * If you look at this structure you're already wrong. These fields/hooks are 984 * all deprecated. 985 */ 986 struct nand_legacy { 987 void __iomem *IO_ADDR_R; 988 void __iomem *IO_ADDR_W; 989 void (*select_chip)(struct nand_chip *chip, int cs); 990 u8 (*read_byte)(struct nand_chip *chip); 991 void (*write_byte)(struct nand_chip *chip, u8 byte); 992 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 993 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 994 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 995 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 996 int page_addr); 997 int (*dev_ready)(struct nand_chip *chip); 998 int (*waitfunc)(struct nand_chip *chip); 999 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 1000 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 1001 int (*set_features)(struct nand_chip *chip, int feature_addr, 1002 u8 *subfeature_para); 1003 int (*get_features)(struct nand_chip *chip, int feature_addr, 1004 u8 *subfeature_para); 1005 int chip_delay; 1006 struct nand_controller dummy_controller; 1007 }; 1008 1009 /** 1010 * struct nand_chip_ops - NAND chip operations 1011 * @suspend: Suspend operation 1012 * @resume: Resume operation 1013 * @lock_area: Lock operation 1014 * @unlock_area: Unlock operation 1015 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs) 1016 * @choose_interface_config: Choose the best interface configuration 1017 */ 1018 struct nand_chip_ops { 1019 int (*suspend)(struct nand_chip *chip); 1020 void (*resume)(struct nand_chip *chip); 1021 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1022 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1023 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1024 int (*choose_interface_config)(struct nand_chip *chip, 1025 struct nand_interface_config *iface); 1026 }; 1027 1028 /** 1029 * struct nand_manufacturer - NAND manufacturer structure 1030 * @desc: The manufacturer description 1031 * @priv: Private information for the manufacturer driver 1032 */ 1033 struct nand_manufacturer { 1034 const struct nand_manufacturer_desc *desc; 1035 void *priv; 1036 }; 1037 1038 /** 1039 * struct nand_secure_region - NAND secure region structure 1040 * @offset: Offset of the start of the secure region 1041 * @size: Size of the secure region 1042 */ 1043 struct nand_secure_region { 1044 u64 offset; 1045 u64 size; 1046 }; 1047 1048 /** 1049 * struct nand_chip - NAND Private Flash Chip Data 1050 * @base: Inherit from the generic NAND device 1051 * @id: Holds NAND ID 1052 * @parameters: Holds generic parameters under an easily readable form 1053 * @manufacturer: Manufacturer information 1054 * @ops: NAND chip operations 1055 * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try 1056 * to use any of these fields/hooks, and if you're modifying an 1057 * existing driver that is using those fields/hooks, you should 1058 * consider reworking the driver and avoid using them. 1059 * @options: Various chip options. They can partly be set to inform nand_scan 1060 * about special functionality. See the defines for further 1061 * explanation. 1062 * @current_interface_config: The currently used NAND interface configuration 1063 * @best_interface_config: The best NAND interface configuration which fits both 1064 * the NAND chip and NAND controller constraints. If 1065 * unset, the default reset interface configuration must 1066 * be used. 1067 * @bbt_erase_shift: Number of address bits in a bbt entry 1068 * @bbt_options: Bad block table specific options. All options used here must 1069 * come from bbm.h. By default, these options will be copied to 1070 * the appropriate nand_bbt_descr's. 1071 * @badblockpos: Bad block marker position in the oob area 1072 * @badblockbits: Minimum number of set bits in a good block's bad block marker 1073 * position; i.e., BBM = 11110111b is good when badblockbits = 7 1074 * @bbt_td: Bad block table descriptor for flash lookup 1075 * @bbt_md: Bad block table mirror descriptor 1076 * @badblock_pattern: Bad block scan pattern used for initial bad block scan 1077 * @bbt: Bad block table pointer 1078 * @page_shift: Number of address bits in a page (column address bits) 1079 * @phys_erase_shift: Number of address bits in a physical eraseblock 1080 * @chip_shift: Number of address bits in one chip 1081 * @pagemask: Page number mask = number of (pages / chip) - 1 1082 * @subpagesize: Holds the subpagesize 1083 * @data_buf: Buffer for data, size is (page size + oobsize) 1084 * @oob_poi: pointer on the OOB area covered by data_buf 1085 * @pagecache: Structure containing page cache related fields 1086 * @pagecache.bitflips: Number of bitflips of the cached page 1087 * @pagecache.page: Page number currently in the cache. -1 means no page is 1088 * currently cached 1089 * @buf_align: Minimum buffer alignment required by a platform 1090 * @lock: Lock protecting the suspended field. Also used to serialize accesses 1091 * to the NAND device 1092 * @suspended: Set to 1 when the device is suspended, 0 when it's not 1093 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we 1094 * should always have cur_cs >= 0 && cur_cs < nanddev_ntargets(). 1095 * NAND Controller drivers should not modify this value, but they're 1096 * allowed to read it. 1097 * @read_retries: The number of read retry modes supported 1098 * @secure_regions: Structure containing the secure regions info 1099 * @nr_secure_regions: Number of secure regions 1100 * @controller: The hardware controller structure which is shared among multiple 1101 * independent devices 1102 * @ecc: The ECC controller structure 1103 * @priv: Chip private data 1104 */ 1105 struct nand_chip { 1106 struct nand_device base; 1107 struct nand_id id; 1108 struct nand_parameters parameters; 1109 struct nand_manufacturer manufacturer; 1110 struct nand_chip_ops ops; 1111 struct nand_legacy legacy; 1112 unsigned int options; 1113 1114 /* Data interface */ 1115 const struct nand_interface_config *current_interface_config; 1116 struct nand_interface_config *best_interface_config; 1117 1118 /* Bad block information */ 1119 unsigned int bbt_erase_shift; 1120 unsigned int bbt_options; 1121 unsigned int badblockpos; 1122 unsigned int badblockbits; 1123 struct nand_bbt_descr *bbt_td; 1124 struct nand_bbt_descr *bbt_md; 1125 struct nand_bbt_descr *badblock_pattern; 1126 u8 *bbt; 1127 1128 /* Device internal layout */ 1129 unsigned int page_shift; 1130 unsigned int phys_erase_shift; 1131 unsigned int chip_shift; 1132 unsigned int pagemask; 1133 unsigned int subpagesize; 1134 1135 /* Buffers */ 1136 u8 *data_buf; 1137 u8 *oob_poi; 1138 struct { 1139 unsigned int bitflips; 1140 int page; 1141 } pagecache; 1142 unsigned long buf_align; 1143 1144 /* Internals */ 1145 struct mutex lock; 1146 unsigned int suspended : 1; 1147 int cur_cs; 1148 int read_retries; 1149 struct nand_secure_region *secure_regions; 1150 u8 nr_secure_regions; 1151 1152 /* Externals */ 1153 struct nand_controller *controller; 1154 struct nand_ecc_ctrl ecc; 1155 void *priv; 1156 }; 1157 1158 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1159 { 1160 return container_of(mtd, struct nand_chip, base.mtd); 1161 } 1162 1163 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1164 { 1165 return &chip->base.mtd; 1166 } 1167 1168 static inline void *nand_get_controller_data(struct nand_chip *chip) 1169 { 1170 return chip->priv; 1171 } 1172 1173 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1174 { 1175 chip->priv = priv; 1176 } 1177 1178 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1179 void *priv) 1180 { 1181 chip->manufacturer.priv = priv; 1182 } 1183 1184 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1185 { 1186 return chip->manufacturer.priv; 1187 } 1188 1189 static inline void nand_set_flash_node(struct nand_chip *chip, 1190 struct device_node *np) 1191 { 1192 mtd_set_of_node(nand_to_mtd(chip), np); 1193 } 1194 1195 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1196 { 1197 return mtd_get_of_node(nand_to_mtd(chip)); 1198 } 1199 1200 /** 1201 * nand_get_interface_config - Retrieve the current interface configuration 1202 * of a NAND chip 1203 * @chip: The NAND chip 1204 */ 1205 static inline const struct nand_interface_config * 1206 nand_get_interface_config(struct nand_chip *chip) 1207 { 1208 return chip->current_interface_config; 1209 } 1210 1211 /* 1212 * A helper for defining older NAND chips where the second ID byte fully 1213 * defined the chip, including the geometry (chip size, eraseblock size, page 1214 * size). All these chips have 512 bytes NAND page size. 1215 */ 1216 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1217 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1218 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1219 1220 /* 1221 * A helper for defining newer chips which report their page size and 1222 * eraseblock size via the extended ID bytes. 1223 * 1224 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1225 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1226 * device ID now only represented a particular total chip size (and voltage, 1227 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1228 * using the same device ID. 1229 */ 1230 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1231 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1232 .options = (opts) } 1233 1234 #define NAND_ECC_INFO(_strength, _step) \ 1235 { .strength_ds = (_strength), .step_ds = (_step) } 1236 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1237 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1238 1239 /** 1240 * struct nand_flash_dev - NAND Flash Device ID Structure 1241 * @name: a human-readable name of the NAND chip 1242 * @dev_id: the device ID (the second byte of the full chip ID array) 1243 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same 1244 * memory address as ``id[0]``) 1245 * @dev_id: device ID part of the full chip ID array (refers the same memory 1246 * address as ``id[1]``) 1247 * @id: full device ID array 1248 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1249 * well as the eraseblock size) is determined from the extended NAND 1250 * chip ID array) 1251 * @chipsize: total chip size in MiB 1252 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1253 * @options: stores various chip bit options 1254 * @id_len: The valid length of the @id. 1255 * @oobsize: OOB size 1256 * @ecc: ECC correctability and step information from the datasheet. 1257 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1258 * @ecc_strength_ds in nand_chip{}. 1259 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1260 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1261 * For example, the "4bit ECC for each 512Byte" can be set with 1262 * NAND_ECC_INFO(4, 512). 1263 */ 1264 struct nand_flash_dev { 1265 char *name; 1266 union { 1267 struct { 1268 uint8_t mfr_id; 1269 uint8_t dev_id; 1270 }; 1271 uint8_t id[NAND_MAX_ID_LEN]; 1272 }; 1273 unsigned int pagesize; 1274 unsigned int chipsize; 1275 unsigned int erasesize; 1276 unsigned int options; 1277 uint16_t id_len; 1278 uint16_t oobsize; 1279 struct { 1280 uint16_t strength_ds; 1281 uint16_t step_ds; 1282 } ecc; 1283 }; 1284 1285 int nand_create_bbt(struct nand_chip *chip); 1286 1287 /* 1288 * Check if it is a SLC nand. 1289 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1290 * We do not distinguish the MLC and TLC now. 1291 */ 1292 static inline bool nand_is_slc(struct nand_chip *chip) 1293 { 1294 WARN(nanddev_bits_per_cell(&chip->base) == 0, 1295 "chip->bits_per_cell is used uninitialized\n"); 1296 return nanddev_bits_per_cell(&chip->base) == 1; 1297 } 1298 1299 /** 1300 * nand_opcode_8bits - Check if the opcode's address should be sent only on the 1301 * lower 8 bits 1302 * @command: opcode to check 1303 */ 1304 static inline int nand_opcode_8bits(unsigned int command) 1305 { 1306 switch (command) { 1307 case NAND_CMD_READID: 1308 case NAND_CMD_PARAM: 1309 case NAND_CMD_GET_FEATURES: 1310 case NAND_CMD_SET_FEATURES: 1311 return 1; 1312 default: 1313 break; 1314 } 1315 return 0; 1316 } 1317 1318 int rawnand_sw_hamming_init(struct nand_chip *chip); 1319 int rawnand_sw_hamming_calculate(struct nand_chip *chip, 1320 const unsigned char *buf, 1321 unsigned char *code); 1322 int rawnand_sw_hamming_correct(struct nand_chip *chip, 1323 unsigned char *buf, 1324 unsigned char *read_ecc, 1325 unsigned char *calc_ecc); 1326 void rawnand_sw_hamming_cleanup(struct nand_chip *chip); 1327 int rawnand_sw_bch_init(struct nand_chip *chip); 1328 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf, 1329 unsigned char *read_ecc, unsigned char *calc_ecc); 1330 void rawnand_sw_bch_cleanup(struct nand_chip *chip); 1331 1332 int nand_check_erased_ecc_chunk(void *data, int datalen, 1333 void *ecc, int ecclen, 1334 void *extraoob, int extraooblen, 1335 int threshold); 1336 1337 int nand_ecc_choose_conf(struct nand_chip *chip, 1338 const struct nand_ecc_caps *caps, int oobavail); 1339 1340 /* Default write_oob implementation */ 1341 int nand_write_oob_std(struct nand_chip *chip, int page); 1342 1343 /* Default read_oob implementation */ 1344 int nand_read_oob_std(struct nand_chip *chip, int page); 1345 1346 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1347 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1348 u8 *subfeature_param); 1349 1350 /* read_page_raw implementations */ 1351 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1352 int page); 1353 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf, 1354 int oob_required, int page); 1355 1356 /* write_page_raw implementations */ 1357 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1358 int oob_required, int page); 1359 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1360 int oob_required, int page); 1361 1362 /* Reset and initialize a NAND device */ 1363 int nand_reset(struct nand_chip *chip, int chipnr); 1364 1365 /* NAND operation helpers */ 1366 int nand_reset_op(struct nand_chip *chip); 1367 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1368 unsigned int len); 1369 int nand_status_op(struct nand_chip *chip, u8 *status); 1370 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1371 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1372 unsigned int offset_in_page, void *buf, unsigned int len); 1373 int nand_change_read_column_op(struct nand_chip *chip, 1374 unsigned int offset_in_page, void *buf, 1375 unsigned int len, bool force_8bit); 1376 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1377 unsigned int offset_in_page, void *buf, unsigned int len); 1378 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1379 unsigned int offset_in_page, const void *buf, 1380 unsigned int len); 1381 int nand_prog_page_end_op(struct nand_chip *chip); 1382 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1383 unsigned int offset_in_page, const void *buf, 1384 unsigned int len); 1385 int nand_change_write_column_op(struct nand_chip *chip, 1386 unsigned int offset_in_page, const void *buf, 1387 unsigned int len, bool force_8bit); 1388 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1389 bool force_8bit, bool check_only); 1390 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1391 unsigned int len, bool force_8bit); 1392 1393 /* Scan and identify a NAND device */ 1394 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1395 struct nand_flash_dev *ids); 1396 1397 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1398 { 1399 return nand_scan_with_ids(chip, max_chips, NULL); 1400 } 1401 1402 /* Internal helper for board drivers which need to override command function */ 1403 void nand_wait_ready(struct nand_chip *chip); 1404 1405 /* 1406 * Free resources held by the NAND device, must be called on error after a 1407 * sucessful nand_scan(). 1408 */ 1409 void nand_cleanup(struct nand_chip *chip); 1410 1411 /* 1412 * External helper for controller drivers that have to implement the WAITRDY 1413 * instruction and have no physical pin to check it. 1414 */ 1415 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1416 struct gpio_desc; 1417 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 1418 unsigned long timeout_ms); 1419 1420 /* Select/deselect a NAND target. */ 1421 void nand_select_target(struct nand_chip *chip, unsigned int cs); 1422 void nand_deselect_target(struct nand_chip *chip); 1423 1424 /* Bitops */ 1425 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src, 1426 unsigned int src_off, unsigned int nbits); 1427 1428 /** 1429 * nand_get_data_buf() - Get the internal page buffer 1430 * @chip: NAND chip object 1431 * 1432 * Returns the pre-allocated page buffer after invalidating the cache. This 1433 * function should be used by drivers that do not want to allocate their own 1434 * bounce buffer and still need such a buffer for specific operations (most 1435 * commonly when reading OOB data only). 1436 * 1437 * Be careful to never call this function in the write/write_oob path, because 1438 * the core may have placed the data to be written out in this buffer. 1439 * 1440 * Return: pointer to the page cache buffer 1441 */ 1442 static inline void *nand_get_data_buf(struct nand_chip *chip) 1443 { 1444 chip->pagecache.page = -1; 1445 1446 return chip->data_buf; 1447 } 1448 1449 #endif /* __LINUX_MTD_RAWNAND_H */ 1450