1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 /* Scan and identify a NAND device */ 30 extern int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 extern int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Free resources held by the NAND device */ 40 extern void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 extern void nand_wait_ready(struct mtd_info *mtd); 44 45 /* locks all blocks present in the device */ 46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 47 48 /* unlocks specified locked blocks */ 49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 50 51 /* The maximum number of NAND chips in an array */ 52 #define NAND_MAX_CHIPS 8 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 #define NAND_CMD_NONE -1 100 101 /* Status bits */ 102 #define NAND_STATUS_FAIL 0x01 103 #define NAND_STATUS_FAIL_N1 0x02 104 #define NAND_STATUS_TRUE_READY 0x20 105 #define NAND_STATUS_READY 0x40 106 #define NAND_STATUS_WP 0x80 107 108 /* 109 * Constants for ECC_MODES 110 */ 111 typedef enum { 112 NAND_ECC_NONE, 113 NAND_ECC_SOFT, 114 NAND_ECC_HW, 115 NAND_ECC_HW_SYNDROME, 116 NAND_ECC_HW_OOB_FIRST, 117 NAND_ECC_SOFT_BCH, 118 } nand_ecc_modes_t; 119 120 /* 121 * Constants for Hardware ECC 122 */ 123 /* Reset Hardware ECC for read */ 124 #define NAND_ECC_READ 0 125 /* Reset Hardware ECC for write */ 126 #define NAND_ECC_WRITE 1 127 /* Enable Hardware ECC before syndrome is read back from flash */ 128 #define NAND_ECC_READSYN 2 129 130 /* Bit mask for flags passed to do_nand_read_ecc */ 131 #define NAND_GET_DEVICE 0x80 132 133 134 /* 135 * Option constants for bizarre disfunctionality and real 136 * features. 137 */ 138 /* Buswidth is 16 bit */ 139 #define NAND_BUSWIDTH_16 0x00000002 140 /* Chip has cache program function */ 141 #define NAND_CACHEPRG 0x00000008 142 /* 143 * Chip requires ready check on read (for auto-incremented sequential read). 144 * True only for small page devices; large page devices do not support 145 * autoincrement. 146 */ 147 #define NAND_NEED_READRDY 0x00000100 148 149 /* Chip does not allow subpage writes */ 150 #define NAND_NO_SUBPAGE_WRITE 0x00000200 151 152 /* Device is one of 'new' xD cards that expose fake nand command set */ 153 #define NAND_BROKEN_XD 0x00000400 154 155 /* Device behaves just like nand, but is readonly */ 156 #define NAND_ROM 0x00000800 157 158 /* Device supports subpage reads */ 159 #define NAND_SUBPAGE_READ 0x00001000 160 161 /* Options valid for Samsung large page devices */ 162 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 163 164 /* Macros to identify the above */ 165 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 166 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 167 168 /* Non chip related options */ 169 /* This option skips the bbt scan during initialization. */ 170 #define NAND_SKIP_BBTSCAN 0x00010000 171 /* 172 * This option is defined if the board driver allocates its own buffers 173 * (e.g. because it needs them DMA-coherent). 174 */ 175 #define NAND_OWN_BUFFERS 0x00020000 176 /* Chip may not exist, so silence any errors in scan */ 177 #define NAND_SCAN_SILENT_NODEV 0x00040000 178 /* 179 * This option could be defined by controller drivers to protect against 180 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 181 */ 182 #define NAND_USE_BOUNCE_BUFFER 0x00080000 183 /* 184 * Autodetect nand buswidth with readid/onfi. 185 * This suppose the driver will configure the hardware in 8 bits mode 186 * when calling nand_scan_ident, and update its configuration 187 * before calling nand_scan_tail. 188 */ 189 #define NAND_BUSWIDTH_AUTO 0x00080000 190 191 /* Options set by nand scan */ 192 /* Nand scan has allocated controller struct */ 193 #define NAND_CONTROLLER_ALLOC 0x80000000 194 195 /* Cell info constants */ 196 #define NAND_CI_CHIPNR_MSK 0x03 197 #define NAND_CI_CELLTYPE_MSK 0x0C 198 #define NAND_CI_CELLTYPE_SHIFT 2 199 200 /* Keep gcc happy */ 201 struct nand_chip; 202 203 /* ONFI features */ 204 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 205 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 206 207 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 208 #define ONFI_TIMING_MODE_0 (1 << 0) 209 #define ONFI_TIMING_MODE_1 (1 << 1) 210 #define ONFI_TIMING_MODE_2 (1 << 2) 211 #define ONFI_TIMING_MODE_3 (1 << 3) 212 #define ONFI_TIMING_MODE_4 (1 << 4) 213 #define ONFI_TIMING_MODE_5 (1 << 5) 214 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 215 216 /* ONFI feature address */ 217 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 218 219 /* Vendor-specific feature address (Micron) */ 220 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 221 222 /* ONFI subfeature parameters length */ 223 #define ONFI_SUBFEATURE_PARAM_LEN 4 224 225 /* ONFI optional commands SET/GET FEATURES supported? */ 226 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 227 228 struct nand_onfi_params { 229 /* rev info and features block */ 230 /* 'O' 'N' 'F' 'I' */ 231 u8 sig[4]; 232 __le16 revision; 233 __le16 features; 234 __le16 opt_cmd; 235 u8 reserved0[2]; 236 __le16 ext_param_page_length; /* since ONFI 2.1 */ 237 u8 num_of_param_pages; /* since ONFI 2.1 */ 238 u8 reserved1[17]; 239 240 /* manufacturer information block */ 241 char manufacturer[12]; 242 char model[20]; 243 u8 jedec_id; 244 __le16 date_code; 245 u8 reserved2[13]; 246 247 /* memory organization block */ 248 __le32 byte_per_page; 249 __le16 spare_bytes_per_page; 250 __le32 data_bytes_per_ppage; 251 __le16 spare_bytes_per_ppage; 252 __le32 pages_per_block; 253 __le32 blocks_per_lun; 254 u8 lun_count; 255 u8 addr_cycles; 256 u8 bits_per_cell; 257 __le16 bb_per_lun; 258 __le16 block_endurance; 259 u8 guaranteed_good_blocks; 260 __le16 guaranteed_block_endurance; 261 u8 programs_per_page; 262 u8 ppage_attr; 263 u8 ecc_bits; 264 u8 interleaved_bits; 265 u8 interleaved_ops; 266 u8 reserved3[13]; 267 268 /* electrical parameter block */ 269 u8 io_pin_capacitance_max; 270 __le16 async_timing_mode; 271 __le16 program_cache_timing_mode; 272 __le16 t_prog; 273 __le16 t_bers; 274 __le16 t_r; 275 __le16 t_ccs; 276 __le16 src_sync_timing_mode; 277 __le16 src_ssync_features; 278 __le16 clk_pin_capacitance_typ; 279 __le16 io_pin_capacitance_typ; 280 __le16 input_pin_capacitance_typ; 281 u8 input_pin_capacitance_max; 282 u8 driver_strength_support; 283 __le16 t_int_r; 284 __le16 t_ald; 285 u8 reserved4[7]; 286 287 /* vendor */ 288 __le16 vendor_revision; 289 u8 vendor[88]; 290 291 __le16 crc; 292 } __packed; 293 294 #define ONFI_CRC_BASE 0x4F4E 295 296 /* Extended ECC information Block Definition (since ONFI 2.1) */ 297 struct onfi_ext_ecc_info { 298 u8 ecc_bits; 299 u8 codeword_size; 300 __le16 bb_per_lun; 301 __le16 block_endurance; 302 u8 reserved[2]; 303 } __packed; 304 305 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 306 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 307 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 308 struct onfi_ext_section { 309 u8 type; 310 u8 length; 311 } __packed; 312 313 #define ONFI_EXT_SECTION_MAX 8 314 315 /* Extended Parameter Page Definition (since ONFI 2.1) */ 316 struct onfi_ext_param_page { 317 __le16 crc; 318 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 319 u8 reserved0[10]; 320 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 321 322 /* 323 * The actual size of the Extended Parameter Page is in 324 * @ext_param_page_length of nand_onfi_params{}. 325 * The following are the variable length sections. 326 * So we do not add any fields below. Please see the ONFI spec. 327 */ 328 } __packed; 329 330 struct nand_onfi_vendor_micron { 331 u8 two_plane_read; 332 u8 read_cache; 333 u8 read_unique_id; 334 u8 dq_imped; 335 u8 dq_imped_num_settings; 336 u8 dq_imped_feat_addr; 337 u8 rb_pulldown_strength; 338 u8 rb_pulldown_strength_feat_addr; 339 u8 rb_pulldown_strength_num_settings; 340 u8 otp_mode; 341 u8 otp_page_start; 342 u8 otp_data_prot_addr; 343 u8 otp_num_pages; 344 u8 otp_feat_addr; 345 u8 read_retry_options; 346 u8 reserved[72]; 347 u8 param_revision; 348 } __packed; 349 350 struct jedec_ecc_info { 351 u8 ecc_bits; 352 u8 codeword_size; 353 __le16 bb_per_lun; 354 __le16 block_endurance; 355 u8 reserved[2]; 356 } __packed; 357 358 /* JEDEC features */ 359 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 360 361 struct nand_jedec_params { 362 /* rev info and features block */ 363 /* 'J' 'E' 'S' 'D' */ 364 u8 sig[4]; 365 __le16 revision; 366 __le16 features; 367 u8 opt_cmd[3]; 368 __le16 sec_cmd; 369 u8 num_of_param_pages; 370 u8 reserved0[18]; 371 372 /* manufacturer information block */ 373 char manufacturer[12]; 374 char model[20]; 375 u8 jedec_id[6]; 376 u8 reserved1[10]; 377 378 /* memory organization block */ 379 __le32 byte_per_page; 380 __le16 spare_bytes_per_page; 381 u8 reserved2[6]; 382 __le32 pages_per_block; 383 __le32 blocks_per_lun; 384 u8 lun_count; 385 u8 addr_cycles; 386 u8 bits_per_cell; 387 u8 programs_per_page; 388 u8 multi_plane_addr; 389 u8 multi_plane_op_attr; 390 u8 reserved3[38]; 391 392 /* electrical parameter block */ 393 __le16 async_sdr_speed_grade; 394 __le16 toggle_ddr_speed_grade; 395 __le16 sync_ddr_speed_grade; 396 u8 async_sdr_features; 397 u8 toggle_ddr_features; 398 u8 sync_ddr_features; 399 __le16 t_prog; 400 __le16 t_bers; 401 __le16 t_r; 402 __le16 t_r_multi_plane; 403 __le16 t_ccs; 404 __le16 io_pin_capacitance_typ; 405 __le16 input_pin_capacitance_typ; 406 __le16 clk_pin_capacitance_typ; 407 u8 driver_strength_support; 408 __le16 t_ald; 409 u8 reserved4[36]; 410 411 /* ECC and endurance block */ 412 u8 guaranteed_good_blocks; 413 __le16 guaranteed_block_endurance; 414 struct jedec_ecc_info ecc_info[4]; 415 u8 reserved5[29]; 416 417 /* reserved */ 418 u8 reserved6[148]; 419 420 /* vendor */ 421 __le16 vendor_rev_num; 422 u8 reserved7[88]; 423 424 /* CRC for Parameter Page */ 425 __le16 crc; 426 } __packed; 427 428 /** 429 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 430 * @lock: protection lock 431 * @active: the mtd device which holds the controller currently 432 * @wq: wait queue to sleep on if a NAND operation is in 433 * progress used instead of the per chip wait queue 434 * when a hw controller is available. 435 */ 436 struct nand_hw_control { 437 spinlock_t lock; 438 struct nand_chip *active; 439 wait_queue_head_t wq; 440 }; 441 442 /** 443 * struct nand_ecc_ctrl - Control structure for ECC 444 * @mode: ECC mode 445 * @steps: number of ECC steps per page 446 * @size: data bytes per ECC step 447 * @bytes: ECC bytes per step 448 * @strength: max number of correctible bits per ECC step 449 * @total: total number of ECC bytes per page 450 * @prepad: padding information for syndrome based ECC generators 451 * @postpad: padding information for syndrome based ECC generators 452 * @layout: ECC layout control struct pointer 453 * @priv: pointer to private ECC control data 454 * @hwctl: function to control hardware ECC generator. Must only 455 * be provided if an hardware ECC is available 456 * @calculate: function for ECC calculation or readback from ECC hardware 457 * @correct: function for ECC correction, matching to ECC generator (sw/hw) 458 * @read_page_raw: function to read a raw page without ECC 459 * @write_page_raw: function to write a raw page without ECC 460 * @read_page: function to read a page according to the ECC generator 461 * requirements; returns maximum number of bitflips corrected in 462 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 463 * @read_subpage: function to read parts of the page covered by ECC; 464 * returns same as read_page() 465 * @write_subpage: function to write parts of the page covered by ECC. 466 * @write_page: function to write a page according to the ECC generator 467 * requirements. 468 * @write_oob_raw: function to write chip OOB data without ECC 469 * @read_oob_raw: function to read chip OOB data without ECC 470 * @read_oob: function to read chip OOB data 471 * @write_oob: function to write chip OOB data 472 */ 473 struct nand_ecc_ctrl { 474 nand_ecc_modes_t mode; 475 int steps; 476 int size; 477 int bytes; 478 int total; 479 int strength; 480 int prepad; 481 int postpad; 482 struct nand_ecclayout *layout; 483 void *priv; 484 void (*hwctl)(struct mtd_info *mtd, int mode); 485 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 486 uint8_t *ecc_code); 487 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 488 uint8_t *calc_ecc); 489 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 490 uint8_t *buf, int oob_required, int page); 491 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 492 const uint8_t *buf, int oob_required); 493 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 494 uint8_t *buf, int oob_required, int page); 495 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 496 uint32_t offs, uint32_t len, uint8_t *buf, int page); 497 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 498 uint32_t offset, uint32_t data_len, 499 const uint8_t *data_buf, int oob_required); 500 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 501 const uint8_t *buf, int oob_required); 502 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 503 int page); 504 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 505 int page); 506 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 507 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 508 int page); 509 }; 510 511 /** 512 * struct nand_buffers - buffer structure for read/write 513 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 514 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 515 * @databuf: buffer pointer for data, size is (page size + oobsize). 516 * 517 * Do not change the order of buffers. databuf and oobrbuf must be in 518 * consecutive order. 519 */ 520 struct nand_buffers { 521 uint8_t *ecccalc; 522 uint8_t *ecccode; 523 uint8_t *databuf; 524 }; 525 526 /** 527 * struct nand_chip - NAND Private Flash Chip Data 528 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 529 * flash device 530 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 531 * flash device. 532 * @read_byte: [REPLACEABLE] read one byte from the chip 533 * @read_word: [REPLACEABLE] read one word from the chip 534 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 535 * low 8 I/O lines 536 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 537 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 538 * @select_chip: [REPLACEABLE] select chip nr 539 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 540 * @block_markbad: [REPLACEABLE] mark a block bad 541 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 542 * ALE/CLE/nCE. Also used to write command and address 543 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 544 * mtd->oobsize, mtd->writesize and so on. 545 * @id_data contains the 8 bytes values of NAND_CMD_READID. 546 * Return with the bus width. 547 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 548 * device ready/busy line. If set to NULL no access to 549 * ready/busy is available and the ready/busy information 550 * is read from the chip status register. 551 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 552 * commands to the chip. 553 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 554 * ready. 555 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 556 * setting the read-retry mode. Mostly needed for MLC NAND. 557 * @ecc: [BOARDSPECIFIC] ECC control structure 558 * @buffers: buffer structure for read/write 559 * @hwcontrol: platform-specific hardware control structure 560 * @erase: [REPLACEABLE] erase function 561 * @scan_bbt: [REPLACEABLE] function to scan bad block table 562 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 563 * data from array to read regs (tR). 564 * @state: [INTERN] the current state of the NAND device 565 * @oob_poi: "poison value buffer," used for laying out OOB data 566 * before writing 567 * @page_shift: [INTERN] number of address bits in a page (column 568 * address bits). 569 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 570 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 571 * @chip_shift: [INTERN] number of address bits in one chip 572 * @options: [BOARDSPECIFIC] various chip options. They can partly 573 * be set to inform nand_scan about special functionality. 574 * See the defines for further explanation. 575 * @bbt_options: [INTERN] bad block specific options. All options used 576 * here must come from bbm.h. By default, these options 577 * will be copied to the appropriate nand_bbt_descr's. 578 * @badblockpos: [INTERN] position of the bad block marker in the oob 579 * area. 580 * @badblockbits: [INTERN] minimum number of set bits in a good block's 581 * bad block marker position; i.e., BBM == 11110111b is 582 * not bad when badblockbits == 7 583 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 584 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 585 * Minimum amount of bit errors per @ecc_step_ds guaranteed 586 * to be correctable. If unknown, set to zero. 587 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 588 * also from the datasheet. It is the recommended ECC step 589 * size, if known; if unknown, set to zero. 590 * @numchips: [INTERN] number of physical chips 591 * @chipsize: [INTERN] the size of one chip for multichip arrays 592 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 593 * @pagebuf: [INTERN] holds the pagenumber which is currently in 594 * data_buf. 595 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 596 * currently in data_buf. 597 * @subpagesize: [INTERN] holds the subpagesize 598 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 599 * non 0 if ONFI supported. 600 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 601 * non 0 if JEDEC supported. 602 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 603 * supported, 0 otherwise. 604 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 605 * supported, 0 otherwise. 606 * @read_retries: [INTERN] the number of read retry modes supported 607 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 608 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 609 * @bbt: [INTERN] bad block table pointer 610 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 611 * lookup. 612 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 613 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 614 * bad block scan. 615 * @controller: [REPLACEABLE] a pointer to a hardware controller 616 * structure which is shared among multiple independent 617 * devices. 618 * @priv: [OPTIONAL] pointer to private chip data 619 * @errstat: [OPTIONAL] hardware specific function to perform 620 * additional error status checks (determine if errors are 621 * correctable). 622 * @write_page: [REPLACEABLE] High-level page write function 623 */ 624 625 struct nand_chip { 626 void __iomem *IO_ADDR_R; 627 void __iomem *IO_ADDR_W; 628 629 uint8_t (*read_byte)(struct mtd_info *mtd); 630 u16 (*read_word)(struct mtd_info *mtd); 631 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 632 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 633 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 634 void (*select_chip)(struct mtd_info *mtd, int chip); 635 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 636 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 637 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 638 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 639 u8 *id_data); 640 int (*dev_ready)(struct mtd_info *mtd); 641 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 642 int page_addr); 643 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 644 int (*erase)(struct mtd_info *mtd, int page); 645 int (*scan_bbt)(struct mtd_info *mtd); 646 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 647 int status, int page); 648 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 649 uint32_t offset, int data_len, const uint8_t *buf, 650 int oob_required, int page, int cached, int raw); 651 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 652 int feature_addr, uint8_t *subfeature_para); 653 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 654 int feature_addr, uint8_t *subfeature_para); 655 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 656 657 int chip_delay; 658 unsigned int options; 659 unsigned int bbt_options; 660 661 int page_shift; 662 int phys_erase_shift; 663 int bbt_erase_shift; 664 int chip_shift; 665 int numchips; 666 uint64_t chipsize; 667 int pagemask; 668 int pagebuf; 669 unsigned int pagebuf_bitflips; 670 int subpagesize; 671 uint8_t bits_per_cell; 672 uint16_t ecc_strength_ds; 673 uint16_t ecc_step_ds; 674 int badblockpos; 675 int badblockbits; 676 677 int onfi_version; 678 int jedec_version; 679 union { 680 struct nand_onfi_params onfi_params; 681 struct nand_jedec_params jedec_params; 682 }; 683 684 int read_retries; 685 686 flstate_t state; 687 688 uint8_t *oob_poi; 689 struct nand_hw_control *controller; 690 691 struct nand_ecc_ctrl ecc; 692 struct nand_buffers *buffers; 693 struct nand_hw_control hwcontrol; 694 695 uint8_t *bbt; 696 struct nand_bbt_descr *bbt_td; 697 struct nand_bbt_descr *bbt_md; 698 699 struct nand_bbt_descr *badblock_pattern; 700 701 void *priv; 702 }; 703 704 /* 705 * NAND Flash Manufacturer ID Codes 706 */ 707 #define NAND_MFR_TOSHIBA 0x98 708 #define NAND_MFR_SAMSUNG 0xec 709 #define NAND_MFR_FUJITSU 0x04 710 #define NAND_MFR_NATIONAL 0x8f 711 #define NAND_MFR_RENESAS 0x07 712 #define NAND_MFR_STMICRO 0x20 713 #define NAND_MFR_HYNIX 0xad 714 #define NAND_MFR_MICRON 0x2c 715 #define NAND_MFR_AMD 0x01 716 #define NAND_MFR_MACRONIX 0xc2 717 #define NAND_MFR_EON 0x92 718 #define NAND_MFR_SANDISK 0x45 719 #define NAND_MFR_INTEL 0x89 720 721 /* The maximum expected count of bytes in the NAND ID sequence */ 722 #define NAND_MAX_ID_LEN 8 723 724 /* 725 * A helper for defining older NAND chips where the second ID byte fully 726 * defined the chip, including the geometry (chip size, eraseblock size, page 727 * size). All these chips have 512 bytes NAND page size. 728 */ 729 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 730 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 731 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 732 733 /* 734 * A helper for defining newer chips which report their page size and 735 * eraseblock size via the extended ID bytes. 736 * 737 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 738 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 739 * device ID now only represented a particular total chip size (and voltage, 740 * buswidth), and the page size, eraseblock size, and OOB size could vary while 741 * using the same device ID. 742 */ 743 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 744 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 745 .options = (opts) } 746 747 #define NAND_ECC_INFO(_strength, _step) \ 748 { .strength_ds = (_strength), .step_ds = (_step) } 749 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 750 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 751 752 /** 753 * struct nand_flash_dev - NAND Flash Device ID Structure 754 * @name: a human-readable name of the NAND chip 755 * @dev_id: the device ID (the second byte of the full chip ID array) 756 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 757 * memory address as @id[0]) 758 * @dev_id: device ID part of the full chip ID array (refers the same memory 759 * address as @id[1]) 760 * @id: full device ID array 761 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 762 * well as the eraseblock size) is determined from the extended NAND 763 * chip ID array) 764 * @chipsize: total chip size in MiB 765 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 766 * @options: stores various chip bit options 767 * @id_len: The valid length of the @id. 768 * @oobsize: OOB size 769 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 770 * @ecc_strength_ds in nand_chip{}. 771 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 772 * @ecc_step_ds in nand_chip{}, also from the datasheet. 773 * For example, the "4bit ECC for each 512Byte" can be set with 774 * NAND_ECC_INFO(4, 512). 775 */ 776 struct nand_flash_dev { 777 char *name; 778 union { 779 struct { 780 uint8_t mfr_id; 781 uint8_t dev_id; 782 }; 783 uint8_t id[NAND_MAX_ID_LEN]; 784 }; 785 unsigned int pagesize; 786 unsigned int chipsize; 787 unsigned int erasesize; 788 unsigned int options; 789 uint16_t id_len; 790 uint16_t oobsize; 791 struct { 792 uint16_t strength_ds; 793 uint16_t step_ds; 794 } ecc; 795 }; 796 797 /** 798 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 799 * @name: Manufacturer name 800 * @id: manufacturer ID code of device. 801 */ 802 struct nand_manufacturers { 803 int id; 804 char *name; 805 }; 806 807 extern struct nand_flash_dev nand_flash_ids[]; 808 extern struct nand_manufacturers nand_manuf_ids[]; 809 810 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 811 extern int nand_default_bbt(struct mtd_info *mtd); 812 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 813 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 814 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 815 int allowbbt); 816 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 817 size_t *retlen, uint8_t *buf); 818 819 /** 820 * struct platform_nand_chip - chip level device structure 821 * @nr_chips: max. number of chips to scan for 822 * @chip_offset: chip number offset 823 * @nr_partitions: number of partitions pointed to by partitions (or zero) 824 * @partitions: mtd partition list 825 * @chip_delay: R/B delay value in us 826 * @options: Option flags, e.g. 16bit buswidth 827 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 828 * @ecclayout: ECC layout info structure 829 * @part_probe_types: NULL-terminated array of probe types 830 */ 831 struct platform_nand_chip { 832 int nr_chips; 833 int chip_offset; 834 int nr_partitions; 835 struct mtd_partition *partitions; 836 struct nand_ecclayout *ecclayout; 837 int chip_delay; 838 unsigned int options; 839 unsigned int bbt_options; 840 const char **part_probe_types; 841 }; 842 843 /* Keep gcc happy */ 844 struct platform_device; 845 846 /** 847 * struct platform_nand_ctrl - controller level device structure 848 * @probe: platform specific function to probe/setup hardware 849 * @remove: platform specific function to remove/teardown hardware 850 * @hwcontrol: platform specific hardware control structure 851 * @dev_ready: platform specific function to read ready/busy pin 852 * @select_chip: platform specific chip select function 853 * @cmd_ctrl: platform specific function for controlling 854 * ALE/CLE/nCE. Also used to write command and address 855 * @write_buf: platform specific function for write buffer 856 * @read_buf: platform specific function for read buffer 857 * @read_byte: platform specific function to read one byte from chip 858 * @priv: private data to transport driver specific settings 859 * 860 * All fields are optional and depend on the hardware driver requirements 861 */ 862 struct platform_nand_ctrl { 863 int (*probe)(struct platform_device *pdev); 864 void (*remove)(struct platform_device *pdev); 865 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 866 int (*dev_ready)(struct mtd_info *mtd); 867 void (*select_chip)(struct mtd_info *mtd, int chip); 868 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 869 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 870 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 871 unsigned char (*read_byte)(struct mtd_info *mtd); 872 void *priv; 873 }; 874 875 /** 876 * struct platform_nand_data - container structure for platform-specific data 877 * @chip: chip level chip structure 878 * @ctrl: controller level device structure 879 */ 880 struct platform_nand_data { 881 struct platform_nand_chip chip; 882 struct platform_nand_ctrl ctrl; 883 }; 884 885 /* Some helpers to access the data structures */ 886 static inline 887 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 888 { 889 struct nand_chip *chip = mtd->priv; 890 891 return chip->priv; 892 } 893 894 /* return the supported features. */ 895 static inline int onfi_feature(struct nand_chip *chip) 896 { 897 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 898 } 899 900 /* return the supported asynchronous timing mode. */ 901 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 902 { 903 if (!chip->onfi_version) 904 return ONFI_TIMING_MODE_UNKNOWN; 905 return le16_to_cpu(chip->onfi_params.async_timing_mode); 906 } 907 908 /* return the supported synchronous timing mode. */ 909 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 910 { 911 if (!chip->onfi_version) 912 return ONFI_TIMING_MODE_UNKNOWN; 913 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 914 } 915 916 /* 917 * Check if it is a SLC nand. 918 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 919 * We do not distinguish the MLC and TLC now. 920 */ 921 static inline bool nand_is_slc(struct nand_chip *chip) 922 { 923 return chip->bits_per_cell == 1; 924 } 925 926 /** 927 * Check if the opcode's address should be sent only on the lower 8 bits 928 * @command: opcode to check 929 */ 930 static inline int nand_opcode_8bits(unsigned int command) 931 { 932 switch (command) { 933 case NAND_CMD_READID: 934 case NAND_CMD_PARAM: 935 case NAND_CMD_GET_FEATURES: 936 case NAND_CMD_SET_FEATURES: 937 return 1; 938 default: 939 break; 940 } 941 return 0; 942 } 943 944 /* return the supported JEDEC features. */ 945 static inline int jedec_feature(struct nand_chip *chip) 946 { 947 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 948 : 0; 949 } 950 #endif /* __LINUX_MTD_NAND_H */ 951