1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 struct device_node; 30 31 /* Scan and identify a NAND device */ 32 extern int nand_scan(struct mtd_info *mtd, int max_chips); 33 /* 34 * Separate phases of nand_scan(), allowing board driver to intervene 35 * and override command or ECC setup according to flash type. 36 */ 37 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 38 struct nand_flash_dev *table); 39 extern int nand_scan_tail(struct mtd_info *mtd); 40 41 /* Free resources held by the NAND device */ 42 extern void nand_release(struct mtd_info *mtd); 43 44 /* Internal helper for board drivers which need to override command function */ 45 extern void nand_wait_ready(struct mtd_info *mtd); 46 47 /* locks all blocks present in the device */ 48 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 49 50 /* unlocks specified locked blocks */ 51 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 52 53 /* The maximum number of NAND chips in an array */ 54 #define NAND_MAX_CHIPS 8 55 56 /* 57 * Constants for hardware specific CLE/ALE/NCE function 58 * 59 * These are bits which can be or'ed to set/clear multiple 60 * bits in one go. 61 */ 62 /* Select the chip by setting nCE to low */ 63 #define NAND_NCE 0x01 64 /* Select the command latch by setting CLE to high */ 65 #define NAND_CLE 0x02 66 /* Select the address latch by setting ALE to high */ 67 #define NAND_ALE 0x04 68 69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 71 #define NAND_CTRL_CHANGE 0x80 72 73 /* 74 * Standard NAND flash commands 75 */ 76 #define NAND_CMD_READ0 0 77 #define NAND_CMD_READ1 1 78 #define NAND_CMD_RNDOUT 5 79 #define NAND_CMD_PAGEPROG 0x10 80 #define NAND_CMD_READOOB 0x50 81 #define NAND_CMD_ERASE1 0x60 82 #define NAND_CMD_STATUS 0x70 83 #define NAND_CMD_SEQIN 0x80 84 #define NAND_CMD_RNDIN 0x85 85 #define NAND_CMD_READID 0x90 86 #define NAND_CMD_ERASE2 0xd0 87 #define NAND_CMD_PARAM 0xec 88 #define NAND_CMD_GET_FEATURES 0xee 89 #define NAND_CMD_SET_FEATURES 0xef 90 #define NAND_CMD_RESET 0xff 91 92 #define NAND_CMD_LOCK 0x2a 93 #define NAND_CMD_UNLOCK1 0x23 94 #define NAND_CMD_UNLOCK2 0x24 95 96 /* Extended commands for large page devices */ 97 #define NAND_CMD_READSTART 0x30 98 #define NAND_CMD_RNDOUTSTART 0xE0 99 #define NAND_CMD_CACHEDPROG 0x15 100 101 #define NAND_CMD_NONE -1 102 103 /* Status bits */ 104 #define NAND_STATUS_FAIL 0x01 105 #define NAND_STATUS_FAIL_N1 0x02 106 #define NAND_STATUS_TRUE_READY 0x20 107 #define NAND_STATUS_READY 0x40 108 #define NAND_STATUS_WP 0x80 109 110 /* 111 * Constants for ECC_MODES 112 */ 113 typedef enum { 114 NAND_ECC_NONE, 115 NAND_ECC_SOFT, 116 NAND_ECC_HW, 117 NAND_ECC_HW_SYNDROME, 118 NAND_ECC_HW_OOB_FIRST, 119 NAND_ECC_SOFT_BCH, 120 } nand_ecc_modes_t; 121 122 /* 123 * Constants for Hardware ECC 124 */ 125 /* Reset Hardware ECC for read */ 126 #define NAND_ECC_READ 0 127 /* Reset Hardware ECC for write */ 128 #define NAND_ECC_WRITE 1 129 /* Enable Hardware ECC before syndrome is read back from flash */ 130 #define NAND_ECC_READSYN 2 131 132 /* 133 * Enable generic NAND 'page erased' check. This check is only done when 134 * ecc.correct() returns -EBADMSG. 135 * Set this flag if your implementation does not fix bitflips in erased 136 * pages and you want to rely on the default implementation. 137 */ 138 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 139 140 /* Bit mask for flags passed to do_nand_read_ecc */ 141 #define NAND_GET_DEVICE 0x80 142 143 144 /* 145 * Option constants for bizarre disfunctionality and real 146 * features. 147 */ 148 /* Buswidth is 16 bit */ 149 #define NAND_BUSWIDTH_16 0x00000002 150 /* Chip has cache program function */ 151 #define NAND_CACHEPRG 0x00000008 152 /* 153 * Chip requires ready check on read (for auto-incremented sequential read). 154 * True only for small page devices; large page devices do not support 155 * autoincrement. 156 */ 157 #define NAND_NEED_READRDY 0x00000100 158 159 /* Chip does not allow subpage writes */ 160 #define NAND_NO_SUBPAGE_WRITE 0x00000200 161 162 /* Device is one of 'new' xD cards that expose fake nand command set */ 163 #define NAND_BROKEN_XD 0x00000400 164 165 /* Device behaves just like nand, but is readonly */ 166 #define NAND_ROM 0x00000800 167 168 /* Device supports subpage reads */ 169 #define NAND_SUBPAGE_READ 0x00001000 170 171 /* 172 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 173 * patterns. 174 */ 175 #define NAND_NEED_SCRAMBLING 0x00002000 176 177 /* Options valid for Samsung large page devices */ 178 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 179 180 /* Macros to identify the above */ 181 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 182 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 183 184 /* Non chip related options */ 185 /* This option skips the bbt scan during initialization. */ 186 #define NAND_SKIP_BBTSCAN 0x00010000 187 /* 188 * This option is defined if the board driver allocates its own buffers 189 * (e.g. because it needs them DMA-coherent). 190 */ 191 #define NAND_OWN_BUFFERS 0x00020000 192 /* Chip may not exist, so silence any errors in scan */ 193 #define NAND_SCAN_SILENT_NODEV 0x00040000 194 /* 195 * Autodetect nand buswidth with readid/onfi. 196 * This suppose the driver will configure the hardware in 8 bits mode 197 * when calling nand_scan_ident, and update its configuration 198 * before calling nand_scan_tail. 199 */ 200 #define NAND_BUSWIDTH_AUTO 0x00080000 201 /* 202 * This option could be defined by controller drivers to protect against 203 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 204 */ 205 #define NAND_USE_BOUNCE_BUFFER 0x00100000 206 207 /* Options set by nand scan */ 208 /* Nand scan has allocated controller struct */ 209 #define NAND_CONTROLLER_ALLOC 0x80000000 210 211 /* Cell info constants */ 212 #define NAND_CI_CHIPNR_MSK 0x03 213 #define NAND_CI_CELLTYPE_MSK 0x0C 214 #define NAND_CI_CELLTYPE_SHIFT 2 215 216 /* Keep gcc happy */ 217 struct nand_chip; 218 219 /* ONFI features */ 220 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 221 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 222 223 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 224 #define ONFI_TIMING_MODE_0 (1 << 0) 225 #define ONFI_TIMING_MODE_1 (1 << 1) 226 #define ONFI_TIMING_MODE_2 (1 << 2) 227 #define ONFI_TIMING_MODE_3 (1 << 3) 228 #define ONFI_TIMING_MODE_4 (1 << 4) 229 #define ONFI_TIMING_MODE_5 (1 << 5) 230 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 231 232 /* ONFI feature address */ 233 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 234 235 /* Vendor-specific feature address (Micron) */ 236 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 237 238 /* ONFI subfeature parameters length */ 239 #define ONFI_SUBFEATURE_PARAM_LEN 4 240 241 /* ONFI optional commands SET/GET FEATURES supported? */ 242 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 243 244 struct nand_onfi_params { 245 /* rev info and features block */ 246 /* 'O' 'N' 'F' 'I' */ 247 u8 sig[4]; 248 __le16 revision; 249 __le16 features; 250 __le16 opt_cmd; 251 u8 reserved0[2]; 252 __le16 ext_param_page_length; /* since ONFI 2.1 */ 253 u8 num_of_param_pages; /* since ONFI 2.1 */ 254 u8 reserved1[17]; 255 256 /* manufacturer information block */ 257 char manufacturer[12]; 258 char model[20]; 259 u8 jedec_id; 260 __le16 date_code; 261 u8 reserved2[13]; 262 263 /* memory organization block */ 264 __le32 byte_per_page; 265 __le16 spare_bytes_per_page; 266 __le32 data_bytes_per_ppage; 267 __le16 spare_bytes_per_ppage; 268 __le32 pages_per_block; 269 __le32 blocks_per_lun; 270 u8 lun_count; 271 u8 addr_cycles; 272 u8 bits_per_cell; 273 __le16 bb_per_lun; 274 __le16 block_endurance; 275 u8 guaranteed_good_blocks; 276 __le16 guaranteed_block_endurance; 277 u8 programs_per_page; 278 u8 ppage_attr; 279 u8 ecc_bits; 280 u8 interleaved_bits; 281 u8 interleaved_ops; 282 u8 reserved3[13]; 283 284 /* electrical parameter block */ 285 u8 io_pin_capacitance_max; 286 __le16 async_timing_mode; 287 __le16 program_cache_timing_mode; 288 __le16 t_prog; 289 __le16 t_bers; 290 __le16 t_r; 291 __le16 t_ccs; 292 __le16 src_sync_timing_mode; 293 u8 src_ssync_features; 294 __le16 clk_pin_capacitance_typ; 295 __le16 io_pin_capacitance_typ; 296 __le16 input_pin_capacitance_typ; 297 u8 input_pin_capacitance_max; 298 u8 driver_strength_support; 299 __le16 t_int_r; 300 __le16 t_adl; 301 u8 reserved4[8]; 302 303 /* vendor */ 304 __le16 vendor_revision; 305 u8 vendor[88]; 306 307 __le16 crc; 308 } __packed; 309 310 #define ONFI_CRC_BASE 0x4F4E 311 312 /* Extended ECC information Block Definition (since ONFI 2.1) */ 313 struct onfi_ext_ecc_info { 314 u8 ecc_bits; 315 u8 codeword_size; 316 __le16 bb_per_lun; 317 __le16 block_endurance; 318 u8 reserved[2]; 319 } __packed; 320 321 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 322 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 323 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 324 struct onfi_ext_section { 325 u8 type; 326 u8 length; 327 } __packed; 328 329 #define ONFI_EXT_SECTION_MAX 8 330 331 /* Extended Parameter Page Definition (since ONFI 2.1) */ 332 struct onfi_ext_param_page { 333 __le16 crc; 334 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 335 u8 reserved0[10]; 336 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 337 338 /* 339 * The actual size of the Extended Parameter Page is in 340 * @ext_param_page_length of nand_onfi_params{}. 341 * The following are the variable length sections. 342 * So we do not add any fields below. Please see the ONFI spec. 343 */ 344 } __packed; 345 346 struct nand_onfi_vendor_micron { 347 u8 two_plane_read; 348 u8 read_cache; 349 u8 read_unique_id; 350 u8 dq_imped; 351 u8 dq_imped_num_settings; 352 u8 dq_imped_feat_addr; 353 u8 rb_pulldown_strength; 354 u8 rb_pulldown_strength_feat_addr; 355 u8 rb_pulldown_strength_num_settings; 356 u8 otp_mode; 357 u8 otp_page_start; 358 u8 otp_data_prot_addr; 359 u8 otp_num_pages; 360 u8 otp_feat_addr; 361 u8 read_retry_options; 362 u8 reserved[72]; 363 u8 param_revision; 364 } __packed; 365 366 struct jedec_ecc_info { 367 u8 ecc_bits; 368 u8 codeword_size; 369 __le16 bb_per_lun; 370 __le16 block_endurance; 371 u8 reserved[2]; 372 } __packed; 373 374 /* JEDEC features */ 375 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 376 377 struct nand_jedec_params { 378 /* rev info and features block */ 379 /* 'J' 'E' 'S' 'D' */ 380 u8 sig[4]; 381 __le16 revision; 382 __le16 features; 383 u8 opt_cmd[3]; 384 __le16 sec_cmd; 385 u8 num_of_param_pages; 386 u8 reserved0[18]; 387 388 /* manufacturer information block */ 389 char manufacturer[12]; 390 char model[20]; 391 u8 jedec_id[6]; 392 u8 reserved1[10]; 393 394 /* memory organization block */ 395 __le32 byte_per_page; 396 __le16 spare_bytes_per_page; 397 u8 reserved2[6]; 398 __le32 pages_per_block; 399 __le32 blocks_per_lun; 400 u8 lun_count; 401 u8 addr_cycles; 402 u8 bits_per_cell; 403 u8 programs_per_page; 404 u8 multi_plane_addr; 405 u8 multi_plane_op_attr; 406 u8 reserved3[38]; 407 408 /* electrical parameter block */ 409 __le16 async_sdr_speed_grade; 410 __le16 toggle_ddr_speed_grade; 411 __le16 sync_ddr_speed_grade; 412 u8 async_sdr_features; 413 u8 toggle_ddr_features; 414 u8 sync_ddr_features; 415 __le16 t_prog; 416 __le16 t_bers; 417 __le16 t_r; 418 __le16 t_r_multi_plane; 419 __le16 t_ccs; 420 __le16 io_pin_capacitance_typ; 421 __le16 input_pin_capacitance_typ; 422 __le16 clk_pin_capacitance_typ; 423 u8 driver_strength_support; 424 __le16 t_adl; 425 u8 reserved4[36]; 426 427 /* ECC and endurance block */ 428 u8 guaranteed_good_blocks; 429 __le16 guaranteed_block_endurance; 430 struct jedec_ecc_info ecc_info[4]; 431 u8 reserved5[29]; 432 433 /* reserved */ 434 u8 reserved6[148]; 435 436 /* vendor */ 437 __le16 vendor_rev_num; 438 u8 reserved7[88]; 439 440 /* CRC for Parameter Page */ 441 __le16 crc; 442 } __packed; 443 444 /** 445 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 446 * @lock: protection lock 447 * @active: the mtd device which holds the controller currently 448 * @wq: wait queue to sleep on if a NAND operation is in 449 * progress used instead of the per chip wait queue 450 * when a hw controller is available. 451 */ 452 struct nand_hw_control { 453 spinlock_t lock; 454 struct nand_chip *active; 455 wait_queue_head_t wq; 456 }; 457 458 /** 459 * struct nand_ecc_ctrl - Control structure for ECC 460 * @mode: ECC mode 461 * @steps: number of ECC steps per page 462 * @size: data bytes per ECC step 463 * @bytes: ECC bytes per step 464 * @strength: max number of correctible bits per ECC step 465 * @total: total number of ECC bytes per page 466 * @prepad: padding information for syndrome based ECC generators 467 * @postpad: padding information for syndrome based ECC generators 468 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 469 * @layout: ECC layout control struct pointer 470 * @priv: pointer to private ECC control data 471 * @hwctl: function to control hardware ECC generator. Must only 472 * be provided if an hardware ECC is available 473 * @calculate: function for ECC calculation or readback from ECC hardware 474 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 475 * Should return a positive number representing the number of 476 * corrected bitflips, -EBADMSG if the number of bitflips exceed 477 * ECC strength, or any other error code if the error is not 478 * directly related to correction. 479 * If -EBADMSG is returned the input buffers should be left 480 * untouched. 481 * @read_page_raw: function to read a raw page without ECC. This function 482 * should hide the specific layout used by the ECC 483 * controller and always return contiguous in-band and 484 * out-of-band data even if they're not stored 485 * contiguously on the NAND chip (e.g. 486 * NAND_ECC_HW_SYNDROME interleaves in-band and 487 * out-of-band data). 488 * @write_page_raw: function to write a raw page without ECC. This function 489 * should hide the specific layout used by the ECC 490 * controller and consider the passed data as contiguous 491 * in-band and out-of-band data. ECC controller is 492 * responsible for doing the appropriate transformations 493 * to adapt to its specific layout (e.g. 494 * NAND_ECC_HW_SYNDROME interleaves in-band and 495 * out-of-band data). 496 * @read_page: function to read a page according to the ECC generator 497 * requirements; returns maximum number of bitflips corrected in 498 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 499 * @read_subpage: function to read parts of the page covered by ECC; 500 * returns same as read_page() 501 * @write_subpage: function to write parts of the page covered by ECC. 502 * @write_page: function to write a page according to the ECC generator 503 * requirements. 504 * @write_oob_raw: function to write chip OOB data without ECC 505 * @read_oob_raw: function to read chip OOB data without ECC 506 * @read_oob: function to read chip OOB data 507 * @write_oob: function to write chip OOB data 508 */ 509 struct nand_ecc_ctrl { 510 nand_ecc_modes_t mode; 511 int steps; 512 int size; 513 int bytes; 514 int total; 515 int strength; 516 int prepad; 517 int postpad; 518 unsigned int options; 519 struct nand_ecclayout *layout; 520 void *priv; 521 void (*hwctl)(struct mtd_info *mtd, int mode); 522 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 523 uint8_t *ecc_code); 524 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 525 uint8_t *calc_ecc); 526 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 527 uint8_t *buf, int oob_required, int page); 528 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 529 const uint8_t *buf, int oob_required, int page); 530 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 531 uint8_t *buf, int oob_required, int page); 532 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 533 uint32_t offs, uint32_t len, uint8_t *buf, int page); 534 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 535 uint32_t offset, uint32_t data_len, 536 const uint8_t *data_buf, int oob_required, int page); 537 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 538 const uint8_t *buf, int oob_required, int page); 539 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 540 int page); 541 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 542 int page); 543 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 544 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 545 int page); 546 }; 547 548 /** 549 * struct nand_buffers - buffer structure for read/write 550 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 551 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 552 * @databuf: buffer pointer for data, size is (page size + oobsize). 553 * 554 * Do not change the order of buffers. databuf and oobrbuf must be in 555 * consecutive order. 556 */ 557 struct nand_buffers { 558 uint8_t *ecccalc; 559 uint8_t *ecccode; 560 uint8_t *databuf; 561 }; 562 563 /** 564 * struct nand_chip - NAND Private Flash Chip Data 565 * @mtd: MTD device registered to the MTD framework 566 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 567 * flash device 568 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 569 * flash device. 570 * @read_byte: [REPLACEABLE] read one byte from the chip 571 * @read_word: [REPLACEABLE] read one word from the chip 572 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 573 * low 8 I/O lines 574 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 575 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 576 * @select_chip: [REPLACEABLE] select chip nr 577 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 578 * @block_markbad: [REPLACEABLE] mark a block bad 579 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 580 * ALE/CLE/nCE. Also used to write command and address 581 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 582 * device ready/busy line. If set to NULL no access to 583 * ready/busy is available and the ready/busy information 584 * is read from the chip status register. 585 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 586 * commands to the chip. 587 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 588 * ready. 589 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 590 * setting the read-retry mode. Mostly needed for MLC NAND. 591 * @ecc: [BOARDSPECIFIC] ECC control structure 592 * @buffers: buffer structure for read/write 593 * @hwcontrol: platform-specific hardware control structure 594 * @erase: [REPLACEABLE] erase function 595 * @scan_bbt: [REPLACEABLE] function to scan bad block table 596 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 597 * data from array to read regs (tR). 598 * @state: [INTERN] the current state of the NAND device 599 * @oob_poi: "poison value buffer," used for laying out OOB data 600 * before writing 601 * @page_shift: [INTERN] number of address bits in a page (column 602 * address bits). 603 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 604 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 605 * @chip_shift: [INTERN] number of address bits in one chip 606 * @options: [BOARDSPECIFIC] various chip options. They can partly 607 * be set to inform nand_scan about special functionality. 608 * See the defines for further explanation. 609 * @bbt_options: [INTERN] bad block specific options. All options used 610 * here must come from bbm.h. By default, these options 611 * will be copied to the appropriate nand_bbt_descr's. 612 * @badblockpos: [INTERN] position of the bad block marker in the oob 613 * area. 614 * @badblockbits: [INTERN] minimum number of set bits in a good block's 615 * bad block marker position; i.e., BBM == 11110111b is 616 * not bad when badblockbits == 7 617 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 618 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 619 * Minimum amount of bit errors per @ecc_step_ds guaranteed 620 * to be correctable. If unknown, set to zero. 621 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 622 * also from the datasheet. It is the recommended ECC step 623 * size, if known; if unknown, set to zero. 624 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 625 * either deduced from the datasheet if the NAND 626 * chip is not ONFI compliant or set to 0 if it is 627 * (an ONFI chip is always configured in mode 0 628 * after a NAND reset) 629 * @numchips: [INTERN] number of physical chips 630 * @chipsize: [INTERN] the size of one chip for multichip arrays 631 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 632 * @pagebuf: [INTERN] holds the pagenumber which is currently in 633 * data_buf. 634 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 635 * currently in data_buf. 636 * @subpagesize: [INTERN] holds the subpagesize 637 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 638 * non 0 if ONFI supported. 639 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 640 * non 0 if JEDEC supported. 641 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 642 * supported, 0 otherwise. 643 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 644 * supported, 0 otherwise. 645 * @read_retries: [INTERN] the number of read retry modes supported 646 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 647 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 648 * @bbt: [INTERN] bad block table pointer 649 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 650 * lookup. 651 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 652 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 653 * bad block scan. 654 * @controller: [REPLACEABLE] a pointer to a hardware controller 655 * structure which is shared among multiple independent 656 * devices. 657 * @priv: [OPTIONAL] pointer to private chip data 658 * @errstat: [OPTIONAL] hardware specific function to perform 659 * additional error status checks (determine if errors are 660 * correctable). 661 * @write_page: [REPLACEABLE] High-level page write function 662 */ 663 664 struct nand_chip { 665 struct mtd_info mtd; 666 void __iomem *IO_ADDR_R; 667 void __iomem *IO_ADDR_W; 668 669 uint8_t (*read_byte)(struct mtd_info *mtd); 670 u16 (*read_word)(struct mtd_info *mtd); 671 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 672 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 673 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 674 void (*select_chip)(struct mtd_info *mtd, int chip); 675 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 676 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 677 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 678 int (*dev_ready)(struct mtd_info *mtd); 679 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 680 int page_addr); 681 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 682 int (*erase)(struct mtd_info *mtd, int page); 683 int (*scan_bbt)(struct mtd_info *mtd); 684 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 685 int status, int page); 686 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 687 uint32_t offset, int data_len, const uint8_t *buf, 688 int oob_required, int page, int cached, int raw); 689 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 690 int feature_addr, uint8_t *subfeature_para); 691 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 692 int feature_addr, uint8_t *subfeature_para); 693 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 694 695 int chip_delay; 696 unsigned int options; 697 unsigned int bbt_options; 698 699 int page_shift; 700 int phys_erase_shift; 701 int bbt_erase_shift; 702 int chip_shift; 703 int numchips; 704 uint64_t chipsize; 705 int pagemask; 706 int pagebuf; 707 unsigned int pagebuf_bitflips; 708 int subpagesize; 709 uint8_t bits_per_cell; 710 uint16_t ecc_strength_ds; 711 uint16_t ecc_step_ds; 712 int onfi_timing_mode_default; 713 int badblockpos; 714 int badblockbits; 715 716 int onfi_version; 717 int jedec_version; 718 union { 719 struct nand_onfi_params onfi_params; 720 struct nand_jedec_params jedec_params; 721 }; 722 723 int read_retries; 724 725 flstate_t state; 726 727 uint8_t *oob_poi; 728 struct nand_hw_control *controller; 729 730 struct nand_ecc_ctrl ecc; 731 struct nand_buffers *buffers; 732 struct nand_hw_control hwcontrol; 733 734 uint8_t *bbt; 735 struct nand_bbt_descr *bbt_td; 736 struct nand_bbt_descr *bbt_md; 737 738 struct nand_bbt_descr *badblock_pattern; 739 740 void *priv; 741 }; 742 743 static inline void nand_set_flash_node(struct nand_chip *chip, 744 struct device_node *np) 745 { 746 mtd_set_of_node(&chip->mtd, np); 747 } 748 749 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 750 { 751 return mtd_get_of_node(&chip->mtd); 752 } 753 754 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 755 { 756 return container_of(mtd, struct nand_chip, mtd); 757 } 758 759 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 760 { 761 return &chip->mtd; 762 } 763 764 static inline void *nand_get_controller_data(struct nand_chip *chip) 765 { 766 return chip->priv; 767 } 768 769 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 770 { 771 chip->priv = priv; 772 } 773 774 /* 775 * NAND Flash Manufacturer ID Codes 776 */ 777 #define NAND_MFR_TOSHIBA 0x98 778 #define NAND_MFR_SAMSUNG 0xec 779 #define NAND_MFR_FUJITSU 0x04 780 #define NAND_MFR_NATIONAL 0x8f 781 #define NAND_MFR_RENESAS 0x07 782 #define NAND_MFR_STMICRO 0x20 783 #define NAND_MFR_HYNIX 0xad 784 #define NAND_MFR_MICRON 0x2c 785 #define NAND_MFR_AMD 0x01 786 #define NAND_MFR_MACRONIX 0xc2 787 #define NAND_MFR_EON 0x92 788 #define NAND_MFR_SANDISK 0x45 789 #define NAND_MFR_INTEL 0x89 790 #define NAND_MFR_ATO 0x9b 791 792 /* The maximum expected count of bytes in the NAND ID sequence */ 793 #define NAND_MAX_ID_LEN 8 794 795 /* 796 * A helper for defining older NAND chips where the second ID byte fully 797 * defined the chip, including the geometry (chip size, eraseblock size, page 798 * size). All these chips have 512 bytes NAND page size. 799 */ 800 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 801 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 802 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 803 804 /* 805 * A helper for defining newer chips which report their page size and 806 * eraseblock size via the extended ID bytes. 807 * 808 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 809 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 810 * device ID now only represented a particular total chip size (and voltage, 811 * buswidth), and the page size, eraseblock size, and OOB size could vary while 812 * using the same device ID. 813 */ 814 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 815 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 816 .options = (opts) } 817 818 #define NAND_ECC_INFO(_strength, _step) \ 819 { .strength_ds = (_strength), .step_ds = (_step) } 820 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 821 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 822 823 /** 824 * struct nand_flash_dev - NAND Flash Device ID Structure 825 * @name: a human-readable name of the NAND chip 826 * @dev_id: the device ID (the second byte of the full chip ID array) 827 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 828 * memory address as @id[0]) 829 * @dev_id: device ID part of the full chip ID array (refers the same memory 830 * address as @id[1]) 831 * @id: full device ID array 832 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 833 * well as the eraseblock size) is determined from the extended NAND 834 * chip ID array) 835 * @chipsize: total chip size in MiB 836 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 837 * @options: stores various chip bit options 838 * @id_len: The valid length of the @id. 839 * @oobsize: OOB size 840 * @ecc: ECC correctability and step information from the datasheet. 841 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 842 * @ecc_strength_ds in nand_chip{}. 843 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 844 * @ecc_step_ds in nand_chip{}, also from the datasheet. 845 * For example, the "4bit ECC for each 512Byte" can be set with 846 * NAND_ECC_INFO(4, 512). 847 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 848 * reset. Should be deduced from timings described 849 * in the datasheet. 850 * 851 */ 852 struct nand_flash_dev { 853 char *name; 854 union { 855 struct { 856 uint8_t mfr_id; 857 uint8_t dev_id; 858 }; 859 uint8_t id[NAND_MAX_ID_LEN]; 860 }; 861 unsigned int pagesize; 862 unsigned int chipsize; 863 unsigned int erasesize; 864 unsigned int options; 865 uint16_t id_len; 866 uint16_t oobsize; 867 struct { 868 uint16_t strength_ds; 869 uint16_t step_ds; 870 } ecc; 871 int onfi_timing_mode_default; 872 }; 873 874 /** 875 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 876 * @name: Manufacturer name 877 * @id: manufacturer ID code of device. 878 */ 879 struct nand_manufacturers { 880 int id; 881 char *name; 882 }; 883 884 extern struct nand_flash_dev nand_flash_ids[]; 885 extern struct nand_manufacturers nand_manuf_ids[]; 886 887 extern int nand_default_bbt(struct mtd_info *mtd); 888 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 889 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 890 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 891 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 892 int allowbbt); 893 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 894 size_t *retlen, uint8_t *buf); 895 896 /** 897 * struct platform_nand_chip - chip level device structure 898 * @nr_chips: max. number of chips to scan for 899 * @chip_offset: chip number offset 900 * @nr_partitions: number of partitions pointed to by partitions (or zero) 901 * @partitions: mtd partition list 902 * @chip_delay: R/B delay value in us 903 * @options: Option flags, e.g. 16bit buswidth 904 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 905 * @part_probe_types: NULL-terminated array of probe types 906 */ 907 struct platform_nand_chip { 908 int nr_chips; 909 int chip_offset; 910 int nr_partitions; 911 struct mtd_partition *partitions; 912 int chip_delay; 913 unsigned int options; 914 unsigned int bbt_options; 915 const char **part_probe_types; 916 }; 917 918 /* Keep gcc happy */ 919 struct platform_device; 920 921 /** 922 * struct platform_nand_ctrl - controller level device structure 923 * @probe: platform specific function to probe/setup hardware 924 * @remove: platform specific function to remove/teardown hardware 925 * @hwcontrol: platform specific hardware control structure 926 * @dev_ready: platform specific function to read ready/busy pin 927 * @select_chip: platform specific chip select function 928 * @cmd_ctrl: platform specific function for controlling 929 * ALE/CLE/nCE. Also used to write command and address 930 * @write_buf: platform specific function for write buffer 931 * @read_buf: platform specific function for read buffer 932 * @read_byte: platform specific function to read one byte from chip 933 * @priv: private data to transport driver specific settings 934 * 935 * All fields are optional and depend on the hardware driver requirements 936 */ 937 struct platform_nand_ctrl { 938 int (*probe)(struct platform_device *pdev); 939 void (*remove)(struct platform_device *pdev); 940 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 941 int (*dev_ready)(struct mtd_info *mtd); 942 void (*select_chip)(struct mtd_info *mtd, int chip); 943 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 944 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 945 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 946 unsigned char (*read_byte)(struct mtd_info *mtd); 947 void *priv; 948 }; 949 950 /** 951 * struct platform_nand_data - container structure for platform-specific data 952 * @chip: chip level chip structure 953 * @ctrl: controller level device structure 954 */ 955 struct platform_nand_data { 956 struct platform_nand_chip chip; 957 struct platform_nand_ctrl ctrl; 958 }; 959 960 /* return the supported features. */ 961 static inline int onfi_feature(struct nand_chip *chip) 962 { 963 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 964 } 965 966 /* return the supported asynchronous timing mode. */ 967 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 968 { 969 if (!chip->onfi_version) 970 return ONFI_TIMING_MODE_UNKNOWN; 971 return le16_to_cpu(chip->onfi_params.async_timing_mode); 972 } 973 974 /* return the supported synchronous timing mode. */ 975 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 976 { 977 if (!chip->onfi_version) 978 return ONFI_TIMING_MODE_UNKNOWN; 979 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 980 } 981 982 /* 983 * Check if it is a SLC nand. 984 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 985 * We do not distinguish the MLC and TLC now. 986 */ 987 static inline bool nand_is_slc(struct nand_chip *chip) 988 { 989 return chip->bits_per_cell == 1; 990 } 991 992 /** 993 * Check if the opcode's address should be sent only on the lower 8 bits 994 * @command: opcode to check 995 */ 996 static inline int nand_opcode_8bits(unsigned int command) 997 { 998 switch (command) { 999 case NAND_CMD_READID: 1000 case NAND_CMD_PARAM: 1001 case NAND_CMD_GET_FEATURES: 1002 case NAND_CMD_SET_FEATURES: 1003 return 1; 1004 default: 1005 break; 1006 } 1007 return 0; 1008 } 1009 1010 /* return the supported JEDEC features. */ 1011 static inline int jedec_feature(struct nand_chip *chip) 1012 { 1013 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1014 : 0; 1015 } 1016 1017 /* 1018 * struct nand_sdr_timings - SDR NAND chip timings 1019 * 1020 * This struct defines the timing requirements of a SDR NAND chip. 1021 * These informations can be found in every NAND datasheets and the timings 1022 * meaning are described in the ONFI specifications: 1023 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 1024 * Parameters) 1025 * 1026 * All these timings are expressed in picoseconds. 1027 */ 1028 1029 struct nand_sdr_timings { 1030 u32 tALH_min; 1031 u32 tADL_min; 1032 u32 tALS_min; 1033 u32 tAR_min; 1034 u32 tCEA_max; 1035 u32 tCEH_min; 1036 u32 tCH_min; 1037 u32 tCHZ_max; 1038 u32 tCLH_min; 1039 u32 tCLR_min; 1040 u32 tCLS_min; 1041 u32 tCOH_min; 1042 u32 tCS_min; 1043 u32 tDH_min; 1044 u32 tDS_min; 1045 u32 tFEAT_max; 1046 u32 tIR_min; 1047 u32 tITC_max; 1048 u32 tRC_min; 1049 u32 tREA_max; 1050 u32 tREH_min; 1051 u32 tRHOH_min; 1052 u32 tRHW_min; 1053 u32 tRHZ_max; 1054 u32 tRLOH_min; 1055 u32 tRP_min; 1056 u32 tRR_min; 1057 u64 tRST_max; 1058 u32 tWB_max; 1059 u32 tWC_min; 1060 u32 tWH_min; 1061 u32 tWHR_min; 1062 u32 tWP_min; 1063 u32 tWW_min; 1064 }; 1065 1066 /* get timing characteristics from ONFI timing mode. */ 1067 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1068 1069 int nand_check_erased_ecc_chunk(void *data, int datalen, 1070 void *ecc, int ecclen, 1071 void *extraoob, int extraooblen, 1072 int threshold); 1073 #endif /* __LINUX_MTD_NAND_H */ 1074