1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Info: 15 * Contains standard defines and IDs for NAND flash devices 16 * 17 * Changelog: 18 * See git changelog. 19 */ 20 #ifndef __LINUX_MTD_NAND_H 21 #define __LINUX_MTD_NAND_H 22 23 #include <linux/wait.h> 24 #include <linux/spinlock.h> 25 #include <linux/mtd/mtd.h> 26 27 struct mtd_info; 28 /* Scan and identify a NAND device */ 29 extern int nand_scan (struct mtd_info *mtd, int max_chips); 30 /* Separate phases of nand_scan(), allowing board driver to intervene 31 * and override command or ECC setup according to flash type */ 32 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); 33 extern int nand_scan_tail(struct mtd_info *mtd); 34 35 /* Free resources held by the NAND device */ 36 extern void nand_release (struct mtd_info *mtd); 37 38 /* Internal helper for board drivers which need to override command function */ 39 extern void nand_wait_ready(struct mtd_info *mtd); 40 41 /* The maximum number of NAND chips in an array */ 42 #define NAND_MAX_CHIPS 8 43 44 /* This constant declares the max. oobsize / page, which 45 * is supported now. If you add a chip with bigger oobsize/page 46 * adjust this accordingly. 47 */ 48 #define NAND_MAX_OOBSIZE 64 49 #define NAND_MAX_PAGESIZE 2048 50 51 /* 52 * Constants for hardware specific CLE/ALE/NCE function 53 * 54 * These are bits which can be or'ed to set/clear multiple 55 * bits in one go. 56 */ 57 /* Select the chip by setting nCE to low */ 58 #define NAND_NCE 0x01 59 /* Select the command latch by setting CLE to high */ 60 #define NAND_CLE 0x02 61 /* Select the address latch by setting ALE to high */ 62 #define NAND_ALE 0x04 63 64 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 65 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 66 #define NAND_CTRL_CHANGE 0x80 67 68 /* 69 * Standard NAND flash commands 70 */ 71 #define NAND_CMD_READ0 0 72 #define NAND_CMD_READ1 1 73 #define NAND_CMD_RNDOUT 5 74 #define NAND_CMD_PAGEPROG 0x10 75 #define NAND_CMD_READOOB 0x50 76 #define NAND_CMD_ERASE1 0x60 77 #define NAND_CMD_STATUS 0x70 78 #define NAND_CMD_STATUS_MULTI 0x71 79 #define NAND_CMD_SEQIN 0x80 80 #define NAND_CMD_RNDIN 0x85 81 #define NAND_CMD_READID 0x90 82 #define NAND_CMD_ERASE2 0xd0 83 #define NAND_CMD_RESET 0xff 84 85 /* Extended commands for large page devices */ 86 #define NAND_CMD_READSTART 0x30 87 #define NAND_CMD_RNDOUTSTART 0xE0 88 #define NAND_CMD_CACHEDPROG 0x15 89 90 /* Extended commands for AG-AND device */ 91 /* 92 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 93 * there is no way to distinguish that from NAND_CMD_READ0 94 * until the remaining sequence of commands has been completed 95 * so add a high order bit and mask it off in the command. 96 */ 97 #define NAND_CMD_DEPLETE1 0x100 98 #define NAND_CMD_DEPLETE2 0x38 99 #define NAND_CMD_STATUS_MULTI 0x71 100 #define NAND_CMD_STATUS_ERROR 0x72 101 /* multi-bank error status (banks 0-3) */ 102 #define NAND_CMD_STATUS_ERROR0 0x73 103 #define NAND_CMD_STATUS_ERROR1 0x74 104 #define NAND_CMD_STATUS_ERROR2 0x75 105 #define NAND_CMD_STATUS_ERROR3 0x76 106 #define NAND_CMD_STATUS_RESET 0x7f 107 #define NAND_CMD_STATUS_CLEAR 0xff 108 109 #define NAND_CMD_NONE -1 110 111 /* Status bits */ 112 #define NAND_STATUS_FAIL 0x01 113 #define NAND_STATUS_FAIL_N1 0x02 114 #define NAND_STATUS_TRUE_READY 0x20 115 #define NAND_STATUS_READY 0x40 116 #define NAND_STATUS_WP 0x80 117 118 /* 119 * Constants for ECC_MODES 120 */ 121 typedef enum { 122 NAND_ECC_NONE, 123 NAND_ECC_SOFT, 124 NAND_ECC_HW, 125 NAND_ECC_HW_SYNDROME, 126 } nand_ecc_modes_t; 127 128 /* 129 * Constants for Hardware ECC 130 */ 131 /* Reset Hardware ECC for read */ 132 #define NAND_ECC_READ 0 133 /* Reset Hardware ECC for write */ 134 #define NAND_ECC_WRITE 1 135 /* Enable Hardware ECC before syndrom is read back from flash */ 136 #define NAND_ECC_READSYN 2 137 138 /* Bit mask for flags passed to do_nand_read_ecc */ 139 #define NAND_GET_DEVICE 0x80 140 141 142 /* Option constants for bizarre disfunctionality and real 143 * features 144 */ 145 /* Chip can not auto increment pages */ 146 #define NAND_NO_AUTOINCR 0x00000001 147 /* Buswitdh is 16 bit */ 148 #define NAND_BUSWIDTH_16 0x00000002 149 /* Device supports partial programming without padding */ 150 #define NAND_NO_PADDING 0x00000004 151 /* Chip has cache program function */ 152 #define NAND_CACHEPRG 0x00000008 153 /* Chip has copy back function */ 154 #define NAND_COPYBACK 0x00000010 155 /* AND Chip which has 4 banks and a confusing page / block 156 * assignment. See Renesas datasheet for further information */ 157 #define NAND_IS_AND 0x00000020 158 /* Chip has a array of 4 pages which can be read without 159 * additional ready /busy waits */ 160 #define NAND_4PAGE_ARRAY 0x00000040 161 /* Chip requires that BBT is periodically rewritten to prevent 162 * bits from adjacent blocks from 'leaking' in altering data. 163 * This happens with the Renesas AG-AND chips, possibly others. */ 164 #define BBT_AUTO_REFRESH 0x00000080 165 /* Chip does not require ready check on read. True 166 * for all large page devices, as they do not support 167 * autoincrement.*/ 168 #define NAND_NO_READRDY 0x00000100 169 /* Chip does not allow subpage writes */ 170 #define NAND_NO_SUBPAGE_WRITE 0x00000200 171 172 173 /* Options valid for Samsung large page devices */ 174 #define NAND_SAMSUNG_LP_OPTIONS \ 175 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 176 177 /* Macros to identify the above */ 178 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 179 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 180 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 181 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 182 183 /* Mask to zero out the chip options, which come from the id table */ 184 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 185 186 /* Non chip related options */ 187 /* Use a flash based bad block table. This option is passed to the 188 * default bad block table function. */ 189 #define NAND_USE_FLASH_BBT 0x00010000 190 /* This option skips the bbt scan during initialization. */ 191 #define NAND_SKIP_BBTSCAN 0x00020000 192 /* This option is defined if the board driver allocates its own buffers 193 (e.g. because it needs them DMA-coherent */ 194 #define NAND_OWN_BUFFERS 0x00040000 195 /* Options set by nand scan */ 196 /* Nand scan has allocated controller struct */ 197 #define NAND_CONTROLLER_ALLOC 0x80000000 198 199 /* Cell info constants */ 200 #define NAND_CI_CHIPNR_MSK 0x03 201 #define NAND_CI_CELLTYPE_MSK 0x0C 202 203 /* 204 * nand_state_t - chip states 205 * Enumeration for NAND flash chip state 206 */ 207 typedef enum { 208 FL_READY, 209 FL_READING, 210 FL_WRITING, 211 FL_ERASING, 212 FL_SYNCING, 213 FL_CACHEDPRG, 214 FL_PM_SUSPENDED, 215 } nand_state_t; 216 217 /* Keep gcc happy */ 218 struct nand_chip; 219 220 /** 221 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 222 * @lock: protection lock 223 * @active: the mtd device which holds the controller currently 224 * @wq: wait queue to sleep on if a NAND operation is in progress 225 * used instead of the per chip wait queue when a hw controller is available 226 */ 227 struct nand_hw_control { 228 spinlock_t lock; 229 struct nand_chip *active; 230 wait_queue_head_t wq; 231 }; 232 233 /** 234 * struct nand_ecc_ctrl - Control structure for ecc 235 * @mode: ecc mode 236 * @steps: number of ecc steps per page 237 * @size: data bytes per ecc step 238 * @bytes: ecc bytes per step 239 * @total: total number of ecc bytes per page 240 * @prepad: padding information for syndrome based ecc generators 241 * @postpad: padding information for syndrome based ecc generators 242 * @layout: ECC layout control struct pointer 243 * @hwctl: function to control hardware ecc generator. Must only 244 * be provided if an hardware ECC is available 245 * @calculate: function for ecc calculation or readback from ecc hardware 246 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 247 * @read_page_raw: function to read a raw page without ECC 248 * @write_page_raw: function to write a raw page without ECC 249 * @read_page: function to read a page according to the ecc generator requirements 250 * @write_page: function to write a page according to the ecc generator requirements 251 * @read_oob: function to read chip OOB data 252 * @write_oob: function to write chip OOB data 253 */ 254 struct nand_ecc_ctrl { 255 nand_ecc_modes_t mode; 256 int steps; 257 int size; 258 int bytes; 259 int total; 260 int prepad; 261 int postpad; 262 struct nand_ecclayout *layout; 263 void (*hwctl)(struct mtd_info *mtd, int mode); 264 int (*calculate)(struct mtd_info *mtd, 265 const uint8_t *dat, 266 uint8_t *ecc_code); 267 int (*correct)(struct mtd_info *mtd, uint8_t *dat, 268 uint8_t *read_ecc, 269 uint8_t *calc_ecc); 270 int (*read_page_raw)(struct mtd_info *mtd, 271 struct nand_chip *chip, 272 uint8_t *buf); 273 void (*write_page_raw)(struct mtd_info *mtd, 274 struct nand_chip *chip, 275 const uint8_t *buf); 276 int (*read_page)(struct mtd_info *mtd, 277 struct nand_chip *chip, 278 uint8_t *buf); 279 void (*write_page)(struct mtd_info *mtd, 280 struct nand_chip *chip, 281 const uint8_t *buf); 282 int (*read_oob)(struct mtd_info *mtd, 283 struct nand_chip *chip, 284 int page, 285 int sndcmd); 286 int (*write_oob)(struct mtd_info *mtd, 287 struct nand_chip *chip, 288 int page); 289 }; 290 291 /** 292 * struct nand_buffers - buffer structure for read/write 293 * @ecccalc: buffer for calculated ecc 294 * @ecccode: buffer for ecc read from flash 295 * @databuf: buffer for data - dynamically sized 296 * 297 * Do not change the order of buffers. databuf and oobrbuf must be in 298 * consecutive order. 299 */ 300 struct nand_buffers { 301 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 302 uint8_t ecccode[NAND_MAX_OOBSIZE]; 303 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 304 }; 305 306 /** 307 * struct nand_chip - NAND Private Flash Chip Data 308 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 309 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 310 * @read_byte: [REPLACEABLE] read one byte from the chip 311 * @read_word: [REPLACEABLE] read one word from the chip 312 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 313 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 314 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 315 * @select_chip: [REPLACEABLE] select chip nr 316 * @block_bad: [REPLACEABLE] check, if the block is bad 317 * @block_markbad: [REPLACEABLE] mark the block bad 318 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling 319 * ALE/CLE/nCE. Also used to write command and address 320 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 321 * If set to NULL no access to ready/busy is available and the ready/busy information 322 * is read from the chip status register 323 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 324 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 325 * @ecc: [BOARDSPECIFIC] ecc control ctructure 326 * @buffers: buffer structure for read/write 327 * @hwcontrol: platform-specific hardware control structure 328 * @ops: oob operation operands 329 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 330 * @scan_bbt: [REPLACEABLE] function to scan bad block table 331 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 332 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 333 * @state: [INTERN] the current state of the NAND device 334 * @oob_poi: poison value buffer 335 * @page_shift: [INTERN] number of address bits in a page (column address bits) 336 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 337 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 338 * @chip_shift: [INTERN] number of address bits in one chip 339 * @datbuf: [INTERN] internal buffer for one page + oob 340 * @oobbuf: [INTERN] oob buffer for one eraseblock 341 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 342 * @data_poi: [INTERN] pointer to a data buffer 343 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 344 * special functionality. See the defines for further explanation 345 * @badblockpos: [INTERN] position of the bad block marker in the oob area 346 * @cellinfo: [INTERN] MLC/multichip data from chip ident 347 * @numchips: [INTERN] number of physical chips 348 * @chipsize: [INTERN] the size of one chip for multichip arrays 349 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 350 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 351 * @subpagesize: [INTERN] holds the subpagesize 352 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 353 * @bbt: [INTERN] bad block table pointer 354 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 355 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 356 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 357 * @controller: [REPLACEABLE] a pointer to a hardware controller structure 358 * which is shared among multiple independend devices 359 * @priv: [OPTIONAL] pointer to private chip date 360 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 361 * (determine if errors are correctable) 362 * @write_page: [REPLACEABLE] High-level page write function 363 */ 364 365 struct nand_chip { 366 void __iomem *IO_ADDR_R; 367 void __iomem *IO_ADDR_W; 368 369 uint8_t (*read_byte)(struct mtd_info *mtd); 370 u16 (*read_word)(struct mtd_info *mtd); 371 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 372 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 373 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 374 void (*select_chip)(struct mtd_info *mtd, int chip); 375 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 376 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 377 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 378 unsigned int ctrl); 379 int (*dev_ready)(struct mtd_info *mtd); 380 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 381 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 382 void (*erase_cmd)(struct mtd_info *mtd, int page); 383 int (*scan_bbt)(struct mtd_info *mtd); 384 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); 385 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 386 const uint8_t *buf, int page, int cached, int raw); 387 388 int chip_delay; 389 unsigned int options; 390 391 int page_shift; 392 int phys_erase_shift; 393 int bbt_erase_shift; 394 int chip_shift; 395 int numchips; 396 unsigned long chipsize; 397 int pagemask; 398 int pagebuf; 399 int subpagesize; 400 uint8_t cellinfo; 401 int badblockpos; 402 403 nand_state_t state; 404 405 uint8_t *oob_poi; 406 struct nand_hw_control *controller; 407 struct nand_ecclayout *ecclayout; 408 409 struct nand_ecc_ctrl ecc; 410 struct nand_buffers *buffers; 411 struct nand_hw_control hwcontrol; 412 413 struct mtd_oob_ops ops; 414 415 uint8_t *bbt; 416 struct nand_bbt_descr *bbt_td; 417 struct nand_bbt_descr *bbt_md; 418 419 struct nand_bbt_descr *badblock_pattern; 420 421 void *priv; 422 }; 423 424 /* 425 * NAND Flash Manufacturer ID Codes 426 */ 427 #define NAND_MFR_TOSHIBA 0x98 428 #define NAND_MFR_SAMSUNG 0xec 429 #define NAND_MFR_FUJITSU 0x04 430 #define NAND_MFR_NATIONAL 0x8f 431 #define NAND_MFR_RENESAS 0x07 432 #define NAND_MFR_STMICRO 0x20 433 #define NAND_MFR_HYNIX 0xad 434 435 /** 436 * struct nand_flash_dev - NAND Flash Device ID Structure 437 * @name: Identify the device type 438 * @id: device ID code 439 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 440 * If the pagesize is 0, then the real pagesize 441 * and the eraseize are determined from the 442 * extended id bytes in the chip 443 * @erasesize: Size of an erase block in the flash device. 444 * @chipsize: Total chipsize in Mega Bytes 445 * @options: Bitfield to store chip relevant options 446 */ 447 struct nand_flash_dev { 448 char *name; 449 int id; 450 unsigned long pagesize; 451 unsigned long chipsize; 452 unsigned long erasesize; 453 unsigned long options; 454 }; 455 456 /** 457 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 458 * @name: Manufacturer name 459 * @id: manufacturer ID code of device. 460 */ 461 struct nand_manufacturers { 462 int id; 463 char * name; 464 }; 465 466 extern struct nand_flash_dev nand_flash_ids[]; 467 extern struct nand_manufacturers nand_manuf_ids[]; 468 469 /** 470 * struct nand_bbt_descr - bad block table descriptor 471 * @options: options for this descriptor 472 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE 473 * when bbt is searched, then we store the found bbts pages here. 474 * Its an array and supports up to 8 chips now 475 * @offs: offset of the pattern in the oob area of the page 476 * @veroffs: offset of the bbt version counter in the oob are of the page 477 * @version: version read from the bbt page during scan 478 * @len: length of the pattern, if 0 no pattern check is performed 479 * @maxblocks: maximum number of blocks to search for a bbt. This number of 480 * blocks is reserved at the end of the device where the tables are 481 * written. 482 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than 483 * bad) block in the stored bbt 484 * @pattern: pattern to identify bad block table or factory marked good / 485 * bad blocks, can be NULL, if len = 0 486 * 487 * Descriptor for the bad block table marker and the descriptor for the 488 * pattern which identifies good and bad blocks. The assumption is made 489 * that the pattern and the version count are always located in the oob area 490 * of the first block. 491 */ 492 struct nand_bbt_descr { 493 int options; 494 int pages[NAND_MAX_CHIPS]; 495 int offs; 496 int veroffs; 497 uint8_t version[NAND_MAX_CHIPS]; 498 int len; 499 int maxblocks; 500 int reserved_block_code; 501 uint8_t *pattern; 502 }; 503 504 /* Options for the bad block table descriptors */ 505 506 /* The number of bits used per block in the bbt on the device */ 507 #define NAND_BBT_NRBITS_MSK 0x0000000F 508 #define NAND_BBT_1BIT 0x00000001 509 #define NAND_BBT_2BIT 0x00000002 510 #define NAND_BBT_4BIT 0x00000004 511 #define NAND_BBT_8BIT 0x00000008 512 /* The bad block table is in the last good block of the device */ 513 #define NAND_BBT_LASTBLOCK 0x00000010 514 /* The bbt is at the given page, else we must scan for the bbt */ 515 #define NAND_BBT_ABSPAGE 0x00000020 516 /* The bbt is at the given page, else we must scan for the bbt */ 517 #define NAND_BBT_SEARCH 0x00000040 518 /* bbt is stored per chip on multichip devices */ 519 #define NAND_BBT_PERCHIP 0x00000080 520 /* bbt has a version counter at offset veroffs */ 521 #define NAND_BBT_VERSION 0x00000100 522 /* Create a bbt if none axists */ 523 #define NAND_BBT_CREATE 0x00000200 524 /* Search good / bad pattern through all pages of a block */ 525 #define NAND_BBT_SCANALLPAGES 0x00000400 526 /* Scan block empty during good / bad block scan */ 527 #define NAND_BBT_SCANEMPTY 0x00000800 528 /* Write bbt if neccecary */ 529 #define NAND_BBT_WRITE 0x00001000 530 /* Read and write back block contents when writing bbt */ 531 #define NAND_BBT_SAVECONTENT 0x00002000 532 /* Search good / bad pattern on the first and the second page */ 533 #define NAND_BBT_SCAN2NDPAGE 0x00004000 534 535 /* The maximum number of blocks to scan for a bbt */ 536 #define NAND_BBT_SCAN_MAXBLOCKS 4 537 538 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 539 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 540 extern int nand_default_bbt(struct mtd_info *mtd); 541 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 542 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 543 int allowbbt); 544 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 545 size_t * retlen, uint8_t * buf); 546 547 /* 548 * Constants for oob configuration 549 */ 550 #define NAND_SMALL_BADBLOCK_POS 5 551 #define NAND_LARGE_BADBLOCK_POS 0 552 553 /** 554 * struct platform_nand_chip - chip level device structure 555 * @nr_chips: max. number of chips to scan for 556 * @chip_offset: chip number offset 557 * @nr_partitions: number of partitions pointed to by partitions (or zero) 558 * @partitions: mtd partition list 559 * @chip_delay: R/B delay value in us 560 * @options: Option flags, e.g. 16bit buswidth 561 * @ecclayout: ecc layout info structure 562 * @priv: hardware controller specific settings 563 */ 564 struct platform_nand_chip { 565 int nr_chips; 566 int chip_offset; 567 int nr_partitions; 568 struct mtd_partition *partitions; 569 struct nand_ecclayout *ecclayout; 570 int chip_delay; 571 unsigned int options; 572 void *priv; 573 }; 574 575 /** 576 * struct platform_nand_ctrl - controller level device structure 577 * @hwcontrol: platform specific hardware control structure 578 * @dev_ready: platform specific function to read ready/busy pin 579 * @select_chip: platform specific chip select function 580 * @priv: private data to transport driver specific settings 581 * 582 * All fields are optional and depend on the hardware driver requirements 583 */ 584 struct platform_nand_ctrl { 585 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 586 int (*dev_ready)(struct mtd_info *mtd); 587 void (*select_chip)(struct mtd_info *mtd, int chip); 588 void *priv; 589 }; 590 591 /* Some helpers to access the data structures */ 592 static inline 593 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 594 { 595 struct nand_chip *chip = mtd->priv; 596 597 return chip->priv; 598 } 599 600 #endif /* __LINUX_MTD_NAND_H */ 601