1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 /* Scan and identify a NAND device */ 30 extern int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 extern int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Free resources held by the NAND device */ 40 extern void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 extern void nand_wait_ready(struct mtd_info *mtd); 44 45 /* locks all blocks present in the device */ 46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 47 48 /* unlocks specified locked blocks */ 49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 50 51 /* The maximum number of NAND chips in an array */ 52 #define NAND_MAX_CHIPS 8 53 54 /* 55 * This constant declares the max. oobsize / page, which 56 * is supported now. If you add a chip with bigger oobsize/page 57 * adjust this accordingly. 58 */ 59 #define NAND_MAX_OOBSIZE 576 60 #define NAND_MAX_PAGESIZE 8192 61 62 /* 63 * Constants for hardware specific CLE/ALE/NCE function 64 * 65 * These are bits which can be or'ed to set/clear multiple 66 * bits in one go. 67 */ 68 /* Select the chip by setting nCE to low */ 69 #define NAND_NCE 0x01 70 /* Select the command latch by setting CLE to high */ 71 #define NAND_CLE 0x02 72 /* Select the address latch by setting ALE to high */ 73 #define NAND_ALE 0x04 74 75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 77 #define NAND_CTRL_CHANGE 0x80 78 79 /* 80 * Standard NAND flash commands 81 */ 82 #define NAND_CMD_READ0 0 83 #define NAND_CMD_READ1 1 84 #define NAND_CMD_RNDOUT 5 85 #define NAND_CMD_PAGEPROG 0x10 86 #define NAND_CMD_READOOB 0x50 87 #define NAND_CMD_ERASE1 0x60 88 #define NAND_CMD_STATUS 0x70 89 #define NAND_CMD_STATUS_MULTI 0x71 90 #define NAND_CMD_SEQIN 0x80 91 #define NAND_CMD_RNDIN 0x85 92 #define NAND_CMD_READID 0x90 93 #define NAND_CMD_ERASE2 0xd0 94 #define NAND_CMD_PARAM 0xec 95 #define NAND_CMD_RESET 0xff 96 97 #define NAND_CMD_LOCK 0x2a 98 #define NAND_CMD_UNLOCK1 0x23 99 #define NAND_CMD_UNLOCK2 0x24 100 101 /* Extended commands for large page devices */ 102 #define NAND_CMD_READSTART 0x30 103 #define NAND_CMD_RNDOUTSTART 0xE0 104 #define NAND_CMD_CACHEDPROG 0x15 105 106 /* Extended commands for AG-AND device */ 107 /* 108 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 109 * there is no way to distinguish that from NAND_CMD_READ0 110 * until the remaining sequence of commands has been completed 111 * so add a high order bit and mask it off in the command. 112 */ 113 #define NAND_CMD_DEPLETE1 0x100 114 #define NAND_CMD_DEPLETE2 0x38 115 #define NAND_CMD_STATUS_MULTI 0x71 116 #define NAND_CMD_STATUS_ERROR 0x72 117 /* multi-bank error status (banks 0-3) */ 118 #define NAND_CMD_STATUS_ERROR0 0x73 119 #define NAND_CMD_STATUS_ERROR1 0x74 120 #define NAND_CMD_STATUS_ERROR2 0x75 121 #define NAND_CMD_STATUS_ERROR3 0x76 122 #define NAND_CMD_STATUS_RESET 0x7f 123 #define NAND_CMD_STATUS_CLEAR 0xff 124 125 #define NAND_CMD_NONE -1 126 127 /* Status bits */ 128 #define NAND_STATUS_FAIL 0x01 129 #define NAND_STATUS_FAIL_N1 0x02 130 #define NAND_STATUS_TRUE_READY 0x20 131 #define NAND_STATUS_READY 0x40 132 #define NAND_STATUS_WP 0x80 133 134 /* 135 * Constants for ECC_MODES 136 */ 137 typedef enum { 138 NAND_ECC_NONE, 139 NAND_ECC_SOFT, 140 NAND_ECC_HW, 141 NAND_ECC_HW_SYNDROME, 142 NAND_ECC_HW_OOB_FIRST, 143 NAND_ECC_SOFT_BCH, 144 } nand_ecc_modes_t; 145 146 /* 147 * Constants for Hardware ECC 148 */ 149 /* Reset Hardware ECC for read */ 150 #define NAND_ECC_READ 0 151 /* Reset Hardware ECC for write */ 152 #define NAND_ECC_WRITE 1 153 /* Enable Hardware ECC before syndrome is read back from flash */ 154 #define NAND_ECC_READSYN 2 155 156 /* Bit mask for flags passed to do_nand_read_ecc */ 157 #define NAND_GET_DEVICE 0x80 158 159 160 /* 161 * Option constants for bizarre disfunctionality and real 162 * features. 163 */ 164 /* Buswidth is 16 bit */ 165 #define NAND_BUSWIDTH_16 0x00000002 166 /* Device supports partial programming without padding */ 167 #define NAND_NO_PADDING 0x00000004 168 /* Chip has cache program function */ 169 #define NAND_CACHEPRG 0x00000008 170 /* Chip has copy back function */ 171 #define NAND_COPYBACK 0x00000010 172 /* 173 * AND Chip which has 4 banks and a confusing page / block 174 * assignment. See Renesas datasheet for further information. 175 */ 176 #define NAND_IS_AND 0x00000020 177 /* 178 * Chip has a array of 4 pages which can be read without 179 * additional ready /busy waits. 180 */ 181 #define NAND_4PAGE_ARRAY 0x00000040 182 /* 183 * Chip requires that BBT is periodically rewritten to prevent 184 * bits from adjacent blocks from 'leaking' in altering data. 185 * This happens with the Renesas AG-AND chips, possibly others. 186 */ 187 #define BBT_AUTO_REFRESH 0x00000080 188 /* 189 * Chip does not require ready check on read. True 190 * for all large page devices, as they do not support 191 * autoincrement. 192 */ 193 #define NAND_NO_READRDY 0x00000100 194 /* Chip does not allow subpage writes */ 195 #define NAND_NO_SUBPAGE_WRITE 0x00000200 196 197 /* Device is one of 'new' xD cards that expose fake nand command set */ 198 #define NAND_BROKEN_XD 0x00000400 199 200 /* Device behaves just like nand, but is readonly */ 201 #define NAND_ROM 0x00000800 202 203 /* Options valid for Samsung large page devices */ 204 #define NAND_SAMSUNG_LP_OPTIONS \ 205 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 206 207 /* Macros to identify the above */ 208 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 209 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 210 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 211 /* Large page NAND with SOFT_ECC should support subpage reads */ 212 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 213 && (chip->page_shift > 9)) 214 215 /* Mask to zero out the chip options, which come from the id table */ 216 #define NAND_CHIPOPTIONS_MSK 0x0000ffff 217 218 /* Non chip related options */ 219 /* This option skips the bbt scan during initialization. */ 220 #define NAND_SKIP_BBTSCAN 0x00010000 221 /* 222 * This option is defined if the board driver allocates its own buffers 223 * (e.g. because it needs them DMA-coherent). 224 */ 225 #define NAND_OWN_BUFFERS 0x00020000 226 /* Chip may not exist, so silence any errors in scan */ 227 #define NAND_SCAN_SILENT_NODEV 0x00040000 228 229 /* Options set by nand scan */ 230 /* Nand scan has allocated controller struct */ 231 #define NAND_CONTROLLER_ALLOC 0x80000000 232 233 /* Cell info constants */ 234 #define NAND_CI_CHIPNR_MSK 0x03 235 #define NAND_CI_CELLTYPE_MSK 0x0C 236 237 /* Keep gcc happy */ 238 struct nand_chip; 239 240 struct nand_onfi_params { 241 /* rev info and features block */ 242 /* 'O' 'N' 'F' 'I' */ 243 u8 sig[4]; 244 __le16 revision; 245 __le16 features; 246 __le16 opt_cmd; 247 u8 reserved[22]; 248 249 /* manufacturer information block */ 250 char manufacturer[12]; 251 char model[20]; 252 u8 jedec_id; 253 __le16 date_code; 254 u8 reserved2[13]; 255 256 /* memory organization block */ 257 __le32 byte_per_page; 258 __le16 spare_bytes_per_page; 259 __le32 data_bytes_per_ppage; 260 __le16 spare_bytes_per_ppage; 261 __le32 pages_per_block; 262 __le32 blocks_per_lun; 263 u8 lun_count; 264 u8 addr_cycles; 265 u8 bits_per_cell; 266 __le16 bb_per_lun; 267 __le16 block_endurance; 268 u8 guaranteed_good_blocks; 269 __le16 guaranteed_block_endurance; 270 u8 programs_per_page; 271 u8 ppage_attr; 272 u8 ecc_bits; 273 u8 interleaved_bits; 274 u8 interleaved_ops; 275 u8 reserved3[13]; 276 277 /* electrical parameter block */ 278 u8 io_pin_capacitance_max; 279 __le16 async_timing_mode; 280 __le16 program_cache_timing_mode; 281 __le16 t_prog; 282 __le16 t_bers; 283 __le16 t_r; 284 __le16 t_ccs; 285 __le16 src_sync_timing_mode; 286 __le16 src_ssync_features; 287 __le16 clk_pin_capacitance_typ; 288 __le16 io_pin_capacitance_typ; 289 __le16 input_pin_capacitance_typ; 290 u8 input_pin_capacitance_max; 291 u8 driver_strenght_support; 292 __le16 t_int_r; 293 __le16 t_ald; 294 u8 reserved4[7]; 295 296 /* vendor */ 297 u8 reserved5[90]; 298 299 __le16 crc; 300 } __attribute__((packed)); 301 302 #define ONFI_CRC_BASE 0x4F4E 303 304 /** 305 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 306 * @lock: protection lock 307 * @active: the mtd device which holds the controller currently 308 * @wq: wait queue to sleep on if a NAND operation is in 309 * progress used instead of the per chip wait queue 310 * when a hw controller is available. 311 */ 312 struct nand_hw_control { 313 spinlock_t lock; 314 struct nand_chip *active; 315 wait_queue_head_t wq; 316 }; 317 318 /** 319 * struct nand_ecc_ctrl - Control structure for ECC 320 * @mode: ECC mode 321 * @steps: number of ECC steps per page 322 * @size: data bytes per ECC step 323 * @bytes: ECC bytes per step 324 * @strength: max number of correctible bits per ECC step 325 * @total: total number of ECC bytes per page 326 * @prepad: padding information for syndrome based ECC generators 327 * @postpad: padding information for syndrome based ECC generators 328 * @layout: ECC layout control struct pointer 329 * @priv: pointer to private ECC control data 330 * @hwctl: function to control hardware ECC generator. Must only 331 * be provided if an hardware ECC is available 332 * @calculate: function for ECC calculation or readback from ECC hardware 333 * @correct: function for ECC correction, matching to ECC generator (sw/hw) 334 * @read_page_raw: function to read a raw page without ECC 335 * @write_page_raw: function to write a raw page without ECC 336 * @read_page: function to read a page according to the ECC generator 337 * requirements. 338 * @read_subpage: function to read parts of the page covered by ECC. 339 * @write_page: function to write a page according to the ECC generator 340 * requirements. 341 * @write_oob_raw: function to write chip OOB data without ECC 342 * @read_oob_raw: function to read chip OOB data without ECC 343 * @read_oob: function to read chip OOB data 344 * @write_oob: function to write chip OOB data 345 */ 346 struct nand_ecc_ctrl { 347 nand_ecc_modes_t mode; 348 int steps; 349 int size; 350 int bytes; 351 int total; 352 int strength; 353 int prepad; 354 int postpad; 355 struct nand_ecclayout *layout; 356 void *priv; 357 void (*hwctl)(struct mtd_info *mtd, int mode); 358 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 359 uint8_t *ecc_code); 360 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 361 uint8_t *calc_ecc); 362 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 363 uint8_t *buf, int oob_required, int page); 364 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 365 const uint8_t *buf, int oob_required); 366 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 367 uint8_t *buf, int oob_required, int page); 368 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 369 uint32_t offs, uint32_t len, uint8_t *buf); 370 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 371 const uint8_t *buf, int oob_required); 372 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 373 int page); 374 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 375 int page); 376 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 377 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 378 int page); 379 }; 380 381 /** 382 * struct nand_buffers - buffer structure for read/write 383 * @ecccalc: buffer for calculated ECC 384 * @ecccode: buffer for ECC read from flash 385 * @databuf: buffer for data - dynamically sized 386 * 387 * Do not change the order of buffers. databuf and oobrbuf must be in 388 * consecutive order. 389 */ 390 struct nand_buffers { 391 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 392 uint8_t ecccode[NAND_MAX_OOBSIZE]; 393 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 394 }; 395 396 /** 397 * struct nand_chip - NAND Private Flash Chip Data 398 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 399 * flash device 400 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 401 * flash device. 402 * @read_byte: [REPLACEABLE] read one byte from the chip 403 * @read_word: [REPLACEABLE] read one word from the chip 404 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 405 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 406 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip 407 * data. 408 * @select_chip: [REPLACEABLE] select chip nr 409 * @block_bad: [REPLACEABLE] check, if the block is bad 410 * @block_markbad: [REPLACEABLE] mark the block bad 411 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 412 * ALE/CLE/nCE. Also used to write command and address 413 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 414 * mtd->oobsize, mtd->writesize and so on. 415 * @id_data contains the 8 bytes values of NAND_CMD_READID. 416 * Return with the bus width. 417 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 418 * device ready/busy line. If set to NULL no access to 419 * ready/busy is available and the ready/busy information 420 * is read from the chip status register. 421 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 422 * commands to the chip. 423 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 424 * ready. 425 * @ecc: [BOARDSPECIFIC] ECC control structure 426 * @buffers: buffer structure for read/write 427 * @hwcontrol: platform-specific hardware control structure 428 * @erase_cmd: [INTERN] erase command write function, selectable due 429 * to AND support. 430 * @scan_bbt: [REPLACEABLE] function to scan bad block table 431 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 432 * data from array to read regs (tR). 433 * @state: [INTERN] the current state of the NAND device 434 * @oob_poi: "poison value buffer," used for laying out OOB data 435 * before writing 436 * @page_shift: [INTERN] number of address bits in a page (column 437 * address bits). 438 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 439 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 440 * @chip_shift: [INTERN] number of address bits in one chip 441 * @options: [BOARDSPECIFIC] various chip options. They can partly 442 * be set to inform nand_scan about special functionality. 443 * See the defines for further explanation. 444 * @bbt_options: [INTERN] bad block specific options. All options used 445 * here must come from bbm.h. By default, these options 446 * will be copied to the appropriate nand_bbt_descr's. 447 * @badblockpos: [INTERN] position of the bad block marker in the oob 448 * area. 449 * @badblockbits: [INTERN] minimum number of set bits in a good block's 450 * bad block marker position; i.e., BBM == 11110111b is 451 * not bad when badblockbits == 7 452 * @cellinfo: [INTERN] MLC/multichip data from chip ident 453 * @numchips: [INTERN] number of physical chips 454 * @chipsize: [INTERN] the size of one chip for multichip arrays 455 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 456 * @pagebuf: [INTERN] holds the pagenumber which is currently in 457 * data_buf. 458 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 459 * currently in data_buf. 460 * @subpagesize: [INTERN] holds the subpagesize 461 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 462 * non 0 if ONFI supported. 463 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 464 * supported, 0 otherwise. 465 * @ecclayout: [REPLACEABLE] the default ECC placement scheme 466 * @bbt: [INTERN] bad block table pointer 467 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 468 * lookup. 469 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 470 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 471 * bad block scan. 472 * @controller: [REPLACEABLE] a pointer to a hardware controller 473 * structure which is shared among multiple independent 474 * devices. 475 * @priv: [OPTIONAL] pointer to private chip data 476 * @errstat: [OPTIONAL] hardware specific function to perform 477 * additional error status checks (determine if errors are 478 * correctable). 479 * @write_page: [REPLACEABLE] High-level page write function 480 */ 481 482 struct nand_chip { 483 void __iomem *IO_ADDR_R; 484 void __iomem *IO_ADDR_W; 485 486 uint8_t (*read_byte)(struct mtd_info *mtd); 487 u16 (*read_word)(struct mtd_info *mtd); 488 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 489 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 490 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 491 void (*select_chip)(struct mtd_info *mtd, int chip); 492 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 493 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 494 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 495 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 496 u8 *id_data); 497 int (*dev_ready)(struct mtd_info *mtd); 498 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 499 int page_addr); 500 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 501 void (*erase_cmd)(struct mtd_info *mtd, int page); 502 int (*scan_bbt)(struct mtd_info *mtd); 503 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 504 int status, int page); 505 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 506 const uint8_t *buf, int oob_required, int page, 507 int cached, int raw); 508 509 int chip_delay; 510 unsigned int options; 511 unsigned int bbt_options; 512 513 int page_shift; 514 int phys_erase_shift; 515 int bbt_erase_shift; 516 int chip_shift; 517 int numchips; 518 uint64_t chipsize; 519 int pagemask; 520 int pagebuf; 521 unsigned int pagebuf_bitflips; 522 int subpagesize; 523 uint8_t cellinfo; 524 int badblockpos; 525 int badblockbits; 526 527 int onfi_version; 528 struct nand_onfi_params onfi_params; 529 530 flstate_t state; 531 532 uint8_t *oob_poi; 533 struct nand_hw_control *controller; 534 struct nand_ecclayout *ecclayout; 535 536 struct nand_ecc_ctrl ecc; 537 struct nand_buffers *buffers; 538 struct nand_hw_control hwcontrol; 539 540 uint8_t *bbt; 541 struct nand_bbt_descr *bbt_td; 542 struct nand_bbt_descr *bbt_md; 543 544 struct nand_bbt_descr *badblock_pattern; 545 546 void *priv; 547 }; 548 549 /* 550 * NAND Flash Manufacturer ID Codes 551 */ 552 #define NAND_MFR_TOSHIBA 0x98 553 #define NAND_MFR_SAMSUNG 0xec 554 #define NAND_MFR_FUJITSU 0x04 555 #define NAND_MFR_NATIONAL 0x8f 556 #define NAND_MFR_RENESAS 0x07 557 #define NAND_MFR_STMICRO 0x20 558 #define NAND_MFR_HYNIX 0xad 559 #define NAND_MFR_MICRON 0x2c 560 #define NAND_MFR_AMD 0x01 561 #define NAND_MFR_MACRONIX 0xc2 562 563 /** 564 * struct nand_flash_dev - NAND Flash Device ID Structure 565 * @name: Identify the device type 566 * @id: device ID code 567 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 568 * If the pagesize is 0, then the real pagesize 569 * and the eraseize are determined from the 570 * extended id bytes in the chip 571 * @erasesize: Size of an erase block in the flash device. 572 * @chipsize: Total chipsize in Mega Bytes 573 * @options: Bitfield to store chip relevant options 574 */ 575 struct nand_flash_dev { 576 char *name; 577 int id; 578 unsigned long pagesize; 579 unsigned long chipsize; 580 unsigned long erasesize; 581 unsigned long options; 582 }; 583 584 /** 585 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 586 * @name: Manufacturer name 587 * @id: manufacturer ID code of device. 588 */ 589 struct nand_manufacturers { 590 int id; 591 char *name; 592 }; 593 594 extern struct nand_flash_dev nand_flash_ids[]; 595 extern struct nand_manufacturers nand_manuf_ids[]; 596 597 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 598 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 599 extern int nand_default_bbt(struct mtd_info *mtd); 600 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 601 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 602 int allowbbt); 603 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 604 size_t *retlen, uint8_t *buf); 605 606 /** 607 * struct platform_nand_chip - chip level device structure 608 * @nr_chips: max. number of chips to scan for 609 * @chip_offset: chip number offset 610 * @nr_partitions: number of partitions pointed to by partitions (or zero) 611 * @partitions: mtd partition list 612 * @chip_delay: R/B delay value in us 613 * @options: Option flags, e.g. 16bit buswidth 614 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 615 * @ecclayout: ECC layout info structure 616 * @part_probe_types: NULL-terminated array of probe types 617 */ 618 struct platform_nand_chip { 619 int nr_chips; 620 int chip_offset; 621 int nr_partitions; 622 struct mtd_partition *partitions; 623 struct nand_ecclayout *ecclayout; 624 int chip_delay; 625 unsigned int options; 626 unsigned int bbt_options; 627 const char **part_probe_types; 628 }; 629 630 /* Keep gcc happy */ 631 struct platform_device; 632 633 /** 634 * struct platform_nand_ctrl - controller level device structure 635 * @probe: platform specific function to probe/setup hardware 636 * @remove: platform specific function to remove/teardown hardware 637 * @hwcontrol: platform specific hardware control structure 638 * @dev_ready: platform specific function to read ready/busy pin 639 * @select_chip: platform specific chip select function 640 * @cmd_ctrl: platform specific function for controlling 641 * ALE/CLE/nCE. Also used to write command and address 642 * @write_buf: platform specific function for write buffer 643 * @read_buf: platform specific function for read buffer 644 * @priv: private data to transport driver specific settings 645 * 646 * All fields are optional and depend on the hardware driver requirements 647 */ 648 struct platform_nand_ctrl { 649 int (*probe)(struct platform_device *pdev); 650 void (*remove)(struct platform_device *pdev); 651 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 652 int (*dev_ready)(struct mtd_info *mtd); 653 void (*select_chip)(struct mtd_info *mtd, int chip); 654 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 655 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 656 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 657 unsigned char (*read_byte)(struct mtd_info *mtd); 658 void *priv; 659 }; 660 661 /** 662 * struct platform_nand_data - container structure for platform-specific data 663 * @chip: chip level chip structure 664 * @ctrl: controller level device structure 665 */ 666 struct platform_nand_data { 667 struct platform_nand_chip chip; 668 struct platform_nand_ctrl ctrl; 669 }; 670 671 /* Some helpers to access the data structures */ 672 static inline 673 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 674 { 675 struct nand_chip *chip = mtd->priv; 676 677 return chip->priv; 678 } 679 680 #endif /* __LINUX_MTD_NAND_H */ 681