1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 /* Scan and identify a NAND device */ 30 extern int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 extern int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Free resources held by the NAND device */ 40 extern void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 extern void nand_wait_ready(struct mtd_info *mtd); 44 45 /* locks all blocks present in the device */ 46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 47 48 /* unlocks specified locked blocks */ 49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 50 51 /* The maximum number of NAND chips in an array */ 52 #define NAND_MAX_CHIPS 8 53 54 /* 55 * This constant declares the max. oobsize / page, which 56 * is supported now. If you add a chip with bigger oobsize/page 57 * adjust this accordingly. 58 */ 59 #define NAND_MAX_OOBSIZE 640 60 #define NAND_MAX_PAGESIZE 8192 61 62 /* 63 * Constants for hardware specific CLE/ALE/NCE function 64 * 65 * These are bits which can be or'ed to set/clear multiple 66 * bits in one go. 67 */ 68 /* Select the chip by setting nCE to low */ 69 #define NAND_NCE 0x01 70 /* Select the command latch by setting CLE to high */ 71 #define NAND_CLE 0x02 72 /* Select the address latch by setting ALE to high */ 73 #define NAND_ALE 0x04 74 75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 77 #define NAND_CTRL_CHANGE 0x80 78 79 /* 80 * Standard NAND flash commands 81 */ 82 #define NAND_CMD_READ0 0 83 #define NAND_CMD_READ1 1 84 #define NAND_CMD_RNDOUT 5 85 #define NAND_CMD_PAGEPROG 0x10 86 #define NAND_CMD_READOOB 0x50 87 #define NAND_CMD_ERASE1 0x60 88 #define NAND_CMD_STATUS 0x70 89 #define NAND_CMD_STATUS_MULTI 0x71 90 #define NAND_CMD_SEQIN 0x80 91 #define NAND_CMD_RNDIN 0x85 92 #define NAND_CMD_READID 0x90 93 #define NAND_CMD_ERASE2 0xd0 94 #define NAND_CMD_PARAM 0xec 95 #define NAND_CMD_GET_FEATURES 0xee 96 #define NAND_CMD_SET_FEATURES 0xef 97 #define NAND_CMD_RESET 0xff 98 99 #define NAND_CMD_LOCK 0x2a 100 #define NAND_CMD_UNLOCK1 0x23 101 #define NAND_CMD_UNLOCK2 0x24 102 103 /* Extended commands for large page devices */ 104 #define NAND_CMD_READSTART 0x30 105 #define NAND_CMD_RNDOUTSTART 0xE0 106 #define NAND_CMD_CACHEDPROG 0x15 107 108 /* Extended commands for AG-AND device */ 109 /* 110 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 111 * there is no way to distinguish that from NAND_CMD_READ0 112 * until the remaining sequence of commands has been completed 113 * so add a high order bit and mask it off in the command. 114 */ 115 #define NAND_CMD_DEPLETE1 0x100 116 #define NAND_CMD_DEPLETE2 0x38 117 #define NAND_CMD_STATUS_MULTI 0x71 118 #define NAND_CMD_STATUS_ERROR 0x72 119 /* multi-bank error status (banks 0-3) */ 120 #define NAND_CMD_STATUS_ERROR0 0x73 121 #define NAND_CMD_STATUS_ERROR1 0x74 122 #define NAND_CMD_STATUS_ERROR2 0x75 123 #define NAND_CMD_STATUS_ERROR3 0x76 124 #define NAND_CMD_STATUS_RESET 0x7f 125 #define NAND_CMD_STATUS_CLEAR 0xff 126 127 #define NAND_CMD_NONE -1 128 129 /* Status bits */ 130 #define NAND_STATUS_FAIL 0x01 131 #define NAND_STATUS_FAIL_N1 0x02 132 #define NAND_STATUS_TRUE_READY 0x20 133 #define NAND_STATUS_READY 0x40 134 #define NAND_STATUS_WP 0x80 135 136 /* 137 * Constants for ECC_MODES 138 */ 139 typedef enum { 140 NAND_ECC_NONE, 141 NAND_ECC_SOFT, 142 NAND_ECC_HW, 143 NAND_ECC_HW_SYNDROME, 144 NAND_ECC_HW_OOB_FIRST, 145 NAND_ECC_SOFT_BCH, 146 } nand_ecc_modes_t; 147 148 /* 149 * Constants for Hardware ECC 150 */ 151 /* Reset Hardware ECC for read */ 152 #define NAND_ECC_READ 0 153 /* Reset Hardware ECC for write */ 154 #define NAND_ECC_WRITE 1 155 /* Enable Hardware ECC before syndrome is read back from flash */ 156 #define NAND_ECC_READSYN 2 157 158 /* Bit mask for flags passed to do_nand_read_ecc */ 159 #define NAND_GET_DEVICE 0x80 160 161 162 /* 163 * Option constants for bizarre disfunctionality and real 164 * features. 165 */ 166 /* Buswidth is 16 bit */ 167 #define NAND_BUSWIDTH_16 0x00000002 168 /* Device supports partial programming without padding */ 169 #define NAND_NO_PADDING 0x00000004 170 /* Chip has cache program function */ 171 #define NAND_CACHEPRG 0x00000008 172 /* Chip has copy back function */ 173 #define NAND_COPYBACK 0x00000010 174 /* 175 * AND Chip which has 4 banks and a confusing page / block 176 * assignment. See Renesas datasheet for further information. 177 */ 178 #define NAND_IS_AND 0x00000020 179 /* 180 * Chip has a array of 4 pages which can be read without 181 * additional ready /busy waits. 182 */ 183 #define NAND_4PAGE_ARRAY 0x00000040 184 /* 185 * Chip requires that BBT is periodically rewritten to prevent 186 * bits from adjacent blocks from 'leaking' in altering data. 187 * This happens with the Renesas AG-AND chips, possibly others. 188 */ 189 #define BBT_AUTO_REFRESH 0x00000080 190 /* 191 * Chip requires ready check on read (for auto-incremented sequential read). 192 * True only for small page devices; large page devices do not support 193 * autoincrement. 194 */ 195 #define NAND_NEED_READRDY 0x00000100 196 197 /* Chip does not allow subpage writes */ 198 #define NAND_NO_SUBPAGE_WRITE 0x00000200 199 200 /* Device is one of 'new' xD cards that expose fake nand command set */ 201 #define NAND_BROKEN_XD 0x00000400 202 203 /* Device behaves just like nand, but is readonly */ 204 #define NAND_ROM 0x00000800 205 206 /* Device supports subpage reads */ 207 #define NAND_SUBPAGE_READ 0x00001000 208 209 /* Options valid for Samsung large page devices */ 210 #define NAND_SAMSUNG_LP_OPTIONS \ 211 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 212 213 /* Macros to identify the above */ 214 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 215 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 216 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 217 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 218 219 /* Non chip related options */ 220 /* This option skips the bbt scan during initialization. */ 221 #define NAND_SKIP_BBTSCAN 0x00010000 222 /* 223 * This option is defined if the board driver allocates its own buffers 224 * (e.g. because it needs them DMA-coherent). 225 */ 226 #define NAND_OWN_BUFFERS 0x00020000 227 /* Chip may not exist, so silence any errors in scan */ 228 #define NAND_SCAN_SILENT_NODEV 0x00040000 229 /* 230 * Autodetect nand buswidth with readid/onfi. 231 * This suppose the driver will configure the hardware in 8 bits mode 232 * when calling nand_scan_ident, and update its configuration 233 * before calling nand_scan_tail. 234 */ 235 #define NAND_BUSWIDTH_AUTO 0x00080000 236 237 /* Options set by nand scan */ 238 /* Nand scan has allocated controller struct */ 239 #define NAND_CONTROLLER_ALLOC 0x80000000 240 241 /* Cell info constants */ 242 #define NAND_CI_CHIPNR_MSK 0x03 243 #define NAND_CI_CELLTYPE_MSK 0x0C 244 245 /* Keep gcc happy */ 246 struct nand_chip; 247 248 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 249 #define ONFI_TIMING_MODE_0 (1 << 0) 250 #define ONFI_TIMING_MODE_1 (1 << 1) 251 #define ONFI_TIMING_MODE_2 (1 << 2) 252 #define ONFI_TIMING_MODE_3 (1 << 3) 253 #define ONFI_TIMING_MODE_4 (1 << 4) 254 #define ONFI_TIMING_MODE_5 (1 << 5) 255 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 256 257 /* ONFI feature address */ 258 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 259 260 /* ONFI subfeature parameters length */ 261 #define ONFI_SUBFEATURE_PARAM_LEN 4 262 263 struct nand_onfi_params { 264 /* rev info and features block */ 265 /* 'O' 'N' 'F' 'I' */ 266 u8 sig[4]; 267 __le16 revision; 268 __le16 features; 269 __le16 opt_cmd; 270 u8 reserved[22]; 271 272 /* manufacturer information block */ 273 char manufacturer[12]; 274 char model[20]; 275 u8 jedec_id; 276 __le16 date_code; 277 u8 reserved2[13]; 278 279 /* memory organization block */ 280 __le32 byte_per_page; 281 __le16 spare_bytes_per_page; 282 __le32 data_bytes_per_ppage; 283 __le16 spare_bytes_per_ppage; 284 __le32 pages_per_block; 285 __le32 blocks_per_lun; 286 u8 lun_count; 287 u8 addr_cycles; 288 u8 bits_per_cell; 289 __le16 bb_per_lun; 290 __le16 block_endurance; 291 u8 guaranteed_good_blocks; 292 __le16 guaranteed_block_endurance; 293 u8 programs_per_page; 294 u8 ppage_attr; 295 u8 ecc_bits; 296 u8 interleaved_bits; 297 u8 interleaved_ops; 298 u8 reserved3[13]; 299 300 /* electrical parameter block */ 301 u8 io_pin_capacitance_max; 302 __le16 async_timing_mode; 303 __le16 program_cache_timing_mode; 304 __le16 t_prog; 305 __le16 t_bers; 306 __le16 t_r; 307 __le16 t_ccs; 308 __le16 src_sync_timing_mode; 309 __le16 src_ssync_features; 310 __le16 clk_pin_capacitance_typ; 311 __le16 io_pin_capacitance_typ; 312 __le16 input_pin_capacitance_typ; 313 u8 input_pin_capacitance_max; 314 u8 driver_strenght_support; 315 __le16 t_int_r; 316 __le16 t_ald; 317 u8 reserved4[7]; 318 319 /* vendor */ 320 u8 reserved5[90]; 321 322 __le16 crc; 323 } __attribute__((packed)); 324 325 #define ONFI_CRC_BASE 0x4F4E 326 327 /** 328 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 329 * @lock: protection lock 330 * @active: the mtd device which holds the controller currently 331 * @wq: wait queue to sleep on if a NAND operation is in 332 * progress used instead of the per chip wait queue 333 * when a hw controller is available. 334 */ 335 struct nand_hw_control { 336 spinlock_t lock; 337 struct nand_chip *active; 338 wait_queue_head_t wq; 339 }; 340 341 /** 342 * struct nand_ecc_ctrl - Control structure for ECC 343 * @mode: ECC mode 344 * @steps: number of ECC steps per page 345 * @size: data bytes per ECC step 346 * @bytes: ECC bytes per step 347 * @strength: max number of correctible bits per ECC step 348 * @total: total number of ECC bytes per page 349 * @prepad: padding information for syndrome based ECC generators 350 * @postpad: padding information for syndrome based ECC generators 351 * @layout: ECC layout control struct pointer 352 * @priv: pointer to private ECC control data 353 * @hwctl: function to control hardware ECC generator. Must only 354 * be provided if an hardware ECC is available 355 * @calculate: function for ECC calculation or readback from ECC hardware 356 * @correct: function for ECC correction, matching to ECC generator (sw/hw) 357 * @read_page_raw: function to read a raw page without ECC 358 * @write_page_raw: function to write a raw page without ECC 359 * @read_page: function to read a page according to the ECC generator 360 * requirements; returns maximum number of bitflips corrected in 361 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 362 * @read_subpage: function to read parts of the page covered by ECC; 363 * returns same as read_page() 364 * @write_page: function to write a page according to the ECC generator 365 * requirements. 366 * @write_oob_raw: function to write chip OOB data without ECC 367 * @read_oob_raw: function to read chip OOB data without ECC 368 * @read_oob: function to read chip OOB data 369 * @write_oob: function to write chip OOB data 370 */ 371 struct nand_ecc_ctrl { 372 nand_ecc_modes_t mode; 373 int steps; 374 int size; 375 int bytes; 376 int total; 377 int strength; 378 int prepad; 379 int postpad; 380 struct nand_ecclayout *layout; 381 void *priv; 382 void (*hwctl)(struct mtd_info *mtd, int mode); 383 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 384 uint8_t *ecc_code); 385 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 386 uint8_t *calc_ecc); 387 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 388 uint8_t *buf, int oob_required, int page); 389 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 390 const uint8_t *buf, int oob_required); 391 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 392 uint8_t *buf, int oob_required, int page); 393 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 394 uint32_t offs, uint32_t len, uint8_t *buf); 395 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 396 const uint8_t *buf, int oob_required); 397 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 398 int page); 399 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 400 int page); 401 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 402 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 403 int page); 404 }; 405 406 /** 407 * struct nand_buffers - buffer structure for read/write 408 * @ecccalc: buffer for calculated ECC 409 * @ecccode: buffer for ECC read from flash 410 * @databuf: buffer for data - dynamically sized 411 * 412 * Do not change the order of buffers. databuf and oobrbuf must be in 413 * consecutive order. 414 */ 415 struct nand_buffers { 416 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 417 uint8_t ecccode[NAND_MAX_OOBSIZE]; 418 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 419 }; 420 421 /** 422 * struct nand_chip - NAND Private Flash Chip Data 423 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 424 * flash device 425 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 426 * flash device. 427 * @read_byte: [REPLACEABLE] read one byte from the chip 428 * @read_word: [REPLACEABLE] read one word from the chip 429 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 430 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 431 * @select_chip: [REPLACEABLE] select chip nr 432 * @block_bad: [REPLACEABLE] check, if the block is bad 433 * @block_markbad: [REPLACEABLE] mark the block bad 434 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 435 * ALE/CLE/nCE. Also used to write command and address 436 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 437 * mtd->oobsize, mtd->writesize and so on. 438 * @id_data contains the 8 bytes values of NAND_CMD_READID. 439 * Return with the bus width. 440 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 441 * device ready/busy line. If set to NULL no access to 442 * ready/busy is available and the ready/busy information 443 * is read from the chip status register. 444 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 445 * commands to the chip. 446 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 447 * ready. 448 * @ecc: [BOARDSPECIFIC] ECC control structure 449 * @buffers: buffer structure for read/write 450 * @hwcontrol: platform-specific hardware control structure 451 * @erase_cmd: [INTERN] erase command write function, selectable due 452 * to AND support. 453 * @scan_bbt: [REPLACEABLE] function to scan bad block table 454 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 455 * data from array to read regs (tR). 456 * @state: [INTERN] the current state of the NAND device 457 * @oob_poi: "poison value buffer," used for laying out OOB data 458 * before writing 459 * @page_shift: [INTERN] number of address bits in a page (column 460 * address bits). 461 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 462 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 463 * @chip_shift: [INTERN] number of address bits in one chip 464 * @options: [BOARDSPECIFIC] various chip options. They can partly 465 * be set to inform nand_scan about special functionality. 466 * See the defines for further explanation. 467 * @bbt_options: [INTERN] bad block specific options. All options used 468 * here must come from bbm.h. By default, these options 469 * will be copied to the appropriate nand_bbt_descr's. 470 * @badblockpos: [INTERN] position of the bad block marker in the oob 471 * area. 472 * @badblockbits: [INTERN] minimum number of set bits in a good block's 473 * bad block marker position; i.e., BBM == 11110111b is 474 * not bad when badblockbits == 7 475 * @cellinfo: [INTERN] MLC/multichip data from chip ident 476 * @numchips: [INTERN] number of physical chips 477 * @chipsize: [INTERN] the size of one chip for multichip arrays 478 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 479 * @pagebuf: [INTERN] holds the pagenumber which is currently in 480 * data_buf. 481 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 482 * currently in data_buf. 483 * @subpagesize: [INTERN] holds the subpagesize 484 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 485 * non 0 if ONFI supported. 486 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 487 * supported, 0 otherwise. 488 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 489 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 490 * @ecclayout: [REPLACEABLE] the default ECC placement scheme 491 * @bbt: [INTERN] bad block table pointer 492 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 493 * lookup. 494 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 495 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 496 * bad block scan. 497 * @controller: [REPLACEABLE] a pointer to a hardware controller 498 * structure which is shared among multiple independent 499 * devices. 500 * @priv: [OPTIONAL] pointer to private chip data 501 * @errstat: [OPTIONAL] hardware specific function to perform 502 * additional error status checks (determine if errors are 503 * correctable). 504 * @write_page: [REPLACEABLE] High-level page write function 505 */ 506 507 struct nand_chip { 508 void __iomem *IO_ADDR_R; 509 void __iomem *IO_ADDR_W; 510 511 uint8_t (*read_byte)(struct mtd_info *mtd); 512 u16 (*read_word)(struct mtd_info *mtd); 513 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 514 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 515 void (*select_chip)(struct mtd_info *mtd, int chip); 516 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 517 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 518 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 519 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 520 u8 *id_data); 521 int (*dev_ready)(struct mtd_info *mtd); 522 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 523 int page_addr); 524 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 525 void (*erase_cmd)(struct mtd_info *mtd, int page); 526 int (*scan_bbt)(struct mtd_info *mtd); 527 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 528 int status, int page); 529 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 530 const uint8_t *buf, int oob_required, int page, 531 int cached, int raw); 532 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 533 int feature_addr, uint8_t *subfeature_para); 534 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 535 int feature_addr, uint8_t *subfeature_para); 536 537 int chip_delay; 538 unsigned int options; 539 unsigned int bbt_options; 540 541 int page_shift; 542 int phys_erase_shift; 543 int bbt_erase_shift; 544 int chip_shift; 545 int numchips; 546 uint64_t chipsize; 547 int pagemask; 548 int pagebuf; 549 unsigned int pagebuf_bitflips; 550 int subpagesize; 551 uint8_t cellinfo; 552 int badblockpos; 553 int badblockbits; 554 555 int onfi_version; 556 struct nand_onfi_params onfi_params; 557 558 flstate_t state; 559 560 uint8_t *oob_poi; 561 struct nand_hw_control *controller; 562 struct nand_ecclayout *ecclayout; 563 564 struct nand_ecc_ctrl ecc; 565 struct nand_buffers *buffers; 566 struct nand_hw_control hwcontrol; 567 568 uint8_t *bbt; 569 struct nand_bbt_descr *bbt_td; 570 struct nand_bbt_descr *bbt_md; 571 572 struct nand_bbt_descr *badblock_pattern; 573 574 void *priv; 575 }; 576 577 /* 578 * NAND Flash Manufacturer ID Codes 579 */ 580 #define NAND_MFR_TOSHIBA 0x98 581 #define NAND_MFR_SAMSUNG 0xec 582 #define NAND_MFR_FUJITSU 0x04 583 #define NAND_MFR_NATIONAL 0x8f 584 #define NAND_MFR_RENESAS 0x07 585 #define NAND_MFR_STMICRO 0x20 586 #define NAND_MFR_HYNIX 0xad 587 #define NAND_MFR_MICRON 0x2c 588 #define NAND_MFR_AMD 0x01 589 #define NAND_MFR_MACRONIX 0xc2 590 #define NAND_MFR_EON 0x92 591 592 /** 593 * struct nand_flash_dev - NAND Flash Device ID Structure 594 * @name: Identify the device type 595 * @id: device ID code 596 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 597 * If the pagesize is 0, then the real pagesize 598 * and the eraseize are determined from the 599 * extended id bytes in the chip 600 * @erasesize: Size of an erase block in the flash device. 601 * @chipsize: Total chipsize in Mega Bytes 602 * @options: Bitfield to store chip relevant options 603 */ 604 struct nand_flash_dev { 605 char *name; 606 int id; 607 unsigned long pagesize; 608 unsigned long chipsize; 609 unsigned long erasesize; 610 unsigned long options; 611 }; 612 613 /** 614 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 615 * @name: Manufacturer name 616 * @id: manufacturer ID code of device. 617 */ 618 struct nand_manufacturers { 619 int id; 620 char *name; 621 }; 622 623 extern struct nand_flash_dev nand_flash_ids[]; 624 extern struct nand_manufacturers nand_manuf_ids[]; 625 626 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 627 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 628 extern int nand_default_bbt(struct mtd_info *mtd); 629 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 630 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 631 int allowbbt); 632 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 633 size_t *retlen, uint8_t *buf); 634 635 /** 636 * struct platform_nand_chip - chip level device structure 637 * @nr_chips: max. number of chips to scan for 638 * @chip_offset: chip number offset 639 * @nr_partitions: number of partitions pointed to by partitions (or zero) 640 * @partitions: mtd partition list 641 * @chip_delay: R/B delay value in us 642 * @options: Option flags, e.g. 16bit buswidth 643 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 644 * @ecclayout: ECC layout info structure 645 * @part_probe_types: NULL-terminated array of probe types 646 */ 647 struct platform_nand_chip { 648 int nr_chips; 649 int chip_offset; 650 int nr_partitions; 651 struct mtd_partition *partitions; 652 struct nand_ecclayout *ecclayout; 653 int chip_delay; 654 unsigned int options; 655 unsigned int bbt_options; 656 const char **part_probe_types; 657 }; 658 659 /* Keep gcc happy */ 660 struct platform_device; 661 662 /** 663 * struct platform_nand_ctrl - controller level device structure 664 * @probe: platform specific function to probe/setup hardware 665 * @remove: platform specific function to remove/teardown hardware 666 * @hwcontrol: platform specific hardware control structure 667 * @dev_ready: platform specific function to read ready/busy pin 668 * @select_chip: platform specific chip select function 669 * @cmd_ctrl: platform specific function for controlling 670 * ALE/CLE/nCE. Also used to write command and address 671 * @write_buf: platform specific function for write buffer 672 * @read_buf: platform specific function for read buffer 673 * @read_byte: platform specific function to read one byte from chip 674 * @priv: private data to transport driver specific settings 675 * 676 * All fields are optional and depend on the hardware driver requirements 677 */ 678 struct platform_nand_ctrl { 679 int (*probe)(struct platform_device *pdev); 680 void (*remove)(struct platform_device *pdev); 681 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 682 int (*dev_ready)(struct mtd_info *mtd); 683 void (*select_chip)(struct mtd_info *mtd, int chip); 684 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 685 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 686 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 687 unsigned char (*read_byte)(struct mtd_info *mtd); 688 void *priv; 689 }; 690 691 /** 692 * struct platform_nand_data - container structure for platform-specific data 693 * @chip: chip level chip structure 694 * @ctrl: controller level device structure 695 */ 696 struct platform_nand_data { 697 struct platform_nand_chip chip; 698 struct platform_nand_ctrl ctrl; 699 }; 700 701 /* Some helpers to access the data structures */ 702 static inline 703 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 704 { 705 struct nand_chip *chip = mtd->priv; 706 707 return chip->priv; 708 } 709 710 /* return the supported asynchronous timing mode. */ 711 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 712 { 713 if (!chip->onfi_version) 714 return ONFI_TIMING_MODE_UNKNOWN; 715 return le16_to_cpu(chip->onfi_params.async_timing_mode); 716 } 717 718 /* return the supported synchronous timing mode. */ 719 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 720 { 721 if (!chip->onfi_version) 722 return ONFI_TIMING_MODE_UNKNOWN; 723 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 724 } 725 726 #endif /* __LINUX_MTD_NAND_H */ 727