1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 struct device_node; 30 31 /* Scan and identify a NAND device */ 32 extern int nand_scan(struct mtd_info *mtd, int max_chips); 33 /* 34 * Separate phases of nand_scan(), allowing board driver to intervene 35 * and override command or ECC setup according to flash type. 36 */ 37 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 38 struct nand_flash_dev *table); 39 extern int nand_scan_tail(struct mtd_info *mtd); 40 41 /* Free resources held by the NAND device */ 42 extern void nand_release(struct mtd_info *mtd); 43 44 /* Internal helper for board drivers which need to override command function */ 45 extern void nand_wait_ready(struct mtd_info *mtd); 46 47 /* locks all blocks present in the device */ 48 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 49 50 /* unlocks specified locked blocks */ 51 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 52 53 /* The maximum number of NAND chips in an array */ 54 #define NAND_MAX_CHIPS 8 55 56 /* 57 * Constants for hardware specific CLE/ALE/NCE function 58 * 59 * These are bits which can be or'ed to set/clear multiple 60 * bits in one go. 61 */ 62 /* Select the chip by setting nCE to low */ 63 #define NAND_NCE 0x01 64 /* Select the command latch by setting CLE to high */ 65 #define NAND_CLE 0x02 66 /* Select the address latch by setting ALE to high */ 67 #define NAND_ALE 0x04 68 69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 71 #define NAND_CTRL_CHANGE 0x80 72 73 /* 74 * Standard NAND flash commands 75 */ 76 #define NAND_CMD_READ0 0 77 #define NAND_CMD_READ1 1 78 #define NAND_CMD_RNDOUT 5 79 #define NAND_CMD_PAGEPROG 0x10 80 #define NAND_CMD_READOOB 0x50 81 #define NAND_CMD_ERASE1 0x60 82 #define NAND_CMD_STATUS 0x70 83 #define NAND_CMD_SEQIN 0x80 84 #define NAND_CMD_RNDIN 0x85 85 #define NAND_CMD_READID 0x90 86 #define NAND_CMD_ERASE2 0xd0 87 #define NAND_CMD_PARAM 0xec 88 #define NAND_CMD_GET_FEATURES 0xee 89 #define NAND_CMD_SET_FEATURES 0xef 90 #define NAND_CMD_RESET 0xff 91 92 #define NAND_CMD_LOCK 0x2a 93 #define NAND_CMD_UNLOCK1 0x23 94 #define NAND_CMD_UNLOCK2 0x24 95 96 /* Extended commands for large page devices */ 97 #define NAND_CMD_READSTART 0x30 98 #define NAND_CMD_RNDOUTSTART 0xE0 99 #define NAND_CMD_CACHEDPROG 0x15 100 101 #define NAND_CMD_NONE -1 102 103 /* Status bits */ 104 #define NAND_STATUS_FAIL 0x01 105 #define NAND_STATUS_FAIL_N1 0x02 106 #define NAND_STATUS_TRUE_READY 0x20 107 #define NAND_STATUS_READY 0x40 108 #define NAND_STATUS_WP 0x80 109 110 /* 111 * Constants for ECC_MODES 112 */ 113 typedef enum { 114 NAND_ECC_NONE, 115 NAND_ECC_SOFT, 116 NAND_ECC_HW, 117 NAND_ECC_HW_SYNDROME, 118 NAND_ECC_HW_OOB_FIRST, 119 } nand_ecc_modes_t; 120 121 enum nand_ecc_algo { 122 NAND_ECC_UNKNOWN, 123 NAND_ECC_HAMMING, 124 NAND_ECC_BCH, 125 }; 126 127 /* 128 * Constants for Hardware ECC 129 */ 130 /* Reset Hardware ECC for read */ 131 #define NAND_ECC_READ 0 132 /* Reset Hardware ECC for write */ 133 #define NAND_ECC_WRITE 1 134 /* Enable Hardware ECC before syndrome is read back from flash */ 135 #define NAND_ECC_READSYN 2 136 137 /* 138 * Enable generic NAND 'page erased' check. This check is only done when 139 * ecc.correct() returns -EBADMSG. 140 * Set this flag if your implementation does not fix bitflips in erased 141 * pages and you want to rely on the default implementation. 142 */ 143 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 144 145 /* Bit mask for flags passed to do_nand_read_ecc */ 146 #define NAND_GET_DEVICE 0x80 147 148 149 /* 150 * Option constants for bizarre disfunctionality and real 151 * features. 152 */ 153 /* Buswidth is 16 bit */ 154 #define NAND_BUSWIDTH_16 0x00000002 155 /* Chip has cache program function */ 156 #define NAND_CACHEPRG 0x00000008 157 /* 158 * Chip requires ready check on read (for auto-incremented sequential read). 159 * True only for small page devices; large page devices do not support 160 * autoincrement. 161 */ 162 #define NAND_NEED_READRDY 0x00000100 163 164 /* Chip does not allow subpage writes */ 165 #define NAND_NO_SUBPAGE_WRITE 0x00000200 166 167 /* Device is one of 'new' xD cards that expose fake nand command set */ 168 #define NAND_BROKEN_XD 0x00000400 169 170 /* Device behaves just like nand, but is readonly */ 171 #define NAND_ROM 0x00000800 172 173 /* Device supports subpage reads */ 174 #define NAND_SUBPAGE_READ 0x00001000 175 176 /* 177 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 178 * patterns. 179 */ 180 #define NAND_NEED_SCRAMBLING 0x00002000 181 182 /* Options valid for Samsung large page devices */ 183 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 184 185 /* Macros to identify the above */ 186 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 187 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 188 189 /* Non chip related options */ 190 /* This option skips the bbt scan during initialization. */ 191 #define NAND_SKIP_BBTSCAN 0x00010000 192 /* 193 * This option is defined if the board driver allocates its own buffers 194 * (e.g. because it needs them DMA-coherent). 195 */ 196 #define NAND_OWN_BUFFERS 0x00020000 197 /* Chip may not exist, so silence any errors in scan */ 198 #define NAND_SCAN_SILENT_NODEV 0x00040000 199 /* 200 * Autodetect nand buswidth with readid/onfi. 201 * This suppose the driver will configure the hardware in 8 bits mode 202 * when calling nand_scan_ident, and update its configuration 203 * before calling nand_scan_tail. 204 */ 205 #define NAND_BUSWIDTH_AUTO 0x00080000 206 /* 207 * This option could be defined by controller drivers to protect against 208 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 209 */ 210 #define NAND_USE_BOUNCE_BUFFER 0x00100000 211 212 /* Options set by nand scan */ 213 /* Nand scan has allocated controller struct */ 214 #define NAND_CONTROLLER_ALLOC 0x80000000 215 216 /* Cell info constants */ 217 #define NAND_CI_CHIPNR_MSK 0x03 218 #define NAND_CI_CELLTYPE_MSK 0x0C 219 #define NAND_CI_CELLTYPE_SHIFT 2 220 221 /* Keep gcc happy */ 222 struct nand_chip; 223 224 /* ONFI features */ 225 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 226 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 227 228 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 229 #define ONFI_TIMING_MODE_0 (1 << 0) 230 #define ONFI_TIMING_MODE_1 (1 << 1) 231 #define ONFI_TIMING_MODE_2 (1 << 2) 232 #define ONFI_TIMING_MODE_3 (1 << 3) 233 #define ONFI_TIMING_MODE_4 (1 << 4) 234 #define ONFI_TIMING_MODE_5 (1 << 5) 235 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 236 237 /* ONFI feature address */ 238 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 239 240 /* Vendor-specific feature address (Micron) */ 241 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 242 243 /* ONFI subfeature parameters length */ 244 #define ONFI_SUBFEATURE_PARAM_LEN 4 245 246 /* ONFI optional commands SET/GET FEATURES supported? */ 247 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 248 249 struct nand_onfi_params { 250 /* rev info and features block */ 251 /* 'O' 'N' 'F' 'I' */ 252 u8 sig[4]; 253 __le16 revision; 254 __le16 features; 255 __le16 opt_cmd; 256 u8 reserved0[2]; 257 __le16 ext_param_page_length; /* since ONFI 2.1 */ 258 u8 num_of_param_pages; /* since ONFI 2.1 */ 259 u8 reserved1[17]; 260 261 /* manufacturer information block */ 262 char manufacturer[12]; 263 char model[20]; 264 u8 jedec_id; 265 __le16 date_code; 266 u8 reserved2[13]; 267 268 /* memory organization block */ 269 __le32 byte_per_page; 270 __le16 spare_bytes_per_page; 271 __le32 data_bytes_per_ppage; 272 __le16 spare_bytes_per_ppage; 273 __le32 pages_per_block; 274 __le32 blocks_per_lun; 275 u8 lun_count; 276 u8 addr_cycles; 277 u8 bits_per_cell; 278 __le16 bb_per_lun; 279 __le16 block_endurance; 280 u8 guaranteed_good_blocks; 281 __le16 guaranteed_block_endurance; 282 u8 programs_per_page; 283 u8 ppage_attr; 284 u8 ecc_bits; 285 u8 interleaved_bits; 286 u8 interleaved_ops; 287 u8 reserved3[13]; 288 289 /* electrical parameter block */ 290 u8 io_pin_capacitance_max; 291 __le16 async_timing_mode; 292 __le16 program_cache_timing_mode; 293 __le16 t_prog; 294 __le16 t_bers; 295 __le16 t_r; 296 __le16 t_ccs; 297 __le16 src_sync_timing_mode; 298 u8 src_ssync_features; 299 __le16 clk_pin_capacitance_typ; 300 __le16 io_pin_capacitance_typ; 301 __le16 input_pin_capacitance_typ; 302 u8 input_pin_capacitance_max; 303 u8 driver_strength_support; 304 __le16 t_int_r; 305 __le16 t_adl; 306 u8 reserved4[8]; 307 308 /* vendor */ 309 __le16 vendor_revision; 310 u8 vendor[88]; 311 312 __le16 crc; 313 } __packed; 314 315 #define ONFI_CRC_BASE 0x4F4E 316 317 /* Extended ECC information Block Definition (since ONFI 2.1) */ 318 struct onfi_ext_ecc_info { 319 u8 ecc_bits; 320 u8 codeword_size; 321 __le16 bb_per_lun; 322 __le16 block_endurance; 323 u8 reserved[2]; 324 } __packed; 325 326 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 327 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 328 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 329 struct onfi_ext_section { 330 u8 type; 331 u8 length; 332 } __packed; 333 334 #define ONFI_EXT_SECTION_MAX 8 335 336 /* Extended Parameter Page Definition (since ONFI 2.1) */ 337 struct onfi_ext_param_page { 338 __le16 crc; 339 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 340 u8 reserved0[10]; 341 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 342 343 /* 344 * The actual size of the Extended Parameter Page is in 345 * @ext_param_page_length of nand_onfi_params{}. 346 * The following are the variable length sections. 347 * So we do not add any fields below. Please see the ONFI spec. 348 */ 349 } __packed; 350 351 struct nand_onfi_vendor_micron { 352 u8 two_plane_read; 353 u8 read_cache; 354 u8 read_unique_id; 355 u8 dq_imped; 356 u8 dq_imped_num_settings; 357 u8 dq_imped_feat_addr; 358 u8 rb_pulldown_strength; 359 u8 rb_pulldown_strength_feat_addr; 360 u8 rb_pulldown_strength_num_settings; 361 u8 otp_mode; 362 u8 otp_page_start; 363 u8 otp_data_prot_addr; 364 u8 otp_num_pages; 365 u8 otp_feat_addr; 366 u8 read_retry_options; 367 u8 reserved[72]; 368 u8 param_revision; 369 } __packed; 370 371 struct jedec_ecc_info { 372 u8 ecc_bits; 373 u8 codeword_size; 374 __le16 bb_per_lun; 375 __le16 block_endurance; 376 u8 reserved[2]; 377 } __packed; 378 379 /* JEDEC features */ 380 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 381 382 struct nand_jedec_params { 383 /* rev info and features block */ 384 /* 'J' 'E' 'S' 'D' */ 385 u8 sig[4]; 386 __le16 revision; 387 __le16 features; 388 u8 opt_cmd[3]; 389 __le16 sec_cmd; 390 u8 num_of_param_pages; 391 u8 reserved0[18]; 392 393 /* manufacturer information block */ 394 char manufacturer[12]; 395 char model[20]; 396 u8 jedec_id[6]; 397 u8 reserved1[10]; 398 399 /* memory organization block */ 400 __le32 byte_per_page; 401 __le16 spare_bytes_per_page; 402 u8 reserved2[6]; 403 __le32 pages_per_block; 404 __le32 blocks_per_lun; 405 u8 lun_count; 406 u8 addr_cycles; 407 u8 bits_per_cell; 408 u8 programs_per_page; 409 u8 multi_plane_addr; 410 u8 multi_plane_op_attr; 411 u8 reserved3[38]; 412 413 /* electrical parameter block */ 414 __le16 async_sdr_speed_grade; 415 __le16 toggle_ddr_speed_grade; 416 __le16 sync_ddr_speed_grade; 417 u8 async_sdr_features; 418 u8 toggle_ddr_features; 419 u8 sync_ddr_features; 420 __le16 t_prog; 421 __le16 t_bers; 422 __le16 t_r; 423 __le16 t_r_multi_plane; 424 __le16 t_ccs; 425 __le16 io_pin_capacitance_typ; 426 __le16 input_pin_capacitance_typ; 427 __le16 clk_pin_capacitance_typ; 428 u8 driver_strength_support; 429 __le16 t_adl; 430 u8 reserved4[36]; 431 432 /* ECC and endurance block */ 433 u8 guaranteed_good_blocks; 434 __le16 guaranteed_block_endurance; 435 struct jedec_ecc_info ecc_info[4]; 436 u8 reserved5[29]; 437 438 /* reserved */ 439 u8 reserved6[148]; 440 441 /* vendor */ 442 __le16 vendor_rev_num; 443 u8 reserved7[88]; 444 445 /* CRC for Parameter Page */ 446 __le16 crc; 447 } __packed; 448 449 /** 450 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 451 * @lock: protection lock 452 * @active: the mtd device which holds the controller currently 453 * @wq: wait queue to sleep on if a NAND operation is in 454 * progress used instead of the per chip wait queue 455 * when a hw controller is available. 456 */ 457 struct nand_hw_control { 458 spinlock_t lock; 459 struct nand_chip *active; 460 wait_queue_head_t wq; 461 }; 462 463 /** 464 * struct nand_ecc_ctrl - Control structure for ECC 465 * @mode: ECC mode 466 * @algo: ECC algorithm 467 * @steps: number of ECC steps per page 468 * @size: data bytes per ECC step 469 * @bytes: ECC bytes per step 470 * @strength: max number of correctible bits per ECC step 471 * @total: total number of ECC bytes per page 472 * @prepad: padding information for syndrome based ECC generators 473 * @postpad: padding information for syndrome based ECC generators 474 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 475 * @priv: pointer to private ECC control data 476 * @hwctl: function to control hardware ECC generator. Must only 477 * be provided if an hardware ECC is available 478 * @calculate: function for ECC calculation or readback from ECC hardware 479 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 480 * Should return a positive number representing the number of 481 * corrected bitflips, -EBADMSG if the number of bitflips exceed 482 * ECC strength, or any other error code if the error is not 483 * directly related to correction. 484 * If -EBADMSG is returned the input buffers should be left 485 * untouched. 486 * @read_page_raw: function to read a raw page without ECC. This function 487 * should hide the specific layout used by the ECC 488 * controller and always return contiguous in-band and 489 * out-of-band data even if they're not stored 490 * contiguously on the NAND chip (e.g. 491 * NAND_ECC_HW_SYNDROME interleaves in-band and 492 * out-of-band data). 493 * @write_page_raw: function to write a raw page without ECC. This function 494 * should hide the specific layout used by the ECC 495 * controller and consider the passed data as contiguous 496 * in-band and out-of-band data. ECC controller is 497 * responsible for doing the appropriate transformations 498 * to adapt to its specific layout (e.g. 499 * NAND_ECC_HW_SYNDROME interleaves in-band and 500 * out-of-band data). 501 * @read_page: function to read a page according to the ECC generator 502 * requirements; returns maximum number of bitflips corrected in 503 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 504 * @read_subpage: function to read parts of the page covered by ECC; 505 * returns same as read_page() 506 * @write_subpage: function to write parts of the page covered by ECC. 507 * @write_page: function to write a page according to the ECC generator 508 * requirements. 509 * @write_oob_raw: function to write chip OOB data without ECC 510 * @read_oob_raw: function to read chip OOB data without ECC 511 * @read_oob: function to read chip OOB data 512 * @write_oob: function to write chip OOB data 513 */ 514 struct nand_ecc_ctrl { 515 nand_ecc_modes_t mode; 516 enum nand_ecc_algo algo; 517 int steps; 518 int size; 519 int bytes; 520 int total; 521 int strength; 522 int prepad; 523 int postpad; 524 unsigned int options; 525 void *priv; 526 void (*hwctl)(struct mtd_info *mtd, int mode); 527 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 528 uint8_t *ecc_code); 529 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 530 uint8_t *calc_ecc); 531 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 532 uint8_t *buf, int oob_required, int page); 533 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 534 const uint8_t *buf, int oob_required, int page); 535 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 536 uint8_t *buf, int oob_required, int page); 537 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 538 uint32_t offs, uint32_t len, uint8_t *buf, int page); 539 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 540 uint32_t offset, uint32_t data_len, 541 const uint8_t *data_buf, int oob_required, int page); 542 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 543 const uint8_t *buf, int oob_required, int page); 544 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 545 int page); 546 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 547 int page); 548 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 549 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 550 int page); 551 }; 552 553 /** 554 * struct nand_buffers - buffer structure for read/write 555 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 556 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 557 * @databuf: buffer pointer for data, size is (page size + oobsize). 558 * 559 * Do not change the order of buffers. databuf and oobrbuf must be in 560 * consecutive order. 561 */ 562 struct nand_buffers { 563 uint8_t *ecccalc; 564 uint8_t *ecccode; 565 uint8_t *databuf; 566 }; 567 568 /** 569 * struct nand_chip - NAND Private Flash Chip Data 570 * @mtd: MTD device registered to the MTD framework 571 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 572 * flash device 573 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 574 * flash device. 575 * @read_byte: [REPLACEABLE] read one byte from the chip 576 * @read_word: [REPLACEABLE] read one word from the chip 577 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 578 * low 8 I/O lines 579 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 580 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 581 * @select_chip: [REPLACEABLE] select chip nr 582 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 583 * @block_markbad: [REPLACEABLE] mark a block bad 584 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 585 * ALE/CLE/nCE. Also used to write command and address 586 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 587 * device ready/busy line. If set to NULL no access to 588 * ready/busy is available and the ready/busy information 589 * is read from the chip status register. 590 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 591 * commands to the chip. 592 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 593 * ready. 594 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 595 * setting the read-retry mode. Mostly needed for MLC NAND. 596 * @ecc: [BOARDSPECIFIC] ECC control structure 597 * @buffers: buffer structure for read/write 598 * @hwcontrol: platform-specific hardware control structure 599 * @erase: [REPLACEABLE] erase function 600 * @scan_bbt: [REPLACEABLE] function to scan bad block table 601 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 602 * data from array to read regs (tR). 603 * @state: [INTERN] the current state of the NAND device 604 * @oob_poi: "poison value buffer," used for laying out OOB data 605 * before writing 606 * @page_shift: [INTERN] number of address bits in a page (column 607 * address bits). 608 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 609 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 610 * @chip_shift: [INTERN] number of address bits in one chip 611 * @options: [BOARDSPECIFIC] various chip options. They can partly 612 * be set to inform nand_scan about special functionality. 613 * See the defines for further explanation. 614 * @bbt_options: [INTERN] bad block specific options. All options used 615 * here must come from bbm.h. By default, these options 616 * will be copied to the appropriate nand_bbt_descr's. 617 * @badblockpos: [INTERN] position of the bad block marker in the oob 618 * area. 619 * @badblockbits: [INTERN] minimum number of set bits in a good block's 620 * bad block marker position; i.e., BBM == 11110111b is 621 * not bad when badblockbits == 7 622 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 623 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 624 * Minimum amount of bit errors per @ecc_step_ds guaranteed 625 * to be correctable. If unknown, set to zero. 626 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 627 * also from the datasheet. It is the recommended ECC step 628 * size, if known; if unknown, set to zero. 629 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 630 * either deduced from the datasheet if the NAND 631 * chip is not ONFI compliant or set to 0 if it is 632 * (an ONFI chip is always configured in mode 0 633 * after a NAND reset) 634 * @numchips: [INTERN] number of physical chips 635 * @chipsize: [INTERN] the size of one chip for multichip arrays 636 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 637 * @pagebuf: [INTERN] holds the pagenumber which is currently in 638 * data_buf. 639 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 640 * currently in data_buf. 641 * @subpagesize: [INTERN] holds the subpagesize 642 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 643 * non 0 if ONFI supported. 644 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 645 * non 0 if JEDEC supported. 646 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 647 * supported, 0 otherwise. 648 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 649 * supported, 0 otherwise. 650 * @read_retries: [INTERN] the number of read retry modes supported 651 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 652 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 653 * @bbt: [INTERN] bad block table pointer 654 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 655 * lookup. 656 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 657 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 658 * bad block scan. 659 * @controller: [REPLACEABLE] a pointer to a hardware controller 660 * structure which is shared among multiple independent 661 * devices. 662 * @priv: [OPTIONAL] pointer to private chip data 663 * @errstat: [OPTIONAL] hardware specific function to perform 664 * additional error status checks (determine if errors are 665 * correctable). 666 * @write_page: [REPLACEABLE] High-level page write function 667 */ 668 669 struct nand_chip { 670 struct mtd_info mtd; 671 void __iomem *IO_ADDR_R; 672 void __iomem *IO_ADDR_W; 673 674 uint8_t (*read_byte)(struct mtd_info *mtd); 675 u16 (*read_word)(struct mtd_info *mtd); 676 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 677 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 678 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 679 void (*select_chip)(struct mtd_info *mtd, int chip); 680 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 681 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 682 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 683 int (*dev_ready)(struct mtd_info *mtd); 684 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 685 int page_addr); 686 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 687 int (*erase)(struct mtd_info *mtd, int page); 688 int (*scan_bbt)(struct mtd_info *mtd); 689 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 690 int status, int page); 691 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 692 uint32_t offset, int data_len, const uint8_t *buf, 693 int oob_required, int page, int cached, int raw); 694 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 695 int feature_addr, uint8_t *subfeature_para); 696 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 697 int feature_addr, uint8_t *subfeature_para); 698 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 699 700 int chip_delay; 701 unsigned int options; 702 unsigned int bbt_options; 703 704 int page_shift; 705 int phys_erase_shift; 706 int bbt_erase_shift; 707 int chip_shift; 708 int numchips; 709 uint64_t chipsize; 710 int pagemask; 711 int pagebuf; 712 unsigned int pagebuf_bitflips; 713 int subpagesize; 714 uint8_t bits_per_cell; 715 uint16_t ecc_strength_ds; 716 uint16_t ecc_step_ds; 717 int onfi_timing_mode_default; 718 int badblockpos; 719 int badblockbits; 720 721 int onfi_version; 722 int jedec_version; 723 union { 724 struct nand_onfi_params onfi_params; 725 struct nand_jedec_params jedec_params; 726 }; 727 728 int read_retries; 729 730 flstate_t state; 731 732 uint8_t *oob_poi; 733 struct nand_hw_control *controller; 734 735 struct nand_ecc_ctrl ecc; 736 struct nand_buffers *buffers; 737 struct nand_hw_control hwcontrol; 738 739 uint8_t *bbt; 740 struct nand_bbt_descr *bbt_td; 741 struct nand_bbt_descr *bbt_md; 742 743 struct nand_bbt_descr *badblock_pattern; 744 745 void *priv; 746 }; 747 748 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 749 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 750 751 static inline void nand_set_flash_node(struct nand_chip *chip, 752 struct device_node *np) 753 { 754 mtd_set_of_node(&chip->mtd, np); 755 } 756 757 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 758 { 759 return mtd_get_of_node(&chip->mtd); 760 } 761 762 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 763 { 764 return container_of(mtd, struct nand_chip, mtd); 765 } 766 767 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 768 { 769 return &chip->mtd; 770 } 771 772 static inline void *nand_get_controller_data(struct nand_chip *chip) 773 { 774 return chip->priv; 775 } 776 777 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 778 { 779 chip->priv = priv; 780 } 781 782 /* 783 * NAND Flash Manufacturer ID Codes 784 */ 785 #define NAND_MFR_TOSHIBA 0x98 786 #define NAND_MFR_ESMT 0xc8 787 #define NAND_MFR_SAMSUNG 0xec 788 #define NAND_MFR_FUJITSU 0x04 789 #define NAND_MFR_NATIONAL 0x8f 790 #define NAND_MFR_RENESAS 0x07 791 #define NAND_MFR_STMICRO 0x20 792 #define NAND_MFR_HYNIX 0xad 793 #define NAND_MFR_MICRON 0x2c 794 #define NAND_MFR_AMD 0x01 795 #define NAND_MFR_MACRONIX 0xc2 796 #define NAND_MFR_EON 0x92 797 #define NAND_MFR_SANDISK 0x45 798 #define NAND_MFR_INTEL 0x89 799 #define NAND_MFR_ATO 0x9b 800 801 /* The maximum expected count of bytes in the NAND ID sequence */ 802 #define NAND_MAX_ID_LEN 8 803 804 /* 805 * A helper for defining older NAND chips where the second ID byte fully 806 * defined the chip, including the geometry (chip size, eraseblock size, page 807 * size). All these chips have 512 bytes NAND page size. 808 */ 809 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 810 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 811 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 812 813 /* 814 * A helper for defining newer chips which report their page size and 815 * eraseblock size via the extended ID bytes. 816 * 817 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 818 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 819 * device ID now only represented a particular total chip size (and voltage, 820 * buswidth), and the page size, eraseblock size, and OOB size could vary while 821 * using the same device ID. 822 */ 823 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 824 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 825 .options = (opts) } 826 827 #define NAND_ECC_INFO(_strength, _step) \ 828 { .strength_ds = (_strength), .step_ds = (_step) } 829 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 830 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 831 832 /** 833 * struct nand_flash_dev - NAND Flash Device ID Structure 834 * @name: a human-readable name of the NAND chip 835 * @dev_id: the device ID (the second byte of the full chip ID array) 836 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 837 * memory address as @id[0]) 838 * @dev_id: device ID part of the full chip ID array (refers the same memory 839 * address as @id[1]) 840 * @id: full device ID array 841 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 842 * well as the eraseblock size) is determined from the extended NAND 843 * chip ID array) 844 * @chipsize: total chip size in MiB 845 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 846 * @options: stores various chip bit options 847 * @id_len: The valid length of the @id. 848 * @oobsize: OOB size 849 * @ecc: ECC correctability and step information from the datasheet. 850 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 851 * @ecc_strength_ds in nand_chip{}. 852 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 853 * @ecc_step_ds in nand_chip{}, also from the datasheet. 854 * For example, the "4bit ECC for each 512Byte" can be set with 855 * NAND_ECC_INFO(4, 512). 856 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 857 * reset. Should be deduced from timings described 858 * in the datasheet. 859 * 860 */ 861 struct nand_flash_dev { 862 char *name; 863 union { 864 struct { 865 uint8_t mfr_id; 866 uint8_t dev_id; 867 }; 868 uint8_t id[NAND_MAX_ID_LEN]; 869 }; 870 unsigned int pagesize; 871 unsigned int chipsize; 872 unsigned int erasesize; 873 unsigned int options; 874 uint16_t id_len; 875 uint16_t oobsize; 876 struct { 877 uint16_t strength_ds; 878 uint16_t step_ds; 879 } ecc; 880 int onfi_timing_mode_default; 881 }; 882 883 /** 884 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 885 * @name: Manufacturer name 886 * @id: manufacturer ID code of device. 887 */ 888 struct nand_manufacturers { 889 int id; 890 char *name; 891 }; 892 893 extern struct nand_flash_dev nand_flash_ids[]; 894 extern struct nand_manufacturers nand_manuf_ids[]; 895 896 extern int nand_default_bbt(struct mtd_info *mtd); 897 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 898 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 899 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 900 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 901 int allowbbt); 902 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 903 size_t *retlen, uint8_t *buf); 904 905 /** 906 * struct platform_nand_chip - chip level device structure 907 * @nr_chips: max. number of chips to scan for 908 * @chip_offset: chip number offset 909 * @nr_partitions: number of partitions pointed to by partitions (or zero) 910 * @partitions: mtd partition list 911 * @chip_delay: R/B delay value in us 912 * @options: Option flags, e.g. 16bit buswidth 913 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 914 * @part_probe_types: NULL-terminated array of probe types 915 */ 916 struct platform_nand_chip { 917 int nr_chips; 918 int chip_offset; 919 int nr_partitions; 920 struct mtd_partition *partitions; 921 int chip_delay; 922 unsigned int options; 923 unsigned int bbt_options; 924 const char **part_probe_types; 925 }; 926 927 /* Keep gcc happy */ 928 struct platform_device; 929 930 /** 931 * struct platform_nand_ctrl - controller level device structure 932 * @probe: platform specific function to probe/setup hardware 933 * @remove: platform specific function to remove/teardown hardware 934 * @hwcontrol: platform specific hardware control structure 935 * @dev_ready: platform specific function to read ready/busy pin 936 * @select_chip: platform specific chip select function 937 * @cmd_ctrl: platform specific function for controlling 938 * ALE/CLE/nCE. Also used to write command and address 939 * @write_buf: platform specific function for write buffer 940 * @read_buf: platform specific function for read buffer 941 * @read_byte: platform specific function to read one byte from chip 942 * @priv: private data to transport driver specific settings 943 * 944 * All fields are optional and depend on the hardware driver requirements 945 */ 946 struct platform_nand_ctrl { 947 int (*probe)(struct platform_device *pdev); 948 void (*remove)(struct platform_device *pdev); 949 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 950 int (*dev_ready)(struct mtd_info *mtd); 951 void (*select_chip)(struct mtd_info *mtd, int chip); 952 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 953 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 954 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 955 unsigned char (*read_byte)(struct mtd_info *mtd); 956 void *priv; 957 }; 958 959 /** 960 * struct platform_nand_data - container structure for platform-specific data 961 * @chip: chip level chip structure 962 * @ctrl: controller level device structure 963 */ 964 struct platform_nand_data { 965 struct platform_nand_chip chip; 966 struct platform_nand_ctrl ctrl; 967 }; 968 969 /* return the supported features. */ 970 static inline int onfi_feature(struct nand_chip *chip) 971 { 972 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 973 } 974 975 /* return the supported asynchronous timing mode. */ 976 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 977 { 978 if (!chip->onfi_version) 979 return ONFI_TIMING_MODE_UNKNOWN; 980 return le16_to_cpu(chip->onfi_params.async_timing_mode); 981 } 982 983 /* return the supported synchronous timing mode. */ 984 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 985 { 986 if (!chip->onfi_version) 987 return ONFI_TIMING_MODE_UNKNOWN; 988 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 989 } 990 991 /* 992 * Check if it is a SLC nand. 993 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 994 * We do not distinguish the MLC and TLC now. 995 */ 996 static inline bool nand_is_slc(struct nand_chip *chip) 997 { 998 return chip->bits_per_cell == 1; 999 } 1000 1001 /** 1002 * Check if the opcode's address should be sent only on the lower 8 bits 1003 * @command: opcode to check 1004 */ 1005 static inline int nand_opcode_8bits(unsigned int command) 1006 { 1007 switch (command) { 1008 case NAND_CMD_READID: 1009 case NAND_CMD_PARAM: 1010 case NAND_CMD_GET_FEATURES: 1011 case NAND_CMD_SET_FEATURES: 1012 return 1; 1013 default: 1014 break; 1015 } 1016 return 0; 1017 } 1018 1019 /* return the supported JEDEC features. */ 1020 static inline int jedec_feature(struct nand_chip *chip) 1021 { 1022 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1023 : 0; 1024 } 1025 1026 /* 1027 * struct nand_sdr_timings - SDR NAND chip timings 1028 * 1029 * This struct defines the timing requirements of a SDR NAND chip. 1030 * These informations can be found in every NAND datasheets and the timings 1031 * meaning are described in the ONFI specifications: 1032 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 1033 * Parameters) 1034 * 1035 * All these timings are expressed in picoseconds. 1036 */ 1037 1038 struct nand_sdr_timings { 1039 u32 tALH_min; 1040 u32 tADL_min; 1041 u32 tALS_min; 1042 u32 tAR_min; 1043 u32 tCEA_max; 1044 u32 tCEH_min; 1045 u32 tCH_min; 1046 u32 tCHZ_max; 1047 u32 tCLH_min; 1048 u32 tCLR_min; 1049 u32 tCLS_min; 1050 u32 tCOH_min; 1051 u32 tCS_min; 1052 u32 tDH_min; 1053 u32 tDS_min; 1054 u32 tFEAT_max; 1055 u32 tIR_min; 1056 u32 tITC_max; 1057 u32 tRC_min; 1058 u32 tREA_max; 1059 u32 tREH_min; 1060 u32 tRHOH_min; 1061 u32 tRHW_min; 1062 u32 tRHZ_max; 1063 u32 tRLOH_min; 1064 u32 tRP_min; 1065 u32 tRR_min; 1066 u64 tRST_max; 1067 u32 tWB_max; 1068 u32 tWC_min; 1069 u32 tWH_min; 1070 u32 tWHR_min; 1071 u32 tWP_min; 1072 u32 tWW_min; 1073 }; 1074 1075 /* get timing characteristics from ONFI timing mode. */ 1076 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1077 1078 int nand_check_erased_ecc_chunk(void *data, int datalen, 1079 void *ecc, int ecclen, 1080 void *extraoob, int extraooblen, 1081 int threshold); 1082 1083 /* Default write_oob implementation */ 1084 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1085 1086 /* Default write_oob syndrome implementation */ 1087 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1088 int page); 1089 1090 /* Default read_oob implementation */ 1091 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1092 1093 /* Default read_oob syndrome implementation */ 1094 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1095 int page); 1096 #endif /* __LINUX_MTD_NAND_H */ 1097