1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <[email protected]> 5 * Steven J. Hill <[email protected]> 6 * Thomas Gleixner <[email protected]> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include <linux/wait.h> 22 #include <linux/spinlock.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/flashchip.h> 25 #include <linux/mtd/bbm.h> 26 27 struct mtd_info; 28 struct nand_flash_dev; 29 struct device_node; 30 31 /* Scan and identify a NAND device */ 32 int nand_scan(struct mtd_info *mtd, int max_chips); 33 /* 34 * Separate phases of nand_scan(), allowing board driver to intervene 35 * and override command or ECC setup according to flash type. 36 */ 37 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 38 struct nand_flash_dev *table); 39 int nand_scan_tail(struct mtd_info *mtd); 40 41 /* Unregister the MTD device and free resources held by the NAND device */ 42 void nand_release(struct mtd_info *mtd); 43 44 /* Internal helper for board drivers which need to override command function */ 45 void nand_wait_ready(struct mtd_info *mtd); 46 47 /* locks all blocks present in the device */ 48 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 49 50 /* unlocks specified locked blocks */ 51 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 52 53 /* The maximum number of NAND chips in an array */ 54 #define NAND_MAX_CHIPS 8 55 56 /* 57 * Constants for hardware specific CLE/ALE/NCE function 58 * 59 * These are bits which can be or'ed to set/clear multiple 60 * bits in one go. 61 */ 62 /* Select the chip by setting nCE to low */ 63 #define NAND_NCE 0x01 64 /* Select the command latch by setting CLE to high */ 65 #define NAND_CLE 0x02 66 /* Select the address latch by setting ALE to high */ 67 #define NAND_ALE 0x04 68 69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 71 #define NAND_CTRL_CHANGE 0x80 72 73 /* 74 * Standard NAND flash commands 75 */ 76 #define NAND_CMD_READ0 0 77 #define NAND_CMD_READ1 1 78 #define NAND_CMD_RNDOUT 5 79 #define NAND_CMD_PAGEPROG 0x10 80 #define NAND_CMD_READOOB 0x50 81 #define NAND_CMD_ERASE1 0x60 82 #define NAND_CMD_STATUS 0x70 83 #define NAND_CMD_SEQIN 0x80 84 #define NAND_CMD_RNDIN 0x85 85 #define NAND_CMD_READID 0x90 86 #define NAND_CMD_ERASE2 0xd0 87 #define NAND_CMD_PARAM 0xec 88 #define NAND_CMD_GET_FEATURES 0xee 89 #define NAND_CMD_SET_FEATURES 0xef 90 #define NAND_CMD_RESET 0xff 91 92 #define NAND_CMD_LOCK 0x2a 93 #define NAND_CMD_UNLOCK1 0x23 94 #define NAND_CMD_UNLOCK2 0x24 95 96 /* Extended commands for large page devices */ 97 #define NAND_CMD_READSTART 0x30 98 #define NAND_CMD_RNDOUTSTART 0xE0 99 #define NAND_CMD_CACHEDPROG 0x15 100 101 #define NAND_CMD_NONE -1 102 103 /* Status bits */ 104 #define NAND_STATUS_FAIL 0x01 105 #define NAND_STATUS_FAIL_N1 0x02 106 #define NAND_STATUS_TRUE_READY 0x20 107 #define NAND_STATUS_READY 0x40 108 #define NAND_STATUS_WP 0x80 109 110 #define NAND_DATA_IFACE_CHECK_ONLY -1 111 112 /* 113 * Constants for ECC_MODES 114 */ 115 typedef enum { 116 NAND_ECC_NONE, 117 NAND_ECC_SOFT, 118 NAND_ECC_HW, 119 NAND_ECC_HW_SYNDROME, 120 NAND_ECC_HW_OOB_FIRST, 121 NAND_ECC_ON_DIE, 122 } nand_ecc_modes_t; 123 124 enum nand_ecc_algo { 125 NAND_ECC_UNKNOWN, 126 NAND_ECC_HAMMING, 127 NAND_ECC_BCH, 128 }; 129 130 /* 131 * Constants for Hardware ECC 132 */ 133 /* Reset Hardware ECC for read */ 134 #define NAND_ECC_READ 0 135 /* Reset Hardware ECC for write */ 136 #define NAND_ECC_WRITE 1 137 /* Enable Hardware ECC before syndrome is read back from flash */ 138 #define NAND_ECC_READSYN 2 139 140 /* 141 * Enable generic NAND 'page erased' check. This check is only done when 142 * ecc.correct() returns -EBADMSG. 143 * Set this flag if your implementation does not fix bitflips in erased 144 * pages and you want to rely on the default implementation. 145 */ 146 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 147 #define NAND_ECC_MAXIMIZE BIT(1) 148 /* 149 * If your controller already sends the required NAND commands when 150 * reading or writing a page, then the framework is not supposed to 151 * send READ0 and SEQIN/PAGEPROG respectively. 152 */ 153 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 154 155 /* Bit mask for flags passed to do_nand_read_ecc */ 156 #define NAND_GET_DEVICE 0x80 157 158 159 /* 160 * Option constants for bizarre disfunctionality and real 161 * features. 162 */ 163 /* Buswidth is 16 bit */ 164 #define NAND_BUSWIDTH_16 0x00000002 165 /* Chip has cache program function */ 166 #define NAND_CACHEPRG 0x00000008 167 /* 168 * Chip requires ready check on read (for auto-incremented sequential read). 169 * True only for small page devices; large page devices do not support 170 * autoincrement. 171 */ 172 #define NAND_NEED_READRDY 0x00000100 173 174 /* Chip does not allow subpage writes */ 175 #define NAND_NO_SUBPAGE_WRITE 0x00000200 176 177 /* Device is one of 'new' xD cards that expose fake nand command set */ 178 #define NAND_BROKEN_XD 0x00000400 179 180 /* Device behaves just like nand, but is readonly */ 181 #define NAND_ROM 0x00000800 182 183 /* Device supports subpage reads */ 184 #define NAND_SUBPAGE_READ 0x00001000 185 186 /* 187 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 188 * patterns. 189 */ 190 #define NAND_NEED_SCRAMBLING 0x00002000 191 192 /* Options valid for Samsung large page devices */ 193 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 194 195 /* Macros to identify the above */ 196 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 197 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 198 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 199 200 /* Non chip related options */ 201 /* This option skips the bbt scan during initialization. */ 202 #define NAND_SKIP_BBTSCAN 0x00010000 203 /* 204 * This option is defined if the board driver allocates its own buffers 205 * (e.g. because it needs them DMA-coherent). 206 */ 207 #define NAND_OWN_BUFFERS 0x00020000 208 /* Chip may not exist, so silence any errors in scan */ 209 #define NAND_SCAN_SILENT_NODEV 0x00040000 210 /* 211 * Autodetect nand buswidth with readid/onfi. 212 * This suppose the driver will configure the hardware in 8 bits mode 213 * when calling nand_scan_ident, and update its configuration 214 * before calling nand_scan_tail. 215 */ 216 #define NAND_BUSWIDTH_AUTO 0x00080000 217 /* 218 * This option could be defined by controller drivers to protect against 219 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 220 */ 221 #define NAND_USE_BOUNCE_BUFFER 0x00100000 222 223 /* 224 * In case your controller is implementing ->cmd_ctrl() and is relying on the 225 * default ->cmdfunc() implementation, you may want to let the core handle the 226 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is 227 * requested. 228 * If your controller already takes care of this delay, you don't need to set 229 * this flag. 230 */ 231 #define NAND_WAIT_TCCS 0x00200000 232 233 /* Options set by nand scan */ 234 /* Nand scan has allocated controller struct */ 235 #define NAND_CONTROLLER_ALLOC 0x80000000 236 237 /* Cell info constants */ 238 #define NAND_CI_CHIPNR_MSK 0x03 239 #define NAND_CI_CELLTYPE_MSK 0x0C 240 #define NAND_CI_CELLTYPE_SHIFT 2 241 242 /* Keep gcc happy */ 243 struct nand_chip; 244 245 /* ONFI features */ 246 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 247 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 248 249 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 250 #define ONFI_TIMING_MODE_0 (1 << 0) 251 #define ONFI_TIMING_MODE_1 (1 << 1) 252 #define ONFI_TIMING_MODE_2 (1 << 2) 253 #define ONFI_TIMING_MODE_3 (1 << 3) 254 #define ONFI_TIMING_MODE_4 (1 << 4) 255 #define ONFI_TIMING_MODE_5 (1 << 5) 256 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 257 258 /* ONFI feature address */ 259 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 260 261 /* Vendor-specific feature address (Micron) */ 262 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 263 #define ONFI_FEATURE_ON_DIE_ECC 0x90 264 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) 265 266 /* ONFI subfeature parameters length */ 267 #define ONFI_SUBFEATURE_PARAM_LEN 4 268 269 /* ONFI optional commands SET/GET FEATURES supported? */ 270 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 271 272 struct nand_onfi_params { 273 /* rev info and features block */ 274 /* 'O' 'N' 'F' 'I' */ 275 u8 sig[4]; 276 __le16 revision; 277 __le16 features; 278 __le16 opt_cmd; 279 u8 reserved0[2]; 280 __le16 ext_param_page_length; /* since ONFI 2.1 */ 281 u8 num_of_param_pages; /* since ONFI 2.1 */ 282 u8 reserved1[17]; 283 284 /* manufacturer information block */ 285 char manufacturer[12]; 286 char model[20]; 287 u8 jedec_id; 288 __le16 date_code; 289 u8 reserved2[13]; 290 291 /* memory organization block */ 292 __le32 byte_per_page; 293 __le16 spare_bytes_per_page; 294 __le32 data_bytes_per_ppage; 295 __le16 spare_bytes_per_ppage; 296 __le32 pages_per_block; 297 __le32 blocks_per_lun; 298 u8 lun_count; 299 u8 addr_cycles; 300 u8 bits_per_cell; 301 __le16 bb_per_lun; 302 __le16 block_endurance; 303 u8 guaranteed_good_blocks; 304 __le16 guaranteed_block_endurance; 305 u8 programs_per_page; 306 u8 ppage_attr; 307 u8 ecc_bits; 308 u8 interleaved_bits; 309 u8 interleaved_ops; 310 u8 reserved3[13]; 311 312 /* electrical parameter block */ 313 u8 io_pin_capacitance_max; 314 __le16 async_timing_mode; 315 __le16 program_cache_timing_mode; 316 __le16 t_prog; 317 __le16 t_bers; 318 __le16 t_r; 319 __le16 t_ccs; 320 __le16 src_sync_timing_mode; 321 u8 src_ssync_features; 322 __le16 clk_pin_capacitance_typ; 323 __le16 io_pin_capacitance_typ; 324 __le16 input_pin_capacitance_typ; 325 u8 input_pin_capacitance_max; 326 u8 driver_strength_support; 327 __le16 t_int_r; 328 __le16 t_adl; 329 u8 reserved4[8]; 330 331 /* vendor */ 332 __le16 vendor_revision; 333 u8 vendor[88]; 334 335 __le16 crc; 336 } __packed; 337 338 #define ONFI_CRC_BASE 0x4F4E 339 340 /* Extended ECC information Block Definition (since ONFI 2.1) */ 341 struct onfi_ext_ecc_info { 342 u8 ecc_bits; 343 u8 codeword_size; 344 __le16 bb_per_lun; 345 __le16 block_endurance; 346 u8 reserved[2]; 347 } __packed; 348 349 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 350 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 351 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 352 struct onfi_ext_section { 353 u8 type; 354 u8 length; 355 } __packed; 356 357 #define ONFI_EXT_SECTION_MAX 8 358 359 /* Extended Parameter Page Definition (since ONFI 2.1) */ 360 struct onfi_ext_param_page { 361 __le16 crc; 362 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 363 u8 reserved0[10]; 364 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 365 366 /* 367 * The actual size of the Extended Parameter Page is in 368 * @ext_param_page_length of nand_onfi_params{}. 369 * The following are the variable length sections. 370 * So we do not add any fields below. Please see the ONFI spec. 371 */ 372 } __packed; 373 374 struct jedec_ecc_info { 375 u8 ecc_bits; 376 u8 codeword_size; 377 __le16 bb_per_lun; 378 __le16 block_endurance; 379 u8 reserved[2]; 380 } __packed; 381 382 /* JEDEC features */ 383 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 384 385 struct nand_jedec_params { 386 /* rev info and features block */ 387 /* 'J' 'E' 'S' 'D' */ 388 u8 sig[4]; 389 __le16 revision; 390 __le16 features; 391 u8 opt_cmd[3]; 392 __le16 sec_cmd; 393 u8 num_of_param_pages; 394 u8 reserved0[18]; 395 396 /* manufacturer information block */ 397 char manufacturer[12]; 398 char model[20]; 399 u8 jedec_id[6]; 400 u8 reserved1[10]; 401 402 /* memory organization block */ 403 __le32 byte_per_page; 404 __le16 spare_bytes_per_page; 405 u8 reserved2[6]; 406 __le32 pages_per_block; 407 __le32 blocks_per_lun; 408 u8 lun_count; 409 u8 addr_cycles; 410 u8 bits_per_cell; 411 u8 programs_per_page; 412 u8 multi_plane_addr; 413 u8 multi_plane_op_attr; 414 u8 reserved3[38]; 415 416 /* electrical parameter block */ 417 __le16 async_sdr_speed_grade; 418 __le16 toggle_ddr_speed_grade; 419 __le16 sync_ddr_speed_grade; 420 u8 async_sdr_features; 421 u8 toggle_ddr_features; 422 u8 sync_ddr_features; 423 __le16 t_prog; 424 __le16 t_bers; 425 __le16 t_r; 426 __le16 t_r_multi_plane; 427 __le16 t_ccs; 428 __le16 io_pin_capacitance_typ; 429 __le16 input_pin_capacitance_typ; 430 __le16 clk_pin_capacitance_typ; 431 u8 driver_strength_support; 432 __le16 t_adl; 433 u8 reserved4[36]; 434 435 /* ECC and endurance block */ 436 u8 guaranteed_good_blocks; 437 __le16 guaranteed_block_endurance; 438 struct jedec_ecc_info ecc_info[4]; 439 u8 reserved5[29]; 440 441 /* reserved */ 442 u8 reserved6[148]; 443 444 /* vendor */ 445 __le16 vendor_rev_num; 446 u8 reserved7[88]; 447 448 /* CRC for Parameter Page */ 449 __le16 crc; 450 } __packed; 451 452 /** 453 * struct nand_id - NAND id structure 454 * @data: buffer containing the id bytes. Currently 8 bytes large, but can 455 * be extended if required. 456 * @len: ID length. 457 */ 458 struct nand_id { 459 u8 data[8]; 460 int len; 461 }; 462 463 /** 464 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 465 * @lock: protection lock 466 * @active: the mtd device which holds the controller currently 467 * @wq: wait queue to sleep on if a NAND operation is in 468 * progress used instead of the per chip wait queue 469 * when a hw controller is available. 470 */ 471 struct nand_hw_control { 472 spinlock_t lock; 473 struct nand_chip *active; 474 wait_queue_head_t wq; 475 }; 476 477 static inline void nand_hw_control_init(struct nand_hw_control *nfc) 478 { 479 nfc->active = NULL; 480 spin_lock_init(&nfc->lock); 481 init_waitqueue_head(&nfc->wq); 482 } 483 484 /** 485 * struct nand_ecc_step_info - ECC step information of ECC engine 486 * @stepsize: data bytes per ECC step 487 * @strengths: array of supported strengths 488 * @nstrengths: number of supported strengths 489 */ 490 struct nand_ecc_step_info { 491 int stepsize; 492 const int *strengths; 493 int nstrengths; 494 }; 495 496 /** 497 * struct nand_ecc_caps - capability of ECC engine 498 * @stepinfos: array of ECC step information 499 * @nstepinfos: number of ECC step information 500 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 501 */ 502 struct nand_ecc_caps { 503 const struct nand_ecc_step_info *stepinfos; 504 int nstepinfos; 505 int (*calc_ecc_bytes)(int step_size, int strength); 506 }; 507 508 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 509 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 510 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 511 static const struct nand_ecc_step_info __name##_stepinfo = { \ 512 .stepsize = __step, \ 513 .strengths = __name##_strengths, \ 514 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 515 }; \ 516 static const struct nand_ecc_caps __name = { \ 517 .stepinfos = &__name##_stepinfo, \ 518 .nstepinfos = 1, \ 519 .calc_ecc_bytes = __calc, \ 520 } 521 522 /** 523 * struct nand_ecc_ctrl - Control structure for ECC 524 * @mode: ECC mode 525 * @algo: ECC algorithm 526 * @steps: number of ECC steps per page 527 * @size: data bytes per ECC step 528 * @bytes: ECC bytes per step 529 * @strength: max number of correctible bits per ECC step 530 * @total: total number of ECC bytes per page 531 * @prepad: padding information for syndrome based ECC generators 532 * @postpad: padding information for syndrome based ECC generators 533 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 534 * @priv: pointer to private ECC control data 535 * @hwctl: function to control hardware ECC generator. Must only 536 * be provided if an hardware ECC is available 537 * @calculate: function for ECC calculation or readback from ECC hardware 538 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 539 * Should return a positive number representing the number of 540 * corrected bitflips, -EBADMSG if the number of bitflips exceed 541 * ECC strength, or any other error code if the error is not 542 * directly related to correction. 543 * If -EBADMSG is returned the input buffers should be left 544 * untouched. 545 * @read_page_raw: function to read a raw page without ECC. This function 546 * should hide the specific layout used by the ECC 547 * controller and always return contiguous in-band and 548 * out-of-band data even if they're not stored 549 * contiguously on the NAND chip (e.g. 550 * NAND_ECC_HW_SYNDROME interleaves in-band and 551 * out-of-band data). 552 * @write_page_raw: function to write a raw page without ECC. This function 553 * should hide the specific layout used by the ECC 554 * controller and consider the passed data as contiguous 555 * in-band and out-of-band data. ECC controller is 556 * responsible for doing the appropriate transformations 557 * to adapt to its specific layout (e.g. 558 * NAND_ECC_HW_SYNDROME interleaves in-band and 559 * out-of-band data). 560 * @read_page: function to read a page according to the ECC generator 561 * requirements; returns maximum number of bitflips corrected in 562 * any single ECC step, -EIO hw error 563 * @read_subpage: function to read parts of the page covered by ECC; 564 * returns same as read_page() 565 * @write_subpage: function to write parts of the page covered by ECC. 566 * @write_page: function to write a page according to the ECC generator 567 * requirements. 568 * @write_oob_raw: function to write chip OOB data without ECC 569 * @read_oob_raw: function to read chip OOB data without ECC 570 * @read_oob: function to read chip OOB data 571 * @write_oob: function to write chip OOB data 572 */ 573 struct nand_ecc_ctrl { 574 nand_ecc_modes_t mode; 575 enum nand_ecc_algo algo; 576 int steps; 577 int size; 578 int bytes; 579 int total; 580 int strength; 581 int prepad; 582 int postpad; 583 unsigned int options; 584 void *priv; 585 void (*hwctl)(struct mtd_info *mtd, int mode); 586 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 587 uint8_t *ecc_code); 588 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 589 uint8_t *calc_ecc); 590 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 591 uint8_t *buf, int oob_required, int page); 592 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 593 const uint8_t *buf, int oob_required, int page); 594 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 595 uint8_t *buf, int oob_required, int page); 596 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 597 uint32_t offs, uint32_t len, uint8_t *buf, int page); 598 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 599 uint32_t offset, uint32_t data_len, 600 const uint8_t *data_buf, int oob_required, int page); 601 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 602 const uint8_t *buf, int oob_required, int page); 603 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 604 int page); 605 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 606 int page); 607 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 608 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 609 int page); 610 }; 611 612 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 613 { 614 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 615 } 616 617 /** 618 * struct nand_buffers - buffer structure for read/write 619 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 620 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 621 * @databuf: buffer pointer for data, size is (page size + oobsize). 622 * 623 * Do not change the order of buffers. databuf and oobrbuf must be in 624 * consecutive order. 625 */ 626 struct nand_buffers { 627 uint8_t *ecccalc; 628 uint8_t *ecccode; 629 uint8_t *databuf; 630 }; 631 632 /** 633 * struct nand_sdr_timings - SDR NAND chip timings 634 * 635 * This struct defines the timing requirements of a SDR NAND chip. 636 * These information can be found in every NAND datasheets and the timings 637 * meaning are described in the ONFI specifications: 638 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 639 * Parameters) 640 * 641 * All these timings are expressed in picoseconds. 642 * 643 * @tBERS_max: Block erase time 644 * @tCCS_min: Change column setup time 645 * @tPROG_max: Page program time 646 * @tR_max: Page read time 647 * @tALH_min: ALE hold time 648 * @tADL_min: ALE to data loading time 649 * @tALS_min: ALE setup time 650 * @tAR_min: ALE to RE# delay 651 * @tCEA_max: CE# access time 652 * @tCEH_min: CE# high hold time 653 * @tCH_min: CE# hold time 654 * @tCHZ_max: CE# high to output hi-Z 655 * @tCLH_min: CLE hold time 656 * @tCLR_min: CLE to RE# delay 657 * @tCLS_min: CLE setup time 658 * @tCOH_min: CE# high to output hold 659 * @tCS_min: CE# setup time 660 * @tDH_min: Data hold time 661 * @tDS_min: Data setup time 662 * @tFEAT_max: Busy time for Set Features and Get Features 663 * @tIR_min: Output hi-Z to RE# low 664 * @tITC_max: Interface and Timing Mode Change time 665 * @tRC_min: RE# cycle time 666 * @tREA_max: RE# access time 667 * @tREH_min: RE# high hold time 668 * @tRHOH_min: RE# high to output hold 669 * @tRHW_min: RE# high to WE# low 670 * @tRHZ_max: RE# high to output hi-Z 671 * @tRLOH_min: RE# low to output hold 672 * @tRP_min: RE# pulse width 673 * @tRR_min: Ready to RE# low (data only) 674 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 675 * rising edge of R/B#. 676 * @tWB_max: WE# high to SR[6] low 677 * @tWC_min: WE# cycle time 678 * @tWH_min: WE# high hold time 679 * @tWHR_min: WE# high to RE# low 680 * @tWP_min: WE# pulse width 681 * @tWW_min: WP# transition to WE# low 682 */ 683 struct nand_sdr_timings { 684 u32 tBERS_max; 685 u32 tCCS_min; 686 u32 tPROG_max; 687 u32 tR_max; 688 u32 tALH_min; 689 u32 tADL_min; 690 u32 tALS_min; 691 u32 tAR_min; 692 u32 tCEA_max; 693 u32 tCEH_min; 694 u32 tCH_min; 695 u32 tCHZ_max; 696 u32 tCLH_min; 697 u32 tCLR_min; 698 u32 tCLS_min; 699 u32 tCOH_min; 700 u32 tCS_min; 701 u32 tDH_min; 702 u32 tDS_min; 703 u32 tFEAT_max; 704 u32 tIR_min; 705 u32 tITC_max; 706 u32 tRC_min; 707 u32 tREA_max; 708 u32 tREH_min; 709 u32 tRHOH_min; 710 u32 tRHW_min; 711 u32 tRHZ_max; 712 u32 tRLOH_min; 713 u32 tRP_min; 714 u32 tRR_min; 715 u64 tRST_max; 716 u32 tWB_max; 717 u32 tWC_min; 718 u32 tWH_min; 719 u32 tWHR_min; 720 u32 tWP_min; 721 u32 tWW_min; 722 }; 723 724 /** 725 * enum nand_data_interface_type - NAND interface timing type 726 * @NAND_SDR_IFACE: Single Data Rate interface 727 */ 728 enum nand_data_interface_type { 729 NAND_SDR_IFACE, 730 }; 731 732 /** 733 * struct nand_data_interface - NAND interface timing 734 * @type: type of the timing 735 * @timings: The timing, type according to @type 736 */ 737 struct nand_data_interface { 738 enum nand_data_interface_type type; 739 union { 740 struct nand_sdr_timings sdr; 741 } timings; 742 }; 743 744 /** 745 * nand_get_sdr_timings - get SDR timing from data interface 746 * @conf: The data interface 747 */ 748 static inline const struct nand_sdr_timings * 749 nand_get_sdr_timings(const struct nand_data_interface *conf) 750 { 751 if (conf->type != NAND_SDR_IFACE) 752 return ERR_PTR(-EINVAL); 753 754 return &conf->timings.sdr; 755 } 756 757 /** 758 * struct nand_manufacturer_ops - NAND Manufacturer operations 759 * @detect: detect the NAND memory organization and capabilities 760 * @init: initialize all vendor specific fields (like the ->read_retry() 761 * implementation) if any. 762 * @cleanup: the ->init() function may have allocated resources, ->cleanup() 763 * is here to let vendor specific code release those resources. 764 */ 765 struct nand_manufacturer_ops { 766 void (*detect)(struct nand_chip *chip); 767 int (*init)(struct nand_chip *chip); 768 void (*cleanup)(struct nand_chip *chip); 769 }; 770 771 /** 772 * struct nand_chip - NAND Private Flash Chip Data 773 * @mtd: MTD device registered to the MTD framework 774 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 775 * flash device 776 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 777 * flash device. 778 * @read_byte: [REPLACEABLE] read one byte from the chip 779 * @read_word: [REPLACEABLE] read one word from the chip 780 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 781 * low 8 I/O lines 782 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 783 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 784 * @select_chip: [REPLACEABLE] select chip nr 785 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 786 * @block_markbad: [REPLACEABLE] mark a block bad 787 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 788 * ALE/CLE/nCE. Also used to write command and address 789 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 790 * device ready/busy line. If set to NULL no access to 791 * ready/busy is available and the ready/busy information 792 * is read from the chip status register. 793 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 794 * commands to the chip. 795 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 796 * ready. 797 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 798 * setting the read-retry mode. Mostly needed for MLC NAND. 799 * @ecc: [BOARDSPECIFIC] ECC control structure 800 * @buffers: buffer structure for read/write 801 * @buf_align: minimum buffer alignment required by a platform 802 * @hwcontrol: platform-specific hardware control structure 803 * @erase: [REPLACEABLE] erase function 804 * @scan_bbt: [REPLACEABLE] function to scan bad block table 805 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 806 * data from array to read regs (tR). 807 * @state: [INTERN] the current state of the NAND device 808 * @oob_poi: "poison value buffer," used for laying out OOB data 809 * before writing 810 * @page_shift: [INTERN] number of address bits in a page (column 811 * address bits). 812 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 813 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 814 * @chip_shift: [INTERN] number of address bits in one chip 815 * @options: [BOARDSPECIFIC] various chip options. They can partly 816 * be set to inform nand_scan about special functionality. 817 * See the defines for further explanation. 818 * @bbt_options: [INTERN] bad block specific options. All options used 819 * here must come from bbm.h. By default, these options 820 * will be copied to the appropriate nand_bbt_descr's. 821 * @badblockpos: [INTERN] position of the bad block marker in the oob 822 * area. 823 * @badblockbits: [INTERN] minimum number of set bits in a good block's 824 * bad block marker position; i.e., BBM == 11110111b is 825 * not bad when badblockbits == 7 826 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 827 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 828 * Minimum amount of bit errors per @ecc_step_ds guaranteed 829 * to be correctable. If unknown, set to zero. 830 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 831 * also from the datasheet. It is the recommended ECC step 832 * size, if known; if unknown, set to zero. 833 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 834 * set to the actually used ONFI mode if the chip is 835 * ONFI compliant or deduced from the datasheet if 836 * the NAND chip is not ONFI compliant. 837 * @numchips: [INTERN] number of physical chips 838 * @chipsize: [INTERN] the size of one chip for multichip arrays 839 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 840 * @pagebuf: [INTERN] holds the pagenumber which is currently in 841 * data_buf. 842 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 843 * currently in data_buf. 844 * @subpagesize: [INTERN] holds the subpagesize 845 * @id: [INTERN] holds NAND ID 846 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 847 * non 0 if ONFI supported. 848 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 849 * non 0 if JEDEC supported. 850 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 851 * supported, 0 otherwise. 852 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 853 * supported, 0 otherwise. 854 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 855 * this nand device will encounter their life times. 856 * @blocks_per_die: [INTERN] The number of PEBs in a die 857 * @data_interface: [INTERN] NAND interface timing information 858 * @read_retries: [INTERN] the number of read retry modes supported 859 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 860 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 861 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 862 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 863 * means the configuration should not be applied but 864 * only checked. 865 * @bbt: [INTERN] bad block table pointer 866 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 867 * lookup. 868 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 869 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 870 * bad block scan. 871 * @controller: [REPLACEABLE] a pointer to a hardware controller 872 * structure which is shared among multiple independent 873 * devices. 874 * @priv: [OPTIONAL] pointer to private chip data 875 * @manufacturer: [INTERN] Contains manufacturer information 876 */ 877 878 struct nand_chip { 879 struct mtd_info mtd; 880 void __iomem *IO_ADDR_R; 881 void __iomem *IO_ADDR_W; 882 883 uint8_t (*read_byte)(struct mtd_info *mtd); 884 u16 (*read_word)(struct mtd_info *mtd); 885 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 886 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 887 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 888 void (*select_chip)(struct mtd_info *mtd, int chip); 889 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 890 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 891 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 892 int (*dev_ready)(struct mtd_info *mtd); 893 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 894 int page_addr); 895 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 896 int (*erase)(struct mtd_info *mtd, int page); 897 int (*scan_bbt)(struct mtd_info *mtd); 898 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 899 int feature_addr, uint8_t *subfeature_para); 900 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 901 int feature_addr, uint8_t *subfeature_para); 902 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 903 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 904 const struct nand_data_interface *conf); 905 906 907 int chip_delay; 908 unsigned int options; 909 unsigned int bbt_options; 910 911 int page_shift; 912 int phys_erase_shift; 913 int bbt_erase_shift; 914 int chip_shift; 915 int numchips; 916 uint64_t chipsize; 917 int pagemask; 918 int pagebuf; 919 unsigned int pagebuf_bitflips; 920 int subpagesize; 921 uint8_t bits_per_cell; 922 uint16_t ecc_strength_ds; 923 uint16_t ecc_step_ds; 924 int onfi_timing_mode_default; 925 int badblockpos; 926 int badblockbits; 927 928 struct nand_id id; 929 int onfi_version; 930 int jedec_version; 931 union { 932 struct nand_onfi_params onfi_params; 933 struct nand_jedec_params jedec_params; 934 }; 935 u16 max_bb_per_die; 936 u32 blocks_per_die; 937 938 struct nand_data_interface *data_interface; 939 940 int read_retries; 941 942 flstate_t state; 943 944 uint8_t *oob_poi; 945 struct nand_hw_control *controller; 946 947 struct nand_ecc_ctrl ecc; 948 struct nand_buffers *buffers; 949 unsigned long buf_align; 950 struct nand_hw_control hwcontrol; 951 952 uint8_t *bbt; 953 struct nand_bbt_descr *bbt_td; 954 struct nand_bbt_descr *bbt_md; 955 956 struct nand_bbt_descr *badblock_pattern; 957 958 void *priv; 959 960 struct { 961 const struct nand_manufacturer *desc; 962 void *priv; 963 } manufacturer; 964 }; 965 966 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 967 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 968 969 static inline void nand_set_flash_node(struct nand_chip *chip, 970 struct device_node *np) 971 { 972 mtd_set_of_node(&chip->mtd, np); 973 } 974 975 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 976 { 977 return mtd_get_of_node(&chip->mtd); 978 } 979 980 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 981 { 982 return container_of(mtd, struct nand_chip, mtd); 983 } 984 985 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 986 { 987 return &chip->mtd; 988 } 989 990 static inline void *nand_get_controller_data(struct nand_chip *chip) 991 { 992 return chip->priv; 993 } 994 995 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 996 { 997 chip->priv = priv; 998 } 999 1000 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1001 void *priv) 1002 { 1003 chip->manufacturer.priv = priv; 1004 } 1005 1006 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1007 { 1008 return chip->manufacturer.priv; 1009 } 1010 1011 /* 1012 * NAND Flash Manufacturer ID Codes 1013 */ 1014 #define NAND_MFR_TOSHIBA 0x98 1015 #define NAND_MFR_ESMT 0xc8 1016 #define NAND_MFR_SAMSUNG 0xec 1017 #define NAND_MFR_FUJITSU 0x04 1018 #define NAND_MFR_NATIONAL 0x8f 1019 #define NAND_MFR_RENESAS 0x07 1020 #define NAND_MFR_STMICRO 0x20 1021 #define NAND_MFR_HYNIX 0xad 1022 #define NAND_MFR_MICRON 0x2c 1023 #define NAND_MFR_AMD 0x01 1024 #define NAND_MFR_MACRONIX 0xc2 1025 #define NAND_MFR_EON 0x92 1026 #define NAND_MFR_SANDISK 0x45 1027 #define NAND_MFR_INTEL 0x89 1028 #define NAND_MFR_ATO 0x9b 1029 #define NAND_MFR_WINBOND 0xef 1030 1031 /* The maximum expected count of bytes in the NAND ID sequence */ 1032 #define NAND_MAX_ID_LEN 8 1033 1034 /* 1035 * A helper for defining older NAND chips where the second ID byte fully 1036 * defined the chip, including the geometry (chip size, eraseblock size, page 1037 * size). All these chips have 512 bytes NAND page size. 1038 */ 1039 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1040 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1041 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1042 1043 /* 1044 * A helper for defining newer chips which report their page size and 1045 * eraseblock size via the extended ID bytes. 1046 * 1047 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1048 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1049 * device ID now only represented a particular total chip size (and voltage, 1050 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1051 * using the same device ID. 1052 */ 1053 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1054 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1055 .options = (opts) } 1056 1057 #define NAND_ECC_INFO(_strength, _step) \ 1058 { .strength_ds = (_strength), .step_ds = (_step) } 1059 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1060 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1061 1062 /** 1063 * struct nand_flash_dev - NAND Flash Device ID Structure 1064 * @name: a human-readable name of the NAND chip 1065 * @dev_id: the device ID (the second byte of the full chip ID array) 1066 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1067 * memory address as @id[0]) 1068 * @dev_id: device ID part of the full chip ID array (refers the same memory 1069 * address as @id[1]) 1070 * @id: full device ID array 1071 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1072 * well as the eraseblock size) is determined from the extended NAND 1073 * chip ID array) 1074 * @chipsize: total chip size in MiB 1075 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1076 * @options: stores various chip bit options 1077 * @id_len: The valid length of the @id. 1078 * @oobsize: OOB size 1079 * @ecc: ECC correctability and step information from the datasheet. 1080 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1081 * @ecc_strength_ds in nand_chip{}. 1082 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1083 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1084 * For example, the "4bit ECC for each 512Byte" can be set with 1085 * NAND_ECC_INFO(4, 512). 1086 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1087 * reset. Should be deduced from timings described 1088 * in the datasheet. 1089 * 1090 */ 1091 struct nand_flash_dev { 1092 char *name; 1093 union { 1094 struct { 1095 uint8_t mfr_id; 1096 uint8_t dev_id; 1097 }; 1098 uint8_t id[NAND_MAX_ID_LEN]; 1099 }; 1100 unsigned int pagesize; 1101 unsigned int chipsize; 1102 unsigned int erasesize; 1103 unsigned int options; 1104 uint16_t id_len; 1105 uint16_t oobsize; 1106 struct { 1107 uint16_t strength_ds; 1108 uint16_t step_ds; 1109 } ecc; 1110 int onfi_timing_mode_default; 1111 }; 1112 1113 /** 1114 * struct nand_manufacturer - NAND Flash Manufacturer structure 1115 * @name: Manufacturer name 1116 * @id: manufacturer ID code of device. 1117 * @ops: manufacturer operations 1118 */ 1119 struct nand_manufacturer { 1120 int id; 1121 char *name; 1122 const struct nand_manufacturer_ops *ops; 1123 }; 1124 1125 const struct nand_manufacturer *nand_get_manufacturer(u8 id); 1126 1127 static inline const char * 1128 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 1129 { 1130 return manufacturer ? manufacturer->name : "Unknown"; 1131 } 1132 1133 extern struct nand_flash_dev nand_flash_ids[]; 1134 1135 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 1136 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; 1137 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; 1138 extern const struct nand_manufacturer_ops micron_nand_manuf_ops; 1139 extern const struct nand_manufacturer_ops amd_nand_manuf_ops; 1140 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; 1141 1142 int nand_default_bbt(struct mtd_info *mtd); 1143 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1144 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1145 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1146 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1147 int allowbbt); 1148 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1149 size_t *retlen, uint8_t *buf); 1150 1151 /** 1152 * struct platform_nand_chip - chip level device structure 1153 * @nr_chips: max. number of chips to scan for 1154 * @chip_offset: chip number offset 1155 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1156 * @partitions: mtd partition list 1157 * @chip_delay: R/B delay value in us 1158 * @options: Option flags, e.g. 16bit buswidth 1159 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1160 * @part_probe_types: NULL-terminated array of probe types 1161 */ 1162 struct platform_nand_chip { 1163 int nr_chips; 1164 int chip_offset; 1165 int nr_partitions; 1166 struct mtd_partition *partitions; 1167 int chip_delay; 1168 unsigned int options; 1169 unsigned int bbt_options; 1170 const char **part_probe_types; 1171 }; 1172 1173 /* Keep gcc happy */ 1174 struct platform_device; 1175 1176 /** 1177 * struct platform_nand_ctrl - controller level device structure 1178 * @probe: platform specific function to probe/setup hardware 1179 * @remove: platform specific function to remove/teardown hardware 1180 * @hwcontrol: platform specific hardware control structure 1181 * @dev_ready: platform specific function to read ready/busy pin 1182 * @select_chip: platform specific chip select function 1183 * @cmd_ctrl: platform specific function for controlling 1184 * ALE/CLE/nCE. Also used to write command and address 1185 * @write_buf: platform specific function for write buffer 1186 * @read_buf: platform specific function for read buffer 1187 * @read_byte: platform specific function to read one byte from chip 1188 * @priv: private data to transport driver specific settings 1189 * 1190 * All fields are optional and depend on the hardware driver requirements 1191 */ 1192 struct platform_nand_ctrl { 1193 int (*probe)(struct platform_device *pdev); 1194 void (*remove)(struct platform_device *pdev); 1195 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1196 int (*dev_ready)(struct mtd_info *mtd); 1197 void (*select_chip)(struct mtd_info *mtd, int chip); 1198 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1199 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1200 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1201 unsigned char (*read_byte)(struct mtd_info *mtd); 1202 void *priv; 1203 }; 1204 1205 /** 1206 * struct platform_nand_data - container structure for platform-specific data 1207 * @chip: chip level chip structure 1208 * @ctrl: controller level device structure 1209 */ 1210 struct platform_nand_data { 1211 struct platform_nand_chip chip; 1212 struct platform_nand_ctrl ctrl; 1213 }; 1214 1215 /* return the supported features. */ 1216 static inline int onfi_feature(struct nand_chip *chip) 1217 { 1218 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1219 } 1220 1221 /* return the supported asynchronous timing mode. */ 1222 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1223 { 1224 if (!chip->onfi_version) 1225 return ONFI_TIMING_MODE_UNKNOWN; 1226 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1227 } 1228 1229 /* return the supported synchronous timing mode. */ 1230 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1231 { 1232 if (!chip->onfi_version) 1233 return ONFI_TIMING_MODE_UNKNOWN; 1234 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1235 } 1236 1237 int onfi_init_data_interface(struct nand_chip *chip, 1238 struct nand_data_interface *iface, 1239 enum nand_data_interface_type type, 1240 int timing_mode); 1241 1242 /* 1243 * Check if it is a SLC nand. 1244 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1245 * We do not distinguish the MLC and TLC now. 1246 */ 1247 static inline bool nand_is_slc(struct nand_chip *chip) 1248 { 1249 return chip->bits_per_cell == 1; 1250 } 1251 1252 /** 1253 * Check if the opcode's address should be sent only on the lower 8 bits 1254 * @command: opcode to check 1255 */ 1256 static inline int nand_opcode_8bits(unsigned int command) 1257 { 1258 switch (command) { 1259 case NAND_CMD_READID: 1260 case NAND_CMD_PARAM: 1261 case NAND_CMD_GET_FEATURES: 1262 case NAND_CMD_SET_FEATURES: 1263 return 1; 1264 default: 1265 break; 1266 } 1267 return 0; 1268 } 1269 1270 /* return the supported JEDEC features. */ 1271 static inline int jedec_feature(struct nand_chip *chip) 1272 { 1273 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1274 : 0; 1275 } 1276 1277 /* get timing characteristics from ONFI timing mode. */ 1278 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1279 /* get data interface from ONFI timing mode 0, used after reset. */ 1280 const struct nand_data_interface *nand_get_default_data_interface(void); 1281 1282 int nand_check_erased_ecc_chunk(void *data, int datalen, 1283 void *ecc, int ecclen, 1284 void *extraoob, int extraooblen, 1285 int threshold); 1286 1287 int nand_check_ecc_caps(struct nand_chip *chip, 1288 const struct nand_ecc_caps *caps, int oobavail); 1289 1290 int nand_match_ecc_req(struct nand_chip *chip, 1291 const struct nand_ecc_caps *caps, int oobavail); 1292 1293 int nand_maximize_ecc(struct nand_chip *chip, 1294 const struct nand_ecc_caps *caps, int oobavail); 1295 1296 /* Default write_oob implementation */ 1297 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1298 1299 /* Default write_oob syndrome implementation */ 1300 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1301 int page); 1302 1303 /* Default read_oob implementation */ 1304 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); 1305 1306 /* Default read_oob syndrome implementation */ 1307 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1308 int page); 1309 1310 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1311 int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, 1312 struct nand_chip *chip, int addr, 1313 u8 *subfeature_param); 1314 1315 /* Default read_page_raw implementation */ 1316 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1317 uint8_t *buf, int oob_required, int page); 1318 1319 /* Default write_page_raw implementation */ 1320 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1321 const uint8_t *buf, int oob_required, int page); 1322 1323 /* Reset and initialize a NAND device */ 1324 int nand_reset(struct nand_chip *chip, int chipnr); 1325 1326 /* Free resources held by the NAND device */ 1327 void nand_cleanup(struct nand_chip *chip); 1328 1329 /* Default extended ID decoding function */ 1330 void nand_decode_ext_id(struct nand_chip *chip); 1331 #endif /* __LINUX_MTD_NAND_H */ 1332