1 2 /* Common Flash Interface structures 3 * See http://support.intel.com/design/flash/technote/index.htm 4 * $Id: cfi.h,v 1.57 2005/11/15 23:28:17 tpoynor Exp $ 5 */ 6 7 #ifndef __MTD_CFI_H__ 8 #define __MTD_CFI_H__ 9 10 #include <linux/delay.h> 11 #include <linux/types.h> 12 #include <linux/interrupt.h> 13 #include <linux/mtd/flashchip.h> 14 #include <linux/mtd/map.h> 15 #include <linux/mtd/cfi_endian.h> 16 17 #ifdef CONFIG_MTD_CFI_I1 18 #define cfi_interleave(cfi) 1 19 #define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1) 20 #else 21 #define cfi_interleave_is_1(cfi) (0) 22 #endif 23 24 #ifdef CONFIG_MTD_CFI_I2 25 # ifdef cfi_interleave 26 # undef cfi_interleave 27 # define cfi_interleave(cfi) ((cfi)->interleave) 28 # else 29 # define cfi_interleave(cfi) 2 30 # endif 31 #define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2) 32 #else 33 #define cfi_interleave_is_2(cfi) (0) 34 #endif 35 36 #ifdef CONFIG_MTD_CFI_I4 37 # ifdef cfi_interleave 38 # undef cfi_interleave 39 # define cfi_interleave(cfi) ((cfi)->interleave) 40 # else 41 # define cfi_interleave(cfi) 4 42 # endif 43 #define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4) 44 #else 45 #define cfi_interleave_is_4(cfi) (0) 46 #endif 47 48 #ifdef CONFIG_MTD_CFI_I8 49 # ifdef cfi_interleave 50 # undef cfi_interleave 51 # define cfi_interleave(cfi) ((cfi)->interleave) 52 # else 53 # define cfi_interleave(cfi) 8 54 # endif 55 #define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8) 56 #else 57 #define cfi_interleave_is_8(cfi) (0) 58 #endif 59 60 #ifndef cfi_interleave 61 #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. 62 static inline int cfi_interleave(void *cfi) 63 { 64 BUG(); 65 return 0; 66 } 67 #endif 68 69 static inline int cfi_interleave_supported(int i) 70 { 71 switch (i) { 72 #ifdef CONFIG_MTD_CFI_I1 73 case 1: 74 #endif 75 #ifdef CONFIG_MTD_CFI_I2 76 case 2: 77 #endif 78 #ifdef CONFIG_MTD_CFI_I4 79 case 4: 80 #endif 81 #ifdef CONFIG_MTD_CFI_I8 82 case 8: 83 #endif 84 return 1; 85 86 default: 87 return 0; 88 } 89 } 90 91 92 /* NB: these values must represents the number of bytes needed to meet the 93 * device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes. 94 * These numbers are used in calculations. 95 */ 96 #define CFI_DEVICETYPE_X8 (8 / 8) 97 #define CFI_DEVICETYPE_X16 (16 / 8) 98 #define CFI_DEVICETYPE_X32 (32 / 8) 99 #define CFI_DEVICETYPE_X64 (64 / 8) 100 101 /* NB: We keep these structures in memory in HOST byteorder, except 102 * where individually noted. 103 */ 104 105 /* Basic Query Structure */ 106 struct cfi_ident { 107 uint8_t qry[3]; 108 uint16_t P_ID; 109 uint16_t P_ADR; 110 uint16_t A_ID; 111 uint16_t A_ADR; 112 uint8_t VccMin; 113 uint8_t VccMax; 114 uint8_t VppMin; 115 uint8_t VppMax; 116 uint8_t WordWriteTimeoutTyp; 117 uint8_t BufWriteTimeoutTyp; 118 uint8_t BlockEraseTimeoutTyp; 119 uint8_t ChipEraseTimeoutTyp; 120 uint8_t WordWriteTimeoutMax; 121 uint8_t BufWriteTimeoutMax; 122 uint8_t BlockEraseTimeoutMax; 123 uint8_t ChipEraseTimeoutMax; 124 uint8_t DevSize; 125 uint16_t InterfaceDesc; 126 uint16_t MaxBufWriteSize; 127 uint8_t NumEraseRegions; 128 uint32_t EraseRegionInfo[0]; /* Not host ordered */ 129 } __attribute__((packed)); 130 131 /* Extended Query Structure for both PRI and ALT */ 132 133 struct cfi_extquery { 134 uint8_t pri[3]; 135 uint8_t MajorVersion; 136 uint8_t MinorVersion; 137 } __attribute__((packed)); 138 139 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */ 140 141 struct cfi_pri_intelext { 142 uint8_t pri[3]; 143 uint8_t MajorVersion; 144 uint8_t MinorVersion; 145 uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature 146 block follows - FIXME - not currently supported */ 147 uint8_t SuspendCmdSupport; 148 uint16_t BlkStatusRegMask; 149 uint8_t VccOptimal; 150 uint8_t VppOptimal; 151 uint8_t NumProtectionFields; 152 uint16_t ProtRegAddr; 153 uint8_t FactProtRegSize; 154 uint8_t UserProtRegSize; 155 uint8_t extra[0]; 156 } __attribute__((packed)); 157 158 struct cfi_intelext_otpinfo { 159 uint32_t ProtRegAddr; 160 uint16_t FactGroups; 161 uint8_t FactProtRegSize; 162 uint16_t UserGroups; 163 uint8_t UserProtRegSize; 164 } __attribute__((packed)); 165 166 struct cfi_intelext_blockinfo { 167 uint16_t NumIdentBlocks; 168 uint16_t BlockSize; 169 uint16_t MinBlockEraseCycles; 170 uint8_t BitsPerCell; 171 uint8_t BlockCap; 172 } __attribute__((packed)); 173 174 struct cfi_intelext_regioninfo { 175 uint16_t NumIdentPartitions; 176 uint8_t NumOpAllowed; 177 uint8_t NumOpAllowedSimProgMode; 178 uint8_t NumOpAllowedSimEraMode; 179 uint8_t NumBlockTypes; 180 struct cfi_intelext_blockinfo BlockTypes[1]; 181 } __attribute__((packed)); 182 183 struct cfi_intelext_programming_regioninfo { 184 uint8_t ProgRegShift; 185 uint8_t Reserved1; 186 uint8_t ControlValid; 187 uint8_t Reserved2; 188 uint8_t ControlInvalid; 189 uint8_t Reserved3; 190 } __attribute__((packed)); 191 192 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */ 193 194 struct cfi_pri_amdstd { 195 uint8_t pri[3]; 196 uint8_t MajorVersion; 197 uint8_t MinorVersion; 198 uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */ 199 uint8_t EraseSuspend; 200 uint8_t BlkProt; 201 uint8_t TmpBlkUnprotect; 202 uint8_t BlkProtUnprot; 203 uint8_t SimultaneousOps; 204 uint8_t BurstMode; 205 uint8_t PageMode; 206 uint8_t VppMin; 207 uint8_t VppMax; 208 uint8_t TopBottom; 209 } __attribute__((packed)); 210 211 /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ 212 213 struct cfi_pri_atmel { 214 uint8_t pri[3]; 215 uint8_t MajorVersion; 216 uint8_t MinorVersion; 217 uint8_t Features; 218 uint8_t BottomBoot; 219 uint8_t BurstMode; 220 uint8_t PageMode; 221 } __attribute__((packed)); 222 223 struct cfi_pri_query { 224 uint8_t NumFields; 225 uint32_t ProtField[1]; /* Not host ordered */ 226 } __attribute__((packed)); 227 228 struct cfi_bri_query { 229 uint8_t PageModeReadCap; 230 uint8_t NumFields; 231 uint32_t ConfField[1]; /* Not host ordered */ 232 } __attribute__((packed)); 233 234 #define P_ID_NONE 0x0000 235 #define P_ID_INTEL_EXT 0x0001 236 #define P_ID_AMD_STD 0x0002 237 #define P_ID_INTEL_STD 0x0003 238 #define P_ID_AMD_EXT 0x0004 239 #define P_ID_WINBOND 0x0006 240 #define P_ID_ST_ADV 0x0020 241 #define P_ID_MITSUBISHI_STD 0x0100 242 #define P_ID_MITSUBISHI_EXT 0x0101 243 #define P_ID_SST_PAGE 0x0102 244 #define P_ID_INTEL_PERFORMANCE 0x0200 245 #define P_ID_INTEL_DATA 0x0210 246 #define P_ID_RESERVED 0xffff 247 248 249 #define CFI_MODE_CFI 1 250 #define CFI_MODE_JEDEC 0 251 252 struct cfi_private { 253 uint16_t cmdset; 254 void *cmdset_priv; 255 int interleave; 256 int device_type; 257 int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */ 258 int addr_unlock1; 259 int addr_unlock2; 260 struct mtd_info *(*cmdset_setup)(struct map_info *); 261 struct cfi_ident *cfiq; /* For now only one. We insist that all devs 262 must be of the same type. */ 263 int mfr, id; 264 int numchips; 265 unsigned long chipshift; /* Because they're of the same type */ 266 const char *im_name; /* inter_module name for cmdset_setup */ 267 struct flchip chips[0]; /* per-chip data structure for each chip */ 268 }; 269 270 /* 271 * Returns the command address according to the given geometry. 272 */ 273 static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type) 274 { 275 return (cmd_ofs * type) * interleave; 276 } 277 278 /* 279 * Transforms the CFI command for the given geometry (bus width & interleave). 280 * It looks too long to be inline, but in the common case it should almost all 281 * get optimised away. 282 */ 283 static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) 284 { 285 map_word val = { {0} }; 286 int wordwidth, words_per_bus, chip_mode, chips_per_word; 287 unsigned long onecmd; 288 int i; 289 290 /* We do it this way to give the compiler a fighting chance 291 of optimising away all the crap for 'bankwidth' larger than 292 an unsigned long, in the common case where that support is 293 disabled */ 294 if (map_bankwidth_is_large(map)) { 295 wordwidth = sizeof(unsigned long); 296 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1 297 } else { 298 wordwidth = map_bankwidth(map); 299 words_per_bus = 1; 300 } 301 302 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); 303 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); 304 305 /* First, determine what the bit-pattern should be for a single 306 device, according to chip mode and endianness... */ 307 switch (chip_mode) { 308 default: BUG(); 309 case 1: 310 onecmd = cmd; 311 break; 312 case 2: 313 onecmd = cpu_to_cfi16(cmd); 314 break; 315 case 4: 316 onecmd = cpu_to_cfi32(cmd); 317 break; 318 } 319 320 /* Now replicate it across the size of an unsigned long, or 321 just to the bus width as appropriate */ 322 switch (chips_per_word) { 323 default: BUG(); 324 #if BITS_PER_LONG >= 64 325 case 8: 326 onecmd |= (onecmd << (chip_mode * 32)); 327 #endif 328 case 4: 329 onecmd |= (onecmd << (chip_mode * 16)); 330 case 2: 331 onecmd |= (onecmd << (chip_mode * 8)); 332 case 1: 333 ; 334 } 335 336 /* And finally, for the multi-word case, replicate it 337 in all words in the structure */ 338 for (i=0; i < words_per_bus; i++) { 339 val.x[i] = onecmd; 340 } 341 342 return val; 343 } 344 #define CMD(x) cfi_build_cmd((x), map, cfi) 345 346 347 static inline unsigned long cfi_merge_status(map_word val, struct map_info *map, 348 struct cfi_private *cfi) 349 { 350 int wordwidth, words_per_bus, chip_mode, chips_per_word; 351 unsigned long onestat, res = 0; 352 int i; 353 354 /* We do it this way to give the compiler a fighting chance 355 of optimising away all the crap for 'bankwidth' larger than 356 an unsigned long, in the common case where that support is 357 disabled */ 358 if (map_bankwidth_is_large(map)) { 359 wordwidth = sizeof(unsigned long); 360 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1 361 } else { 362 wordwidth = map_bankwidth(map); 363 words_per_bus = 1; 364 } 365 366 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); 367 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); 368 369 onestat = val.x[0]; 370 /* Or all status words together */ 371 for (i=1; i < words_per_bus; i++) { 372 onestat |= val.x[i]; 373 } 374 375 res = onestat; 376 switch(chips_per_word) { 377 default: BUG(); 378 #if BITS_PER_LONG >= 64 379 case 8: 380 res |= (onestat >> (chip_mode * 32)); 381 #endif 382 case 4: 383 res |= (onestat >> (chip_mode * 16)); 384 case 2: 385 res |= (onestat >> (chip_mode * 8)); 386 case 1: 387 ; 388 } 389 390 /* Last, determine what the bit-pattern should be for a single 391 device, according to chip mode and endianness... */ 392 switch (chip_mode) { 393 case 1: 394 break; 395 case 2: 396 res = cfi16_to_cpu(res); 397 break; 398 case 4: 399 res = cfi32_to_cpu(res); 400 break; 401 default: BUG(); 402 } 403 return res; 404 } 405 406 #define MERGESTATUS(x) cfi_merge_status((x), map, cfi) 407 408 409 /* 410 * Sends a CFI command to a bank of flash for the given geometry. 411 * 412 * Returns the offset in flash where the command was written. 413 * If prev_val is non-null, it will be set to the value at the command address, 414 * before the command was written. 415 */ 416 static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, 417 struct map_info *map, struct cfi_private *cfi, 418 int type, map_word *prev_val) 419 { 420 map_word val; 421 uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type); 422 423 val = cfi_build_cmd(cmd, map, cfi); 424 425 if (prev_val) 426 *prev_val = map_read(map, addr); 427 428 map_write(map, val, addr); 429 430 return addr - base; 431 } 432 433 static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr) 434 { 435 map_word val = map_read(map, addr); 436 437 if (map_bankwidth_is_1(map)) { 438 return val.x[0]; 439 } else if (map_bankwidth_is_2(map)) { 440 return cfi16_to_cpu(val.x[0]); 441 } else { 442 /* No point in a 64-bit byteswap since that would just be 443 swapping the responses from different chips, and we are 444 only interested in one chip (a representative sample) */ 445 return cfi32_to_cpu(val.x[0]); 446 } 447 } 448 449 static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr) 450 { 451 map_word val = map_read(map, addr); 452 453 if (map_bankwidth_is_1(map)) { 454 return val.x[0] & 0xff; 455 } else if (map_bankwidth_is_2(map)) { 456 return cfi16_to_cpu(val.x[0]); 457 } else { 458 /* No point in a 64-bit byteswap since that would just be 459 swapping the responses from different chips, and we are 460 only interested in one chip (a representative sample) */ 461 return cfi32_to_cpu(val.x[0]); 462 } 463 } 464 465 static inline void cfi_udelay(int us) 466 { 467 if (us >= 1000) { 468 msleep((us+999)/1000); 469 } else { 470 udelay(us); 471 cond_resched(); 472 } 473 } 474 475 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size, 476 const char* name); 477 struct cfi_fixup { 478 uint16_t mfr; 479 uint16_t id; 480 void (*fixup)(struct mtd_info *mtd, void* param); 481 void* param; 482 }; 483 484 #define CFI_MFR_ANY 0xffff 485 #define CFI_ID_ANY 0xffff 486 487 #define CFI_MFR_AMD 0x0001 488 #define CFI_MFR_ATMEL 0x001F 489 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ 490 491 void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups); 492 493 typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip, 494 unsigned long adr, int len, void *thunk); 495 496 int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob, 497 loff_t ofs, size_t len, void *thunk); 498 499 500 #endif /* __MTD_CFI_H__ */ 501