1 #ifndef LINUX_MSI_H 2 #define LINUX_MSI_H 3 4 #include <linux/kobject.h> 5 #include <linux/list.h> 6 7 struct msi_msg { 8 u32 address_lo; /* low 32 bits of msi message address */ 9 u32 address_hi; /* high 32 bits of msi message address */ 10 u32 data; /* 16 bits of msi message data */ 11 }; 12 13 extern int pci_msi_ignore_mask; 14 /* Helper functions */ 15 struct irq_data; 16 struct msi_desc; 17 struct pci_dev; 18 struct platform_msi_priv_data; 19 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); 20 #ifdef CONFIG_GENERIC_MSI_IRQ 21 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); 22 #else 23 static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) 24 { 25 } 26 #endif 27 28 typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc, 29 struct msi_msg *msg); 30 31 /** 32 * platform_msi_desc - Platform device specific msi descriptor data 33 * @msi_priv_data: Pointer to platform private data 34 * @msi_index: The index of the MSI descriptor for multi MSI 35 */ 36 struct platform_msi_desc { 37 struct platform_msi_priv_data *msi_priv_data; 38 u16 msi_index; 39 }; 40 41 /** 42 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data 43 * @msi_index: The index of the MSI descriptor 44 */ 45 struct fsl_mc_msi_desc { 46 u16 msi_index; 47 }; 48 49 /** 50 * struct msi_desc - Descriptor structure for MSI based interrupts 51 * @list: List head for management 52 * @irq: The base interrupt number 53 * @nvec_used: The number of vectors used 54 * @dev: Pointer to the device which uses this descriptor 55 * @msg: The last set MSI message cached for reuse 56 * @affinity: Optional pointer to a cpu affinity mask for this descriptor 57 * 58 * @masked: [PCI MSI/X] Mask bits 59 * @is_msix: [PCI MSI/X] True if MSI-X 60 * @multiple: [PCI MSI/X] log2 num of messages allocated 61 * @multi_cap: [PCI MSI/X] log2 num of messages supported 62 * @maskbit: [PCI MSI/X] Mask-Pending bit supported? 63 * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit 64 * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor 65 * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq 66 * @mask_pos: [PCI MSI] Mask register position 67 * @mask_base: [PCI MSI-X] Mask register base address 68 * @platform: [platform] Platform device specific msi descriptor data 69 */ 70 struct msi_desc { 71 /* Shared device/bus type independent data */ 72 struct list_head list; 73 unsigned int irq; 74 unsigned int nvec_used; 75 struct device *dev; 76 struct msi_msg msg; 77 struct cpumask *affinity; 78 79 union { 80 /* PCI MSI/X specific data */ 81 struct { 82 u32 masked; 83 struct { 84 __u8 is_msix : 1; 85 __u8 multiple : 3; 86 __u8 multi_cap : 3; 87 __u8 maskbit : 1; 88 __u8 is_64 : 1; 89 __u16 entry_nr; 90 unsigned default_irq; 91 } msi_attrib; 92 union { 93 u8 mask_pos; 94 void __iomem *mask_base; 95 }; 96 }; 97 98 /* 99 * Non PCI variants add their data structure here. New 100 * entries need to use a named structure. We want 101 * proper name spaces for this. The PCI part is 102 * anonymous for now as it would require an immediate 103 * tree wide cleanup. 104 */ 105 struct platform_msi_desc platform; 106 struct fsl_mc_msi_desc fsl_mc; 107 }; 108 }; 109 110 /* Helpers to hide struct msi_desc implementation details */ 111 #define msi_desc_to_dev(desc) ((desc)->dev) 112 #define dev_to_msi_list(dev) (&(dev)->msi_list) 113 #define first_msi_entry(dev) \ 114 list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list) 115 #define for_each_msi_entry(desc, dev) \ 116 list_for_each_entry((desc), dev_to_msi_list((dev)), list) 117 118 #ifdef CONFIG_PCI_MSI 119 #define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev) 120 #define for_each_pci_msi_entry(desc, pdev) \ 121 for_each_msi_entry((desc), &(pdev)->dev) 122 123 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc); 124 void *msi_desc_to_pci_sysdata(struct msi_desc *desc); 125 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg); 126 #else /* CONFIG_PCI_MSI */ 127 static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc) 128 { 129 return NULL; 130 } 131 static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) 132 { 133 } 134 #endif /* CONFIG_PCI_MSI */ 135 136 struct msi_desc *alloc_msi_entry(struct device *dev, int nvec, 137 const struct cpumask *affinity); 138 void free_msi_entry(struct msi_desc *entry); 139 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); 140 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); 141 142 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); 143 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); 144 void pci_msi_mask_irq(struct irq_data *data); 145 void pci_msi_unmask_irq(struct irq_data *data); 146 147 /* Conversion helpers. Should be removed after merging */ 148 static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 149 { 150 __pci_write_msi_msg(entry, msg); 151 } 152 static inline void write_msi_msg(int irq, struct msi_msg *msg) 153 { 154 pci_write_msi_msg(irq, msg); 155 } 156 static inline void mask_msi_irq(struct irq_data *data) 157 { 158 pci_msi_mask_irq(data); 159 } 160 static inline void unmask_msi_irq(struct irq_data *data) 161 { 162 pci_msi_unmask_irq(data); 163 } 164 165 /* 166 * The arch hooks to setup up msi irqs. Those functions are 167 * implemented as weak symbols so that they /can/ be overriden by 168 * architecture specific code if needed. 169 */ 170 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); 171 void arch_teardown_msi_irq(unsigned int irq); 172 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); 173 void arch_teardown_msi_irqs(struct pci_dev *dev); 174 void arch_restore_msi_irqs(struct pci_dev *dev); 175 176 void default_teardown_msi_irqs(struct pci_dev *dev); 177 void default_restore_msi_irqs(struct pci_dev *dev); 178 179 struct msi_controller { 180 struct module *owner; 181 struct device *dev; 182 struct device_node *of_node; 183 struct list_head list; 184 185 int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev, 186 struct msi_desc *desc); 187 int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev, 188 int nvec, int type); 189 void (*teardown_irq)(struct msi_controller *chip, unsigned int irq); 190 }; 191 192 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN 193 194 #include <linux/irqhandler.h> 195 #include <asm/msi.h> 196 197 struct irq_domain; 198 struct irq_domain_ops; 199 struct irq_chip; 200 struct device_node; 201 struct fwnode_handle; 202 struct msi_domain_info; 203 204 /** 205 * struct msi_domain_ops - MSI interrupt domain callbacks 206 * @get_hwirq: Retrieve the resulting hw irq number 207 * @msi_init: Domain specific init function for MSI interrupts 208 * @msi_free: Domain specific function to free a MSI interrupts 209 * @msi_check: Callback for verification of the domain/info/dev data 210 * @msi_prepare: Prepare the allocation of the interrupts in the domain 211 * @msi_finish: Optional callback to finalize the allocation 212 * @set_desc: Set the msi descriptor for an interrupt 213 * @handle_error: Optional error handler if the allocation fails 214 * 215 * @get_hwirq, @msi_init and @msi_free are callbacks used by 216 * msi_create_irq_domain() and related interfaces 217 * 218 * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error 219 * are callbacks used by msi_domain_alloc_irqs() and related 220 * interfaces which are based on msi_desc. 221 */ 222 struct msi_domain_ops { 223 irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info, 224 msi_alloc_info_t *arg); 225 int (*msi_init)(struct irq_domain *domain, 226 struct msi_domain_info *info, 227 unsigned int virq, irq_hw_number_t hwirq, 228 msi_alloc_info_t *arg); 229 void (*msi_free)(struct irq_domain *domain, 230 struct msi_domain_info *info, 231 unsigned int virq); 232 int (*msi_check)(struct irq_domain *domain, 233 struct msi_domain_info *info, 234 struct device *dev); 235 int (*msi_prepare)(struct irq_domain *domain, 236 struct device *dev, int nvec, 237 msi_alloc_info_t *arg); 238 void (*msi_finish)(msi_alloc_info_t *arg, int retval); 239 void (*set_desc)(msi_alloc_info_t *arg, 240 struct msi_desc *desc); 241 int (*handle_error)(struct irq_domain *domain, 242 struct msi_desc *desc, int error); 243 }; 244 245 /** 246 * struct msi_domain_info - MSI interrupt domain data 247 * @flags: Flags to decribe features and capabilities 248 * @ops: The callback data structure 249 * @chip: Optional: associated interrupt chip 250 * @chip_data: Optional: associated interrupt chip data 251 * @handler: Optional: associated interrupt flow handler 252 * @handler_data: Optional: associated interrupt flow handler data 253 * @handler_name: Optional: associated interrupt flow handler name 254 * @data: Optional: domain specific data 255 */ 256 struct msi_domain_info { 257 u32 flags; 258 struct msi_domain_ops *ops; 259 struct irq_chip *chip; 260 void *chip_data; 261 irq_flow_handler_t handler; 262 void *handler_data; 263 const char *handler_name; 264 void *data; 265 }; 266 267 /* Flags for msi_domain_info */ 268 enum { 269 /* 270 * Init non implemented ops callbacks with default MSI domain 271 * callbacks. 272 */ 273 MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0), 274 /* 275 * Init non implemented chip callbacks with default MSI chip 276 * callbacks. 277 */ 278 MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), 279 /* Support multiple PCI MSI interrupts */ 280 MSI_FLAG_MULTI_PCI_MSI = (1 << 2), 281 /* Support PCI MSIX interrupts */ 282 MSI_FLAG_PCI_MSIX = (1 << 3), 283 /* Needs early activate, required for PCI */ 284 MSI_FLAG_ACTIVATE_EARLY = (1 << 4), 285 }; 286 287 int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, 288 bool force); 289 290 struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode, 291 struct msi_domain_info *info, 292 struct irq_domain *parent); 293 int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, 294 int nvec); 295 void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev); 296 struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); 297 298 struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, 299 struct msi_domain_info *info, 300 struct irq_domain *parent); 301 int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, 302 irq_write_msi_msg_t write_msi_msg); 303 void platform_msi_domain_free_irqs(struct device *dev); 304 305 /* When an MSI domain is used as an intermediate domain */ 306 int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, 307 int nvec, msi_alloc_info_t *args); 308 int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev, 309 int virq, int nvec, msi_alloc_info_t *args); 310 struct irq_domain * 311 platform_msi_create_device_domain(struct device *dev, 312 unsigned int nvec, 313 irq_write_msi_msg_t write_msi_msg, 314 const struct irq_domain_ops *ops, 315 void *host_data); 316 int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 317 unsigned int nr_irqs); 318 void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq, 319 unsigned int nvec); 320 void *platform_msi_get_host_data(struct irq_domain *domain); 321 #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ 322 323 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 324 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg); 325 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, 326 struct msi_domain_info *info, 327 struct irq_domain *parent); 328 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, 329 struct msi_desc *desc); 330 int pci_msi_domain_check_cap(struct irq_domain *domain, 331 struct msi_domain_info *info, struct device *dev); 332 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev); 333 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); 334 #else 335 static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) 336 { 337 return NULL; 338 } 339 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ 340 341 #endif /* LINUX_MSI_H */ 342