1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 }; 108 109 enum { 110 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 111 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 112 MLX5_CMD_OP_INIT_HCA = 0x102, 113 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 114 MLX5_CMD_OP_ENABLE_HCA = 0x104, 115 MLX5_CMD_OP_DISABLE_HCA = 0x105, 116 MLX5_CMD_OP_QUERY_PAGES = 0x107, 117 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 118 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 119 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 120 MLX5_CMD_OP_SET_ISSI = 0x10b, 121 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 122 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 123 MLX5_CMD_OP_ALLOC_SF = 0x113, 124 MLX5_CMD_OP_DEALLOC_SF = 0x114, 125 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 126 MLX5_CMD_OP_RESUME_VHCA = 0x116, 127 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 128 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 129 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 130 MLX5_CMD_OP_CREATE_MKEY = 0x200, 131 MLX5_CMD_OP_QUERY_MKEY = 0x201, 132 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 133 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 134 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 135 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 136 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 137 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 138 MLX5_CMD_OP_CREATE_EQ = 0x301, 139 MLX5_CMD_OP_DESTROY_EQ = 0x302, 140 MLX5_CMD_OP_QUERY_EQ = 0x303, 141 MLX5_CMD_OP_GEN_EQE = 0x304, 142 MLX5_CMD_OP_CREATE_CQ = 0x400, 143 MLX5_CMD_OP_DESTROY_CQ = 0x401, 144 MLX5_CMD_OP_QUERY_CQ = 0x402, 145 MLX5_CMD_OP_MODIFY_CQ = 0x403, 146 MLX5_CMD_OP_CREATE_QP = 0x500, 147 MLX5_CMD_OP_DESTROY_QP = 0x501, 148 MLX5_CMD_OP_RST2INIT_QP = 0x502, 149 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 150 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 151 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 152 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 153 MLX5_CMD_OP_2ERR_QP = 0x507, 154 MLX5_CMD_OP_2RST_QP = 0x50a, 155 MLX5_CMD_OP_QUERY_QP = 0x50b, 156 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 157 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 158 MLX5_CMD_OP_CREATE_PSV = 0x600, 159 MLX5_CMD_OP_DESTROY_PSV = 0x601, 160 MLX5_CMD_OP_CREATE_SRQ = 0x700, 161 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 162 MLX5_CMD_OP_QUERY_SRQ = 0x702, 163 MLX5_CMD_OP_ARM_RQ = 0x703, 164 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 165 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 166 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 167 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 168 MLX5_CMD_OP_CREATE_DCT = 0x710, 169 MLX5_CMD_OP_DESTROY_DCT = 0x711, 170 MLX5_CMD_OP_DRAIN_DCT = 0x712, 171 MLX5_CMD_OP_QUERY_DCT = 0x713, 172 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 173 MLX5_CMD_OP_CREATE_XRQ = 0x717, 174 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 175 MLX5_CMD_OP_QUERY_XRQ = 0x719, 176 MLX5_CMD_OP_ARM_XRQ = 0x71a, 177 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 178 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 179 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 180 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 181 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 182 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 183 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 184 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 185 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 186 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 187 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 188 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 189 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 190 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 192 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 195 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 196 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 197 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 198 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 199 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 200 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 201 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 202 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 203 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 204 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 205 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 206 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 207 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 208 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 209 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 210 MLX5_CMD_OP_ALLOC_PD = 0x800, 211 MLX5_CMD_OP_DEALLOC_PD = 0x801, 212 MLX5_CMD_OP_ALLOC_UAR = 0x802, 213 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 214 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 215 MLX5_CMD_OP_ACCESS_REG = 0x805, 216 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 217 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 218 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 219 MLX5_CMD_OP_MAD_IFC = 0x50d, 220 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 221 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 222 MLX5_CMD_OP_NOP = 0x80d, 223 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 224 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 225 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 226 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 227 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 228 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 229 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 230 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 231 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 232 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 233 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 234 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 235 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 236 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 237 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 238 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 239 MLX5_CMD_OP_CREATE_LAG = 0x840, 240 MLX5_CMD_OP_MODIFY_LAG = 0x841, 241 MLX5_CMD_OP_QUERY_LAG = 0x842, 242 MLX5_CMD_OP_DESTROY_LAG = 0x843, 243 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 244 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 245 MLX5_CMD_OP_CREATE_TIR = 0x900, 246 MLX5_CMD_OP_MODIFY_TIR = 0x901, 247 MLX5_CMD_OP_DESTROY_TIR = 0x902, 248 MLX5_CMD_OP_QUERY_TIR = 0x903, 249 MLX5_CMD_OP_CREATE_SQ = 0x904, 250 MLX5_CMD_OP_MODIFY_SQ = 0x905, 251 MLX5_CMD_OP_DESTROY_SQ = 0x906, 252 MLX5_CMD_OP_QUERY_SQ = 0x907, 253 MLX5_CMD_OP_CREATE_RQ = 0x908, 254 MLX5_CMD_OP_MODIFY_RQ = 0x909, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 257 MLX5_CMD_OP_QUERY_RQ = 0x90b, 258 MLX5_CMD_OP_CREATE_RMP = 0x90c, 259 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 260 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 261 MLX5_CMD_OP_QUERY_RMP = 0x90f, 262 MLX5_CMD_OP_CREATE_TIS = 0x912, 263 MLX5_CMD_OP_MODIFY_TIS = 0x913, 264 MLX5_CMD_OP_DESTROY_TIS = 0x914, 265 MLX5_CMD_OP_QUERY_TIS = 0x915, 266 MLX5_CMD_OP_CREATE_RQT = 0x916, 267 MLX5_CMD_OP_MODIFY_RQT = 0x917, 268 MLX5_CMD_OP_DESTROY_RQT = 0x918, 269 MLX5_CMD_OP_QUERY_RQT = 0x919, 270 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 271 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 272 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 274 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 275 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 276 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 277 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 278 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 279 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 280 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 281 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 282 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 283 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 284 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 285 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 286 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 287 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 288 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 289 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 290 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 291 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 292 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 293 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 294 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 295 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 296 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 297 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 298 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 299 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 300 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 301 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 302 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 303 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 304 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 305 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 306 MLX5_CMD_OP_MAX 307 }; 308 309 /* Valid range for general commands that don't work over an object */ 310 enum { 311 MLX5_CMD_OP_GENERAL_START = 0xb00, 312 MLX5_CMD_OP_GENERAL_END = 0xd00, 313 }; 314 315 struct mlx5_ifc_flow_table_fields_supported_bits { 316 u8 outer_dmac[0x1]; 317 u8 outer_smac[0x1]; 318 u8 outer_ether_type[0x1]; 319 u8 outer_ip_version[0x1]; 320 u8 outer_first_prio[0x1]; 321 u8 outer_first_cfi[0x1]; 322 u8 outer_first_vid[0x1]; 323 u8 outer_ipv4_ttl[0x1]; 324 u8 outer_second_prio[0x1]; 325 u8 outer_second_cfi[0x1]; 326 u8 outer_second_vid[0x1]; 327 u8 reserved_at_b[0x1]; 328 u8 outer_sip[0x1]; 329 u8 outer_dip[0x1]; 330 u8 outer_frag[0x1]; 331 u8 outer_ip_protocol[0x1]; 332 u8 outer_ip_ecn[0x1]; 333 u8 outer_ip_dscp[0x1]; 334 u8 outer_udp_sport[0x1]; 335 u8 outer_udp_dport[0x1]; 336 u8 outer_tcp_sport[0x1]; 337 u8 outer_tcp_dport[0x1]; 338 u8 outer_tcp_flags[0x1]; 339 u8 outer_gre_protocol[0x1]; 340 u8 outer_gre_key[0x1]; 341 u8 outer_vxlan_vni[0x1]; 342 u8 outer_geneve_vni[0x1]; 343 u8 outer_geneve_oam[0x1]; 344 u8 outer_geneve_protocol_type[0x1]; 345 u8 outer_geneve_opt_len[0x1]; 346 u8 source_vhca_port[0x1]; 347 u8 source_eswitch_port[0x1]; 348 349 u8 inner_dmac[0x1]; 350 u8 inner_smac[0x1]; 351 u8 inner_ether_type[0x1]; 352 u8 inner_ip_version[0x1]; 353 u8 inner_first_prio[0x1]; 354 u8 inner_first_cfi[0x1]; 355 u8 inner_first_vid[0x1]; 356 u8 reserved_at_27[0x1]; 357 u8 inner_second_prio[0x1]; 358 u8 inner_second_cfi[0x1]; 359 u8 inner_second_vid[0x1]; 360 u8 reserved_at_2b[0x1]; 361 u8 inner_sip[0x1]; 362 u8 inner_dip[0x1]; 363 u8 inner_frag[0x1]; 364 u8 inner_ip_protocol[0x1]; 365 u8 inner_ip_ecn[0x1]; 366 u8 inner_ip_dscp[0x1]; 367 u8 inner_udp_sport[0x1]; 368 u8 inner_udp_dport[0x1]; 369 u8 inner_tcp_sport[0x1]; 370 u8 inner_tcp_dport[0x1]; 371 u8 inner_tcp_flags[0x1]; 372 u8 reserved_at_37[0x9]; 373 374 u8 geneve_tlv_option_0_data[0x1]; 375 u8 geneve_tlv_option_0_exist[0x1]; 376 u8 reserved_at_42[0x3]; 377 u8 outer_first_mpls_over_udp[0x4]; 378 u8 outer_first_mpls_over_gre[0x4]; 379 u8 inner_first_mpls[0x4]; 380 u8 outer_first_mpls[0x4]; 381 u8 reserved_at_55[0x2]; 382 u8 outer_esp_spi[0x1]; 383 u8 reserved_at_58[0x2]; 384 u8 bth_dst_qp[0x1]; 385 u8 reserved_at_5b[0x5]; 386 387 u8 reserved_at_60[0x18]; 388 u8 metadata_reg_c_7[0x1]; 389 u8 metadata_reg_c_6[0x1]; 390 u8 metadata_reg_c_5[0x1]; 391 u8 metadata_reg_c_4[0x1]; 392 u8 metadata_reg_c_3[0x1]; 393 u8 metadata_reg_c_2[0x1]; 394 u8 metadata_reg_c_1[0x1]; 395 u8 metadata_reg_c_0[0x1]; 396 }; 397 398 struct mlx5_ifc_flow_table_fields_supported_2_bits { 399 u8 reserved_at_0[0xe]; 400 u8 bth_opcode[0x1]; 401 u8 reserved_at_f[0x11]; 402 403 u8 reserved_at_20[0x60]; 404 }; 405 406 struct mlx5_ifc_flow_table_prop_layout_bits { 407 u8 ft_support[0x1]; 408 u8 reserved_at_1[0x1]; 409 u8 flow_counter[0x1]; 410 u8 flow_modify_en[0x1]; 411 u8 modify_root[0x1]; 412 u8 identified_miss_table_mode[0x1]; 413 u8 flow_table_modify[0x1]; 414 u8 reformat[0x1]; 415 u8 decap[0x1]; 416 u8 reserved_at_9[0x1]; 417 u8 pop_vlan[0x1]; 418 u8 push_vlan[0x1]; 419 u8 reserved_at_c[0x1]; 420 u8 pop_vlan_2[0x1]; 421 u8 push_vlan_2[0x1]; 422 u8 reformat_and_vlan_action[0x1]; 423 u8 reserved_at_10[0x1]; 424 u8 sw_owner[0x1]; 425 u8 reformat_l3_tunnel_to_l2[0x1]; 426 u8 reformat_l2_to_l3_tunnel[0x1]; 427 u8 reformat_and_modify_action[0x1]; 428 u8 ignore_flow_level[0x1]; 429 u8 reserved_at_16[0x1]; 430 u8 table_miss_action_domain[0x1]; 431 u8 termination_table[0x1]; 432 u8 reformat_and_fwd_to_table[0x1]; 433 u8 reserved_at_1a[0x2]; 434 u8 ipsec_encrypt[0x1]; 435 u8 ipsec_decrypt[0x1]; 436 u8 sw_owner_v2[0x1]; 437 u8 reserved_at_1f[0x1]; 438 439 u8 termination_table_raw_traffic[0x1]; 440 u8 reserved_at_21[0x1]; 441 u8 log_max_ft_size[0x6]; 442 u8 log_max_modify_header_context[0x8]; 443 u8 max_modify_header_actions[0x8]; 444 u8 max_ft_level[0x8]; 445 446 u8 reserved_at_40[0x6]; 447 u8 execute_aso[0x1]; 448 u8 reserved_at_47[0x19]; 449 450 u8 reserved_at_60[0x2]; 451 u8 reformat_insert[0x1]; 452 u8 reformat_remove[0x1]; 453 u8 reserver_at_64[0x14]; 454 u8 log_max_ft_num[0x8]; 455 456 u8 reserved_at_80[0x10]; 457 u8 log_max_flow_counter[0x8]; 458 u8 log_max_destination[0x8]; 459 460 u8 reserved_at_a0[0x18]; 461 u8 log_max_flow[0x8]; 462 463 u8 reserved_at_c0[0x40]; 464 465 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 466 467 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 468 }; 469 470 struct mlx5_ifc_odp_per_transport_service_cap_bits { 471 u8 send[0x1]; 472 u8 receive[0x1]; 473 u8 write[0x1]; 474 u8 read[0x1]; 475 u8 atomic[0x1]; 476 u8 srq_receive[0x1]; 477 u8 reserved_at_6[0x1a]; 478 }; 479 480 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 481 u8 smac_47_16[0x20]; 482 483 u8 smac_15_0[0x10]; 484 u8 ethertype[0x10]; 485 486 u8 dmac_47_16[0x20]; 487 488 u8 dmac_15_0[0x10]; 489 u8 first_prio[0x3]; 490 u8 first_cfi[0x1]; 491 u8 first_vid[0xc]; 492 493 u8 ip_protocol[0x8]; 494 u8 ip_dscp[0x6]; 495 u8 ip_ecn[0x2]; 496 u8 cvlan_tag[0x1]; 497 u8 svlan_tag[0x1]; 498 u8 frag[0x1]; 499 u8 ip_version[0x4]; 500 u8 tcp_flags[0x9]; 501 502 u8 tcp_sport[0x10]; 503 u8 tcp_dport[0x10]; 504 505 u8 reserved_at_c0[0x10]; 506 u8 ipv4_ihl[0x4]; 507 u8 reserved_at_c4[0x4]; 508 509 u8 ttl_hoplimit[0x8]; 510 511 u8 udp_sport[0x10]; 512 u8 udp_dport[0x10]; 513 514 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 515 516 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 517 }; 518 519 struct mlx5_ifc_nvgre_key_bits { 520 u8 hi[0x18]; 521 u8 lo[0x8]; 522 }; 523 524 union mlx5_ifc_gre_key_bits { 525 struct mlx5_ifc_nvgre_key_bits nvgre; 526 u8 key[0x20]; 527 }; 528 529 struct mlx5_ifc_fte_match_set_misc_bits { 530 u8 gre_c_present[0x1]; 531 u8 reserved_at_1[0x1]; 532 u8 gre_k_present[0x1]; 533 u8 gre_s_present[0x1]; 534 u8 source_vhca_port[0x4]; 535 u8 source_sqn[0x18]; 536 537 u8 source_eswitch_owner_vhca_id[0x10]; 538 u8 source_port[0x10]; 539 540 u8 outer_second_prio[0x3]; 541 u8 outer_second_cfi[0x1]; 542 u8 outer_second_vid[0xc]; 543 u8 inner_second_prio[0x3]; 544 u8 inner_second_cfi[0x1]; 545 u8 inner_second_vid[0xc]; 546 547 u8 outer_second_cvlan_tag[0x1]; 548 u8 inner_second_cvlan_tag[0x1]; 549 u8 outer_second_svlan_tag[0x1]; 550 u8 inner_second_svlan_tag[0x1]; 551 u8 reserved_at_64[0xc]; 552 u8 gre_protocol[0x10]; 553 554 union mlx5_ifc_gre_key_bits gre_key; 555 556 u8 vxlan_vni[0x18]; 557 u8 bth_opcode[0x8]; 558 559 u8 geneve_vni[0x18]; 560 u8 reserved_at_d8[0x6]; 561 u8 geneve_tlv_option_0_exist[0x1]; 562 u8 geneve_oam[0x1]; 563 564 u8 reserved_at_e0[0xc]; 565 u8 outer_ipv6_flow_label[0x14]; 566 567 u8 reserved_at_100[0xc]; 568 u8 inner_ipv6_flow_label[0x14]; 569 570 u8 reserved_at_120[0xa]; 571 u8 geneve_opt_len[0x6]; 572 u8 geneve_protocol_type[0x10]; 573 574 u8 reserved_at_140[0x8]; 575 u8 bth_dst_qp[0x18]; 576 u8 reserved_at_160[0x20]; 577 u8 outer_esp_spi[0x20]; 578 u8 reserved_at_1a0[0x60]; 579 }; 580 581 struct mlx5_ifc_fte_match_mpls_bits { 582 u8 mpls_label[0x14]; 583 u8 mpls_exp[0x3]; 584 u8 mpls_s_bos[0x1]; 585 u8 mpls_ttl[0x8]; 586 }; 587 588 struct mlx5_ifc_fte_match_set_misc2_bits { 589 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 590 591 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 592 593 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 594 595 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 596 597 u8 metadata_reg_c_7[0x20]; 598 599 u8 metadata_reg_c_6[0x20]; 600 601 u8 metadata_reg_c_5[0x20]; 602 603 u8 metadata_reg_c_4[0x20]; 604 605 u8 metadata_reg_c_3[0x20]; 606 607 u8 metadata_reg_c_2[0x20]; 608 609 u8 metadata_reg_c_1[0x20]; 610 611 u8 metadata_reg_c_0[0x20]; 612 613 u8 metadata_reg_a[0x20]; 614 615 u8 reserved_at_1a0[0x60]; 616 }; 617 618 struct mlx5_ifc_fte_match_set_misc3_bits { 619 u8 inner_tcp_seq_num[0x20]; 620 621 u8 outer_tcp_seq_num[0x20]; 622 623 u8 inner_tcp_ack_num[0x20]; 624 625 u8 outer_tcp_ack_num[0x20]; 626 627 u8 reserved_at_80[0x8]; 628 u8 outer_vxlan_gpe_vni[0x18]; 629 630 u8 outer_vxlan_gpe_next_protocol[0x8]; 631 u8 outer_vxlan_gpe_flags[0x8]; 632 u8 reserved_at_b0[0x10]; 633 634 u8 icmp_header_data[0x20]; 635 636 u8 icmpv6_header_data[0x20]; 637 638 u8 icmp_type[0x8]; 639 u8 icmp_code[0x8]; 640 u8 icmpv6_type[0x8]; 641 u8 icmpv6_code[0x8]; 642 643 u8 geneve_tlv_option_0_data[0x20]; 644 645 u8 gtpu_teid[0x20]; 646 647 u8 gtpu_msg_type[0x8]; 648 u8 gtpu_msg_flags[0x8]; 649 u8 reserved_at_170[0x10]; 650 651 u8 gtpu_dw_2[0x20]; 652 653 u8 gtpu_first_ext_dw_0[0x20]; 654 655 u8 gtpu_dw_0[0x20]; 656 657 u8 reserved_at_1e0[0x20]; 658 }; 659 660 struct mlx5_ifc_fte_match_set_misc4_bits { 661 u8 prog_sample_field_value_0[0x20]; 662 663 u8 prog_sample_field_id_0[0x20]; 664 665 u8 prog_sample_field_value_1[0x20]; 666 667 u8 prog_sample_field_id_1[0x20]; 668 669 u8 prog_sample_field_value_2[0x20]; 670 671 u8 prog_sample_field_id_2[0x20]; 672 673 u8 prog_sample_field_value_3[0x20]; 674 675 u8 prog_sample_field_id_3[0x20]; 676 677 u8 reserved_at_100[0x100]; 678 }; 679 680 struct mlx5_ifc_fte_match_set_misc5_bits { 681 u8 macsec_tag_0[0x20]; 682 683 u8 macsec_tag_1[0x20]; 684 685 u8 macsec_tag_2[0x20]; 686 687 u8 macsec_tag_3[0x20]; 688 689 u8 tunnel_header_0[0x20]; 690 691 u8 tunnel_header_1[0x20]; 692 693 u8 tunnel_header_2[0x20]; 694 695 u8 tunnel_header_3[0x20]; 696 697 u8 reserved_at_100[0x100]; 698 }; 699 700 struct mlx5_ifc_cmd_pas_bits { 701 u8 pa_h[0x20]; 702 703 u8 pa_l[0x14]; 704 u8 reserved_at_34[0xc]; 705 }; 706 707 struct mlx5_ifc_uint64_bits { 708 u8 hi[0x20]; 709 710 u8 lo[0x20]; 711 }; 712 713 enum { 714 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 715 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 716 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 717 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 718 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 719 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 720 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 721 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 722 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 723 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 724 }; 725 726 struct mlx5_ifc_ads_bits { 727 u8 fl[0x1]; 728 u8 free_ar[0x1]; 729 u8 reserved_at_2[0xe]; 730 u8 pkey_index[0x10]; 731 732 u8 reserved_at_20[0x8]; 733 u8 grh[0x1]; 734 u8 mlid[0x7]; 735 u8 rlid[0x10]; 736 737 u8 ack_timeout[0x5]; 738 u8 reserved_at_45[0x3]; 739 u8 src_addr_index[0x8]; 740 u8 reserved_at_50[0x4]; 741 u8 stat_rate[0x4]; 742 u8 hop_limit[0x8]; 743 744 u8 reserved_at_60[0x4]; 745 u8 tclass[0x8]; 746 u8 flow_label[0x14]; 747 748 u8 rgid_rip[16][0x8]; 749 750 u8 reserved_at_100[0x4]; 751 u8 f_dscp[0x1]; 752 u8 f_ecn[0x1]; 753 u8 reserved_at_106[0x1]; 754 u8 f_eth_prio[0x1]; 755 u8 ecn[0x2]; 756 u8 dscp[0x6]; 757 u8 udp_sport[0x10]; 758 759 u8 dei_cfi[0x1]; 760 u8 eth_prio[0x3]; 761 u8 sl[0x4]; 762 u8 vhca_port_num[0x8]; 763 u8 rmac_47_32[0x10]; 764 765 u8 rmac_31_0[0x20]; 766 }; 767 768 struct mlx5_ifc_flow_table_nic_cap_bits { 769 u8 nic_rx_multi_path_tirs[0x1]; 770 u8 nic_rx_multi_path_tirs_fts[0x1]; 771 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 772 u8 reserved_at_3[0x4]; 773 u8 sw_owner_reformat_supported[0x1]; 774 u8 reserved_at_8[0x18]; 775 776 u8 encap_general_header[0x1]; 777 u8 reserved_at_21[0xa]; 778 u8 log_max_packet_reformat_context[0x5]; 779 u8 reserved_at_30[0x6]; 780 u8 max_encap_header_size[0xa]; 781 u8 reserved_at_40[0x1c0]; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 784 785 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 786 787 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 788 789 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 790 791 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 792 793 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 794 795 u8 reserved_at_e00[0x700]; 796 797 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 798 799 u8 reserved_at_1580[0x280]; 800 801 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 802 803 u8 reserved_at_1880[0x780]; 804 805 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 806 807 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 808 809 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 810 811 u8 reserved_at_20c0[0x5f40]; 812 }; 813 814 struct mlx5_ifc_port_selection_cap_bits { 815 u8 reserved_at_0[0x10]; 816 u8 port_select_flow_table[0x1]; 817 u8 reserved_at_11[0xf]; 818 819 u8 reserved_at_20[0x1e0]; 820 821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 822 823 u8 reserved_at_400[0x7c00]; 824 }; 825 826 enum { 827 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 828 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 829 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 830 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 831 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 832 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 833 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 834 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 835 }; 836 837 struct mlx5_ifc_flow_table_eswitch_cap_bits { 838 u8 fdb_to_vport_reg_c_id[0x8]; 839 u8 reserved_at_8[0xd]; 840 u8 fdb_modify_header_fwd_to_table[0x1]; 841 u8 fdb_ipv4_ttl_modify[0x1]; 842 u8 flow_source[0x1]; 843 u8 reserved_at_18[0x2]; 844 u8 multi_fdb_encap[0x1]; 845 u8 egress_acl_forward_to_vport[0x1]; 846 u8 fdb_multi_path_to_table[0x1]; 847 u8 reserved_at_1d[0x3]; 848 849 u8 reserved_at_20[0x1e0]; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 856 857 u8 reserved_at_800[0x1000]; 858 859 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 860 861 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 862 863 u8 sw_steering_uplink_icm_address_rx[0x40]; 864 865 u8 sw_steering_uplink_icm_address_tx[0x40]; 866 867 u8 reserved_at_1900[0x6700]; 868 }; 869 870 enum { 871 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 872 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 873 }; 874 875 struct mlx5_ifc_e_switch_cap_bits { 876 u8 vport_svlan_strip[0x1]; 877 u8 vport_cvlan_strip[0x1]; 878 u8 vport_svlan_insert[0x1]; 879 u8 vport_cvlan_insert_if_not_exist[0x1]; 880 u8 vport_cvlan_insert_overwrite[0x1]; 881 u8 reserved_at_5[0x2]; 882 u8 esw_shared_ingress_acl[0x1]; 883 u8 esw_uplink_ingress_acl[0x1]; 884 u8 root_ft_on_other_esw[0x1]; 885 u8 reserved_at_a[0xf]; 886 u8 esw_functions_changed[0x1]; 887 u8 reserved_at_1a[0x1]; 888 u8 ecpf_vport_exists[0x1]; 889 u8 counter_eswitch_affinity[0x1]; 890 u8 merged_eswitch[0x1]; 891 u8 nic_vport_node_guid_modify[0x1]; 892 u8 nic_vport_port_guid_modify[0x1]; 893 894 u8 vxlan_encap_decap[0x1]; 895 u8 nvgre_encap_decap[0x1]; 896 u8 reserved_at_22[0x1]; 897 u8 log_max_fdb_encap_uplink[0x5]; 898 u8 reserved_at_21[0x3]; 899 u8 log_max_packet_reformat_context[0x5]; 900 u8 reserved_2b[0x6]; 901 u8 max_encap_header_size[0xa]; 902 903 u8 reserved_at_40[0xb]; 904 u8 log_max_esw_sf[0x5]; 905 u8 esw_sf_base_id[0x10]; 906 907 u8 reserved_at_60[0x7a0]; 908 909 }; 910 911 struct mlx5_ifc_qos_cap_bits { 912 u8 packet_pacing[0x1]; 913 u8 esw_scheduling[0x1]; 914 u8 esw_bw_share[0x1]; 915 u8 esw_rate_limit[0x1]; 916 u8 reserved_at_4[0x1]; 917 u8 packet_pacing_burst_bound[0x1]; 918 u8 packet_pacing_typical_size[0x1]; 919 u8 reserved_at_7[0x1]; 920 u8 nic_sq_scheduling[0x1]; 921 u8 nic_bw_share[0x1]; 922 u8 nic_rate_limit[0x1]; 923 u8 packet_pacing_uid[0x1]; 924 u8 log_esw_max_sched_depth[0x4]; 925 u8 reserved_at_10[0x10]; 926 927 u8 reserved_at_20[0xb]; 928 u8 log_max_qos_nic_queue_group[0x5]; 929 u8 reserved_at_30[0x10]; 930 931 u8 packet_pacing_max_rate[0x20]; 932 933 u8 packet_pacing_min_rate[0x20]; 934 935 u8 reserved_at_80[0x10]; 936 u8 packet_pacing_rate_table_size[0x10]; 937 938 u8 esw_element_type[0x10]; 939 u8 esw_tsar_type[0x10]; 940 941 u8 reserved_at_c0[0x10]; 942 u8 max_qos_para_vport[0x10]; 943 944 u8 max_tsar_bw_share[0x20]; 945 946 u8 reserved_at_100[0x20]; 947 948 u8 reserved_at_120[0x3]; 949 u8 log_meter_aso_granularity[0x5]; 950 u8 reserved_at_128[0x3]; 951 u8 log_meter_aso_max_alloc[0x5]; 952 u8 reserved_at_130[0x3]; 953 u8 log_max_num_meter_aso[0x5]; 954 u8 reserved_at_138[0x8]; 955 956 u8 reserved_at_140[0x6c0]; 957 }; 958 959 struct mlx5_ifc_debug_cap_bits { 960 u8 core_dump_general[0x1]; 961 u8 core_dump_qp[0x1]; 962 u8 reserved_at_2[0x7]; 963 u8 resource_dump[0x1]; 964 u8 reserved_at_a[0x16]; 965 966 u8 reserved_at_20[0x2]; 967 u8 stall_detect[0x1]; 968 u8 reserved_at_23[0x1d]; 969 970 u8 reserved_at_40[0x7c0]; 971 }; 972 973 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 974 u8 csum_cap[0x1]; 975 u8 vlan_cap[0x1]; 976 u8 lro_cap[0x1]; 977 u8 lro_psh_flag[0x1]; 978 u8 lro_time_stamp[0x1]; 979 u8 reserved_at_5[0x2]; 980 u8 wqe_vlan_insert[0x1]; 981 u8 self_lb_en_modifiable[0x1]; 982 u8 reserved_at_9[0x2]; 983 u8 max_lso_cap[0x5]; 984 u8 multi_pkt_send_wqe[0x2]; 985 u8 wqe_inline_mode[0x2]; 986 u8 rss_ind_tbl_cap[0x4]; 987 u8 reg_umr_sq[0x1]; 988 u8 scatter_fcs[0x1]; 989 u8 enhanced_multi_pkt_send_wqe[0x1]; 990 u8 tunnel_lso_const_out_ip_id[0x1]; 991 u8 tunnel_lro_gre[0x1]; 992 u8 tunnel_lro_vxlan[0x1]; 993 u8 tunnel_stateless_gre[0x1]; 994 u8 tunnel_stateless_vxlan[0x1]; 995 996 u8 swp[0x1]; 997 u8 swp_csum[0x1]; 998 u8 swp_lso[0x1]; 999 u8 cqe_checksum_full[0x1]; 1000 u8 tunnel_stateless_geneve_tx[0x1]; 1001 u8 tunnel_stateless_mpls_over_udp[0x1]; 1002 u8 tunnel_stateless_mpls_over_gre[0x1]; 1003 u8 tunnel_stateless_vxlan_gpe[0x1]; 1004 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1005 u8 tunnel_stateless_ip_over_ip[0x1]; 1006 u8 insert_trailer[0x1]; 1007 u8 reserved_at_2b[0x1]; 1008 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1009 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1010 u8 reserved_at_2e[0x2]; 1011 u8 max_vxlan_udp_ports[0x8]; 1012 u8 reserved_at_38[0x6]; 1013 u8 max_geneve_opt_len[0x1]; 1014 u8 tunnel_stateless_geneve_rx[0x1]; 1015 1016 u8 reserved_at_40[0x10]; 1017 u8 lro_min_mss_size[0x10]; 1018 1019 u8 reserved_at_60[0x120]; 1020 1021 u8 lro_timer_supported_periods[4][0x20]; 1022 1023 u8 reserved_at_200[0x600]; 1024 }; 1025 1026 enum { 1027 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1028 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1029 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1030 }; 1031 1032 struct mlx5_ifc_roce_cap_bits { 1033 u8 roce_apm[0x1]; 1034 u8 reserved_at_1[0x3]; 1035 u8 sw_r_roce_src_udp_port[0x1]; 1036 u8 fl_rc_qp_when_roce_disabled[0x1]; 1037 u8 fl_rc_qp_when_roce_enabled[0x1]; 1038 u8 reserved_at_7[0x17]; 1039 u8 qp_ts_format[0x2]; 1040 1041 u8 reserved_at_20[0x60]; 1042 1043 u8 reserved_at_80[0xc]; 1044 u8 l3_type[0x4]; 1045 u8 reserved_at_90[0x8]; 1046 u8 roce_version[0x8]; 1047 1048 u8 reserved_at_a0[0x10]; 1049 u8 r_roce_dest_udp_port[0x10]; 1050 1051 u8 r_roce_max_src_udp_port[0x10]; 1052 u8 r_roce_min_src_udp_port[0x10]; 1053 1054 u8 reserved_at_e0[0x10]; 1055 u8 roce_address_table_size[0x10]; 1056 1057 u8 reserved_at_100[0x700]; 1058 }; 1059 1060 struct mlx5_ifc_sync_steering_in_bits { 1061 u8 opcode[0x10]; 1062 u8 uid[0x10]; 1063 1064 u8 reserved_at_20[0x10]; 1065 u8 op_mod[0x10]; 1066 1067 u8 reserved_at_40[0xc0]; 1068 }; 1069 1070 struct mlx5_ifc_sync_steering_out_bits { 1071 u8 status[0x8]; 1072 u8 reserved_at_8[0x18]; 1073 1074 u8 syndrome[0x20]; 1075 1076 u8 reserved_at_40[0x40]; 1077 }; 1078 1079 struct mlx5_ifc_device_mem_cap_bits { 1080 u8 memic[0x1]; 1081 u8 reserved_at_1[0x1f]; 1082 1083 u8 reserved_at_20[0xb]; 1084 u8 log_min_memic_alloc_size[0x5]; 1085 u8 reserved_at_30[0x8]; 1086 u8 log_max_memic_addr_alignment[0x8]; 1087 1088 u8 memic_bar_start_addr[0x40]; 1089 1090 u8 memic_bar_size[0x20]; 1091 1092 u8 max_memic_size[0x20]; 1093 1094 u8 steering_sw_icm_start_address[0x40]; 1095 1096 u8 reserved_at_100[0x8]; 1097 u8 log_header_modify_sw_icm_size[0x8]; 1098 u8 reserved_at_110[0x2]; 1099 u8 log_sw_icm_alloc_granularity[0x6]; 1100 u8 log_steering_sw_icm_size[0x8]; 1101 1102 u8 reserved_at_120[0x18]; 1103 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1104 1105 u8 header_modify_sw_icm_start_address[0x40]; 1106 1107 u8 reserved_at_180[0x40]; 1108 1109 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1110 1111 u8 memic_operations[0x20]; 1112 1113 u8 reserved_at_220[0x5e0]; 1114 }; 1115 1116 struct mlx5_ifc_device_event_cap_bits { 1117 u8 user_affiliated_events[4][0x40]; 1118 1119 u8 user_unaffiliated_events[4][0x40]; 1120 }; 1121 1122 struct mlx5_ifc_virtio_emulation_cap_bits { 1123 u8 desc_tunnel_offload_type[0x1]; 1124 u8 eth_frame_offload_type[0x1]; 1125 u8 virtio_version_1_0[0x1]; 1126 u8 device_features_bits_mask[0xd]; 1127 u8 event_mode[0x8]; 1128 u8 virtio_queue_type[0x8]; 1129 1130 u8 max_tunnel_desc[0x10]; 1131 u8 reserved_at_30[0x3]; 1132 u8 log_doorbell_stride[0x5]; 1133 u8 reserved_at_38[0x3]; 1134 u8 log_doorbell_bar_size[0x5]; 1135 1136 u8 doorbell_bar_offset[0x40]; 1137 1138 u8 max_emulated_devices[0x8]; 1139 u8 max_num_virtio_queues[0x18]; 1140 1141 u8 reserved_at_a0[0x60]; 1142 1143 u8 umem_1_buffer_param_a[0x20]; 1144 1145 u8 umem_1_buffer_param_b[0x20]; 1146 1147 u8 umem_2_buffer_param_a[0x20]; 1148 1149 u8 umem_2_buffer_param_b[0x20]; 1150 1151 u8 umem_3_buffer_param_a[0x20]; 1152 1153 u8 umem_3_buffer_param_b[0x20]; 1154 1155 u8 reserved_at_1c0[0x640]; 1156 }; 1157 1158 enum { 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1167 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1168 }; 1169 1170 enum { 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1179 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1180 }; 1181 1182 struct mlx5_ifc_atomic_caps_bits { 1183 u8 reserved_at_0[0x40]; 1184 1185 u8 atomic_req_8B_endianness_mode[0x2]; 1186 u8 reserved_at_42[0x4]; 1187 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1188 1189 u8 reserved_at_47[0x19]; 1190 1191 u8 reserved_at_60[0x20]; 1192 1193 u8 reserved_at_80[0x10]; 1194 u8 atomic_operations[0x10]; 1195 1196 u8 reserved_at_a0[0x10]; 1197 u8 atomic_size_qp[0x10]; 1198 1199 u8 reserved_at_c0[0x10]; 1200 u8 atomic_size_dc[0x10]; 1201 1202 u8 reserved_at_e0[0x720]; 1203 }; 1204 1205 struct mlx5_ifc_odp_cap_bits { 1206 u8 reserved_at_0[0x40]; 1207 1208 u8 sig[0x1]; 1209 u8 reserved_at_41[0x1f]; 1210 1211 u8 reserved_at_60[0x20]; 1212 1213 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1214 1215 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1216 1217 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1218 1219 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1220 1221 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1222 1223 u8 reserved_at_120[0x6E0]; 1224 }; 1225 1226 struct mlx5_ifc_calc_op { 1227 u8 reserved_at_0[0x10]; 1228 u8 reserved_at_10[0x9]; 1229 u8 op_swap_endianness[0x1]; 1230 u8 op_min[0x1]; 1231 u8 op_xor[0x1]; 1232 u8 op_or[0x1]; 1233 u8 op_and[0x1]; 1234 u8 op_max[0x1]; 1235 u8 op_add[0x1]; 1236 }; 1237 1238 struct mlx5_ifc_vector_calc_cap_bits { 1239 u8 calc_matrix[0x1]; 1240 u8 reserved_at_1[0x1f]; 1241 u8 reserved_at_20[0x8]; 1242 u8 max_vec_count[0x8]; 1243 u8 reserved_at_30[0xd]; 1244 u8 max_chunk_size[0x3]; 1245 struct mlx5_ifc_calc_op calc0; 1246 struct mlx5_ifc_calc_op calc1; 1247 struct mlx5_ifc_calc_op calc2; 1248 struct mlx5_ifc_calc_op calc3; 1249 1250 u8 reserved_at_c0[0x720]; 1251 }; 1252 1253 struct mlx5_ifc_tls_cap_bits { 1254 u8 tls_1_2_aes_gcm_128[0x1]; 1255 u8 tls_1_3_aes_gcm_128[0x1]; 1256 u8 tls_1_2_aes_gcm_256[0x1]; 1257 u8 tls_1_3_aes_gcm_256[0x1]; 1258 u8 reserved_at_4[0x1c]; 1259 1260 u8 reserved_at_20[0x7e0]; 1261 }; 1262 1263 struct mlx5_ifc_ipsec_cap_bits { 1264 u8 ipsec_full_offload[0x1]; 1265 u8 ipsec_crypto_offload[0x1]; 1266 u8 ipsec_esn[0x1]; 1267 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1268 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1269 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1270 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1271 u8 reserved_at_7[0x4]; 1272 u8 log_max_ipsec_offload[0x5]; 1273 u8 reserved_at_10[0x10]; 1274 1275 u8 min_log_ipsec_full_replay_window[0x8]; 1276 u8 max_log_ipsec_full_replay_window[0x8]; 1277 u8 reserved_at_30[0x7d0]; 1278 }; 1279 1280 enum { 1281 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1282 MLX5_WQ_TYPE_CYCLIC = 0x1, 1283 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1284 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1285 }; 1286 1287 enum { 1288 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1289 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1290 }; 1291 1292 enum { 1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1297 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1298 }; 1299 1300 enum { 1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1306 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1307 }; 1308 1309 enum { 1310 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1311 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1312 }; 1313 1314 enum { 1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1317 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1318 }; 1319 1320 enum { 1321 MLX5_CAP_PORT_TYPE_IB = 0x0, 1322 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1323 }; 1324 1325 enum { 1326 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1327 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1328 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1329 }; 1330 1331 enum { 1332 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1333 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1334 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1335 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1336 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1337 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1338 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1339 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1340 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1341 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1342 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1343 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1344 }; 1345 1346 enum { 1347 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1348 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1349 }; 1350 1351 #define MLX5_FC_BULK_SIZE_FACTOR 128 1352 1353 enum mlx5_fc_bulk_alloc_bitmask { 1354 MLX5_FC_BULK_128 = (1 << 0), 1355 MLX5_FC_BULK_256 = (1 << 1), 1356 MLX5_FC_BULK_512 = (1 << 2), 1357 MLX5_FC_BULK_1024 = (1 << 3), 1358 MLX5_FC_BULK_2048 = (1 << 4), 1359 MLX5_FC_BULK_4096 = (1 << 5), 1360 MLX5_FC_BULK_8192 = (1 << 6), 1361 MLX5_FC_BULK_16384 = (1 << 7), 1362 }; 1363 1364 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1365 1366 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1367 1368 enum { 1369 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1370 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1371 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1372 }; 1373 1374 struct mlx5_ifc_cmd_hca_cap_bits { 1375 u8 reserved_at_0[0x10]; 1376 u8 shared_object_to_user_object_allowed[0x1]; 1377 u8 reserved_at_13[0xe]; 1378 u8 vhca_resource_manager[0x1]; 1379 1380 u8 hca_cap_2[0x1]; 1381 u8 create_lag_when_not_master_up[0x1]; 1382 u8 dtor[0x1]; 1383 u8 event_on_vhca_state_teardown_request[0x1]; 1384 u8 event_on_vhca_state_in_use[0x1]; 1385 u8 event_on_vhca_state_active[0x1]; 1386 u8 event_on_vhca_state_allocated[0x1]; 1387 u8 event_on_vhca_state_invalid[0x1]; 1388 u8 reserved_at_28[0x8]; 1389 u8 vhca_id[0x10]; 1390 1391 u8 reserved_at_40[0x40]; 1392 1393 u8 log_max_srq_sz[0x8]; 1394 u8 log_max_qp_sz[0x8]; 1395 u8 event_cap[0x1]; 1396 u8 reserved_at_91[0x2]; 1397 u8 isolate_vl_tc_new[0x1]; 1398 u8 reserved_at_94[0x4]; 1399 u8 prio_tag_required[0x1]; 1400 u8 reserved_at_99[0x2]; 1401 u8 log_max_qp[0x5]; 1402 1403 u8 reserved_at_a0[0x3]; 1404 u8 ece_support[0x1]; 1405 u8 reserved_at_a4[0x5]; 1406 u8 reg_c_preserve[0x1]; 1407 u8 reserved_at_aa[0x1]; 1408 u8 log_max_srq[0x5]; 1409 u8 reserved_at_b0[0x1]; 1410 u8 uplink_follow[0x1]; 1411 u8 ts_cqe_to_dest_cqn[0x1]; 1412 u8 reserved_at_b3[0x7]; 1413 u8 shampo[0x1]; 1414 u8 reserved_at_bb[0x5]; 1415 1416 u8 max_sgl_for_optimized_performance[0x8]; 1417 u8 log_max_cq_sz[0x8]; 1418 u8 relaxed_ordering_write_umr[0x1]; 1419 u8 relaxed_ordering_read_umr[0x1]; 1420 u8 reserved_at_d2[0x7]; 1421 u8 virtio_net_device_emualtion_manager[0x1]; 1422 u8 virtio_blk_device_emualtion_manager[0x1]; 1423 u8 log_max_cq[0x5]; 1424 1425 u8 log_max_eq_sz[0x8]; 1426 u8 relaxed_ordering_write[0x1]; 1427 u8 relaxed_ordering_read[0x1]; 1428 u8 log_max_mkey[0x6]; 1429 u8 reserved_at_f0[0x8]; 1430 u8 dump_fill_mkey[0x1]; 1431 u8 reserved_at_f9[0x2]; 1432 u8 fast_teardown[0x1]; 1433 u8 log_max_eq[0x4]; 1434 1435 u8 max_indirection[0x8]; 1436 u8 fixed_buffer_size[0x1]; 1437 u8 log_max_mrw_sz[0x7]; 1438 u8 force_teardown[0x1]; 1439 u8 reserved_at_111[0x1]; 1440 u8 log_max_bsf_list_size[0x6]; 1441 u8 umr_extended_translation_offset[0x1]; 1442 u8 null_mkey[0x1]; 1443 u8 log_max_klm_list_size[0x6]; 1444 1445 u8 reserved_at_120[0xa]; 1446 u8 log_max_ra_req_dc[0x6]; 1447 u8 reserved_at_130[0x9]; 1448 u8 vnic_env_cq_overrun[0x1]; 1449 u8 log_max_ra_res_dc[0x6]; 1450 1451 u8 reserved_at_140[0x5]; 1452 u8 release_all_pages[0x1]; 1453 u8 must_not_use[0x1]; 1454 u8 reserved_at_147[0x2]; 1455 u8 roce_accl[0x1]; 1456 u8 log_max_ra_req_qp[0x6]; 1457 u8 reserved_at_150[0xa]; 1458 u8 log_max_ra_res_qp[0x6]; 1459 1460 u8 end_pad[0x1]; 1461 u8 cc_query_allowed[0x1]; 1462 u8 cc_modify_allowed[0x1]; 1463 u8 start_pad[0x1]; 1464 u8 cache_line_128byte[0x1]; 1465 u8 reserved_at_165[0x4]; 1466 u8 rts2rts_qp_counters_set_id[0x1]; 1467 u8 reserved_at_16a[0x2]; 1468 u8 vnic_env_int_rq_oob[0x1]; 1469 u8 sbcam_reg[0x1]; 1470 u8 reserved_at_16e[0x1]; 1471 u8 qcam_reg[0x1]; 1472 u8 gid_table_size[0x10]; 1473 1474 u8 out_of_seq_cnt[0x1]; 1475 u8 vport_counters[0x1]; 1476 u8 retransmission_q_counters[0x1]; 1477 u8 debug[0x1]; 1478 u8 modify_rq_counter_set_id[0x1]; 1479 u8 rq_delay_drop[0x1]; 1480 u8 max_qp_cnt[0xa]; 1481 u8 pkey_table_size[0x10]; 1482 1483 u8 vport_group_manager[0x1]; 1484 u8 vhca_group_manager[0x1]; 1485 u8 ib_virt[0x1]; 1486 u8 eth_virt[0x1]; 1487 u8 vnic_env_queue_counters[0x1]; 1488 u8 ets[0x1]; 1489 u8 nic_flow_table[0x1]; 1490 u8 eswitch_manager[0x1]; 1491 u8 device_memory[0x1]; 1492 u8 mcam_reg[0x1]; 1493 u8 pcam_reg[0x1]; 1494 u8 local_ca_ack_delay[0x5]; 1495 u8 port_module_event[0x1]; 1496 u8 enhanced_error_q_counters[0x1]; 1497 u8 ports_check[0x1]; 1498 u8 reserved_at_1b3[0x1]; 1499 u8 disable_link_up[0x1]; 1500 u8 beacon_led[0x1]; 1501 u8 port_type[0x2]; 1502 u8 num_ports[0x8]; 1503 1504 u8 reserved_at_1c0[0x1]; 1505 u8 pps[0x1]; 1506 u8 pps_modify[0x1]; 1507 u8 log_max_msg[0x5]; 1508 u8 reserved_at_1c8[0x4]; 1509 u8 max_tc[0x4]; 1510 u8 temp_warn_event[0x1]; 1511 u8 dcbx[0x1]; 1512 u8 general_notification_event[0x1]; 1513 u8 reserved_at_1d3[0x2]; 1514 u8 fpga[0x1]; 1515 u8 rol_s[0x1]; 1516 u8 rol_g[0x1]; 1517 u8 reserved_at_1d8[0x1]; 1518 u8 wol_s[0x1]; 1519 u8 wol_g[0x1]; 1520 u8 wol_a[0x1]; 1521 u8 wol_b[0x1]; 1522 u8 wol_m[0x1]; 1523 u8 wol_u[0x1]; 1524 u8 wol_p[0x1]; 1525 1526 u8 stat_rate_support[0x10]; 1527 u8 reserved_at_1f0[0x1]; 1528 u8 pci_sync_for_fw_update_event[0x1]; 1529 u8 reserved_at_1f2[0x6]; 1530 u8 init2_lag_tx_port_affinity[0x1]; 1531 u8 reserved_at_1fa[0x3]; 1532 u8 cqe_version[0x4]; 1533 1534 u8 compact_address_vector[0x1]; 1535 u8 striding_rq[0x1]; 1536 u8 reserved_at_202[0x1]; 1537 u8 ipoib_enhanced_offloads[0x1]; 1538 u8 ipoib_basic_offloads[0x1]; 1539 u8 reserved_at_205[0x1]; 1540 u8 repeated_block_disabled[0x1]; 1541 u8 umr_modify_entity_size_disabled[0x1]; 1542 u8 umr_modify_atomic_disabled[0x1]; 1543 u8 umr_indirect_mkey_disabled[0x1]; 1544 u8 umr_fence[0x2]; 1545 u8 dc_req_scat_data_cqe[0x1]; 1546 u8 reserved_at_20d[0x2]; 1547 u8 drain_sigerr[0x1]; 1548 u8 cmdif_checksum[0x2]; 1549 u8 sigerr_cqe[0x1]; 1550 u8 reserved_at_213[0x1]; 1551 u8 wq_signature[0x1]; 1552 u8 sctr_data_cqe[0x1]; 1553 u8 reserved_at_216[0x1]; 1554 u8 sho[0x1]; 1555 u8 tph[0x1]; 1556 u8 rf[0x1]; 1557 u8 dct[0x1]; 1558 u8 qos[0x1]; 1559 u8 eth_net_offloads[0x1]; 1560 u8 roce[0x1]; 1561 u8 atomic[0x1]; 1562 u8 reserved_at_21f[0x1]; 1563 1564 u8 cq_oi[0x1]; 1565 u8 cq_resize[0x1]; 1566 u8 cq_moderation[0x1]; 1567 u8 reserved_at_223[0x3]; 1568 u8 cq_eq_remap[0x1]; 1569 u8 pg[0x1]; 1570 u8 block_lb_mc[0x1]; 1571 u8 reserved_at_229[0x1]; 1572 u8 scqe_break_moderation[0x1]; 1573 u8 cq_period_start_from_cqe[0x1]; 1574 u8 cd[0x1]; 1575 u8 reserved_at_22d[0x1]; 1576 u8 apm[0x1]; 1577 u8 vector_calc[0x1]; 1578 u8 umr_ptr_rlky[0x1]; 1579 u8 imaicl[0x1]; 1580 u8 qp_packet_based[0x1]; 1581 u8 reserved_at_233[0x3]; 1582 u8 qkv[0x1]; 1583 u8 pkv[0x1]; 1584 u8 set_deth_sqpn[0x1]; 1585 u8 reserved_at_239[0x3]; 1586 u8 xrc[0x1]; 1587 u8 ud[0x1]; 1588 u8 uc[0x1]; 1589 u8 rc[0x1]; 1590 1591 u8 uar_4k[0x1]; 1592 u8 reserved_at_241[0x9]; 1593 u8 uar_sz[0x6]; 1594 u8 port_selection_cap[0x1]; 1595 u8 reserved_at_248[0x1]; 1596 u8 umem_uid_0[0x1]; 1597 u8 reserved_at_250[0x5]; 1598 u8 log_pg_sz[0x8]; 1599 1600 u8 bf[0x1]; 1601 u8 driver_version[0x1]; 1602 u8 pad_tx_eth_packet[0x1]; 1603 u8 reserved_at_263[0x3]; 1604 u8 mkey_by_name[0x1]; 1605 u8 reserved_at_267[0x4]; 1606 1607 u8 log_bf_reg_size[0x5]; 1608 1609 u8 reserved_at_270[0x6]; 1610 u8 lag_dct[0x2]; 1611 u8 lag_tx_port_affinity[0x1]; 1612 u8 lag_native_fdb_selection[0x1]; 1613 u8 reserved_at_27a[0x1]; 1614 u8 lag_master[0x1]; 1615 u8 num_lag_ports[0x4]; 1616 1617 u8 reserved_at_280[0x10]; 1618 u8 max_wqe_sz_sq[0x10]; 1619 1620 u8 reserved_at_2a0[0x10]; 1621 u8 max_wqe_sz_rq[0x10]; 1622 1623 u8 max_flow_counter_31_16[0x10]; 1624 u8 max_wqe_sz_sq_dc[0x10]; 1625 1626 u8 reserved_at_2e0[0x7]; 1627 u8 max_qp_mcg[0x19]; 1628 1629 u8 reserved_at_300[0x10]; 1630 u8 flow_counter_bulk_alloc[0x8]; 1631 u8 log_max_mcg[0x8]; 1632 1633 u8 reserved_at_320[0x3]; 1634 u8 log_max_transport_domain[0x5]; 1635 u8 reserved_at_328[0x3]; 1636 u8 log_max_pd[0x5]; 1637 u8 reserved_at_330[0xb]; 1638 u8 log_max_xrcd[0x5]; 1639 1640 u8 nic_receive_steering_discard[0x1]; 1641 u8 receive_discard_vport_down[0x1]; 1642 u8 transmit_discard_vport_down[0x1]; 1643 u8 eq_overrun_count[0x1]; 1644 u8 reserved_at_344[0x1]; 1645 u8 invalid_command_count[0x1]; 1646 u8 quota_exceeded_count[0x1]; 1647 u8 reserved_at_347[0x1]; 1648 u8 log_max_flow_counter_bulk[0x8]; 1649 u8 max_flow_counter_15_0[0x10]; 1650 1651 1652 u8 reserved_at_360[0x3]; 1653 u8 log_max_rq[0x5]; 1654 u8 reserved_at_368[0x3]; 1655 u8 log_max_sq[0x5]; 1656 u8 reserved_at_370[0x3]; 1657 u8 log_max_tir[0x5]; 1658 u8 reserved_at_378[0x3]; 1659 u8 log_max_tis[0x5]; 1660 1661 u8 basic_cyclic_rcv_wqe[0x1]; 1662 u8 reserved_at_381[0x2]; 1663 u8 log_max_rmp[0x5]; 1664 u8 reserved_at_388[0x3]; 1665 u8 log_max_rqt[0x5]; 1666 u8 reserved_at_390[0x3]; 1667 u8 log_max_rqt_size[0x5]; 1668 u8 reserved_at_398[0x3]; 1669 u8 log_max_tis_per_sq[0x5]; 1670 1671 u8 ext_stride_num_range[0x1]; 1672 u8 roce_rw_supported[0x1]; 1673 u8 log_max_current_uc_list_wr_supported[0x1]; 1674 u8 log_max_stride_sz_rq[0x5]; 1675 u8 reserved_at_3a8[0x3]; 1676 u8 log_min_stride_sz_rq[0x5]; 1677 u8 reserved_at_3b0[0x3]; 1678 u8 log_max_stride_sz_sq[0x5]; 1679 u8 reserved_at_3b8[0x3]; 1680 u8 log_min_stride_sz_sq[0x5]; 1681 1682 u8 hairpin[0x1]; 1683 u8 reserved_at_3c1[0x2]; 1684 u8 log_max_hairpin_queues[0x5]; 1685 u8 reserved_at_3c8[0x3]; 1686 u8 log_max_hairpin_wq_data_sz[0x5]; 1687 u8 reserved_at_3d0[0x3]; 1688 u8 log_max_hairpin_num_packets[0x5]; 1689 u8 reserved_at_3d8[0x3]; 1690 u8 log_max_wq_sz[0x5]; 1691 1692 u8 nic_vport_change_event[0x1]; 1693 u8 disable_local_lb_uc[0x1]; 1694 u8 disable_local_lb_mc[0x1]; 1695 u8 log_min_hairpin_wq_data_sz[0x5]; 1696 u8 reserved_at_3e8[0x2]; 1697 u8 vhca_state[0x1]; 1698 u8 log_max_vlan_list[0x5]; 1699 u8 reserved_at_3f0[0x3]; 1700 u8 log_max_current_mc_list[0x5]; 1701 u8 reserved_at_3f8[0x3]; 1702 u8 log_max_current_uc_list[0x5]; 1703 1704 u8 general_obj_types[0x40]; 1705 1706 u8 sq_ts_format[0x2]; 1707 u8 rq_ts_format[0x2]; 1708 u8 steering_format_version[0x4]; 1709 u8 create_qp_start_hint[0x18]; 1710 1711 u8 reserved_at_460[0x3]; 1712 u8 log_max_uctx[0x5]; 1713 u8 reserved_at_468[0x2]; 1714 u8 ipsec_offload[0x1]; 1715 u8 log_max_umem[0x5]; 1716 u8 max_num_eqs[0x10]; 1717 1718 u8 reserved_at_480[0x1]; 1719 u8 tls_tx[0x1]; 1720 u8 tls_rx[0x1]; 1721 u8 log_max_l2_table[0x5]; 1722 u8 reserved_at_488[0x8]; 1723 u8 log_uar_page_sz[0x10]; 1724 1725 u8 reserved_at_4a0[0x20]; 1726 u8 device_frequency_mhz[0x20]; 1727 u8 device_frequency_khz[0x20]; 1728 1729 u8 reserved_at_500[0x20]; 1730 u8 num_of_uars_per_page[0x20]; 1731 1732 u8 flex_parser_protocols[0x20]; 1733 1734 u8 max_geneve_tlv_options[0x8]; 1735 u8 reserved_at_568[0x3]; 1736 u8 max_geneve_tlv_option_data_len[0x5]; 1737 u8 reserved_at_570[0x9]; 1738 u8 adv_virtualization[0x1]; 1739 u8 reserved_at_57a[0x6]; 1740 1741 u8 reserved_at_580[0xb]; 1742 u8 log_max_dci_stream_channels[0x5]; 1743 u8 reserved_at_590[0x3]; 1744 u8 log_max_dci_errored_streams[0x5]; 1745 u8 reserved_at_598[0x8]; 1746 1747 u8 reserved_at_5a0[0x10]; 1748 u8 enhanced_cqe_compression[0x1]; 1749 u8 reserved_at_5b1[0x2]; 1750 u8 log_max_dek[0x5]; 1751 u8 reserved_at_5b8[0x4]; 1752 u8 mini_cqe_resp_stride_index[0x1]; 1753 u8 cqe_128_always[0x1]; 1754 u8 cqe_compression_128[0x1]; 1755 u8 cqe_compression[0x1]; 1756 1757 u8 cqe_compression_timeout[0x10]; 1758 u8 cqe_compression_max_num[0x10]; 1759 1760 u8 reserved_at_5e0[0x8]; 1761 u8 flex_parser_id_gtpu_dw_0[0x4]; 1762 u8 reserved_at_5ec[0x4]; 1763 u8 tag_matching[0x1]; 1764 u8 rndv_offload_rc[0x1]; 1765 u8 rndv_offload_dc[0x1]; 1766 u8 log_tag_matching_list_sz[0x5]; 1767 u8 reserved_at_5f8[0x3]; 1768 u8 log_max_xrq[0x5]; 1769 1770 u8 affiliate_nic_vport_criteria[0x8]; 1771 u8 native_port_num[0x8]; 1772 u8 num_vhca_ports[0x8]; 1773 u8 flex_parser_id_gtpu_teid[0x4]; 1774 u8 reserved_at_61c[0x2]; 1775 u8 sw_owner_id[0x1]; 1776 u8 reserved_at_61f[0x1]; 1777 1778 u8 max_num_of_monitor_counters[0x10]; 1779 u8 num_ppcnt_monitor_counters[0x10]; 1780 1781 u8 max_num_sf[0x10]; 1782 u8 num_q_monitor_counters[0x10]; 1783 1784 u8 reserved_at_660[0x20]; 1785 1786 u8 sf[0x1]; 1787 u8 sf_set_partition[0x1]; 1788 u8 reserved_at_682[0x1]; 1789 u8 log_max_sf[0x5]; 1790 u8 apu[0x1]; 1791 u8 reserved_at_689[0x4]; 1792 u8 migration[0x1]; 1793 u8 reserved_at_68e[0x2]; 1794 u8 log_min_sf_size[0x8]; 1795 u8 max_num_sf_partitions[0x8]; 1796 1797 u8 uctx_cap[0x20]; 1798 1799 u8 reserved_at_6c0[0x4]; 1800 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1801 u8 flex_parser_id_icmp_dw1[0x4]; 1802 u8 flex_parser_id_icmp_dw0[0x4]; 1803 u8 flex_parser_id_icmpv6_dw1[0x4]; 1804 u8 flex_parser_id_icmpv6_dw0[0x4]; 1805 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1806 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1807 1808 u8 max_num_match_definer[0x10]; 1809 u8 sf_base_id[0x10]; 1810 1811 u8 flex_parser_id_gtpu_dw_2[0x4]; 1812 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1813 u8 num_total_dynamic_vf_msix[0x18]; 1814 u8 reserved_at_720[0x14]; 1815 u8 dynamic_msix_table_size[0xc]; 1816 u8 reserved_at_740[0xc]; 1817 u8 min_dynamic_vf_msix_table_size[0x4]; 1818 u8 reserved_at_750[0x4]; 1819 u8 max_dynamic_vf_msix_table_size[0xc]; 1820 1821 u8 reserved_at_760[0x20]; 1822 u8 vhca_tunnel_commands[0x40]; 1823 u8 match_definer_format_supported[0x40]; 1824 }; 1825 1826 struct mlx5_ifc_cmd_hca_cap_2_bits { 1827 u8 reserved_at_0[0xa0]; 1828 1829 u8 max_reformat_insert_size[0x8]; 1830 u8 max_reformat_insert_offset[0x8]; 1831 u8 max_reformat_remove_size[0x8]; 1832 u8 max_reformat_remove_offset[0x8]; 1833 1834 u8 reserved_at_c0[0x160]; 1835 1836 u8 reserved_at_220[0x1]; 1837 u8 sw_vhca_id_valid[0x1]; 1838 u8 sw_vhca_id[0xe]; 1839 u8 reserved_at_230[0x10]; 1840 1841 u8 reserved_at_240[0xb]; 1842 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1843 u8 reserved_at_250[0x10]; 1844 1845 u8 reserved_at_260[0x5a0]; 1846 }; 1847 1848 enum mlx5_ifc_flow_destination_type { 1849 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1850 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1851 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1852 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1853 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1854 }; 1855 1856 enum mlx5_flow_table_miss_action { 1857 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1858 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1859 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1860 }; 1861 1862 struct mlx5_ifc_dest_format_struct_bits { 1863 u8 destination_type[0x8]; 1864 u8 destination_id[0x18]; 1865 1866 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1867 u8 packet_reformat[0x1]; 1868 u8 reserved_at_22[0xe]; 1869 u8 destination_eswitch_owner_vhca_id[0x10]; 1870 }; 1871 1872 struct mlx5_ifc_flow_counter_list_bits { 1873 u8 flow_counter_id[0x20]; 1874 1875 u8 reserved_at_20[0x20]; 1876 }; 1877 1878 struct mlx5_ifc_extended_dest_format_bits { 1879 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1880 1881 u8 packet_reformat_id[0x20]; 1882 1883 u8 reserved_at_60[0x20]; 1884 }; 1885 1886 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1887 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1888 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1889 }; 1890 1891 struct mlx5_ifc_fte_match_param_bits { 1892 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1893 1894 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1895 1896 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1897 1898 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1899 1900 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1901 1902 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1903 1904 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1905 1906 u8 reserved_at_e00[0x200]; 1907 }; 1908 1909 enum { 1910 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1911 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1912 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1913 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1914 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1915 }; 1916 1917 struct mlx5_ifc_rx_hash_field_select_bits { 1918 u8 l3_prot_type[0x1]; 1919 u8 l4_prot_type[0x1]; 1920 u8 selected_fields[0x1e]; 1921 }; 1922 1923 enum { 1924 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1925 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1926 }; 1927 1928 enum { 1929 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1930 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1931 }; 1932 1933 struct mlx5_ifc_wq_bits { 1934 u8 wq_type[0x4]; 1935 u8 wq_signature[0x1]; 1936 u8 end_padding_mode[0x2]; 1937 u8 cd_slave[0x1]; 1938 u8 reserved_at_8[0x18]; 1939 1940 u8 hds_skip_first_sge[0x1]; 1941 u8 log2_hds_buf_size[0x3]; 1942 u8 reserved_at_24[0x7]; 1943 u8 page_offset[0x5]; 1944 u8 lwm[0x10]; 1945 1946 u8 reserved_at_40[0x8]; 1947 u8 pd[0x18]; 1948 1949 u8 reserved_at_60[0x8]; 1950 u8 uar_page[0x18]; 1951 1952 u8 dbr_addr[0x40]; 1953 1954 u8 hw_counter[0x20]; 1955 1956 u8 sw_counter[0x20]; 1957 1958 u8 reserved_at_100[0xc]; 1959 u8 log_wq_stride[0x4]; 1960 u8 reserved_at_110[0x3]; 1961 u8 log_wq_pg_sz[0x5]; 1962 u8 reserved_at_118[0x3]; 1963 u8 log_wq_sz[0x5]; 1964 1965 u8 dbr_umem_valid[0x1]; 1966 u8 wq_umem_valid[0x1]; 1967 u8 reserved_at_122[0x1]; 1968 u8 log_hairpin_num_packets[0x5]; 1969 u8 reserved_at_128[0x3]; 1970 u8 log_hairpin_data_sz[0x5]; 1971 1972 u8 reserved_at_130[0x4]; 1973 u8 log_wqe_num_of_strides[0x4]; 1974 u8 two_byte_shift_en[0x1]; 1975 u8 reserved_at_139[0x4]; 1976 u8 log_wqe_stride_size[0x3]; 1977 1978 u8 reserved_at_140[0x80]; 1979 1980 u8 headers_mkey[0x20]; 1981 1982 u8 shampo_enable[0x1]; 1983 u8 reserved_at_1e1[0x4]; 1984 u8 log_reservation_size[0x3]; 1985 u8 reserved_at_1e8[0x5]; 1986 u8 log_max_num_of_packets_per_reservation[0x3]; 1987 u8 reserved_at_1f0[0x6]; 1988 u8 log_headers_entry_size[0x2]; 1989 u8 reserved_at_1f8[0x4]; 1990 u8 log_headers_buffer_entry_num[0x4]; 1991 1992 u8 reserved_at_200[0x400]; 1993 1994 struct mlx5_ifc_cmd_pas_bits pas[]; 1995 }; 1996 1997 struct mlx5_ifc_rq_num_bits { 1998 u8 reserved_at_0[0x8]; 1999 u8 rq_num[0x18]; 2000 }; 2001 2002 struct mlx5_ifc_mac_address_layout_bits { 2003 u8 reserved_at_0[0x10]; 2004 u8 mac_addr_47_32[0x10]; 2005 2006 u8 mac_addr_31_0[0x20]; 2007 }; 2008 2009 struct mlx5_ifc_vlan_layout_bits { 2010 u8 reserved_at_0[0x14]; 2011 u8 vlan[0x0c]; 2012 2013 u8 reserved_at_20[0x20]; 2014 }; 2015 2016 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2017 u8 reserved_at_0[0xa0]; 2018 2019 u8 min_time_between_cnps[0x20]; 2020 2021 u8 reserved_at_c0[0x12]; 2022 u8 cnp_dscp[0x6]; 2023 u8 reserved_at_d8[0x4]; 2024 u8 cnp_prio_mode[0x1]; 2025 u8 cnp_802p_prio[0x3]; 2026 2027 u8 reserved_at_e0[0x720]; 2028 }; 2029 2030 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2031 u8 reserved_at_0[0x60]; 2032 2033 u8 reserved_at_60[0x4]; 2034 u8 clamp_tgt_rate[0x1]; 2035 u8 reserved_at_65[0x3]; 2036 u8 clamp_tgt_rate_after_time_inc[0x1]; 2037 u8 reserved_at_69[0x17]; 2038 2039 u8 reserved_at_80[0x20]; 2040 2041 u8 rpg_time_reset[0x20]; 2042 2043 u8 rpg_byte_reset[0x20]; 2044 2045 u8 rpg_threshold[0x20]; 2046 2047 u8 rpg_max_rate[0x20]; 2048 2049 u8 rpg_ai_rate[0x20]; 2050 2051 u8 rpg_hai_rate[0x20]; 2052 2053 u8 rpg_gd[0x20]; 2054 2055 u8 rpg_min_dec_fac[0x20]; 2056 2057 u8 rpg_min_rate[0x20]; 2058 2059 u8 reserved_at_1c0[0xe0]; 2060 2061 u8 rate_to_set_on_first_cnp[0x20]; 2062 2063 u8 dce_tcp_g[0x20]; 2064 2065 u8 dce_tcp_rtt[0x20]; 2066 2067 u8 rate_reduce_monitor_period[0x20]; 2068 2069 u8 reserved_at_320[0x20]; 2070 2071 u8 initial_alpha_value[0x20]; 2072 2073 u8 reserved_at_360[0x4a0]; 2074 }; 2075 2076 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2077 u8 reserved_at_0[0x80]; 2078 2079 u8 rppp_max_rps[0x20]; 2080 2081 u8 rpg_time_reset[0x20]; 2082 2083 u8 rpg_byte_reset[0x20]; 2084 2085 u8 rpg_threshold[0x20]; 2086 2087 u8 rpg_max_rate[0x20]; 2088 2089 u8 rpg_ai_rate[0x20]; 2090 2091 u8 rpg_hai_rate[0x20]; 2092 2093 u8 rpg_gd[0x20]; 2094 2095 u8 rpg_min_dec_fac[0x20]; 2096 2097 u8 rpg_min_rate[0x20]; 2098 2099 u8 reserved_at_1c0[0x640]; 2100 }; 2101 2102 enum { 2103 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2104 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2105 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2106 }; 2107 2108 struct mlx5_ifc_resize_field_select_bits { 2109 u8 resize_field_select[0x20]; 2110 }; 2111 2112 struct mlx5_ifc_resource_dump_bits { 2113 u8 more_dump[0x1]; 2114 u8 inline_dump[0x1]; 2115 u8 reserved_at_2[0xa]; 2116 u8 seq_num[0x4]; 2117 u8 segment_type[0x10]; 2118 2119 u8 reserved_at_20[0x10]; 2120 u8 vhca_id[0x10]; 2121 2122 u8 index1[0x20]; 2123 2124 u8 index2[0x20]; 2125 2126 u8 num_of_obj1[0x10]; 2127 u8 num_of_obj2[0x10]; 2128 2129 u8 reserved_at_a0[0x20]; 2130 2131 u8 device_opaque[0x40]; 2132 2133 u8 mkey[0x20]; 2134 2135 u8 size[0x20]; 2136 2137 u8 address[0x40]; 2138 2139 u8 inline_data[52][0x20]; 2140 }; 2141 2142 struct mlx5_ifc_resource_dump_menu_record_bits { 2143 u8 reserved_at_0[0x4]; 2144 u8 num_of_obj2_supports_active[0x1]; 2145 u8 num_of_obj2_supports_all[0x1]; 2146 u8 must_have_num_of_obj2[0x1]; 2147 u8 support_num_of_obj2[0x1]; 2148 u8 num_of_obj1_supports_active[0x1]; 2149 u8 num_of_obj1_supports_all[0x1]; 2150 u8 must_have_num_of_obj1[0x1]; 2151 u8 support_num_of_obj1[0x1]; 2152 u8 must_have_index2[0x1]; 2153 u8 support_index2[0x1]; 2154 u8 must_have_index1[0x1]; 2155 u8 support_index1[0x1]; 2156 u8 segment_type[0x10]; 2157 2158 u8 segment_name[4][0x20]; 2159 2160 u8 index1_name[4][0x20]; 2161 2162 u8 index2_name[4][0x20]; 2163 }; 2164 2165 struct mlx5_ifc_resource_dump_segment_header_bits { 2166 u8 length_dw[0x10]; 2167 u8 segment_type[0x10]; 2168 }; 2169 2170 struct mlx5_ifc_resource_dump_command_segment_bits { 2171 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2172 2173 u8 segment_called[0x10]; 2174 u8 vhca_id[0x10]; 2175 2176 u8 index1[0x20]; 2177 2178 u8 index2[0x20]; 2179 2180 u8 num_of_obj1[0x10]; 2181 u8 num_of_obj2[0x10]; 2182 }; 2183 2184 struct mlx5_ifc_resource_dump_error_segment_bits { 2185 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2186 2187 u8 reserved_at_20[0x10]; 2188 u8 syndrome_id[0x10]; 2189 2190 u8 reserved_at_40[0x40]; 2191 2192 u8 error[8][0x20]; 2193 }; 2194 2195 struct mlx5_ifc_resource_dump_info_segment_bits { 2196 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2197 2198 u8 reserved_at_20[0x18]; 2199 u8 dump_version[0x8]; 2200 2201 u8 hw_version[0x20]; 2202 2203 u8 fw_version[0x20]; 2204 }; 2205 2206 struct mlx5_ifc_resource_dump_menu_segment_bits { 2207 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2208 2209 u8 reserved_at_20[0x10]; 2210 u8 num_of_records[0x10]; 2211 2212 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2213 }; 2214 2215 struct mlx5_ifc_resource_dump_resource_segment_bits { 2216 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2217 2218 u8 reserved_at_20[0x20]; 2219 2220 u8 index1[0x20]; 2221 2222 u8 index2[0x20]; 2223 2224 u8 payload[][0x20]; 2225 }; 2226 2227 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2228 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2229 }; 2230 2231 struct mlx5_ifc_menu_resource_dump_response_bits { 2232 struct mlx5_ifc_resource_dump_info_segment_bits info; 2233 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2234 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2235 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2236 }; 2237 2238 enum { 2239 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2241 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2242 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2243 }; 2244 2245 struct mlx5_ifc_modify_field_select_bits { 2246 u8 modify_field_select[0x20]; 2247 }; 2248 2249 struct mlx5_ifc_field_select_r_roce_np_bits { 2250 u8 field_select_r_roce_np[0x20]; 2251 }; 2252 2253 struct mlx5_ifc_field_select_r_roce_rp_bits { 2254 u8 field_select_r_roce_rp[0x20]; 2255 }; 2256 2257 enum { 2258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2268 }; 2269 2270 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2271 u8 field_select_8021qaurp[0x20]; 2272 }; 2273 2274 struct mlx5_ifc_phys_layer_cntrs_bits { 2275 u8 time_since_last_clear_high[0x20]; 2276 2277 u8 time_since_last_clear_low[0x20]; 2278 2279 u8 symbol_errors_high[0x20]; 2280 2281 u8 symbol_errors_low[0x20]; 2282 2283 u8 sync_headers_errors_high[0x20]; 2284 2285 u8 sync_headers_errors_low[0x20]; 2286 2287 u8 edpl_bip_errors_lane0_high[0x20]; 2288 2289 u8 edpl_bip_errors_lane0_low[0x20]; 2290 2291 u8 edpl_bip_errors_lane1_high[0x20]; 2292 2293 u8 edpl_bip_errors_lane1_low[0x20]; 2294 2295 u8 edpl_bip_errors_lane2_high[0x20]; 2296 2297 u8 edpl_bip_errors_lane2_low[0x20]; 2298 2299 u8 edpl_bip_errors_lane3_high[0x20]; 2300 2301 u8 edpl_bip_errors_lane3_low[0x20]; 2302 2303 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2304 2305 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2306 2307 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2308 2309 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2310 2311 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2312 2313 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2314 2315 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2316 2317 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2318 2319 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2320 2321 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2322 2323 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2324 2325 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2326 2327 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2328 2329 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2330 2331 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2332 2333 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2334 2335 u8 rs_fec_corrected_blocks_high[0x20]; 2336 2337 u8 rs_fec_corrected_blocks_low[0x20]; 2338 2339 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2340 2341 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2342 2343 u8 rs_fec_no_errors_blocks_high[0x20]; 2344 2345 u8 rs_fec_no_errors_blocks_low[0x20]; 2346 2347 u8 rs_fec_single_error_blocks_high[0x20]; 2348 2349 u8 rs_fec_single_error_blocks_low[0x20]; 2350 2351 u8 rs_fec_corrected_symbols_total_high[0x20]; 2352 2353 u8 rs_fec_corrected_symbols_total_low[0x20]; 2354 2355 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2356 2357 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2358 2359 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2360 2361 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2362 2363 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2364 2365 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2366 2367 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2368 2369 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2370 2371 u8 link_down_events[0x20]; 2372 2373 u8 successful_recovery_events[0x20]; 2374 2375 u8 reserved_at_640[0x180]; 2376 }; 2377 2378 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2379 u8 time_since_last_clear_high[0x20]; 2380 2381 u8 time_since_last_clear_low[0x20]; 2382 2383 u8 phy_received_bits_high[0x20]; 2384 2385 u8 phy_received_bits_low[0x20]; 2386 2387 u8 phy_symbol_errors_high[0x20]; 2388 2389 u8 phy_symbol_errors_low[0x20]; 2390 2391 u8 phy_corrected_bits_high[0x20]; 2392 2393 u8 phy_corrected_bits_low[0x20]; 2394 2395 u8 phy_corrected_bits_lane0_high[0x20]; 2396 2397 u8 phy_corrected_bits_lane0_low[0x20]; 2398 2399 u8 phy_corrected_bits_lane1_high[0x20]; 2400 2401 u8 phy_corrected_bits_lane1_low[0x20]; 2402 2403 u8 phy_corrected_bits_lane2_high[0x20]; 2404 2405 u8 phy_corrected_bits_lane2_low[0x20]; 2406 2407 u8 phy_corrected_bits_lane3_high[0x20]; 2408 2409 u8 phy_corrected_bits_lane3_low[0x20]; 2410 2411 u8 reserved_at_200[0x5c0]; 2412 }; 2413 2414 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2415 u8 symbol_error_counter[0x10]; 2416 2417 u8 link_error_recovery_counter[0x8]; 2418 2419 u8 link_downed_counter[0x8]; 2420 2421 u8 port_rcv_errors[0x10]; 2422 2423 u8 port_rcv_remote_physical_errors[0x10]; 2424 2425 u8 port_rcv_switch_relay_errors[0x10]; 2426 2427 u8 port_xmit_discards[0x10]; 2428 2429 u8 port_xmit_constraint_errors[0x8]; 2430 2431 u8 port_rcv_constraint_errors[0x8]; 2432 2433 u8 reserved_at_70[0x8]; 2434 2435 u8 link_overrun_errors[0x8]; 2436 2437 u8 reserved_at_80[0x10]; 2438 2439 u8 vl_15_dropped[0x10]; 2440 2441 u8 reserved_at_a0[0x80]; 2442 2443 u8 port_xmit_wait[0x20]; 2444 }; 2445 2446 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2447 u8 transmit_queue_high[0x20]; 2448 2449 u8 transmit_queue_low[0x20]; 2450 2451 u8 no_buffer_discard_uc_high[0x20]; 2452 2453 u8 no_buffer_discard_uc_low[0x20]; 2454 2455 u8 reserved_at_80[0x740]; 2456 }; 2457 2458 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2459 u8 wred_discard_high[0x20]; 2460 2461 u8 wred_discard_low[0x20]; 2462 2463 u8 ecn_marked_tc_high[0x20]; 2464 2465 u8 ecn_marked_tc_low[0x20]; 2466 2467 u8 reserved_at_80[0x740]; 2468 }; 2469 2470 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2471 u8 rx_octets_high[0x20]; 2472 2473 u8 rx_octets_low[0x20]; 2474 2475 u8 reserved_at_40[0xc0]; 2476 2477 u8 rx_frames_high[0x20]; 2478 2479 u8 rx_frames_low[0x20]; 2480 2481 u8 tx_octets_high[0x20]; 2482 2483 u8 tx_octets_low[0x20]; 2484 2485 u8 reserved_at_180[0xc0]; 2486 2487 u8 tx_frames_high[0x20]; 2488 2489 u8 tx_frames_low[0x20]; 2490 2491 u8 rx_pause_high[0x20]; 2492 2493 u8 rx_pause_low[0x20]; 2494 2495 u8 rx_pause_duration_high[0x20]; 2496 2497 u8 rx_pause_duration_low[0x20]; 2498 2499 u8 tx_pause_high[0x20]; 2500 2501 u8 tx_pause_low[0x20]; 2502 2503 u8 tx_pause_duration_high[0x20]; 2504 2505 u8 tx_pause_duration_low[0x20]; 2506 2507 u8 rx_pause_transition_high[0x20]; 2508 2509 u8 rx_pause_transition_low[0x20]; 2510 2511 u8 rx_discards_high[0x20]; 2512 2513 u8 rx_discards_low[0x20]; 2514 2515 u8 device_stall_minor_watermark_cnt_high[0x20]; 2516 2517 u8 device_stall_minor_watermark_cnt_low[0x20]; 2518 2519 u8 device_stall_critical_watermark_cnt_high[0x20]; 2520 2521 u8 device_stall_critical_watermark_cnt_low[0x20]; 2522 2523 u8 reserved_at_480[0x340]; 2524 }; 2525 2526 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2527 u8 port_transmit_wait_high[0x20]; 2528 2529 u8 port_transmit_wait_low[0x20]; 2530 2531 u8 reserved_at_40[0x100]; 2532 2533 u8 rx_buffer_almost_full_high[0x20]; 2534 2535 u8 rx_buffer_almost_full_low[0x20]; 2536 2537 u8 rx_buffer_full_high[0x20]; 2538 2539 u8 rx_buffer_full_low[0x20]; 2540 2541 u8 rx_icrc_encapsulated_high[0x20]; 2542 2543 u8 rx_icrc_encapsulated_low[0x20]; 2544 2545 u8 reserved_at_200[0x5c0]; 2546 }; 2547 2548 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2549 u8 dot3stats_alignment_errors_high[0x20]; 2550 2551 u8 dot3stats_alignment_errors_low[0x20]; 2552 2553 u8 dot3stats_fcs_errors_high[0x20]; 2554 2555 u8 dot3stats_fcs_errors_low[0x20]; 2556 2557 u8 dot3stats_single_collision_frames_high[0x20]; 2558 2559 u8 dot3stats_single_collision_frames_low[0x20]; 2560 2561 u8 dot3stats_multiple_collision_frames_high[0x20]; 2562 2563 u8 dot3stats_multiple_collision_frames_low[0x20]; 2564 2565 u8 dot3stats_sqe_test_errors_high[0x20]; 2566 2567 u8 dot3stats_sqe_test_errors_low[0x20]; 2568 2569 u8 dot3stats_deferred_transmissions_high[0x20]; 2570 2571 u8 dot3stats_deferred_transmissions_low[0x20]; 2572 2573 u8 dot3stats_late_collisions_high[0x20]; 2574 2575 u8 dot3stats_late_collisions_low[0x20]; 2576 2577 u8 dot3stats_excessive_collisions_high[0x20]; 2578 2579 u8 dot3stats_excessive_collisions_low[0x20]; 2580 2581 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2582 2583 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2584 2585 u8 dot3stats_carrier_sense_errors_high[0x20]; 2586 2587 u8 dot3stats_carrier_sense_errors_low[0x20]; 2588 2589 u8 dot3stats_frame_too_longs_high[0x20]; 2590 2591 u8 dot3stats_frame_too_longs_low[0x20]; 2592 2593 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2594 2595 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2596 2597 u8 dot3stats_symbol_errors_high[0x20]; 2598 2599 u8 dot3stats_symbol_errors_low[0x20]; 2600 2601 u8 dot3control_in_unknown_opcodes_high[0x20]; 2602 2603 u8 dot3control_in_unknown_opcodes_low[0x20]; 2604 2605 u8 dot3in_pause_frames_high[0x20]; 2606 2607 u8 dot3in_pause_frames_low[0x20]; 2608 2609 u8 dot3out_pause_frames_high[0x20]; 2610 2611 u8 dot3out_pause_frames_low[0x20]; 2612 2613 u8 reserved_at_400[0x3c0]; 2614 }; 2615 2616 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2617 u8 ether_stats_drop_events_high[0x20]; 2618 2619 u8 ether_stats_drop_events_low[0x20]; 2620 2621 u8 ether_stats_octets_high[0x20]; 2622 2623 u8 ether_stats_octets_low[0x20]; 2624 2625 u8 ether_stats_pkts_high[0x20]; 2626 2627 u8 ether_stats_pkts_low[0x20]; 2628 2629 u8 ether_stats_broadcast_pkts_high[0x20]; 2630 2631 u8 ether_stats_broadcast_pkts_low[0x20]; 2632 2633 u8 ether_stats_multicast_pkts_high[0x20]; 2634 2635 u8 ether_stats_multicast_pkts_low[0x20]; 2636 2637 u8 ether_stats_crc_align_errors_high[0x20]; 2638 2639 u8 ether_stats_crc_align_errors_low[0x20]; 2640 2641 u8 ether_stats_undersize_pkts_high[0x20]; 2642 2643 u8 ether_stats_undersize_pkts_low[0x20]; 2644 2645 u8 ether_stats_oversize_pkts_high[0x20]; 2646 2647 u8 ether_stats_oversize_pkts_low[0x20]; 2648 2649 u8 ether_stats_fragments_high[0x20]; 2650 2651 u8 ether_stats_fragments_low[0x20]; 2652 2653 u8 ether_stats_jabbers_high[0x20]; 2654 2655 u8 ether_stats_jabbers_low[0x20]; 2656 2657 u8 ether_stats_collisions_high[0x20]; 2658 2659 u8 ether_stats_collisions_low[0x20]; 2660 2661 u8 ether_stats_pkts64octets_high[0x20]; 2662 2663 u8 ether_stats_pkts64octets_low[0x20]; 2664 2665 u8 ether_stats_pkts65to127octets_high[0x20]; 2666 2667 u8 ether_stats_pkts65to127octets_low[0x20]; 2668 2669 u8 ether_stats_pkts128to255octets_high[0x20]; 2670 2671 u8 ether_stats_pkts128to255octets_low[0x20]; 2672 2673 u8 ether_stats_pkts256to511octets_high[0x20]; 2674 2675 u8 ether_stats_pkts256to511octets_low[0x20]; 2676 2677 u8 ether_stats_pkts512to1023octets_high[0x20]; 2678 2679 u8 ether_stats_pkts512to1023octets_low[0x20]; 2680 2681 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2682 2683 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2684 2685 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2686 2687 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2688 2689 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2690 2691 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2692 2693 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2694 2695 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2696 2697 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2698 2699 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2700 2701 u8 reserved_at_540[0x280]; 2702 }; 2703 2704 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2705 u8 if_in_octets_high[0x20]; 2706 2707 u8 if_in_octets_low[0x20]; 2708 2709 u8 if_in_ucast_pkts_high[0x20]; 2710 2711 u8 if_in_ucast_pkts_low[0x20]; 2712 2713 u8 if_in_discards_high[0x20]; 2714 2715 u8 if_in_discards_low[0x20]; 2716 2717 u8 if_in_errors_high[0x20]; 2718 2719 u8 if_in_errors_low[0x20]; 2720 2721 u8 if_in_unknown_protos_high[0x20]; 2722 2723 u8 if_in_unknown_protos_low[0x20]; 2724 2725 u8 if_out_octets_high[0x20]; 2726 2727 u8 if_out_octets_low[0x20]; 2728 2729 u8 if_out_ucast_pkts_high[0x20]; 2730 2731 u8 if_out_ucast_pkts_low[0x20]; 2732 2733 u8 if_out_discards_high[0x20]; 2734 2735 u8 if_out_discards_low[0x20]; 2736 2737 u8 if_out_errors_high[0x20]; 2738 2739 u8 if_out_errors_low[0x20]; 2740 2741 u8 if_in_multicast_pkts_high[0x20]; 2742 2743 u8 if_in_multicast_pkts_low[0x20]; 2744 2745 u8 if_in_broadcast_pkts_high[0x20]; 2746 2747 u8 if_in_broadcast_pkts_low[0x20]; 2748 2749 u8 if_out_multicast_pkts_high[0x20]; 2750 2751 u8 if_out_multicast_pkts_low[0x20]; 2752 2753 u8 if_out_broadcast_pkts_high[0x20]; 2754 2755 u8 if_out_broadcast_pkts_low[0x20]; 2756 2757 u8 reserved_at_340[0x480]; 2758 }; 2759 2760 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2761 u8 a_frames_transmitted_ok_high[0x20]; 2762 2763 u8 a_frames_transmitted_ok_low[0x20]; 2764 2765 u8 a_frames_received_ok_high[0x20]; 2766 2767 u8 a_frames_received_ok_low[0x20]; 2768 2769 u8 a_frame_check_sequence_errors_high[0x20]; 2770 2771 u8 a_frame_check_sequence_errors_low[0x20]; 2772 2773 u8 a_alignment_errors_high[0x20]; 2774 2775 u8 a_alignment_errors_low[0x20]; 2776 2777 u8 a_octets_transmitted_ok_high[0x20]; 2778 2779 u8 a_octets_transmitted_ok_low[0x20]; 2780 2781 u8 a_octets_received_ok_high[0x20]; 2782 2783 u8 a_octets_received_ok_low[0x20]; 2784 2785 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2786 2787 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2788 2789 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2790 2791 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2792 2793 u8 a_multicast_frames_received_ok_high[0x20]; 2794 2795 u8 a_multicast_frames_received_ok_low[0x20]; 2796 2797 u8 a_broadcast_frames_received_ok_high[0x20]; 2798 2799 u8 a_broadcast_frames_received_ok_low[0x20]; 2800 2801 u8 a_in_range_length_errors_high[0x20]; 2802 2803 u8 a_in_range_length_errors_low[0x20]; 2804 2805 u8 a_out_of_range_length_field_high[0x20]; 2806 2807 u8 a_out_of_range_length_field_low[0x20]; 2808 2809 u8 a_frame_too_long_errors_high[0x20]; 2810 2811 u8 a_frame_too_long_errors_low[0x20]; 2812 2813 u8 a_symbol_error_during_carrier_high[0x20]; 2814 2815 u8 a_symbol_error_during_carrier_low[0x20]; 2816 2817 u8 a_mac_control_frames_transmitted_high[0x20]; 2818 2819 u8 a_mac_control_frames_transmitted_low[0x20]; 2820 2821 u8 a_mac_control_frames_received_high[0x20]; 2822 2823 u8 a_mac_control_frames_received_low[0x20]; 2824 2825 u8 a_unsupported_opcodes_received_high[0x20]; 2826 2827 u8 a_unsupported_opcodes_received_low[0x20]; 2828 2829 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2830 2831 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2832 2833 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2834 2835 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2836 2837 u8 reserved_at_4c0[0x300]; 2838 }; 2839 2840 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2841 u8 life_time_counter_high[0x20]; 2842 2843 u8 life_time_counter_low[0x20]; 2844 2845 u8 rx_errors[0x20]; 2846 2847 u8 tx_errors[0x20]; 2848 2849 u8 l0_to_recovery_eieos[0x20]; 2850 2851 u8 l0_to_recovery_ts[0x20]; 2852 2853 u8 l0_to_recovery_framing[0x20]; 2854 2855 u8 l0_to_recovery_retrain[0x20]; 2856 2857 u8 crc_error_dllp[0x20]; 2858 2859 u8 crc_error_tlp[0x20]; 2860 2861 u8 tx_overflow_buffer_pkt_high[0x20]; 2862 2863 u8 tx_overflow_buffer_pkt_low[0x20]; 2864 2865 u8 outbound_stalled_reads[0x20]; 2866 2867 u8 outbound_stalled_writes[0x20]; 2868 2869 u8 outbound_stalled_reads_events[0x20]; 2870 2871 u8 outbound_stalled_writes_events[0x20]; 2872 2873 u8 reserved_at_200[0x5c0]; 2874 }; 2875 2876 struct mlx5_ifc_cmd_inter_comp_event_bits { 2877 u8 command_completion_vector[0x20]; 2878 2879 u8 reserved_at_20[0xc0]; 2880 }; 2881 2882 struct mlx5_ifc_stall_vl_event_bits { 2883 u8 reserved_at_0[0x18]; 2884 u8 port_num[0x1]; 2885 u8 reserved_at_19[0x3]; 2886 u8 vl[0x4]; 2887 2888 u8 reserved_at_20[0xa0]; 2889 }; 2890 2891 struct mlx5_ifc_db_bf_congestion_event_bits { 2892 u8 event_subtype[0x8]; 2893 u8 reserved_at_8[0x8]; 2894 u8 congestion_level[0x8]; 2895 u8 reserved_at_18[0x8]; 2896 2897 u8 reserved_at_20[0xa0]; 2898 }; 2899 2900 struct mlx5_ifc_gpio_event_bits { 2901 u8 reserved_at_0[0x60]; 2902 2903 u8 gpio_event_hi[0x20]; 2904 2905 u8 gpio_event_lo[0x20]; 2906 2907 u8 reserved_at_a0[0x40]; 2908 }; 2909 2910 struct mlx5_ifc_port_state_change_event_bits { 2911 u8 reserved_at_0[0x40]; 2912 2913 u8 port_num[0x4]; 2914 u8 reserved_at_44[0x1c]; 2915 2916 u8 reserved_at_60[0x80]; 2917 }; 2918 2919 struct mlx5_ifc_dropped_packet_logged_bits { 2920 u8 reserved_at_0[0xe0]; 2921 }; 2922 2923 struct mlx5_ifc_default_timeout_bits { 2924 u8 to_multiplier[0x3]; 2925 u8 reserved_at_3[0x9]; 2926 u8 to_value[0x14]; 2927 }; 2928 2929 struct mlx5_ifc_dtor_reg_bits { 2930 u8 reserved_at_0[0x20]; 2931 2932 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2933 2934 u8 reserved_at_40[0x60]; 2935 2936 struct mlx5_ifc_default_timeout_bits health_poll_to; 2937 2938 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2939 2940 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2941 2942 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2943 2944 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2945 2946 struct mlx5_ifc_default_timeout_bits tear_down_to; 2947 2948 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2949 2950 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2951 2952 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2953 2954 u8 reserved_at_1c0[0x40]; 2955 }; 2956 2957 enum { 2958 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2959 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2960 }; 2961 2962 struct mlx5_ifc_cq_error_bits { 2963 u8 reserved_at_0[0x8]; 2964 u8 cqn[0x18]; 2965 2966 u8 reserved_at_20[0x20]; 2967 2968 u8 reserved_at_40[0x18]; 2969 u8 syndrome[0x8]; 2970 2971 u8 reserved_at_60[0x80]; 2972 }; 2973 2974 struct mlx5_ifc_rdma_page_fault_event_bits { 2975 u8 bytes_committed[0x20]; 2976 2977 u8 r_key[0x20]; 2978 2979 u8 reserved_at_40[0x10]; 2980 u8 packet_len[0x10]; 2981 2982 u8 rdma_op_len[0x20]; 2983 2984 u8 rdma_va[0x40]; 2985 2986 u8 reserved_at_c0[0x5]; 2987 u8 rdma[0x1]; 2988 u8 write[0x1]; 2989 u8 requestor[0x1]; 2990 u8 qp_number[0x18]; 2991 }; 2992 2993 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2994 u8 bytes_committed[0x20]; 2995 2996 u8 reserved_at_20[0x10]; 2997 u8 wqe_index[0x10]; 2998 2999 u8 reserved_at_40[0x10]; 3000 u8 len[0x10]; 3001 3002 u8 reserved_at_60[0x60]; 3003 3004 u8 reserved_at_c0[0x5]; 3005 u8 rdma[0x1]; 3006 u8 write_read[0x1]; 3007 u8 requestor[0x1]; 3008 u8 qpn[0x18]; 3009 }; 3010 3011 struct mlx5_ifc_qp_events_bits { 3012 u8 reserved_at_0[0xa0]; 3013 3014 u8 type[0x8]; 3015 u8 reserved_at_a8[0x18]; 3016 3017 u8 reserved_at_c0[0x8]; 3018 u8 qpn_rqn_sqn[0x18]; 3019 }; 3020 3021 struct mlx5_ifc_dct_events_bits { 3022 u8 reserved_at_0[0xc0]; 3023 3024 u8 reserved_at_c0[0x8]; 3025 u8 dct_number[0x18]; 3026 }; 3027 3028 struct mlx5_ifc_comp_event_bits { 3029 u8 reserved_at_0[0xc0]; 3030 3031 u8 reserved_at_c0[0x8]; 3032 u8 cq_number[0x18]; 3033 }; 3034 3035 enum { 3036 MLX5_QPC_STATE_RST = 0x0, 3037 MLX5_QPC_STATE_INIT = 0x1, 3038 MLX5_QPC_STATE_RTR = 0x2, 3039 MLX5_QPC_STATE_RTS = 0x3, 3040 MLX5_QPC_STATE_SQER = 0x4, 3041 MLX5_QPC_STATE_ERR = 0x6, 3042 MLX5_QPC_STATE_SQD = 0x7, 3043 MLX5_QPC_STATE_SUSPENDED = 0x9, 3044 }; 3045 3046 enum { 3047 MLX5_QPC_ST_RC = 0x0, 3048 MLX5_QPC_ST_UC = 0x1, 3049 MLX5_QPC_ST_UD = 0x2, 3050 MLX5_QPC_ST_XRC = 0x3, 3051 MLX5_QPC_ST_DCI = 0x5, 3052 MLX5_QPC_ST_QP0 = 0x7, 3053 MLX5_QPC_ST_QP1 = 0x8, 3054 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3055 MLX5_QPC_ST_REG_UMR = 0xc, 3056 }; 3057 3058 enum { 3059 MLX5_QPC_PM_STATE_ARMED = 0x0, 3060 MLX5_QPC_PM_STATE_REARM = 0x1, 3061 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3062 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3063 }; 3064 3065 enum { 3066 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3067 }; 3068 3069 enum { 3070 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3071 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3072 }; 3073 3074 enum { 3075 MLX5_QPC_MTU_256_BYTES = 0x1, 3076 MLX5_QPC_MTU_512_BYTES = 0x2, 3077 MLX5_QPC_MTU_1K_BYTES = 0x3, 3078 MLX5_QPC_MTU_2K_BYTES = 0x4, 3079 MLX5_QPC_MTU_4K_BYTES = 0x5, 3080 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3081 }; 3082 3083 enum { 3084 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3085 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3086 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3087 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3088 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3089 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3090 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3091 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3092 }; 3093 3094 enum { 3095 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3096 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3097 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3098 }; 3099 3100 enum { 3101 MLX5_QPC_CS_RES_DISABLE = 0x0, 3102 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3103 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3104 }; 3105 3106 enum { 3107 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3108 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3109 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3110 }; 3111 3112 struct mlx5_ifc_qpc_bits { 3113 u8 state[0x4]; 3114 u8 lag_tx_port_affinity[0x4]; 3115 u8 st[0x8]; 3116 u8 reserved_at_10[0x2]; 3117 u8 isolate_vl_tc[0x1]; 3118 u8 pm_state[0x2]; 3119 u8 reserved_at_15[0x1]; 3120 u8 req_e2e_credit_mode[0x2]; 3121 u8 offload_type[0x4]; 3122 u8 end_padding_mode[0x2]; 3123 u8 reserved_at_1e[0x2]; 3124 3125 u8 wq_signature[0x1]; 3126 u8 block_lb_mc[0x1]; 3127 u8 atomic_like_write_en[0x1]; 3128 u8 latency_sensitive[0x1]; 3129 u8 reserved_at_24[0x1]; 3130 u8 drain_sigerr[0x1]; 3131 u8 reserved_at_26[0x2]; 3132 u8 pd[0x18]; 3133 3134 u8 mtu[0x3]; 3135 u8 log_msg_max[0x5]; 3136 u8 reserved_at_48[0x1]; 3137 u8 log_rq_size[0x4]; 3138 u8 log_rq_stride[0x3]; 3139 u8 no_sq[0x1]; 3140 u8 log_sq_size[0x4]; 3141 u8 reserved_at_55[0x3]; 3142 u8 ts_format[0x2]; 3143 u8 reserved_at_5a[0x1]; 3144 u8 rlky[0x1]; 3145 u8 ulp_stateless_offload_mode[0x4]; 3146 3147 u8 counter_set_id[0x8]; 3148 u8 uar_page[0x18]; 3149 3150 u8 reserved_at_80[0x8]; 3151 u8 user_index[0x18]; 3152 3153 u8 reserved_at_a0[0x3]; 3154 u8 log_page_size[0x5]; 3155 u8 remote_qpn[0x18]; 3156 3157 struct mlx5_ifc_ads_bits primary_address_path; 3158 3159 struct mlx5_ifc_ads_bits secondary_address_path; 3160 3161 u8 log_ack_req_freq[0x4]; 3162 u8 reserved_at_384[0x4]; 3163 u8 log_sra_max[0x3]; 3164 u8 reserved_at_38b[0x2]; 3165 u8 retry_count[0x3]; 3166 u8 rnr_retry[0x3]; 3167 u8 reserved_at_393[0x1]; 3168 u8 fre[0x1]; 3169 u8 cur_rnr_retry[0x3]; 3170 u8 cur_retry_count[0x3]; 3171 u8 reserved_at_39b[0x5]; 3172 3173 u8 reserved_at_3a0[0x20]; 3174 3175 u8 reserved_at_3c0[0x8]; 3176 u8 next_send_psn[0x18]; 3177 3178 u8 reserved_at_3e0[0x3]; 3179 u8 log_num_dci_stream_channels[0x5]; 3180 u8 cqn_snd[0x18]; 3181 3182 u8 reserved_at_400[0x3]; 3183 u8 log_num_dci_errored_streams[0x5]; 3184 u8 deth_sqpn[0x18]; 3185 3186 u8 reserved_at_420[0x20]; 3187 3188 u8 reserved_at_440[0x8]; 3189 u8 last_acked_psn[0x18]; 3190 3191 u8 reserved_at_460[0x8]; 3192 u8 ssn[0x18]; 3193 3194 u8 reserved_at_480[0x8]; 3195 u8 log_rra_max[0x3]; 3196 u8 reserved_at_48b[0x1]; 3197 u8 atomic_mode[0x4]; 3198 u8 rre[0x1]; 3199 u8 rwe[0x1]; 3200 u8 rae[0x1]; 3201 u8 reserved_at_493[0x1]; 3202 u8 page_offset[0x6]; 3203 u8 reserved_at_49a[0x3]; 3204 u8 cd_slave_receive[0x1]; 3205 u8 cd_slave_send[0x1]; 3206 u8 cd_master[0x1]; 3207 3208 u8 reserved_at_4a0[0x3]; 3209 u8 min_rnr_nak[0x5]; 3210 u8 next_rcv_psn[0x18]; 3211 3212 u8 reserved_at_4c0[0x8]; 3213 u8 xrcd[0x18]; 3214 3215 u8 reserved_at_4e0[0x8]; 3216 u8 cqn_rcv[0x18]; 3217 3218 u8 dbr_addr[0x40]; 3219 3220 u8 q_key[0x20]; 3221 3222 u8 reserved_at_560[0x5]; 3223 u8 rq_type[0x3]; 3224 u8 srqn_rmpn_xrqn[0x18]; 3225 3226 u8 reserved_at_580[0x8]; 3227 u8 rmsn[0x18]; 3228 3229 u8 hw_sq_wqebb_counter[0x10]; 3230 u8 sw_sq_wqebb_counter[0x10]; 3231 3232 u8 hw_rq_counter[0x20]; 3233 3234 u8 sw_rq_counter[0x20]; 3235 3236 u8 reserved_at_600[0x20]; 3237 3238 u8 reserved_at_620[0xf]; 3239 u8 cgs[0x1]; 3240 u8 cs_req[0x8]; 3241 u8 cs_res[0x8]; 3242 3243 u8 dc_access_key[0x40]; 3244 3245 u8 reserved_at_680[0x3]; 3246 u8 dbr_umem_valid[0x1]; 3247 3248 u8 reserved_at_684[0xbc]; 3249 }; 3250 3251 struct mlx5_ifc_roce_addr_layout_bits { 3252 u8 source_l3_address[16][0x8]; 3253 3254 u8 reserved_at_80[0x3]; 3255 u8 vlan_valid[0x1]; 3256 u8 vlan_id[0xc]; 3257 u8 source_mac_47_32[0x10]; 3258 3259 u8 source_mac_31_0[0x20]; 3260 3261 u8 reserved_at_c0[0x14]; 3262 u8 roce_l3_type[0x4]; 3263 u8 roce_version[0x8]; 3264 3265 u8 reserved_at_e0[0x20]; 3266 }; 3267 3268 struct mlx5_ifc_shampo_cap_bits { 3269 u8 reserved_at_0[0x3]; 3270 u8 shampo_log_max_reservation_size[0x5]; 3271 u8 reserved_at_8[0x3]; 3272 u8 shampo_log_min_reservation_size[0x5]; 3273 u8 shampo_min_mss_size[0x10]; 3274 3275 u8 reserved_at_20[0x3]; 3276 u8 shampo_max_log_headers_entry_size[0x5]; 3277 u8 reserved_at_28[0x18]; 3278 3279 u8 reserved_at_40[0x7c0]; 3280 }; 3281 3282 union mlx5_ifc_hca_cap_union_bits { 3283 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3284 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3285 struct mlx5_ifc_odp_cap_bits odp_cap; 3286 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3287 struct mlx5_ifc_roce_cap_bits roce_cap; 3288 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3289 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3290 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3291 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3292 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3293 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3294 struct mlx5_ifc_qos_cap_bits qos_cap; 3295 struct mlx5_ifc_debug_cap_bits debug_cap; 3296 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3297 struct mlx5_ifc_tls_cap_bits tls_cap; 3298 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3299 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3300 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3301 u8 reserved_at_0[0x8000]; 3302 }; 3303 3304 enum { 3305 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3306 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3307 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3308 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3309 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3310 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3311 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3312 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3313 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3314 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3315 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3316 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3317 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3318 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3319 }; 3320 3321 enum { 3322 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3323 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3324 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3325 }; 3326 3327 struct mlx5_ifc_vlan_bits { 3328 u8 ethtype[0x10]; 3329 u8 prio[0x3]; 3330 u8 cfi[0x1]; 3331 u8 vid[0xc]; 3332 }; 3333 3334 enum { 3335 MLX5_FLOW_METER_COLOR_RED = 0x0, 3336 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3337 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3338 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3339 }; 3340 3341 enum { 3342 MLX5_EXE_ASO_FLOW_METER = 0x2, 3343 }; 3344 3345 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3346 u8 return_reg_id[0x4]; 3347 u8 aso_type[0x4]; 3348 u8 reserved_at_8[0x14]; 3349 u8 action[0x1]; 3350 u8 init_color[0x2]; 3351 u8 meter_id[0x1]; 3352 }; 3353 3354 union mlx5_ifc_exe_aso_ctrl { 3355 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3356 }; 3357 3358 struct mlx5_ifc_execute_aso_bits { 3359 u8 valid[0x1]; 3360 u8 reserved_at_1[0x7]; 3361 u8 aso_object_id[0x18]; 3362 3363 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3364 }; 3365 3366 struct mlx5_ifc_flow_context_bits { 3367 struct mlx5_ifc_vlan_bits push_vlan; 3368 3369 u8 group_id[0x20]; 3370 3371 u8 reserved_at_40[0x8]; 3372 u8 flow_tag[0x18]; 3373 3374 u8 reserved_at_60[0x10]; 3375 u8 action[0x10]; 3376 3377 u8 extended_destination[0x1]; 3378 u8 reserved_at_81[0x1]; 3379 u8 flow_source[0x2]; 3380 u8 reserved_at_84[0x4]; 3381 u8 destination_list_size[0x18]; 3382 3383 u8 reserved_at_a0[0x8]; 3384 u8 flow_counter_list_size[0x18]; 3385 3386 u8 packet_reformat_id[0x20]; 3387 3388 u8 modify_header_id[0x20]; 3389 3390 struct mlx5_ifc_vlan_bits push_vlan_2; 3391 3392 u8 ipsec_obj_id[0x20]; 3393 u8 reserved_at_140[0xc0]; 3394 3395 struct mlx5_ifc_fte_match_param_bits match_value; 3396 3397 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3398 3399 u8 reserved_at_1300[0x500]; 3400 3401 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3402 }; 3403 3404 enum { 3405 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3406 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3407 }; 3408 3409 struct mlx5_ifc_xrc_srqc_bits { 3410 u8 state[0x4]; 3411 u8 log_xrc_srq_size[0x4]; 3412 u8 reserved_at_8[0x18]; 3413 3414 u8 wq_signature[0x1]; 3415 u8 cont_srq[0x1]; 3416 u8 reserved_at_22[0x1]; 3417 u8 rlky[0x1]; 3418 u8 basic_cyclic_rcv_wqe[0x1]; 3419 u8 log_rq_stride[0x3]; 3420 u8 xrcd[0x18]; 3421 3422 u8 page_offset[0x6]; 3423 u8 reserved_at_46[0x1]; 3424 u8 dbr_umem_valid[0x1]; 3425 u8 cqn[0x18]; 3426 3427 u8 reserved_at_60[0x20]; 3428 3429 u8 user_index_equal_xrc_srqn[0x1]; 3430 u8 reserved_at_81[0x1]; 3431 u8 log_page_size[0x6]; 3432 u8 user_index[0x18]; 3433 3434 u8 reserved_at_a0[0x20]; 3435 3436 u8 reserved_at_c0[0x8]; 3437 u8 pd[0x18]; 3438 3439 u8 lwm[0x10]; 3440 u8 wqe_cnt[0x10]; 3441 3442 u8 reserved_at_100[0x40]; 3443 3444 u8 db_record_addr_h[0x20]; 3445 3446 u8 db_record_addr_l[0x1e]; 3447 u8 reserved_at_17e[0x2]; 3448 3449 u8 reserved_at_180[0x80]; 3450 }; 3451 3452 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3453 u8 counter_error_queues[0x20]; 3454 3455 u8 total_error_queues[0x20]; 3456 3457 u8 send_queue_priority_update_flow[0x20]; 3458 3459 u8 reserved_at_60[0x20]; 3460 3461 u8 nic_receive_steering_discard[0x40]; 3462 3463 u8 receive_discard_vport_down[0x40]; 3464 3465 u8 transmit_discard_vport_down[0x40]; 3466 3467 u8 async_eq_overrun[0x20]; 3468 3469 u8 comp_eq_overrun[0x20]; 3470 3471 u8 reserved_at_180[0x20]; 3472 3473 u8 invalid_command[0x20]; 3474 3475 u8 quota_exceeded_command[0x20]; 3476 3477 u8 internal_rq_out_of_buffer[0x20]; 3478 3479 u8 cq_overrun[0x20]; 3480 3481 u8 reserved_at_220[0xde0]; 3482 }; 3483 3484 struct mlx5_ifc_traffic_counter_bits { 3485 u8 packets[0x40]; 3486 3487 u8 octets[0x40]; 3488 }; 3489 3490 struct mlx5_ifc_tisc_bits { 3491 u8 strict_lag_tx_port_affinity[0x1]; 3492 u8 tls_en[0x1]; 3493 u8 reserved_at_2[0x2]; 3494 u8 lag_tx_port_affinity[0x04]; 3495 3496 u8 reserved_at_8[0x4]; 3497 u8 prio[0x4]; 3498 u8 reserved_at_10[0x10]; 3499 3500 u8 reserved_at_20[0x100]; 3501 3502 u8 reserved_at_120[0x8]; 3503 u8 transport_domain[0x18]; 3504 3505 u8 reserved_at_140[0x8]; 3506 u8 underlay_qpn[0x18]; 3507 3508 u8 reserved_at_160[0x8]; 3509 u8 pd[0x18]; 3510 3511 u8 reserved_at_180[0x380]; 3512 }; 3513 3514 enum { 3515 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3516 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3517 }; 3518 3519 enum { 3520 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3521 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3522 }; 3523 3524 enum { 3525 MLX5_RX_HASH_FN_NONE = 0x0, 3526 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3527 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3528 }; 3529 3530 enum { 3531 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3532 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3533 }; 3534 3535 struct mlx5_ifc_tirc_bits { 3536 u8 reserved_at_0[0x20]; 3537 3538 u8 disp_type[0x4]; 3539 u8 tls_en[0x1]; 3540 u8 reserved_at_25[0x1b]; 3541 3542 u8 reserved_at_40[0x40]; 3543 3544 u8 reserved_at_80[0x4]; 3545 u8 lro_timeout_period_usecs[0x10]; 3546 u8 packet_merge_mask[0x4]; 3547 u8 lro_max_ip_payload_size[0x8]; 3548 3549 u8 reserved_at_a0[0x40]; 3550 3551 u8 reserved_at_e0[0x8]; 3552 u8 inline_rqn[0x18]; 3553 3554 u8 rx_hash_symmetric[0x1]; 3555 u8 reserved_at_101[0x1]; 3556 u8 tunneled_offload_en[0x1]; 3557 u8 reserved_at_103[0x5]; 3558 u8 indirect_table[0x18]; 3559 3560 u8 rx_hash_fn[0x4]; 3561 u8 reserved_at_124[0x2]; 3562 u8 self_lb_block[0x2]; 3563 u8 transport_domain[0x18]; 3564 3565 u8 rx_hash_toeplitz_key[10][0x20]; 3566 3567 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3568 3569 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3570 3571 u8 reserved_at_2c0[0x4c0]; 3572 }; 3573 3574 enum { 3575 MLX5_SRQC_STATE_GOOD = 0x0, 3576 MLX5_SRQC_STATE_ERROR = 0x1, 3577 }; 3578 3579 struct mlx5_ifc_srqc_bits { 3580 u8 state[0x4]; 3581 u8 log_srq_size[0x4]; 3582 u8 reserved_at_8[0x18]; 3583 3584 u8 wq_signature[0x1]; 3585 u8 cont_srq[0x1]; 3586 u8 reserved_at_22[0x1]; 3587 u8 rlky[0x1]; 3588 u8 reserved_at_24[0x1]; 3589 u8 log_rq_stride[0x3]; 3590 u8 xrcd[0x18]; 3591 3592 u8 page_offset[0x6]; 3593 u8 reserved_at_46[0x2]; 3594 u8 cqn[0x18]; 3595 3596 u8 reserved_at_60[0x20]; 3597 3598 u8 reserved_at_80[0x2]; 3599 u8 log_page_size[0x6]; 3600 u8 reserved_at_88[0x18]; 3601 3602 u8 reserved_at_a0[0x20]; 3603 3604 u8 reserved_at_c0[0x8]; 3605 u8 pd[0x18]; 3606 3607 u8 lwm[0x10]; 3608 u8 wqe_cnt[0x10]; 3609 3610 u8 reserved_at_100[0x40]; 3611 3612 u8 dbr_addr[0x40]; 3613 3614 u8 reserved_at_180[0x80]; 3615 }; 3616 3617 enum { 3618 MLX5_SQC_STATE_RST = 0x0, 3619 MLX5_SQC_STATE_RDY = 0x1, 3620 MLX5_SQC_STATE_ERR = 0x3, 3621 }; 3622 3623 struct mlx5_ifc_sqc_bits { 3624 u8 rlky[0x1]; 3625 u8 cd_master[0x1]; 3626 u8 fre[0x1]; 3627 u8 flush_in_error_en[0x1]; 3628 u8 allow_multi_pkt_send_wqe[0x1]; 3629 u8 min_wqe_inline_mode[0x3]; 3630 u8 state[0x4]; 3631 u8 reg_umr[0x1]; 3632 u8 allow_swp[0x1]; 3633 u8 hairpin[0x1]; 3634 u8 reserved_at_f[0xb]; 3635 u8 ts_format[0x2]; 3636 u8 reserved_at_1c[0x4]; 3637 3638 u8 reserved_at_20[0x8]; 3639 u8 user_index[0x18]; 3640 3641 u8 reserved_at_40[0x8]; 3642 u8 cqn[0x18]; 3643 3644 u8 reserved_at_60[0x8]; 3645 u8 hairpin_peer_rq[0x18]; 3646 3647 u8 reserved_at_80[0x10]; 3648 u8 hairpin_peer_vhca[0x10]; 3649 3650 u8 reserved_at_a0[0x20]; 3651 3652 u8 reserved_at_c0[0x8]; 3653 u8 ts_cqe_to_dest_cqn[0x18]; 3654 3655 u8 reserved_at_e0[0x10]; 3656 u8 packet_pacing_rate_limit_index[0x10]; 3657 u8 tis_lst_sz[0x10]; 3658 u8 qos_queue_group_id[0x10]; 3659 3660 u8 reserved_at_120[0x40]; 3661 3662 u8 reserved_at_160[0x8]; 3663 u8 tis_num_0[0x18]; 3664 3665 struct mlx5_ifc_wq_bits wq; 3666 }; 3667 3668 enum { 3669 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3670 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3671 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3672 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3673 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3674 }; 3675 3676 enum { 3677 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3678 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3679 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3680 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3681 }; 3682 3683 struct mlx5_ifc_scheduling_context_bits { 3684 u8 element_type[0x8]; 3685 u8 reserved_at_8[0x18]; 3686 3687 u8 element_attributes[0x20]; 3688 3689 u8 parent_element_id[0x20]; 3690 3691 u8 reserved_at_60[0x40]; 3692 3693 u8 bw_share[0x20]; 3694 3695 u8 max_average_bw[0x20]; 3696 3697 u8 reserved_at_e0[0x120]; 3698 }; 3699 3700 struct mlx5_ifc_rqtc_bits { 3701 u8 reserved_at_0[0xa0]; 3702 3703 u8 reserved_at_a0[0x5]; 3704 u8 list_q_type[0x3]; 3705 u8 reserved_at_a8[0x8]; 3706 u8 rqt_max_size[0x10]; 3707 3708 u8 rq_vhca_id_format[0x1]; 3709 u8 reserved_at_c1[0xf]; 3710 u8 rqt_actual_size[0x10]; 3711 3712 u8 reserved_at_e0[0x6a0]; 3713 3714 struct mlx5_ifc_rq_num_bits rq_num[]; 3715 }; 3716 3717 enum { 3718 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3719 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3720 }; 3721 3722 enum { 3723 MLX5_RQC_STATE_RST = 0x0, 3724 MLX5_RQC_STATE_RDY = 0x1, 3725 MLX5_RQC_STATE_ERR = 0x3, 3726 }; 3727 3728 enum { 3729 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3730 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3731 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3732 }; 3733 3734 enum { 3735 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3736 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3737 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3738 }; 3739 3740 struct mlx5_ifc_rqc_bits { 3741 u8 rlky[0x1]; 3742 u8 delay_drop_en[0x1]; 3743 u8 scatter_fcs[0x1]; 3744 u8 vsd[0x1]; 3745 u8 mem_rq_type[0x4]; 3746 u8 state[0x4]; 3747 u8 reserved_at_c[0x1]; 3748 u8 flush_in_error_en[0x1]; 3749 u8 hairpin[0x1]; 3750 u8 reserved_at_f[0xb]; 3751 u8 ts_format[0x2]; 3752 u8 reserved_at_1c[0x4]; 3753 3754 u8 reserved_at_20[0x8]; 3755 u8 user_index[0x18]; 3756 3757 u8 reserved_at_40[0x8]; 3758 u8 cqn[0x18]; 3759 3760 u8 counter_set_id[0x8]; 3761 u8 reserved_at_68[0x18]; 3762 3763 u8 reserved_at_80[0x8]; 3764 u8 rmpn[0x18]; 3765 3766 u8 reserved_at_a0[0x8]; 3767 u8 hairpin_peer_sq[0x18]; 3768 3769 u8 reserved_at_c0[0x10]; 3770 u8 hairpin_peer_vhca[0x10]; 3771 3772 u8 reserved_at_e0[0x46]; 3773 u8 shampo_no_match_alignment_granularity[0x2]; 3774 u8 reserved_at_128[0x6]; 3775 u8 shampo_match_criteria_type[0x2]; 3776 u8 reservation_timeout[0x10]; 3777 3778 u8 reserved_at_140[0x40]; 3779 3780 struct mlx5_ifc_wq_bits wq; 3781 }; 3782 3783 enum { 3784 MLX5_RMPC_STATE_RDY = 0x1, 3785 MLX5_RMPC_STATE_ERR = 0x3, 3786 }; 3787 3788 struct mlx5_ifc_rmpc_bits { 3789 u8 reserved_at_0[0x8]; 3790 u8 state[0x4]; 3791 u8 reserved_at_c[0x14]; 3792 3793 u8 basic_cyclic_rcv_wqe[0x1]; 3794 u8 reserved_at_21[0x1f]; 3795 3796 u8 reserved_at_40[0x140]; 3797 3798 struct mlx5_ifc_wq_bits wq; 3799 }; 3800 3801 enum { 3802 VHCA_ID_TYPE_HW = 0, 3803 VHCA_ID_TYPE_SW = 1, 3804 }; 3805 3806 struct mlx5_ifc_nic_vport_context_bits { 3807 u8 reserved_at_0[0x5]; 3808 u8 min_wqe_inline_mode[0x3]; 3809 u8 reserved_at_8[0x15]; 3810 u8 disable_mc_local_lb[0x1]; 3811 u8 disable_uc_local_lb[0x1]; 3812 u8 roce_en[0x1]; 3813 3814 u8 arm_change_event[0x1]; 3815 u8 reserved_at_21[0x1a]; 3816 u8 event_on_mtu[0x1]; 3817 u8 event_on_promisc_change[0x1]; 3818 u8 event_on_vlan_change[0x1]; 3819 u8 event_on_mc_address_change[0x1]; 3820 u8 event_on_uc_address_change[0x1]; 3821 3822 u8 vhca_id_type[0x1]; 3823 u8 reserved_at_41[0xb]; 3824 u8 affiliation_criteria[0x4]; 3825 u8 affiliated_vhca_id[0x10]; 3826 3827 u8 reserved_at_60[0xd0]; 3828 3829 u8 mtu[0x10]; 3830 3831 u8 system_image_guid[0x40]; 3832 u8 port_guid[0x40]; 3833 u8 node_guid[0x40]; 3834 3835 u8 reserved_at_200[0x140]; 3836 u8 qkey_violation_counter[0x10]; 3837 u8 reserved_at_350[0x430]; 3838 3839 u8 promisc_uc[0x1]; 3840 u8 promisc_mc[0x1]; 3841 u8 promisc_all[0x1]; 3842 u8 reserved_at_783[0x2]; 3843 u8 allowed_list_type[0x3]; 3844 u8 reserved_at_788[0xc]; 3845 u8 allowed_list_size[0xc]; 3846 3847 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3848 3849 u8 reserved_at_7e0[0x20]; 3850 3851 u8 current_uc_mac_address[][0x40]; 3852 }; 3853 3854 enum { 3855 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3856 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3857 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3858 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3859 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3860 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3861 }; 3862 3863 struct mlx5_ifc_mkc_bits { 3864 u8 reserved_at_0[0x1]; 3865 u8 free[0x1]; 3866 u8 reserved_at_2[0x1]; 3867 u8 access_mode_4_2[0x3]; 3868 u8 reserved_at_6[0x7]; 3869 u8 relaxed_ordering_write[0x1]; 3870 u8 reserved_at_e[0x1]; 3871 u8 small_fence_on_rdma_read_response[0x1]; 3872 u8 umr_en[0x1]; 3873 u8 a[0x1]; 3874 u8 rw[0x1]; 3875 u8 rr[0x1]; 3876 u8 lw[0x1]; 3877 u8 lr[0x1]; 3878 u8 access_mode_1_0[0x2]; 3879 u8 reserved_at_18[0x8]; 3880 3881 u8 qpn[0x18]; 3882 u8 mkey_7_0[0x8]; 3883 3884 u8 reserved_at_40[0x20]; 3885 3886 u8 length64[0x1]; 3887 u8 bsf_en[0x1]; 3888 u8 sync_umr[0x1]; 3889 u8 reserved_at_63[0x2]; 3890 u8 expected_sigerr_count[0x1]; 3891 u8 reserved_at_66[0x1]; 3892 u8 en_rinval[0x1]; 3893 u8 pd[0x18]; 3894 3895 u8 start_addr[0x40]; 3896 3897 u8 len[0x40]; 3898 3899 u8 bsf_octword_size[0x20]; 3900 3901 u8 reserved_at_120[0x80]; 3902 3903 u8 translations_octword_size[0x20]; 3904 3905 u8 reserved_at_1c0[0x19]; 3906 u8 relaxed_ordering_read[0x1]; 3907 u8 reserved_at_1d9[0x1]; 3908 u8 log_page_size[0x5]; 3909 3910 u8 reserved_at_1e0[0x20]; 3911 }; 3912 3913 struct mlx5_ifc_pkey_bits { 3914 u8 reserved_at_0[0x10]; 3915 u8 pkey[0x10]; 3916 }; 3917 3918 struct mlx5_ifc_array128_auto_bits { 3919 u8 array128_auto[16][0x8]; 3920 }; 3921 3922 struct mlx5_ifc_hca_vport_context_bits { 3923 u8 field_select[0x20]; 3924 3925 u8 reserved_at_20[0xe0]; 3926 3927 u8 sm_virt_aware[0x1]; 3928 u8 has_smi[0x1]; 3929 u8 has_raw[0x1]; 3930 u8 grh_required[0x1]; 3931 u8 reserved_at_104[0xc]; 3932 u8 port_physical_state[0x4]; 3933 u8 vport_state_policy[0x4]; 3934 u8 port_state[0x4]; 3935 u8 vport_state[0x4]; 3936 3937 u8 reserved_at_120[0x20]; 3938 3939 u8 system_image_guid[0x40]; 3940 3941 u8 port_guid[0x40]; 3942 3943 u8 node_guid[0x40]; 3944 3945 u8 cap_mask1[0x20]; 3946 3947 u8 cap_mask1_field_select[0x20]; 3948 3949 u8 cap_mask2[0x20]; 3950 3951 u8 cap_mask2_field_select[0x20]; 3952 3953 u8 reserved_at_280[0x80]; 3954 3955 u8 lid[0x10]; 3956 u8 reserved_at_310[0x4]; 3957 u8 init_type_reply[0x4]; 3958 u8 lmc[0x3]; 3959 u8 subnet_timeout[0x5]; 3960 3961 u8 sm_lid[0x10]; 3962 u8 sm_sl[0x4]; 3963 u8 reserved_at_334[0xc]; 3964 3965 u8 qkey_violation_counter[0x10]; 3966 u8 pkey_violation_counter[0x10]; 3967 3968 u8 reserved_at_360[0xca0]; 3969 }; 3970 3971 struct mlx5_ifc_esw_vport_context_bits { 3972 u8 fdb_to_vport_reg_c[0x1]; 3973 u8 reserved_at_1[0x2]; 3974 u8 vport_svlan_strip[0x1]; 3975 u8 vport_cvlan_strip[0x1]; 3976 u8 vport_svlan_insert[0x1]; 3977 u8 vport_cvlan_insert[0x2]; 3978 u8 fdb_to_vport_reg_c_id[0x8]; 3979 u8 reserved_at_10[0x10]; 3980 3981 u8 reserved_at_20[0x20]; 3982 3983 u8 svlan_cfi[0x1]; 3984 u8 svlan_pcp[0x3]; 3985 u8 svlan_id[0xc]; 3986 u8 cvlan_cfi[0x1]; 3987 u8 cvlan_pcp[0x3]; 3988 u8 cvlan_id[0xc]; 3989 3990 u8 reserved_at_60[0x720]; 3991 3992 u8 sw_steering_vport_icm_address_rx[0x40]; 3993 3994 u8 sw_steering_vport_icm_address_tx[0x40]; 3995 }; 3996 3997 enum { 3998 MLX5_EQC_STATUS_OK = 0x0, 3999 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4000 }; 4001 4002 enum { 4003 MLX5_EQC_ST_ARMED = 0x9, 4004 MLX5_EQC_ST_FIRED = 0xa, 4005 }; 4006 4007 struct mlx5_ifc_eqc_bits { 4008 u8 status[0x4]; 4009 u8 reserved_at_4[0x9]; 4010 u8 ec[0x1]; 4011 u8 oi[0x1]; 4012 u8 reserved_at_f[0x5]; 4013 u8 st[0x4]; 4014 u8 reserved_at_18[0x8]; 4015 4016 u8 reserved_at_20[0x20]; 4017 4018 u8 reserved_at_40[0x14]; 4019 u8 page_offset[0x6]; 4020 u8 reserved_at_5a[0x6]; 4021 4022 u8 reserved_at_60[0x3]; 4023 u8 log_eq_size[0x5]; 4024 u8 uar_page[0x18]; 4025 4026 u8 reserved_at_80[0x20]; 4027 4028 u8 reserved_at_a0[0x14]; 4029 u8 intr[0xc]; 4030 4031 u8 reserved_at_c0[0x3]; 4032 u8 log_page_size[0x5]; 4033 u8 reserved_at_c8[0x18]; 4034 4035 u8 reserved_at_e0[0x60]; 4036 4037 u8 reserved_at_140[0x8]; 4038 u8 consumer_counter[0x18]; 4039 4040 u8 reserved_at_160[0x8]; 4041 u8 producer_counter[0x18]; 4042 4043 u8 reserved_at_180[0x80]; 4044 }; 4045 4046 enum { 4047 MLX5_DCTC_STATE_ACTIVE = 0x0, 4048 MLX5_DCTC_STATE_DRAINING = 0x1, 4049 MLX5_DCTC_STATE_DRAINED = 0x2, 4050 }; 4051 4052 enum { 4053 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4054 MLX5_DCTC_CS_RES_NA = 0x1, 4055 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4056 }; 4057 4058 enum { 4059 MLX5_DCTC_MTU_256_BYTES = 0x1, 4060 MLX5_DCTC_MTU_512_BYTES = 0x2, 4061 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4062 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4063 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4064 }; 4065 4066 struct mlx5_ifc_dctc_bits { 4067 u8 reserved_at_0[0x4]; 4068 u8 state[0x4]; 4069 u8 reserved_at_8[0x18]; 4070 4071 u8 reserved_at_20[0x8]; 4072 u8 user_index[0x18]; 4073 4074 u8 reserved_at_40[0x8]; 4075 u8 cqn[0x18]; 4076 4077 u8 counter_set_id[0x8]; 4078 u8 atomic_mode[0x4]; 4079 u8 rre[0x1]; 4080 u8 rwe[0x1]; 4081 u8 rae[0x1]; 4082 u8 atomic_like_write_en[0x1]; 4083 u8 latency_sensitive[0x1]; 4084 u8 rlky[0x1]; 4085 u8 free_ar[0x1]; 4086 u8 reserved_at_73[0xd]; 4087 4088 u8 reserved_at_80[0x8]; 4089 u8 cs_res[0x8]; 4090 u8 reserved_at_90[0x3]; 4091 u8 min_rnr_nak[0x5]; 4092 u8 reserved_at_98[0x8]; 4093 4094 u8 reserved_at_a0[0x8]; 4095 u8 srqn_xrqn[0x18]; 4096 4097 u8 reserved_at_c0[0x8]; 4098 u8 pd[0x18]; 4099 4100 u8 tclass[0x8]; 4101 u8 reserved_at_e8[0x4]; 4102 u8 flow_label[0x14]; 4103 4104 u8 dc_access_key[0x40]; 4105 4106 u8 reserved_at_140[0x5]; 4107 u8 mtu[0x3]; 4108 u8 port[0x8]; 4109 u8 pkey_index[0x10]; 4110 4111 u8 reserved_at_160[0x8]; 4112 u8 my_addr_index[0x8]; 4113 u8 reserved_at_170[0x8]; 4114 u8 hop_limit[0x8]; 4115 4116 u8 dc_access_key_violation_count[0x20]; 4117 4118 u8 reserved_at_1a0[0x14]; 4119 u8 dei_cfi[0x1]; 4120 u8 eth_prio[0x3]; 4121 u8 ecn[0x2]; 4122 u8 dscp[0x6]; 4123 4124 u8 reserved_at_1c0[0x20]; 4125 u8 ece[0x20]; 4126 }; 4127 4128 enum { 4129 MLX5_CQC_STATUS_OK = 0x0, 4130 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4131 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4132 }; 4133 4134 enum { 4135 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4136 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4137 }; 4138 4139 enum { 4140 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4141 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4142 MLX5_CQC_ST_FIRED = 0xa, 4143 }; 4144 4145 enum { 4146 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4147 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4148 MLX5_CQ_PERIOD_NUM_MODES 4149 }; 4150 4151 struct mlx5_ifc_cqc_bits { 4152 u8 status[0x4]; 4153 u8 reserved_at_4[0x2]; 4154 u8 dbr_umem_valid[0x1]; 4155 u8 apu_cq[0x1]; 4156 u8 cqe_sz[0x3]; 4157 u8 cc[0x1]; 4158 u8 reserved_at_c[0x1]; 4159 u8 scqe_break_moderation_en[0x1]; 4160 u8 oi[0x1]; 4161 u8 cq_period_mode[0x2]; 4162 u8 cqe_comp_en[0x1]; 4163 u8 mini_cqe_res_format[0x2]; 4164 u8 st[0x4]; 4165 u8 reserved_at_18[0x6]; 4166 u8 cqe_compression_layout[0x2]; 4167 4168 u8 reserved_at_20[0x20]; 4169 4170 u8 reserved_at_40[0x14]; 4171 u8 page_offset[0x6]; 4172 u8 reserved_at_5a[0x6]; 4173 4174 u8 reserved_at_60[0x3]; 4175 u8 log_cq_size[0x5]; 4176 u8 uar_page[0x18]; 4177 4178 u8 reserved_at_80[0x4]; 4179 u8 cq_period[0xc]; 4180 u8 cq_max_count[0x10]; 4181 4182 u8 c_eqn_or_apu_element[0x20]; 4183 4184 u8 reserved_at_c0[0x3]; 4185 u8 log_page_size[0x5]; 4186 u8 reserved_at_c8[0x18]; 4187 4188 u8 reserved_at_e0[0x20]; 4189 4190 u8 reserved_at_100[0x8]; 4191 u8 last_notified_index[0x18]; 4192 4193 u8 reserved_at_120[0x8]; 4194 u8 last_solicit_index[0x18]; 4195 4196 u8 reserved_at_140[0x8]; 4197 u8 consumer_counter[0x18]; 4198 4199 u8 reserved_at_160[0x8]; 4200 u8 producer_counter[0x18]; 4201 4202 u8 reserved_at_180[0x40]; 4203 4204 u8 dbr_addr[0x40]; 4205 }; 4206 4207 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4208 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4209 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4210 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4211 u8 reserved_at_0[0x800]; 4212 }; 4213 4214 struct mlx5_ifc_query_adapter_param_block_bits { 4215 u8 reserved_at_0[0xc0]; 4216 4217 u8 reserved_at_c0[0x8]; 4218 u8 ieee_vendor_id[0x18]; 4219 4220 u8 reserved_at_e0[0x10]; 4221 u8 vsd_vendor_id[0x10]; 4222 4223 u8 vsd[208][0x8]; 4224 4225 u8 vsd_contd_psid[16][0x8]; 4226 }; 4227 4228 enum { 4229 MLX5_XRQC_STATE_GOOD = 0x0, 4230 MLX5_XRQC_STATE_ERROR = 0x1, 4231 }; 4232 4233 enum { 4234 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4235 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4236 }; 4237 4238 enum { 4239 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4240 }; 4241 4242 struct mlx5_ifc_tag_matching_topology_context_bits { 4243 u8 log_matching_list_sz[0x4]; 4244 u8 reserved_at_4[0xc]; 4245 u8 append_next_index[0x10]; 4246 4247 u8 sw_phase_cnt[0x10]; 4248 u8 hw_phase_cnt[0x10]; 4249 4250 u8 reserved_at_40[0x40]; 4251 }; 4252 4253 struct mlx5_ifc_xrqc_bits { 4254 u8 state[0x4]; 4255 u8 rlkey[0x1]; 4256 u8 reserved_at_5[0xf]; 4257 u8 topology[0x4]; 4258 u8 reserved_at_18[0x4]; 4259 u8 offload[0x4]; 4260 4261 u8 reserved_at_20[0x8]; 4262 u8 user_index[0x18]; 4263 4264 u8 reserved_at_40[0x8]; 4265 u8 cqn[0x18]; 4266 4267 u8 reserved_at_60[0xa0]; 4268 4269 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4270 4271 u8 reserved_at_180[0x280]; 4272 4273 struct mlx5_ifc_wq_bits wq; 4274 }; 4275 4276 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4277 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4278 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4279 u8 reserved_at_0[0x20]; 4280 }; 4281 4282 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4283 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4284 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4285 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4286 u8 reserved_at_0[0x20]; 4287 }; 4288 4289 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4290 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4291 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4292 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4293 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4294 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4295 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4296 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4297 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4298 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4299 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4300 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4301 u8 reserved_at_0[0x7c0]; 4302 }; 4303 4304 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4305 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4306 u8 reserved_at_0[0x7c0]; 4307 }; 4308 4309 union mlx5_ifc_event_auto_bits { 4310 struct mlx5_ifc_comp_event_bits comp_event; 4311 struct mlx5_ifc_dct_events_bits dct_events; 4312 struct mlx5_ifc_qp_events_bits qp_events; 4313 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4314 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4315 struct mlx5_ifc_cq_error_bits cq_error; 4316 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4317 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4318 struct mlx5_ifc_gpio_event_bits gpio_event; 4319 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4320 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4321 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4322 u8 reserved_at_0[0xe0]; 4323 }; 4324 4325 struct mlx5_ifc_health_buffer_bits { 4326 u8 reserved_at_0[0x100]; 4327 4328 u8 assert_existptr[0x20]; 4329 4330 u8 assert_callra[0x20]; 4331 4332 u8 reserved_at_140[0x20]; 4333 4334 u8 time[0x20]; 4335 4336 u8 fw_version[0x20]; 4337 4338 u8 hw_id[0x20]; 4339 4340 u8 rfr[0x1]; 4341 u8 reserved_at_1c1[0x3]; 4342 u8 valid[0x1]; 4343 u8 severity[0x3]; 4344 u8 reserved_at_1c8[0x18]; 4345 4346 u8 irisc_index[0x8]; 4347 u8 synd[0x8]; 4348 u8 ext_synd[0x10]; 4349 }; 4350 4351 struct mlx5_ifc_register_loopback_control_bits { 4352 u8 no_lb[0x1]; 4353 u8 reserved_at_1[0x7]; 4354 u8 port[0x8]; 4355 u8 reserved_at_10[0x10]; 4356 4357 u8 reserved_at_20[0x60]; 4358 }; 4359 4360 struct mlx5_ifc_vport_tc_element_bits { 4361 u8 traffic_class[0x4]; 4362 u8 reserved_at_4[0xc]; 4363 u8 vport_number[0x10]; 4364 }; 4365 4366 struct mlx5_ifc_vport_element_bits { 4367 u8 reserved_at_0[0x10]; 4368 u8 vport_number[0x10]; 4369 }; 4370 4371 enum { 4372 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4373 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4374 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4375 }; 4376 4377 struct mlx5_ifc_tsar_element_bits { 4378 u8 reserved_at_0[0x8]; 4379 u8 tsar_type[0x8]; 4380 u8 reserved_at_10[0x10]; 4381 }; 4382 4383 enum { 4384 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4385 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4386 }; 4387 4388 struct mlx5_ifc_teardown_hca_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_at_8[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_at_40[0x3f]; 4395 4396 u8 state[0x1]; 4397 }; 4398 4399 enum { 4400 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4401 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4402 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4403 }; 4404 4405 struct mlx5_ifc_teardown_hca_in_bits { 4406 u8 opcode[0x10]; 4407 u8 reserved_at_10[0x10]; 4408 4409 u8 reserved_at_20[0x10]; 4410 u8 op_mod[0x10]; 4411 4412 u8 reserved_at_40[0x10]; 4413 u8 profile[0x10]; 4414 4415 u8 reserved_at_60[0x20]; 4416 }; 4417 4418 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_at_8[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_at_40[0x40]; 4425 }; 4426 4427 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4428 u8 opcode[0x10]; 4429 u8 uid[0x10]; 4430 4431 u8 reserved_at_20[0x10]; 4432 u8 op_mod[0x10]; 4433 4434 u8 reserved_at_40[0x8]; 4435 u8 qpn[0x18]; 4436 4437 u8 reserved_at_60[0x20]; 4438 4439 u8 opt_param_mask[0x20]; 4440 4441 u8 reserved_at_a0[0x20]; 4442 4443 struct mlx5_ifc_qpc_bits qpc; 4444 4445 u8 reserved_at_800[0x80]; 4446 }; 4447 4448 struct mlx5_ifc_sqd2rts_qp_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_at_8[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 4454 u8 reserved_at_40[0x40]; 4455 }; 4456 4457 struct mlx5_ifc_sqd2rts_qp_in_bits { 4458 u8 opcode[0x10]; 4459 u8 uid[0x10]; 4460 4461 u8 reserved_at_20[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 reserved_at_40[0x8]; 4465 u8 qpn[0x18]; 4466 4467 u8 reserved_at_60[0x20]; 4468 4469 u8 opt_param_mask[0x20]; 4470 4471 u8 reserved_at_a0[0x20]; 4472 4473 struct mlx5_ifc_qpc_bits qpc; 4474 4475 u8 reserved_at_800[0x80]; 4476 }; 4477 4478 struct mlx5_ifc_set_roce_address_out_bits { 4479 u8 status[0x8]; 4480 u8 reserved_at_8[0x18]; 4481 4482 u8 syndrome[0x20]; 4483 4484 u8 reserved_at_40[0x40]; 4485 }; 4486 4487 struct mlx5_ifc_set_roce_address_in_bits { 4488 u8 opcode[0x10]; 4489 u8 reserved_at_10[0x10]; 4490 4491 u8 reserved_at_20[0x10]; 4492 u8 op_mod[0x10]; 4493 4494 u8 roce_address_index[0x10]; 4495 u8 reserved_at_50[0xc]; 4496 u8 vhca_port_num[0x4]; 4497 4498 u8 reserved_at_60[0x20]; 4499 4500 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4501 }; 4502 4503 struct mlx5_ifc_set_mad_demux_out_bits { 4504 u8 status[0x8]; 4505 u8 reserved_at_8[0x18]; 4506 4507 u8 syndrome[0x20]; 4508 4509 u8 reserved_at_40[0x40]; 4510 }; 4511 4512 enum { 4513 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4514 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4515 }; 4516 4517 struct mlx5_ifc_set_mad_demux_in_bits { 4518 u8 opcode[0x10]; 4519 u8 reserved_at_10[0x10]; 4520 4521 u8 reserved_at_20[0x10]; 4522 u8 op_mod[0x10]; 4523 4524 u8 reserved_at_40[0x20]; 4525 4526 u8 reserved_at_60[0x6]; 4527 u8 demux_mode[0x2]; 4528 u8 reserved_at_68[0x18]; 4529 }; 4530 4531 struct mlx5_ifc_set_l2_table_entry_out_bits { 4532 u8 status[0x8]; 4533 u8 reserved_at_8[0x18]; 4534 4535 u8 syndrome[0x20]; 4536 4537 u8 reserved_at_40[0x40]; 4538 }; 4539 4540 struct mlx5_ifc_set_l2_table_entry_in_bits { 4541 u8 opcode[0x10]; 4542 u8 reserved_at_10[0x10]; 4543 4544 u8 reserved_at_20[0x10]; 4545 u8 op_mod[0x10]; 4546 4547 u8 reserved_at_40[0x60]; 4548 4549 u8 reserved_at_a0[0x8]; 4550 u8 table_index[0x18]; 4551 4552 u8 reserved_at_c0[0x20]; 4553 4554 u8 reserved_at_e0[0x13]; 4555 u8 vlan_valid[0x1]; 4556 u8 vlan[0xc]; 4557 4558 struct mlx5_ifc_mac_address_layout_bits mac_address; 4559 4560 u8 reserved_at_140[0xc0]; 4561 }; 4562 4563 struct mlx5_ifc_set_issi_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_at_8[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_at_40[0x40]; 4570 }; 4571 4572 struct mlx5_ifc_set_issi_in_bits { 4573 u8 opcode[0x10]; 4574 u8 reserved_at_10[0x10]; 4575 4576 u8 reserved_at_20[0x10]; 4577 u8 op_mod[0x10]; 4578 4579 u8 reserved_at_40[0x10]; 4580 u8 current_issi[0x10]; 4581 4582 u8 reserved_at_60[0x20]; 4583 }; 4584 4585 struct mlx5_ifc_set_hca_cap_out_bits { 4586 u8 status[0x8]; 4587 u8 reserved_at_8[0x18]; 4588 4589 u8 syndrome[0x20]; 4590 4591 u8 reserved_at_40[0x40]; 4592 }; 4593 4594 struct mlx5_ifc_set_hca_cap_in_bits { 4595 u8 opcode[0x10]; 4596 u8 reserved_at_10[0x10]; 4597 4598 u8 reserved_at_20[0x10]; 4599 u8 op_mod[0x10]; 4600 4601 u8 other_function[0x1]; 4602 u8 reserved_at_41[0xf]; 4603 u8 function_id[0x10]; 4604 4605 u8 reserved_at_60[0x20]; 4606 4607 union mlx5_ifc_hca_cap_union_bits capability; 4608 }; 4609 4610 enum { 4611 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4612 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4613 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4614 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4615 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4616 }; 4617 4618 struct mlx5_ifc_set_fte_out_bits { 4619 u8 status[0x8]; 4620 u8 reserved_at_8[0x18]; 4621 4622 u8 syndrome[0x20]; 4623 4624 u8 reserved_at_40[0x40]; 4625 }; 4626 4627 struct mlx5_ifc_set_fte_in_bits { 4628 u8 opcode[0x10]; 4629 u8 reserved_at_10[0x10]; 4630 4631 u8 reserved_at_20[0x10]; 4632 u8 op_mod[0x10]; 4633 4634 u8 other_vport[0x1]; 4635 u8 reserved_at_41[0xf]; 4636 u8 vport_number[0x10]; 4637 4638 u8 reserved_at_60[0x20]; 4639 4640 u8 table_type[0x8]; 4641 u8 reserved_at_88[0x18]; 4642 4643 u8 reserved_at_a0[0x8]; 4644 u8 table_id[0x18]; 4645 4646 u8 ignore_flow_level[0x1]; 4647 u8 reserved_at_c1[0x17]; 4648 u8 modify_enable_mask[0x8]; 4649 4650 u8 reserved_at_e0[0x20]; 4651 4652 u8 flow_index[0x20]; 4653 4654 u8 reserved_at_120[0xe0]; 4655 4656 struct mlx5_ifc_flow_context_bits flow_context; 4657 }; 4658 4659 struct mlx5_ifc_rts2rts_qp_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_at_8[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 reserved_at_40[0x20]; 4666 u8 ece[0x20]; 4667 }; 4668 4669 struct mlx5_ifc_rts2rts_qp_in_bits { 4670 u8 opcode[0x10]; 4671 u8 uid[0x10]; 4672 4673 u8 reserved_at_20[0x10]; 4674 u8 op_mod[0x10]; 4675 4676 u8 reserved_at_40[0x8]; 4677 u8 qpn[0x18]; 4678 4679 u8 reserved_at_60[0x20]; 4680 4681 u8 opt_param_mask[0x20]; 4682 4683 u8 ece[0x20]; 4684 4685 struct mlx5_ifc_qpc_bits qpc; 4686 4687 u8 reserved_at_800[0x80]; 4688 }; 4689 4690 struct mlx5_ifc_rtr2rts_qp_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x20]; 4697 u8 ece[0x20]; 4698 }; 4699 4700 struct mlx5_ifc_rtr2rts_qp_in_bits { 4701 u8 opcode[0x10]; 4702 u8 uid[0x10]; 4703 4704 u8 reserved_at_20[0x10]; 4705 u8 op_mod[0x10]; 4706 4707 u8 reserved_at_40[0x8]; 4708 u8 qpn[0x18]; 4709 4710 u8 reserved_at_60[0x20]; 4711 4712 u8 opt_param_mask[0x20]; 4713 4714 u8 ece[0x20]; 4715 4716 struct mlx5_ifc_qpc_bits qpc; 4717 4718 u8 reserved_at_800[0x80]; 4719 }; 4720 4721 struct mlx5_ifc_rst2init_qp_out_bits { 4722 u8 status[0x8]; 4723 u8 reserved_at_8[0x18]; 4724 4725 u8 syndrome[0x20]; 4726 4727 u8 reserved_at_40[0x20]; 4728 u8 ece[0x20]; 4729 }; 4730 4731 struct mlx5_ifc_rst2init_qp_in_bits { 4732 u8 opcode[0x10]; 4733 u8 uid[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 reserved_at_40[0x8]; 4739 u8 qpn[0x18]; 4740 4741 u8 reserved_at_60[0x20]; 4742 4743 u8 opt_param_mask[0x20]; 4744 4745 u8 ece[0x20]; 4746 4747 struct mlx5_ifc_qpc_bits qpc; 4748 4749 u8 reserved_at_800[0x80]; 4750 }; 4751 4752 struct mlx5_ifc_query_xrq_out_bits { 4753 u8 status[0x8]; 4754 u8 reserved_at_8[0x18]; 4755 4756 u8 syndrome[0x20]; 4757 4758 u8 reserved_at_40[0x40]; 4759 4760 struct mlx5_ifc_xrqc_bits xrq_context; 4761 }; 4762 4763 struct mlx5_ifc_query_xrq_in_bits { 4764 u8 opcode[0x10]; 4765 u8 reserved_at_10[0x10]; 4766 4767 u8 reserved_at_20[0x10]; 4768 u8 op_mod[0x10]; 4769 4770 u8 reserved_at_40[0x8]; 4771 u8 xrqn[0x18]; 4772 4773 u8 reserved_at_60[0x20]; 4774 }; 4775 4776 struct mlx5_ifc_query_xrc_srq_out_bits { 4777 u8 status[0x8]; 4778 u8 reserved_at_8[0x18]; 4779 4780 u8 syndrome[0x20]; 4781 4782 u8 reserved_at_40[0x40]; 4783 4784 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4785 4786 u8 reserved_at_280[0x600]; 4787 4788 u8 pas[][0x40]; 4789 }; 4790 4791 struct mlx5_ifc_query_xrc_srq_in_bits { 4792 u8 opcode[0x10]; 4793 u8 reserved_at_10[0x10]; 4794 4795 u8 reserved_at_20[0x10]; 4796 u8 op_mod[0x10]; 4797 4798 u8 reserved_at_40[0x8]; 4799 u8 xrc_srqn[0x18]; 4800 4801 u8 reserved_at_60[0x20]; 4802 }; 4803 4804 enum { 4805 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4806 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4807 }; 4808 4809 struct mlx5_ifc_query_vport_state_out_bits { 4810 u8 status[0x8]; 4811 u8 reserved_at_8[0x18]; 4812 4813 u8 syndrome[0x20]; 4814 4815 u8 reserved_at_40[0x20]; 4816 4817 u8 reserved_at_60[0x18]; 4818 u8 admin_state[0x4]; 4819 u8 state[0x4]; 4820 }; 4821 4822 enum { 4823 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4824 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4825 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4826 }; 4827 4828 struct mlx5_ifc_arm_monitor_counter_in_bits { 4829 u8 opcode[0x10]; 4830 u8 uid[0x10]; 4831 4832 u8 reserved_at_20[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 reserved_at_40[0x20]; 4836 4837 u8 reserved_at_60[0x20]; 4838 }; 4839 4840 struct mlx5_ifc_arm_monitor_counter_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0x40]; 4847 }; 4848 4849 enum { 4850 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4851 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4852 }; 4853 4854 enum mlx5_monitor_counter_ppcnt { 4855 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4856 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4857 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4858 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4859 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4860 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4861 }; 4862 4863 enum { 4864 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4865 }; 4866 4867 struct mlx5_ifc_monitor_counter_output_bits { 4868 u8 reserved_at_0[0x4]; 4869 u8 type[0x4]; 4870 u8 reserved_at_8[0x8]; 4871 u8 counter[0x10]; 4872 4873 u8 counter_group_id[0x20]; 4874 }; 4875 4876 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4877 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4878 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4879 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4880 4881 struct mlx5_ifc_set_monitor_counter_in_bits { 4882 u8 opcode[0x10]; 4883 u8 uid[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 reserved_at_40[0x10]; 4889 u8 num_of_counters[0x10]; 4890 4891 u8 reserved_at_60[0x20]; 4892 4893 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4894 }; 4895 4896 struct mlx5_ifc_set_monitor_counter_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x40]; 4903 }; 4904 4905 struct mlx5_ifc_query_vport_state_in_bits { 4906 u8 opcode[0x10]; 4907 u8 reserved_at_10[0x10]; 4908 4909 u8 reserved_at_20[0x10]; 4910 u8 op_mod[0x10]; 4911 4912 u8 other_vport[0x1]; 4913 u8 reserved_at_41[0xf]; 4914 u8 vport_number[0x10]; 4915 4916 u8 reserved_at_60[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_query_vnic_env_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_at_8[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_at_40[0x40]; 4926 4927 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4928 }; 4929 4930 enum { 4931 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4932 }; 4933 4934 struct mlx5_ifc_query_vnic_env_in_bits { 4935 u8 opcode[0x10]; 4936 u8 reserved_at_10[0x10]; 4937 4938 u8 reserved_at_20[0x10]; 4939 u8 op_mod[0x10]; 4940 4941 u8 other_vport[0x1]; 4942 u8 reserved_at_41[0xf]; 4943 u8 vport_number[0x10]; 4944 4945 u8 reserved_at_60[0x20]; 4946 }; 4947 4948 struct mlx5_ifc_query_vport_counter_out_bits { 4949 u8 status[0x8]; 4950 u8 reserved_at_8[0x18]; 4951 4952 u8 syndrome[0x20]; 4953 4954 u8 reserved_at_40[0x40]; 4955 4956 struct mlx5_ifc_traffic_counter_bits received_errors; 4957 4958 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4959 4960 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4961 4962 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4963 4964 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4965 4966 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4967 4968 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4969 4970 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4971 4972 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4973 4974 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4975 4976 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4977 4978 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4979 4980 u8 reserved_at_680[0xa00]; 4981 }; 4982 4983 enum { 4984 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4985 }; 4986 4987 struct mlx5_ifc_query_vport_counter_in_bits { 4988 u8 opcode[0x10]; 4989 u8 reserved_at_10[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 other_vport[0x1]; 4995 u8 reserved_at_41[0xb]; 4996 u8 port_num[0x4]; 4997 u8 vport_number[0x10]; 4998 4999 u8 reserved_at_60[0x60]; 5000 5001 u8 clear[0x1]; 5002 u8 reserved_at_c1[0x1f]; 5003 5004 u8 reserved_at_e0[0x20]; 5005 }; 5006 5007 struct mlx5_ifc_query_tis_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 5015 struct mlx5_ifc_tisc_bits tis_context; 5016 }; 5017 5018 struct mlx5_ifc_query_tis_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_at_40[0x8]; 5026 u8 tisn[0x18]; 5027 5028 u8 reserved_at_60[0x20]; 5029 }; 5030 5031 struct mlx5_ifc_query_tir_out_bits { 5032 u8 status[0x8]; 5033 u8 reserved_at_8[0x18]; 5034 5035 u8 syndrome[0x20]; 5036 5037 u8 reserved_at_40[0xc0]; 5038 5039 struct mlx5_ifc_tirc_bits tir_context; 5040 }; 5041 5042 struct mlx5_ifc_query_tir_in_bits { 5043 u8 opcode[0x10]; 5044 u8 reserved_at_10[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 reserved_at_40[0x8]; 5050 u8 tirn[0x18]; 5051 5052 u8 reserved_at_60[0x20]; 5053 }; 5054 5055 struct mlx5_ifc_query_srq_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0x40]; 5062 5063 struct mlx5_ifc_srqc_bits srq_context_entry; 5064 5065 u8 reserved_at_280[0x600]; 5066 5067 u8 pas[][0x40]; 5068 }; 5069 5070 struct mlx5_ifc_query_srq_in_bits { 5071 u8 opcode[0x10]; 5072 u8 reserved_at_10[0x10]; 5073 5074 u8 reserved_at_20[0x10]; 5075 u8 op_mod[0x10]; 5076 5077 u8 reserved_at_40[0x8]; 5078 u8 srqn[0x18]; 5079 5080 u8 reserved_at_60[0x20]; 5081 }; 5082 5083 struct mlx5_ifc_query_sq_out_bits { 5084 u8 status[0x8]; 5085 u8 reserved_at_8[0x18]; 5086 5087 u8 syndrome[0x20]; 5088 5089 u8 reserved_at_40[0xc0]; 5090 5091 struct mlx5_ifc_sqc_bits sq_context; 5092 }; 5093 5094 struct mlx5_ifc_query_sq_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_at_10[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x8]; 5102 u8 sqn[0x18]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_query_special_contexts_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 dump_fill_mkey[0x20]; 5114 5115 u8 resd_lkey[0x20]; 5116 5117 u8 null_mkey[0x20]; 5118 5119 u8 reserved_at_a0[0x60]; 5120 }; 5121 5122 struct mlx5_ifc_query_special_contexts_in_bits { 5123 u8 opcode[0x10]; 5124 u8 reserved_at_10[0x10]; 5125 5126 u8 reserved_at_20[0x10]; 5127 u8 op_mod[0x10]; 5128 5129 u8 reserved_at_40[0x40]; 5130 }; 5131 5132 struct mlx5_ifc_query_scheduling_element_out_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 reserved_at_40[0xc0]; 5140 5141 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5142 5143 u8 reserved_at_300[0x100]; 5144 }; 5145 5146 enum { 5147 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5148 SCHEDULING_HIERARCHY_NIC = 0x3, 5149 }; 5150 5151 struct mlx5_ifc_query_scheduling_element_in_bits { 5152 u8 opcode[0x10]; 5153 u8 reserved_at_10[0x10]; 5154 5155 u8 reserved_at_20[0x10]; 5156 u8 op_mod[0x10]; 5157 5158 u8 scheduling_hierarchy[0x8]; 5159 u8 reserved_at_48[0x18]; 5160 5161 u8 scheduling_element_id[0x20]; 5162 5163 u8 reserved_at_80[0x180]; 5164 }; 5165 5166 struct mlx5_ifc_query_rqt_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 reserved_at_40[0xc0]; 5173 5174 struct mlx5_ifc_rqtc_bits rqt_context; 5175 }; 5176 5177 struct mlx5_ifc_query_rqt_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_at_10[0x10]; 5180 5181 u8 reserved_at_20[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 reserved_at_40[0x8]; 5185 u8 rqtn[0x18]; 5186 5187 u8 reserved_at_60[0x20]; 5188 }; 5189 5190 struct mlx5_ifc_query_rq_out_bits { 5191 u8 status[0x8]; 5192 u8 reserved_at_8[0x18]; 5193 5194 u8 syndrome[0x20]; 5195 5196 u8 reserved_at_40[0xc0]; 5197 5198 struct mlx5_ifc_rqc_bits rq_context; 5199 }; 5200 5201 struct mlx5_ifc_query_rq_in_bits { 5202 u8 opcode[0x10]; 5203 u8 reserved_at_10[0x10]; 5204 5205 u8 reserved_at_20[0x10]; 5206 u8 op_mod[0x10]; 5207 5208 u8 reserved_at_40[0x8]; 5209 u8 rqn[0x18]; 5210 5211 u8 reserved_at_60[0x20]; 5212 }; 5213 5214 struct mlx5_ifc_query_roce_address_out_bits { 5215 u8 status[0x8]; 5216 u8 reserved_at_8[0x18]; 5217 5218 u8 syndrome[0x20]; 5219 5220 u8 reserved_at_40[0x40]; 5221 5222 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5223 }; 5224 5225 struct mlx5_ifc_query_roce_address_in_bits { 5226 u8 opcode[0x10]; 5227 u8 reserved_at_10[0x10]; 5228 5229 u8 reserved_at_20[0x10]; 5230 u8 op_mod[0x10]; 5231 5232 u8 roce_address_index[0x10]; 5233 u8 reserved_at_50[0xc]; 5234 u8 vhca_port_num[0x4]; 5235 5236 u8 reserved_at_60[0x20]; 5237 }; 5238 5239 struct mlx5_ifc_query_rmp_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_at_8[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_at_40[0xc0]; 5246 5247 struct mlx5_ifc_rmpc_bits rmp_context; 5248 }; 5249 5250 struct mlx5_ifc_query_rmp_in_bits { 5251 u8 opcode[0x10]; 5252 u8 reserved_at_10[0x10]; 5253 5254 u8 reserved_at_20[0x10]; 5255 u8 op_mod[0x10]; 5256 5257 u8 reserved_at_40[0x8]; 5258 u8 rmpn[0x18]; 5259 5260 u8 reserved_at_60[0x20]; 5261 }; 5262 5263 struct mlx5_ifc_query_qp_out_bits { 5264 u8 status[0x8]; 5265 u8 reserved_at_8[0x18]; 5266 5267 u8 syndrome[0x20]; 5268 5269 u8 reserved_at_40[0x40]; 5270 5271 u8 opt_param_mask[0x20]; 5272 5273 u8 ece[0x20]; 5274 5275 struct mlx5_ifc_qpc_bits qpc; 5276 5277 u8 reserved_at_800[0x80]; 5278 5279 u8 pas[][0x40]; 5280 }; 5281 5282 struct mlx5_ifc_query_qp_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_at_10[0x10]; 5285 5286 u8 reserved_at_20[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 reserved_at_40[0x8]; 5290 u8 qpn[0x18]; 5291 5292 u8 reserved_at_60[0x20]; 5293 }; 5294 5295 struct mlx5_ifc_query_q_counter_out_bits { 5296 u8 status[0x8]; 5297 u8 reserved_at_8[0x18]; 5298 5299 u8 syndrome[0x20]; 5300 5301 u8 reserved_at_40[0x40]; 5302 5303 u8 rx_write_requests[0x20]; 5304 5305 u8 reserved_at_a0[0x20]; 5306 5307 u8 rx_read_requests[0x20]; 5308 5309 u8 reserved_at_e0[0x20]; 5310 5311 u8 rx_atomic_requests[0x20]; 5312 5313 u8 reserved_at_120[0x20]; 5314 5315 u8 rx_dct_connect[0x20]; 5316 5317 u8 reserved_at_160[0x20]; 5318 5319 u8 out_of_buffer[0x20]; 5320 5321 u8 reserved_at_1a0[0x20]; 5322 5323 u8 out_of_sequence[0x20]; 5324 5325 u8 reserved_at_1e0[0x20]; 5326 5327 u8 duplicate_request[0x20]; 5328 5329 u8 reserved_at_220[0x20]; 5330 5331 u8 rnr_nak_retry_err[0x20]; 5332 5333 u8 reserved_at_260[0x20]; 5334 5335 u8 packet_seq_err[0x20]; 5336 5337 u8 reserved_at_2a0[0x20]; 5338 5339 u8 implied_nak_seq_err[0x20]; 5340 5341 u8 reserved_at_2e0[0x20]; 5342 5343 u8 local_ack_timeout_err[0x20]; 5344 5345 u8 reserved_at_320[0xa0]; 5346 5347 u8 resp_local_length_error[0x20]; 5348 5349 u8 req_local_length_error[0x20]; 5350 5351 u8 resp_local_qp_error[0x20]; 5352 5353 u8 local_operation_error[0x20]; 5354 5355 u8 resp_local_protection[0x20]; 5356 5357 u8 req_local_protection[0x20]; 5358 5359 u8 resp_cqe_error[0x20]; 5360 5361 u8 req_cqe_error[0x20]; 5362 5363 u8 req_mw_binding[0x20]; 5364 5365 u8 req_bad_response[0x20]; 5366 5367 u8 req_remote_invalid_request[0x20]; 5368 5369 u8 resp_remote_invalid_request[0x20]; 5370 5371 u8 req_remote_access_errors[0x20]; 5372 5373 u8 resp_remote_access_errors[0x20]; 5374 5375 u8 req_remote_operation_errors[0x20]; 5376 5377 u8 req_transport_retries_exceeded[0x20]; 5378 5379 u8 cq_overflow[0x20]; 5380 5381 u8 resp_cqe_flush_error[0x20]; 5382 5383 u8 req_cqe_flush_error[0x20]; 5384 5385 u8 reserved_at_620[0x20]; 5386 5387 u8 roce_adp_retrans[0x20]; 5388 5389 u8 roce_adp_retrans_to[0x20]; 5390 5391 u8 roce_slow_restart[0x20]; 5392 5393 u8 roce_slow_restart_cnps[0x20]; 5394 5395 u8 roce_slow_restart_trans[0x20]; 5396 5397 u8 reserved_at_6e0[0x120]; 5398 }; 5399 5400 struct mlx5_ifc_query_q_counter_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 reserved_at_40[0x80]; 5408 5409 u8 clear[0x1]; 5410 u8 reserved_at_c1[0x1f]; 5411 5412 u8 reserved_at_e0[0x18]; 5413 u8 counter_set_id[0x8]; 5414 }; 5415 5416 struct mlx5_ifc_query_pages_out_bits { 5417 u8 status[0x8]; 5418 u8 reserved_at_8[0x18]; 5419 5420 u8 syndrome[0x20]; 5421 5422 u8 embedded_cpu_function[0x1]; 5423 u8 reserved_at_41[0xf]; 5424 u8 function_id[0x10]; 5425 5426 u8 num_pages[0x20]; 5427 }; 5428 5429 enum { 5430 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5431 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5432 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5433 }; 5434 5435 struct mlx5_ifc_query_pages_in_bits { 5436 u8 opcode[0x10]; 5437 u8 reserved_at_10[0x10]; 5438 5439 u8 reserved_at_20[0x10]; 5440 u8 op_mod[0x10]; 5441 5442 u8 embedded_cpu_function[0x1]; 5443 u8 reserved_at_41[0xf]; 5444 u8 function_id[0x10]; 5445 5446 u8 reserved_at_60[0x20]; 5447 }; 5448 5449 struct mlx5_ifc_query_nic_vport_context_out_bits { 5450 u8 status[0x8]; 5451 u8 reserved_at_8[0x18]; 5452 5453 u8 syndrome[0x20]; 5454 5455 u8 reserved_at_40[0x40]; 5456 5457 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5458 }; 5459 5460 struct mlx5_ifc_query_nic_vport_context_in_bits { 5461 u8 opcode[0x10]; 5462 u8 reserved_at_10[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 other_vport[0x1]; 5468 u8 reserved_at_41[0xf]; 5469 u8 vport_number[0x10]; 5470 5471 u8 reserved_at_60[0x5]; 5472 u8 allowed_list_type[0x3]; 5473 u8 reserved_at_68[0x18]; 5474 }; 5475 5476 struct mlx5_ifc_query_mkey_out_bits { 5477 u8 status[0x8]; 5478 u8 reserved_at_8[0x18]; 5479 5480 u8 syndrome[0x20]; 5481 5482 u8 reserved_at_40[0x40]; 5483 5484 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5485 5486 u8 reserved_at_280[0x600]; 5487 5488 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5489 5490 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5491 }; 5492 5493 struct mlx5_ifc_query_mkey_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_at_10[0x10]; 5496 5497 u8 reserved_at_20[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 reserved_at_40[0x8]; 5501 u8 mkey_index[0x18]; 5502 5503 u8 pg_access[0x1]; 5504 u8 reserved_at_61[0x1f]; 5505 }; 5506 5507 struct mlx5_ifc_query_mad_demux_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0x40]; 5514 5515 u8 mad_dumux_parameters_block[0x20]; 5516 }; 5517 5518 struct mlx5_ifc_query_mad_demux_in_bits { 5519 u8 opcode[0x10]; 5520 u8 reserved_at_10[0x10]; 5521 5522 u8 reserved_at_20[0x10]; 5523 u8 op_mod[0x10]; 5524 5525 u8 reserved_at_40[0x40]; 5526 }; 5527 5528 struct mlx5_ifc_query_l2_table_entry_out_bits { 5529 u8 status[0x8]; 5530 u8 reserved_at_8[0x18]; 5531 5532 u8 syndrome[0x20]; 5533 5534 u8 reserved_at_40[0xa0]; 5535 5536 u8 reserved_at_e0[0x13]; 5537 u8 vlan_valid[0x1]; 5538 u8 vlan[0xc]; 5539 5540 struct mlx5_ifc_mac_address_layout_bits mac_address; 5541 5542 u8 reserved_at_140[0xc0]; 5543 }; 5544 5545 struct mlx5_ifc_query_l2_table_entry_in_bits { 5546 u8 opcode[0x10]; 5547 u8 reserved_at_10[0x10]; 5548 5549 u8 reserved_at_20[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 reserved_at_40[0x60]; 5553 5554 u8 reserved_at_a0[0x8]; 5555 u8 table_index[0x18]; 5556 5557 u8 reserved_at_c0[0x140]; 5558 }; 5559 5560 struct mlx5_ifc_query_issi_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x10]; 5567 u8 current_issi[0x10]; 5568 5569 u8 reserved_at_60[0xa0]; 5570 5571 u8 reserved_at_100[76][0x8]; 5572 u8 supported_issi_dw0[0x20]; 5573 }; 5574 5575 struct mlx5_ifc_query_issi_in_bits { 5576 u8 opcode[0x10]; 5577 u8 reserved_at_10[0x10]; 5578 5579 u8 reserved_at_20[0x10]; 5580 u8 op_mod[0x10]; 5581 5582 u8 reserved_at_40[0x40]; 5583 }; 5584 5585 struct mlx5_ifc_set_driver_version_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_0[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 u8 reserved_1[0x40]; 5591 }; 5592 5593 struct mlx5_ifc_set_driver_version_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_0[0x10]; 5596 5597 u8 reserved_1[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 reserved_2[0x40]; 5601 u8 driver_version[64][0x8]; 5602 }; 5603 5604 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5605 u8 status[0x8]; 5606 u8 reserved_at_8[0x18]; 5607 5608 u8 syndrome[0x20]; 5609 5610 u8 reserved_at_40[0x40]; 5611 5612 struct mlx5_ifc_pkey_bits pkey[]; 5613 }; 5614 5615 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5616 u8 opcode[0x10]; 5617 u8 reserved_at_10[0x10]; 5618 5619 u8 reserved_at_20[0x10]; 5620 u8 op_mod[0x10]; 5621 5622 u8 other_vport[0x1]; 5623 u8 reserved_at_41[0xb]; 5624 u8 port_num[0x4]; 5625 u8 vport_number[0x10]; 5626 5627 u8 reserved_at_60[0x10]; 5628 u8 pkey_index[0x10]; 5629 }; 5630 5631 enum { 5632 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5633 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5634 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5635 }; 5636 5637 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5638 u8 status[0x8]; 5639 u8 reserved_at_8[0x18]; 5640 5641 u8 syndrome[0x20]; 5642 5643 u8 reserved_at_40[0x20]; 5644 5645 u8 gids_num[0x10]; 5646 u8 reserved_at_70[0x10]; 5647 5648 struct mlx5_ifc_array128_auto_bits gid[]; 5649 }; 5650 5651 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 other_vport[0x1]; 5659 u8 reserved_at_41[0xb]; 5660 u8 port_num[0x4]; 5661 u8 vport_number[0x10]; 5662 5663 u8 reserved_at_60[0x10]; 5664 u8 gid_index[0x10]; 5665 }; 5666 5667 struct mlx5_ifc_query_hca_vport_context_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_at_8[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 reserved_at_40[0x40]; 5674 5675 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5676 }; 5677 5678 struct mlx5_ifc_query_hca_vport_context_in_bits { 5679 u8 opcode[0x10]; 5680 u8 reserved_at_10[0x10]; 5681 5682 u8 reserved_at_20[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 other_vport[0x1]; 5686 u8 reserved_at_41[0xb]; 5687 u8 port_num[0x4]; 5688 u8 vport_number[0x10]; 5689 5690 u8 reserved_at_60[0x20]; 5691 }; 5692 5693 struct mlx5_ifc_query_hca_cap_out_bits { 5694 u8 status[0x8]; 5695 u8 reserved_at_8[0x18]; 5696 5697 u8 syndrome[0x20]; 5698 5699 u8 reserved_at_40[0x40]; 5700 5701 union mlx5_ifc_hca_cap_union_bits capability; 5702 }; 5703 5704 struct mlx5_ifc_query_hca_cap_in_bits { 5705 u8 opcode[0x10]; 5706 u8 reserved_at_10[0x10]; 5707 5708 u8 reserved_at_20[0x10]; 5709 u8 op_mod[0x10]; 5710 5711 u8 other_function[0x1]; 5712 u8 reserved_at_41[0xf]; 5713 u8 function_id[0x10]; 5714 5715 u8 reserved_at_60[0x20]; 5716 }; 5717 5718 struct mlx5_ifc_other_hca_cap_bits { 5719 u8 roce[0x1]; 5720 u8 reserved_at_1[0x27f]; 5721 }; 5722 5723 struct mlx5_ifc_query_other_hca_cap_out_bits { 5724 u8 status[0x8]; 5725 u8 reserved_at_8[0x18]; 5726 5727 u8 syndrome[0x20]; 5728 5729 u8 reserved_at_40[0x40]; 5730 5731 struct mlx5_ifc_other_hca_cap_bits other_capability; 5732 }; 5733 5734 struct mlx5_ifc_query_other_hca_cap_in_bits { 5735 u8 opcode[0x10]; 5736 u8 reserved_at_10[0x10]; 5737 5738 u8 reserved_at_20[0x10]; 5739 u8 op_mod[0x10]; 5740 5741 u8 reserved_at_40[0x10]; 5742 u8 function_id[0x10]; 5743 5744 u8 reserved_at_60[0x20]; 5745 }; 5746 5747 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_at_8[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_at_40[0x40]; 5754 }; 5755 5756 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5757 u8 opcode[0x10]; 5758 u8 reserved_at_10[0x10]; 5759 5760 u8 reserved_at_20[0x10]; 5761 u8 op_mod[0x10]; 5762 5763 u8 reserved_at_40[0x10]; 5764 u8 function_id[0x10]; 5765 u8 field_select[0x20]; 5766 5767 struct mlx5_ifc_other_hca_cap_bits other_capability; 5768 }; 5769 5770 struct mlx5_ifc_flow_table_context_bits { 5771 u8 reformat_en[0x1]; 5772 u8 decap_en[0x1]; 5773 u8 sw_owner[0x1]; 5774 u8 termination_table[0x1]; 5775 u8 table_miss_action[0x4]; 5776 u8 level[0x8]; 5777 u8 reserved_at_10[0x8]; 5778 u8 log_size[0x8]; 5779 5780 u8 reserved_at_20[0x8]; 5781 u8 table_miss_id[0x18]; 5782 5783 u8 reserved_at_40[0x8]; 5784 u8 lag_master_next_table_id[0x18]; 5785 5786 u8 reserved_at_60[0x60]; 5787 5788 u8 sw_owner_icm_root_1[0x40]; 5789 5790 u8 sw_owner_icm_root_0[0x40]; 5791 5792 }; 5793 5794 struct mlx5_ifc_query_flow_table_out_bits { 5795 u8 status[0x8]; 5796 u8 reserved_at_8[0x18]; 5797 5798 u8 syndrome[0x20]; 5799 5800 u8 reserved_at_40[0x80]; 5801 5802 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5803 }; 5804 5805 struct mlx5_ifc_query_flow_table_in_bits { 5806 u8 opcode[0x10]; 5807 u8 reserved_at_10[0x10]; 5808 5809 u8 reserved_at_20[0x10]; 5810 u8 op_mod[0x10]; 5811 5812 u8 reserved_at_40[0x40]; 5813 5814 u8 table_type[0x8]; 5815 u8 reserved_at_88[0x18]; 5816 5817 u8 reserved_at_a0[0x8]; 5818 u8 table_id[0x18]; 5819 5820 u8 reserved_at_c0[0x140]; 5821 }; 5822 5823 struct mlx5_ifc_query_fte_out_bits { 5824 u8 status[0x8]; 5825 u8 reserved_at_8[0x18]; 5826 5827 u8 syndrome[0x20]; 5828 5829 u8 reserved_at_40[0x1c0]; 5830 5831 struct mlx5_ifc_flow_context_bits flow_context; 5832 }; 5833 5834 struct mlx5_ifc_query_fte_in_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_at_10[0x10]; 5837 5838 u8 reserved_at_20[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 reserved_at_40[0x40]; 5842 5843 u8 table_type[0x8]; 5844 u8 reserved_at_88[0x18]; 5845 5846 u8 reserved_at_a0[0x8]; 5847 u8 table_id[0x18]; 5848 5849 u8 reserved_at_c0[0x40]; 5850 5851 u8 flow_index[0x20]; 5852 5853 u8 reserved_at_120[0xe0]; 5854 }; 5855 5856 struct mlx5_ifc_match_definer_format_0_bits { 5857 u8 reserved_at_0[0x100]; 5858 5859 u8 metadata_reg_c_0[0x20]; 5860 5861 u8 metadata_reg_c_1[0x20]; 5862 5863 u8 outer_dmac_47_16[0x20]; 5864 5865 u8 outer_dmac_15_0[0x10]; 5866 u8 outer_ethertype[0x10]; 5867 5868 u8 reserved_at_180[0x1]; 5869 u8 sx_sniffer[0x1]; 5870 u8 functional_lb[0x1]; 5871 u8 outer_ip_frag[0x1]; 5872 u8 outer_qp_type[0x2]; 5873 u8 outer_encap_type[0x2]; 5874 u8 port_number[0x2]; 5875 u8 outer_l3_type[0x2]; 5876 u8 outer_l4_type[0x2]; 5877 u8 outer_first_vlan_type[0x2]; 5878 u8 outer_first_vlan_prio[0x3]; 5879 u8 outer_first_vlan_cfi[0x1]; 5880 u8 outer_first_vlan_vid[0xc]; 5881 5882 u8 outer_l4_type_ext[0x4]; 5883 u8 reserved_at_1a4[0x2]; 5884 u8 outer_ipsec_layer[0x2]; 5885 u8 outer_l2_type[0x2]; 5886 u8 force_lb[0x1]; 5887 u8 outer_l2_ok[0x1]; 5888 u8 outer_l3_ok[0x1]; 5889 u8 outer_l4_ok[0x1]; 5890 u8 outer_second_vlan_type[0x2]; 5891 u8 outer_second_vlan_prio[0x3]; 5892 u8 outer_second_vlan_cfi[0x1]; 5893 u8 outer_second_vlan_vid[0xc]; 5894 5895 u8 outer_smac_47_16[0x20]; 5896 5897 u8 outer_smac_15_0[0x10]; 5898 u8 inner_ipv4_checksum_ok[0x1]; 5899 u8 inner_l4_checksum_ok[0x1]; 5900 u8 outer_ipv4_checksum_ok[0x1]; 5901 u8 outer_l4_checksum_ok[0x1]; 5902 u8 inner_l3_ok[0x1]; 5903 u8 inner_l4_ok[0x1]; 5904 u8 outer_l3_ok_duplicate[0x1]; 5905 u8 outer_l4_ok_duplicate[0x1]; 5906 u8 outer_tcp_cwr[0x1]; 5907 u8 outer_tcp_ece[0x1]; 5908 u8 outer_tcp_urg[0x1]; 5909 u8 outer_tcp_ack[0x1]; 5910 u8 outer_tcp_psh[0x1]; 5911 u8 outer_tcp_rst[0x1]; 5912 u8 outer_tcp_syn[0x1]; 5913 u8 outer_tcp_fin[0x1]; 5914 }; 5915 5916 struct mlx5_ifc_match_definer_format_22_bits { 5917 u8 reserved_at_0[0x100]; 5918 5919 u8 outer_ip_src_addr[0x20]; 5920 5921 u8 outer_ip_dest_addr[0x20]; 5922 5923 u8 outer_l4_sport[0x10]; 5924 u8 outer_l4_dport[0x10]; 5925 5926 u8 reserved_at_160[0x1]; 5927 u8 sx_sniffer[0x1]; 5928 u8 functional_lb[0x1]; 5929 u8 outer_ip_frag[0x1]; 5930 u8 outer_qp_type[0x2]; 5931 u8 outer_encap_type[0x2]; 5932 u8 port_number[0x2]; 5933 u8 outer_l3_type[0x2]; 5934 u8 outer_l4_type[0x2]; 5935 u8 outer_first_vlan_type[0x2]; 5936 u8 outer_first_vlan_prio[0x3]; 5937 u8 outer_first_vlan_cfi[0x1]; 5938 u8 outer_first_vlan_vid[0xc]; 5939 5940 u8 metadata_reg_c_0[0x20]; 5941 5942 u8 outer_dmac_47_16[0x20]; 5943 5944 u8 outer_smac_47_16[0x20]; 5945 5946 u8 outer_smac_15_0[0x10]; 5947 u8 outer_dmac_15_0[0x10]; 5948 }; 5949 5950 struct mlx5_ifc_match_definer_format_23_bits { 5951 u8 reserved_at_0[0x100]; 5952 5953 u8 inner_ip_src_addr[0x20]; 5954 5955 u8 inner_ip_dest_addr[0x20]; 5956 5957 u8 inner_l4_sport[0x10]; 5958 u8 inner_l4_dport[0x10]; 5959 5960 u8 reserved_at_160[0x1]; 5961 u8 sx_sniffer[0x1]; 5962 u8 functional_lb[0x1]; 5963 u8 inner_ip_frag[0x1]; 5964 u8 inner_qp_type[0x2]; 5965 u8 inner_encap_type[0x2]; 5966 u8 port_number[0x2]; 5967 u8 inner_l3_type[0x2]; 5968 u8 inner_l4_type[0x2]; 5969 u8 inner_first_vlan_type[0x2]; 5970 u8 inner_first_vlan_prio[0x3]; 5971 u8 inner_first_vlan_cfi[0x1]; 5972 u8 inner_first_vlan_vid[0xc]; 5973 5974 u8 tunnel_header_0[0x20]; 5975 5976 u8 inner_dmac_47_16[0x20]; 5977 5978 u8 inner_smac_47_16[0x20]; 5979 5980 u8 inner_smac_15_0[0x10]; 5981 u8 inner_dmac_15_0[0x10]; 5982 }; 5983 5984 struct mlx5_ifc_match_definer_format_29_bits { 5985 u8 reserved_at_0[0xc0]; 5986 5987 u8 outer_ip_dest_addr[0x80]; 5988 5989 u8 outer_ip_src_addr[0x80]; 5990 5991 u8 outer_l4_sport[0x10]; 5992 u8 outer_l4_dport[0x10]; 5993 5994 u8 reserved_at_1e0[0x20]; 5995 }; 5996 5997 struct mlx5_ifc_match_definer_format_30_bits { 5998 u8 reserved_at_0[0xa0]; 5999 6000 u8 outer_ip_dest_addr[0x80]; 6001 6002 u8 outer_ip_src_addr[0x80]; 6003 6004 u8 outer_dmac_47_16[0x20]; 6005 6006 u8 outer_smac_47_16[0x20]; 6007 6008 u8 outer_smac_15_0[0x10]; 6009 u8 outer_dmac_15_0[0x10]; 6010 }; 6011 6012 struct mlx5_ifc_match_definer_format_31_bits { 6013 u8 reserved_at_0[0xc0]; 6014 6015 u8 inner_ip_dest_addr[0x80]; 6016 6017 u8 inner_ip_src_addr[0x80]; 6018 6019 u8 inner_l4_sport[0x10]; 6020 u8 inner_l4_dport[0x10]; 6021 6022 u8 reserved_at_1e0[0x20]; 6023 }; 6024 6025 struct mlx5_ifc_match_definer_format_32_bits { 6026 u8 reserved_at_0[0xa0]; 6027 6028 u8 inner_ip_dest_addr[0x80]; 6029 6030 u8 inner_ip_src_addr[0x80]; 6031 6032 u8 inner_dmac_47_16[0x20]; 6033 6034 u8 inner_smac_47_16[0x20]; 6035 6036 u8 inner_smac_15_0[0x10]; 6037 u8 inner_dmac_15_0[0x10]; 6038 }; 6039 6040 struct mlx5_ifc_match_definer_bits { 6041 u8 modify_field_select[0x40]; 6042 6043 u8 reserved_at_40[0x40]; 6044 6045 u8 reserved_at_80[0x10]; 6046 u8 format_id[0x10]; 6047 6048 u8 reserved_at_a0[0x160]; 6049 6050 u8 match_mask[16][0x20]; 6051 }; 6052 6053 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6054 u8 opcode[0x10]; 6055 u8 uid[0x10]; 6056 6057 u8 vhca_tunnel_id[0x10]; 6058 u8 obj_type[0x10]; 6059 6060 u8 obj_id[0x20]; 6061 6062 u8 reserved_at_60[0x3]; 6063 u8 log_obj_range[0x5]; 6064 u8 reserved_at_68[0x18]; 6065 }; 6066 6067 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6068 u8 status[0x8]; 6069 u8 reserved_at_8[0x18]; 6070 6071 u8 syndrome[0x20]; 6072 6073 u8 obj_id[0x20]; 6074 6075 u8 reserved_at_60[0x20]; 6076 }; 6077 6078 struct mlx5_ifc_create_match_definer_in_bits { 6079 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6080 6081 struct mlx5_ifc_match_definer_bits obj_context; 6082 }; 6083 6084 struct mlx5_ifc_create_match_definer_out_bits { 6085 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6086 }; 6087 6088 enum { 6089 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6090 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6091 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6092 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6093 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6094 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6095 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6096 }; 6097 6098 struct mlx5_ifc_query_flow_group_out_bits { 6099 u8 status[0x8]; 6100 u8 reserved_at_8[0x18]; 6101 6102 u8 syndrome[0x20]; 6103 6104 u8 reserved_at_40[0xa0]; 6105 6106 u8 start_flow_index[0x20]; 6107 6108 u8 reserved_at_100[0x20]; 6109 6110 u8 end_flow_index[0x20]; 6111 6112 u8 reserved_at_140[0xa0]; 6113 6114 u8 reserved_at_1e0[0x18]; 6115 u8 match_criteria_enable[0x8]; 6116 6117 struct mlx5_ifc_fte_match_param_bits match_criteria; 6118 6119 u8 reserved_at_1200[0xe00]; 6120 }; 6121 6122 struct mlx5_ifc_query_flow_group_in_bits { 6123 u8 opcode[0x10]; 6124 u8 reserved_at_10[0x10]; 6125 6126 u8 reserved_at_20[0x10]; 6127 u8 op_mod[0x10]; 6128 6129 u8 reserved_at_40[0x40]; 6130 6131 u8 table_type[0x8]; 6132 u8 reserved_at_88[0x18]; 6133 6134 u8 reserved_at_a0[0x8]; 6135 u8 table_id[0x18]; 6136 6137 u8 group_id[0x20]; 6138 6139 u8 reserved_at_e0[0x120]; 6140 }; 6141 6142 struct mlx5_ifc_query_flow_counter_out_bits { 6143 u8 status[0x8]; 6144 u8 reserved_at_8[0x18]; 6145 6146 u8 syndrome[0x20]; 6147 6148 u8 reserved_at_40[0x40]; 6149 6150 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6151 }; 6152 6153 struct mlx5_ifc_query_flow_counter_in_bits { 6154 u8 opcode[0x10]; 6155 u8 reserved_at_10[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 reserved_at_40[0x80]; 6161 6162 u8 clear[0x1]; 6163 u8 reserved_at_c1[0xf]; 6164 u8 num_of_counters[0x10]; 6165 6166 u8 flow_counter_id[0x20]; 6167 }; 6168 6169 struct mlx5_ifc_query_esw_vport_context_out_bits { 6170 u8 status[0x8]; 6171 u8 reserved_at_8[0x18]; 6172 6173 u8 syndrome[0x20]; 6174 6175 u8 reserved_at_40[0x40]; 6176 6177 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6178 }; 6179 6180 struct mlx5_ifc_query_esw_vport_context_in_bits { 6181 u8 opcode[0x10]; 6182 u8 reserved_at_10[0x10]; 6183 6184 u8 reserved_at_20[0x10]; 6185 u8 op_mod[0x10]; 6186 6187 u8 other_vport[0x1]; 6188 u8 reserved_at_41[0xf]; 6189 u8 vport_number[0x10]; 6190 6191 u8 reserved_at_60[0x20]; 6192 }; 6193 6194 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x40]; 6201 }; 6202 6203 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6204 u8 reserved_at_0[0x1b]; 6205 u8 fdb_to_vport_reg_c_id[0x1]; 6206 u8 vport_cvlan_insert[0x1]; 6207 u8 vport_svlan_insert[0x1]; 6208 u8 vport_cvlan_strip[0x1]; 6209 u8 vport_svlan_strip[0x1]; 6210 }; 6211 6212 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6213 u8 opcode[0x10]; 6214 u8 reserved_at_10[0x10]; 6215 6216 u8 reserved_at_20[0x10]; 6217 u8 op_mod[0x10]; 6218 6219 u8 other_vport[0x1]; 6220 u8 reserved_at_41[0xf]; 6221 u8 vport_number[0x10]; 6222 6223 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6224 6225 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6226 }; 6227 6228 struct mlx5_ifc_query_eq_out_bits { 6229 u8 status[0x8]; 6230 u8 reserved_at_8[0x18]; 6231 6232 u8 syndrome[0x20]; 6233 6234 u8 reserved_at_40[0x40]; 6235 6236 struct mlx5_ifc_eqc_bits eq_context_entry; 6237 6238 u8 reserved_at_280[0x40]; 6239 6240 u8 event_bitmask[0x40]; 6241 6242 u8 reserved_at_300[0x580]; 6243 6244 u8 pas[][0x40]; 6245 }; 6246 6247 struct mlx5_ifc_query_eq_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x18]; 6255 u8 eq_number[0x8]; 6256 6257 u8 reserved_at_60[0x20]; 6258 }; 6259 6260 struct mlx5_ifc_packet_reformat_context_in_bits { 6261 u8 reformat_type[0x8]; 6262 u8 reserved_at_8[0x4]; 6263 u8 reformat_param_0[0x4]; 6264 u8 reserved_at_10[0x6]; 6265 u8 reformat_data_size[0xa]; 6266 6267 u8 reformat_param_1[0x8]; 6268 u8 reserved_at_28[0x8]; 6269 u8 reformat_data[2][0x8]; 6270 6271 u8 more_reformat_data[][0x8]; 6272 }; 6273 6274 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6275 u8 status[0x8]; 6276 u8 reserved_at_8[0x18]; 6277 6278 u8 syndrome[0x20]; 6279 6280 u8 reserved_at_40[0xa0]; 6281 6282 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6283 }; 6284 6285 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6286 u8 opcode[0x10]; 6287 u8 reserved_at_10[0x10]; 6288 6289 u8 reserved_at_20[0x10]; 6290 u8 op_mod[0x10]; 6291 6292 u8 packet_reformat_id[0x20]; 6293 6294 u8 reserved_at_60[0xa0]; 6295 }; 6296 6297 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_at_8[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 packet_reformat_id[0x20]; 6304 6305 u8 reserved_at_60[0x20]; 6306 }; 6307 6308 enum { 6309 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6310 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6311 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6312 }; 6313 6314 enum mlx5_reformat_ctx_type { 6315 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6316 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6317 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6318 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6319 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6320 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6321 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6322 }; 6323 6324 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6325 u8 opcode[0x10]; 6326 u8 reserved_at_10[0x10]; 6327 6328 u8 reserved_at_20[0x10]; 6329 u8 op_mod[0x10]; 6330 6331 u8 reserved_at_40[0xa0]; 6332 6333 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6334 }; 6335 6336 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6337 u8 status[0x8]; 6338 u8 reserved_at_8[0x18]; 6339 6340 u8 syndrome[0x20]; 6341 6342 u8 reserved_at_40[0x40]; 6343 }; 6344 6345 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6346 u8 opcode[0x10]; 6347 u8 reserved_at_10[0x10]; 6348 6349 u8 reserved_20[0x10]; 6350 u8 op_mod[0x10]; 6351 6352 u8 packet_reformat_id[0x20]; 6353 6354 u8 reserved_60[0x20]; 6355 }; 6356 6357 struct mlx5_ifc_set_action_in_bits { 6358 u8 action_type[0x4]; 6359 u8 field[0xc]; 6360 u8 reserved_at_10[0x3]; 6361 u8 offset[0x5]; 6362 u8 reserved_at_18[0x3]; 6363 u8 length[0x5]; 6364 6365 u8 data[0x20]; 6366 }; 6367 6368 struct mlx5_ifc_add_action_in_bits { 6369 u8 action_type[0x4]; 6370 u8 field[0xc]; 6371 u8 reserved_at_10[0x10]; 6372 6373 u8 data[0x20]; 6374 }; 6375 6376 struct mlx5_ifc_copy_action_in_bits { 6377 u8 action_type[0x4]; 6378 u8 src_field[0xc]; 6379 u8 reserved_at_10[0x3]; 6380 u8 src_offset[0x5]; 6381 u8 reserved_at_18[0x3]; 6382 u8 length[0x5]; 6383 6384 u8 reserved_at_20[0x4]; 6385 u8 dst_field[0xc]; 6386 u8 reserved_at_30[0x3]; 6387 u8 dst_offset[0x5]; 6388 u8 reserved_at_38[0x8]; 6389 }; 6390 6391 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6392 struct mlx5_ifc_set_action_in_bits set_action_in; 6393 struct mlx5_ifc_add_action_in_bits add_action_in; 6394 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6395 u8 reserved_at_0[0x40]; 6396 }; 6397 6398 enum { 6399 MLX5_ACTION_TYPE_SET = 0x1, 6400 MLX5_ACTION_TYPE_ADD = 0x2, 6401 MLX5_ACTION_TYPE_COPY = 0x3, 6402 }; 6403 6404 enum { 6405 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6406 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6407 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6408 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6409 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6410 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6411 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6412 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6413 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6414 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6415 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6416 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6417 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6418 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6419 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6420 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6421 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6422 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6423 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6424 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6425 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6426 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6427 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6428 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6429 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6430 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6431 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6432 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6433 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6434 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6435 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6436 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6437 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6438 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6439 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6440 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6441 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6442 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6443 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6444 }; 6445 6446 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6447 u8 status[0x8]; 6448 u8 reserved_at_8[0x18]; 6449 6450 u8 syndrome[0x20]; 6451 6452 u8 modify_header_id[0x20]; 6453 6454 u8 reserved_at_60[0x20]; 6455 }; 6456 6457 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6458 u8 opcode[0x10]; 6459 u8 reserved_at_10[0x10]; 6460 6461 u8 reserved_at_20[0x10]; 6462 u8 op_mod[0x10]; 6463 6464 u8 reserved_at_40[0x20]; 6465 6466 u8 table_type[0x8]; 6467 u8 reserved_at_68[0x10]; 6468 u8 num_of_actions[0x8]; 6469 6470 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6471 }; 6472 6473 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_at_8[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_at_40[0x40]; 6480 }; 6481 6482 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6483 u8 opcode[0x10]; 6484 u8 reserved_at_10[0x10]; 6485 6486 u8 reserved_at_20[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 modify_header_id[0x20]; 6490 6491 u8 reserved_at_60[0x20]; 6492 }; 6493 6494 struct mlx5_ifc_query_modify_header_context_in_bits { 6495 u8 opcode[0x10]; 6496 u8 uid[0x10]; 6497 6498 u8 reserved_at_20[0x10]; 6499 u8 op_mod[0x10]; 6500 6501 u8 modify_header_id[0x20]; 6502 6503 u8 reserved_at_60[0xa0]; 6504 }; 6505 6506 struct mlx5_ifc_query_dct_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_at_8[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_at_40[0x40]; 6513 6514 struct mlx5_ifc_dctc_bits dct_context_entry; 6515 6516 u8 reserved_at_280[0x180]; 6517 }; 6518 6519 struct mlx5_ifc_query_dct_in_bits { 6520 u8 opcode[0x10]; 6521 u8 reserved_at_10[0x10]; 6522 6523 u8 reserved_at_20[0x10]; 6524 u8 op_mod[0x10]; 6525 6526 u8 reserved_at_40[0x8]; 6527 u8 dctn[0x18]; 6528 6529 u8 reserved_at_60[0x20]; 6530 }; 6531 6532 struct mlx5_ifc_query_cq_out_bits { 6533 u8 status[0x8]; 6534 u8 reserved_at_8[0x18]; 6535 6536 u8 syndrome[0x20]; 6537 6538 u8 reserved_at_40[0x40]; 6539 6540 struct mlx5_ifc_cqc_bits cq_context; 6541 6542 u8 reserved_at_280[0x600]; 6543 6544 u8 pas[][0x40]; 6545 }; 6546 6547 struct mlx5_ifc_query_cq_in_bits { 6548 u8 opcode[0x10]; 6549 u8 reserved_at_10[0x10]; 6550 6551 u8 reserved_at_20[0x10]; 6552 u8 op_mod[0x10]; 6553 6554 u8 reserved_at_40[0x8]; 6555 u8 cqn[0x18]; 6556 6557 u8 reserved_at_60[0x20]; 6558 }; 6559 6560 struct mlx5_ifc_query_cong_status_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x20]; 6567 6568 u8 enable[0x1]; 6569 u8 tag_enable[0x1]; 6570 u8 reserved_at_62[0x1e]; 6571 }; 6572 6573 struct mlx5_ifc_query_cong_status_in_bits { 6574 u8 opcode[0x10]; 6575 u8 reserved_at_10[0x10]; 6576 6577 u8 reserved_at_20[0x10]; 6578 u8 op_mod[0x10]; 6579 6580 u8 reserved_at_40[0x18]; 6581 u8 priority[0x4]; 6582 u8 cong_protocol[0x4]; 6583 6584 u8 reserved_at_60[0x20]; 6585 }; 6586 6587 struct mlx5_ifc_query_cong_statistics_out_bits { 6588 u8 status[0x8]; 6589 u8 reserved_at_8[0x18]; 6590 6591 u8 syndrome[0x20]; 6592 6593 u8 reserved_at_40[0x40]; 6594 6595 u8 rp_cur_flows[0x20]; 6596 6597 u8 sum_flows[0x20]; 6598 6599 u8 rp_cnp_ignored_high[0x20]; 6600 6601 u8 rp_cnp_ignored_low[0x20]; 6602 6603 u8 rp_cnp_handled_high[0x20]; 6604 6605 u8 rp_cnp_handled_low[0x20]; 6606 6607 u8 reserved_at_140[0x100]; 6608 6609 u8 time_stamp_high[0x20]; 6610 6611 u8 time_stamp_low[0x20]; 6612 6613 u8 accumulators_period[0x20]; 6614 6615 u8 np_ecn_marked_roce_packets_high[0x20]; 6616 6617 u8 np_ecn_marked_roce_packets_low[0x20]; 6618 6619 u8 np_cnp_sent_high[0x20]; 6620 6621 u8 np_cnp_sent_low[0x20]; 6622 6623 u8 reserved_at_320[0x560]; 6624 }; 6625 6626 struct mlx5_ifc_query_cong_statistics_in_bits { 6627 u8 opcode[0x10]; 6628 u8 reserved_at_10[0x10]; 6629 6630 u8 reserved_at_20[0x10]; 6631 u8 op_mod[0x10]; 6632 6633 u8 clear[0x1]; 6634 u8 reserved_at_41[0x1f]; 6635 6636 u8 reserved_at_60[0x20]; 6637 }; 6638 6639 struct mlx5_ifc_query_cong_params_out_bits { 6640 u8 status[0x8]; 6641 u8 reserved_at_8[0x18]; 6642 6643 u8 syndrome[0x20]; 6644 6645 u8 reserved_at_40[0x40]; 6646 6647 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6648 }; 6649 6650 struct mlx5_ifc_query_cong_params_in_bits { 6651 u8 opcode[0x10]; 6652 u8 reserved_at_10[0x10]; 6653 6654 u8 reserved_at_20[0x10]; 6655 u8 op_mod[0x10]; 6656 6657 u8 reserved_at_40[0x1c]; 6658 u8 cong_protocol[0x4]; 6659 6660 u8 reserved_at_60[0x20]; 6661 }; 6662 6663 struct mlx5_ifc_query_adapter_out_bits { 6664 u8 status[0x8]; 6665 u8 reserved_at_8[0x18]; 6666 6667 u8 syndrome[0x20]; 6668 6669 u8 reserved_at_40[0x40]; 6670 6671 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6672 }; 6673 6674 struct mlx5_ifc_query_adapter_in_bits { 6675 u8 opcode[0x10]; 6676 u8 reserved_at_10[0x10]; 6677 6678 u8 reserved_at_20[0x10]; 6679 u8 op_mod[0x10]; 6680 6681 u8 reserved_at_40[0x40]; 6682 }; 6683 6684 struct mlx5_ifc_qp_2rst_out_bits { 6685 u8 status[0x8]; 6686 u8 reserved_at_8[0x18]; 6687 6688 u8 syndrome[0x20]; 6689 6690 u8 reserved_at_40[0x40]; 6691 }; 6692 6693 struct mlx5_ifc_qp_2rst_in_bits { 6694 u8 opcode[0x10]; 6695 u8 uid[0x10]; 6696 6697 u8 reserved_at_20[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 reserved_at_40[0x8]; 6701 u8 qpn[0x18]; 6702 6703 u8 reserved_at_60[0x20]; 6704 }; 6705 6706 struct mlx5_ifc_qp_2err_out_bits { 6707 u8 status[0x8]; 6708 u8 reserved_at_8[0x18]; 6709 6710 u8 syndrome[0x20]; 6711 6712 u8 reserved_at_40[0x40]; 6713 }; 6714 6715 struct mlx5_ifc_qp_2err_in_bits { 6716 u8 opcode[0x10]; 6717 u8 uid[0x10]; 6718 6719 u8 reserved_at_20[0x10]; 6720 u8 op_mod[0x10]; 6721 6722 u8 reserved_at_40[0x8]; 6723 u8 qpn[0x18]; 6724 6725 u8 reserved_at_60[0x20]; 6726 }; 6727 6728 struct mlx5_ifc_page_fault_resume_out_bits { 6729 u8 status[0x8]; 6730 u8 reserved_at_8[0x18]; 6731 6732 u8 syndrome[0x20]; 6733 6734 u8 reserved_at_40[0x40]; 6735 }; 6736 6737 struct mlx5_ifc_page_fault_resume_in_bits { 6738 u8 opcode[0x10]; 6739 u8 reserved_at_10[0x10]; 6740 6741 u8 reserved_at_20[0x10]; 6742 u8 op_mod[0x10]; 6743 6744 u8 error[0x1]; 6745 u8 reserved_at_41[0x4]; 6746 u8 page_fault_type[0x3]; 6747 u8 wq_number[0x18]; 6748 6749 u8 reserved_at_60[0x8]; 6750 u8 token[0x18]; 6751 }; 6752 6753 struct mlx5_ifc_nop_out_bits { 6754 u8 status[0x8]; 6755 u8 reserved_at_8[0x18]; 6756 6757 u8 syndrome[0x20]; 6758 6759 u8 reserved_at_40[0x40]; 6760 }; 6761 6762 struct mlx5_ifc_nop_in_bits { 6763 u8 opcode[0x10]; 6764 u8 reserved_at_10[0x10]; 6765 6766 u8 reserved_at_20[0x10]; 6767 u8 op_mod[0x10]; 6768 6769 u8 reserved_at_40[0x40]; 6770 }; 6771 6772 struct mlx5_ifc_modify_vport_state_out_bits { 6773 u8 status[0x8]; 6774 u8 reserved_at_8[0x18]; 6775 6776 u8 syndrome[0x20]; 6777 6778 u8 reserved_at_40[0x40]; 6779 }; 6780 6781 struct mlx5_ifc_modify_vport_state_in_bits { 6782 u8 opcode[0x10]; 6783 u8 reserved_at_10[0x10]; 6784 6785 u8 reserved_at_20[0x10]; 6786 u8 op_mod[0x10]; 6787 6788 u8 other_vport[0x1]; 6789 u8 reserved_at_41[0xf]; 6790 u8 vport_number[0x10]; 6791 6792 u8 reserved_at_60[0x18]; 6793 u8 admin_state[0x4]; 6794 u8 reserved_at_7c[0x4]; 6795 }; 6796 6797 struct mlx5_ifc_modify_tis_out_bits { 6798 u8 status[0x8]; 6799 u8 reserved_at_8[0x18]; 6800 6801 u8 syndrome[0x20]; 6802 6803 u8 reserved_at_40[0x40]; 6804 }; 6805 6806 struct mlx5_ifc_modify_tis_bitmask_bits { 6807 u8 reserved_at_0[0x20]; 6808 6809 u8 reserved_at_20[0x1d]; 6810 u8 lag_tx_port_affinity[0x1]; 6811 u8 strict_lag_tx_port_affinity[0x1]; 6812 u8 prio[0x1]; 6813 }; 6814 6815 struct mlx5_ifc_modify_tis_in_bits { 6816 u8 opcode[0x10]; 6817 u8 uid[0x10]; 6818 6819 u8 reserved_at_20[0x10]; 6820 u8 op_mod[0x10]; 6821 6822 u8 reserved_at_40[0x8]; 6823 u8 tisn[0x18]; 6824 6825 u8 reserved_at_60[0x20]; 6826 6827 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6828 6829 u8 reserved_at_c0[0x40]; 6830 6831 struct mlx5_ifc_tisc_bits ctx; 6832 }; 6833 6834 struct mlx5_ifc_modify_tir_bitmask_bits { 6835 u8 reserved_at_0[0x20]; 6836 6837 u8 reserved_at_20[0x1b]; 6838 u8 self_lb_en[0x1]; 6839 u8 reserved_at_3c[0x1]; 6840 u8 hash[0x1]; 6841 u8 reserved_at_3e[0x1]; 6842 u8 packet_merge[0x1]; 6843 }; 6844 6845 struct mlx5_ifc_modify_tir_out_bits { 6846 u8 status[0x8]; 6847 u8 reserved_at_8[0x18]; 6848 6849 u8 syndrome[0x20]; 6850 6851 u8 reserved_at_40[0x40]; 6852 }; 6853 6854 struct mlx5_ifc_modify_tir_in_bits { 6855 u8 opcode[0x10]; 6856 u8 uid[0x10]; 6857 6858 u8 reserved_at_20[0x10]; 6859 u8 op_mod[0x10]; 6860 6861 u8 reserved_at_40[0x8]; 6862 u8 tirn[0x18]; 6863 6864 u8 reserved_at_60[0x20]; 6865 6866 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6867 6868 u8 reserved_at_c0[0x40]; 6869 6870 struct mlx5_ifc_tirc_bits ctx; 6871 }; 6872 6873 struct mlx5_ifc_modify_sq_out_bits { 6874 u8 status[0x8]; 6875 u8 reserved_at_8[0x18]; 6876 6877 u8 syndrome[0x20]; 6878 6879 u8 reserved_at_40[0x40]; 6880 }; 6881 6882 struct mlx5_ifc_modify_sq_in_bits { 6883 u8 opcode[0x10]; 6884 u8 uid[0x10]; 6885 6886 u8 reserved_at_20[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 sq_state[0x4]; 6890 u8 reserved_at_44[0x4]; 6891 u8 sqn[0x18]; 6892 6893 u8 reserved_at_60[0x20]; 6894 6895 u8 modify_bitmask[0x40]; 6896 6897 u8 reserved_at_c0[0x40]; 6898 6899 struct mlx5_ifc_sqc_bits ctx; 6900 }; 6901 6902 struct mlx5_ifc_modify_scheduling_element_out_bits { 6903 u8 status[0x8]; 6904 u8 reserved_at_8[0x18]; 6905 6906 u8 syndrome[0x20]; 6907 6908 u8 reserved_at_40[0x1c0]; 6909 }; 6910 6911 enum { 6912 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6913 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6914 }; 6915 6916 struct mlx5_ifc_modify_scheduling_element_in_bits { 6917 u8 opcode[0x10]; 6918 u8 reserved_at_10[0x10]; 6919 6920 u8 reserved_at_20[0x10]; 6921 u8 op_mod[0x10]; 6922 6923 u8 scheduling_hierarchy[0x8]; 6924 u8 reserved_at_48[0x18]; 6925 6926 u8 scheduling_element_id[0x20]; 6927 6928 u8 reserved_at_80[0x20]; 6929 6930 u8 modify_bitmask[0x20]; 6931 6932 u8 reserved_at_c0[0x40]; 6933 6934 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6935 6936 u8 reserved_at_300[0x100]; 6937 }; 6938 6939 struct mlx5_ifc_modify_rqt_out_bits { 6940 u8 status[0x8]; 6941 u8 reserved_at_8[0x18]; 6942 6943 u8 syndrome[0x20]; 6944 6945 u8 reserved_at_40[0x40]; 6946 }; 6947 6948 struct mlx5_ifc_rqt_bitmask_bits { 6949 u8 reserved_at_0[0x20]; 6950 6951 u8 reserved_at_20[0x1f]; 6952 u8 rqn_list[0x1]; 6953 }; 6954 6955 struct mlx5_ifc_modify_rqt_in_bits { 6956 u8 opcode[0x10]; 6957 u8 uid[0x10]; 6958 6959 u8 reserved_at_20[0x10]; 6960 u8 op_mod[0x10]; 6961 6962 u8 reserved_at_40[0x8]; 6963 u8 rqtn[0x18]; 6964 6965 u8 reserved_at_60[0x20]; 6966 6967 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6968 6969 u8 reserved_at_c0[0x40]; 6970 6971 struct mlx5_ifc_rqtc_bits ctx; 6972 }; 6973 6974 struct mlx5_ifc_modify_rq_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x40]; 6981 }; 6982 6983 enum { 6984 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6985 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6986 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6987 }; 6988 6989 struct mlx5_ifc_modify_rq_in_bits { 6990 u8 opcode[0x10]; 6991 u8 uid[0x10]; 6992 6993 u8 reserved_at_20[0x10]; 6994 u8 op_mod[0x10]; 6995 6996 u8 rq_state[0x4]; 6997 u8 reserved_at_44[0x4]; 6998 u8 rqn[0x18]; 6999 7000 u8 reserved_at_60[0x20]; 7001 7002 u8 modify_bitmask[0x40]; 7003 7004 u8 reserved_at_c0[0x40]; 7005 7006 struct mlx5_ifc_rqc_bits ctx; 7007 }; 7008 7009 struct mlx5_ifc_modify_rmp_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 }; 7017 7018 struct mlx5_ifc_rmp_bitmask_bits { 7019 u8 reserved_at_0[0x20]; 7020 7021 u8 reserved_at_20[0x1f]; 7022 u8 lwm[0x1]; 7023 }; 7024 7025 struct mlx5_ifc_modify_rmp_in_bits { 7026 u8 opcode[0x10]; 7027 u8 uid[0x10]; 7028 7029 u8 reserved_at_20[0x10]; 7030 u8 op_mod[0x10]; 7031 7032 u8 rmp_state[0x4]; 7033 u8 reserved_at_44[0x4]; 7034 u8 rmpn[0x18]; 7035 7036 u8 reserved_at_60[0x20]; 7037 7038 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7039 7040 u8 reserved_at_c0[0x40]; 7041 7042 struct mlx5_ifc_rmpc_bits ctx; 7043 }; 7044 7045 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7046 u8 status[0x8]; 7047 u8 reserved_at_8[0x18]; 7048 7049 u8 syndrome[0x20]; 7050 7051 u8 reserved_at_40[0x40]; 7052 }; 7053 7054 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7055 u8 reserved_at_0[0x12]; 7056 u8 affiliation[0x1]; 7057 u8 reserved_at_13[0x1]; 7058 u8 disable_uc_local_lb[0x1]; 7059 u8 disable_mc_local_lb[0x1]; 7060 u8 node_guid[0x1]; 7061 u8 port_guid[0x1]; 7062 u8 min_inline[0x1]; 7063 u8 mtu[0x1]; 7064 u8 change_event[0x1]; 7065 u8 promisc[0x1]; 7066 u8 permanent_address[0x1]; 7067 u8 addresses_list[0x1]; 7068 u8 roce_en[0x1]; 7069 u8 reserved_at_1f[0x1]; 7070 }; 7071 7072 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7073 u8 opcode[0x10]; 7074 u8 reserved_at_10[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 other_vport[0x1]; 7080 u8 reserved_at_41[0xf]; 7081 u8 vport_number[0x10]; 7082 7083 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7084 7085 u8 reserved_at_80[0x780]; 7086 7087 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7088 }; 7089 7090 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7091 u8 status[0x8]; 7092 u8 reserved_at_8[0x18]; 7093 7094 u8 syndrome[0x20]; 7095 7096 u8 reserved_at_40[0x40]; 7097 }; 7098 7099 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7100 u8 opcode[0x10]; 7101 u8 reserved_at_10[0x10]; 7102 7103 u8 reserved_at_20[0x10]; 7104 u8 op_mod[0x10]; 7105 7106 u8 other_vport[0x1]; 7107 u8 reserved_at_41[0xb]; 7108 u8 port_num[0x4]; 7109 u8 vport_number[0x10]; 7110 7111 u8 reserved_at_60[0x20]; 7112 7113 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7114 }; 7115 7116 struct mlx5_ifc_modify_cq_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_at_8[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_at_40[0x40]; 7123 }; 7124 7125 enum { 7126 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7127 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7128 }; 7129 7130 struct mlx5_ifc_modify_cq_in_bits { 7131 u8 opcode[0x10]; 7132 u8 uid[0x10]; 7133 7134 u8 reserved_at_20[0x10]; 7135 u8 op_mod[0x10]; 7136 7137 u8 reserved_at_40[0x8]; 7138 u8 cqn[0x18]; 7139 7140 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7141 7142 struct mlx5_ifc_cqc_bits cq_context; 7143 7144 u8 reserved_at_280[0x60]; 7145 7146 u8 cq_umem_valid[0x1]; 7147 u8 reserved_at_2e1[0x1f]; 7148 7149 u8 reserved_at_300[0x580]; 7150 7151 u8 pas[][0x40]; 7152 }; 7153 7154 struct mlx5_ifc_modify_cong_status_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_modify_cong_status_in_bits { 7164 u8 opcode[0x10]; 7165 u8 reserved_at_10[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x18]; 7171 u8 priority[0x4]; 7172 u8 cong_protocol[0x4]; 7173 7174 u8 enable[0x1]; 7175 u8 tag_enable[0x1]; 7176 u8 reserved_at_62[0x1e]; 7177 }; 7178 7179 struct mlx5_ifc_modify_cong_params_out_bits { 7180 u8 status[0x8]; 7181 u8 reserved_at_8[0x18]; 7182 7183 u8 syndrome[0x20]; 7184 7185 u8 reserved_at_40[0x40]; 7186 }; 7187 7188 struct mlx5_ifc_modify_cong_params_in_bits { 7189 u8 opcode[0x10]; 7190 u8 reserved_at_10[0x10]; 7191 7192 u8 reserved_at_20[0x10]; 7193 u8 op_mod[0x10]; 7194 7195 u8 reserved_at_40[0x1c]; 7196 u8 cong_protocol[0x4]; 7197 7198 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7199 7200 u8 reserved_at_80[0x80]; 7201 7202 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7203 }; 7204 7205 struct mlx5_ifc_manage_pages_out_bits { 7206 u8 status[0x8]; 7207 u8 reserved_at_8[0x18]; 7208 7209 u8 syndrome[0x20]; 7210 7211 u8 output_num_entries[0x20]; 7212 7213 u8 reserved_at_60[0x20]; 7214 7215 u8 pas[][0x40]; 7216 }; 7217 7218 enum { 7219 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7220 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7221 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7222 }; 7223 7224 struct mlx5_ifc_manage_pages_in_bits { 7225 u8 opcode[0x10]; 7226 u8 reserved_at_10[0x10]; 7227 7228 u8 reserved_at_20[0x10]; 7229 u8 op_mod[0x10]; 7230 7231 u8 embedded_cpu_function[0x1]; 7232 u8 reserved_at_41[0xf]; 7233 u8 function_id[0x10]; 7234 7235 u8 input_num_entries[0x20]; 7236 7237 u8 pas[][0x40]; 7238 }; 7239 7240 struct mlx5_ifc_mad_ifc_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 7248 u8 response_mad_packet[256][0x8]; 7249 }; 7250 7251 struct mlx5_ifc_mad_ifc_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_at_10[0x10]; 7254 7255 u8 reserved_at_20[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 remote_lid[0x10]; 7259 u8 reserved_at_50[0x8]; 7260 u8 port[0x8]; 7261 7262 u8 reserved_at_60[0x20]; 7263 7264 u8 mad[256][0x8]; 7265 }; 7266 7267 struct mlx5_ifc_init_hca_out_bits { 7268 u8 status[0x8]; 7269 u8 reserved_at_8[0x18]; 7270 7271 u8 syndrome[0x20]; 7272 7273 u8 reserved_at_40[0x40]; 7274 }; 7275 7276 struct mlx5_ifc_init_hca_in_bits { 7277 u8 opcode[0x10]; 7278 u8 reserved_at_10[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_at_40[0x20]; 7284 7285 u8 reserved_at_60[0x2]; 7286 u8 sw_vhca_id[0xe]; 7287 u8 reserved_at_70[0x10]; 7288 7289 u8 sw_owner_id[4][0x20]; 7290 }; 7291 7292 struct mlx5_ifc_init2rtr_qp_out_bits { 7293 u8 status[0x8]; 7294 u8 reserved_at_8[0x18]; 7295 7296 u8 syndrome[0x20]; 7297 7298 u8 reserved_at_40[0x20]; 7299 u8 ece[0x20]; 7300 }; 7301 7302 struct mlx5_ifc_init2rtr_qp_in_bits { 7303 u8 opcode[0x10]; 7304 u8 uid[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 reserved_at_40[0x8]; 7310 u8 qpn[0x18]; 7311 7312 u8 reserved_at_60[0x20]; 7313 7314 u8 opt_param_mask[0x20]; 7315 7316 u8 ece[0x20]; 7317 7318 struct mlx5_ifc_qpc_bits qpc; 7319 7320 u8 reserved_at_800[0x80]; 7321 }; 7322 7323 struct mlx5_ifc_init2init_qp_out_bits { 7324 u8 status[0x8]; 7325 u8 reserved_at_8[0x18]; 7326 7327 u8 syndrome[0x20]; 7328 7329 u8 reserved_at_40[0x20]; 7330 u8 ece[0x20]; 7331 }; 7332 7333 struct mlx5_ifc_init2init_qp_in_bits { 7334 u8 opcode[0x10]; 7335 u8 uid[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 reserved_at_40[0x8]; 7341 u8 qpn[0x18]; 7342 7343 u8 reserved_at_60[0x20]; 7344 7345 u8 opt_param_mask[0x20]; 7346 7347 u8 ece[0x20]; 7348 7349 struct mlx5_ifc_qpc_bits qpc; 7350 7351 u8 reserved_at_800[0x80]; 7352 }; 7353 7354 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_at_8[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_at_40[0x40]; 7361 7362 u8 packet_headers_log[128][0x8]; 7363 7364 u8 packet_syndrome[64][0x8]; 7365 }; 7366 7367 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 reserved_at_40[0x40]; 7375 }; 7376 7377 struct mlx5_ifc_gen_eqe_in_bits { 7378 u8 opcode[0x10]; 7379 u8 reserved_at_10[0x10]; 7380 7381 u8 reserved_at_20[0x10]; 7382 u8 op_mod[0x10]; 7383 7384 u8 reserved_at_40[0x18]; 7385 u8 eq_number[0x8]; 7386 7387 u8 reserved_at_60[0x20]; 7388 7389 u8 eqe[64][0x8]; 7390 }; 7391 7392 struct mlx5_ifc_gen_eq_out_bits { 7393 u8 status[0x8]; 7394 u8 reserved_at_8[0x18]; 7395 7396 u8 syndrome[0x20]; 7397 7398 u8 reserved_at_40[0x40]; 7399 }; 7400 7401 struct mlx5_ifc_enable_hca_out_bits { 7402 u8 status[0x8]; 7403 u8 reserved_at_8[0x18]; 7404 7405 u8 syndrome[0x20]; 7406 7407 u8 reserved_at_40[0x20]; 7408 }; 7409 7410 struct mlx5_ifc_enable_hca_in_bits { 7411 u8 opcode[0x10]; 7412 u8 reserved_at_10[0x10]; 7413 7414 u8 reserved_at_20[0x10]; 7415 u8 op_mod[0x10]; 7416 7417 u8 embedded_cpu_function[0x1]; 7418 u8 reserved_at_41[0xf]; 7419 u8 function_id[0x10]; 7420 7421 u8 reserved_at_60[0x20]; 7422 }; 7423 7424 struct mlx5_ifc_drain_dct_out_bits { 7425 u8 status[0x8]; 7426 u8 reserved_at_8[0x18]; 7427 7428 u8 syndrome[0x20]; 7429 7430 u8 reserved_at_40[0x40]; 7431 }; 7432 7433 struct mlx5_ifc_drain_dct_in_bits { 7434 u8 opcode[0x10]; 7435 u8 uid[0x10]; 7436 7437 u8 reserved_at_20[0x10]; 7438 u8 op_mod[0x10]; 7439 7440 u8 reserved_at_40[0x8]; 7441 u8 dctn[0x18]; 7442 7443 u8 reserved_at_60[0x20]; 7444 }; 7445 7446 struct mlx5_ifc_disable_hca_out_bits { 7447 u8 status[0x8]; 7448 u8 reserved_at_8[0x18]; 7449 7450 u8 syndrome[0x20]; 7451 7452 u8 reserved_at_40[0x20]; 7453 }; 7454 7455 struct mlx5_ifc_disable_hca_in_bits { 7456 u8 opcode[0x10]; 7457 u8 reserved_at_10[0x10]; 7458 7459 u8 reserved_at_20[0x10]; 7460 u8 op_mod[0x10]; 7461 7462 u8 embedded_cpu_function[0x1]; 7463 u8 reserved_at_41[0xf]; 7464 u8 function_id[0x10]; 7465 7466 u8 reserved_at_60[0x20]; 7467 }; 7468 7469 struct mlx5_ifc_detach_from_mcg_out_bits { 7470 u8 status[0x8]; 7471 u8 reserved_at_8[0x18]; 7472 7473 u8 syndrome[0x20]; 7474 7475 u8 reserved_at_40[0x40]; 7476 }; 7477 7478 struct mlx5_ifc_detach_from_mcg_in_bits { 7479 u8 opcode[0x10]; 7480 u8 uid[0x10]; 7481 7482 u8 reserved_at_20[0x10]; 7483 u8 op_mod[0x10]; 7484 7485 u8 reserved_at_40[0x8]; 7486 u8 qpn[0x18]; 7487 7488 u8 reserved_at_60[0x20]; 7489 7490 u8 multicast_gid[16][0x8]; 7491 }; 7492 7493 struct mlx5_ifc_destroy_xrq_out_bits { 7494 u8 status[0x8]; 7495 u8 reserved_at_8[0x18]; 7496 7497 u8 syndrome[0x20]; 7498 7499 u8 reserved_at_40[0x40]; 7500 }; 7501 7502 struct mlx5_ifc_destroy_xrq_in_bits { 7503 u8 opcode[0x10]; 7504 u8 uid[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 reserved_at_40[0x8]; 7510 u8 xrqn[0x18]; 7511 7512 u8 reserved_at_60[0x20]; 7513 }; 7514 7515 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7516 u8 status[0x8]; 7517 u8 reserved_at_8[0x18]; 7518 7519 u8 syndrome[0x20]; 7520 7521 u8 reserved_at_40[0x40]; 7522 }; 7523 7524 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7525 u8 opcode[0x10]; 7526 u8 uid[0x10]; 7527 7528 u8 reserved_at_20[0x10]; 7529 u8 op_mod[0x10]; 7530 7531 u8 reserved_at_40[0x8]; 7532 u8 xrc_srqn[0x18]; 7533 7534 u8 reserved_at_60[0x20]; 7535 }; 7536 7537 struct mlx5_ifc_destroy_tis_out_bits { 7538 u8 status[0x8]; 7539 u8 reserved_at_8[0x18]; 7540 7541 u8 syndrome[0x20]; 7542 7543 u8 reserved_at_40[0x40]; 7544 }; 7545 7546 struct mlx5_ifc_destroy_tis_in_bits { 7547 u8 opcode[0x10]; 7548 u8 uid[0x10]; 7549 7550 u8 reserved_at_20[0x10]; 7551 u8 op_mod[0x10]; 7552 7553 u8 reserved_at_40[0x8]; 7554 u8 tisn[0x18]; 7555 7556 u8 reserved_at_60[0x20]; 7557 }; 7558 7559 struct mlx5_ifc_destroy_tir_out_bits { 7560 u8 status[0x8]; 7561 u8 reserved_at_8[0x18]; 7562 7563 u8 syndrome[0x20]; 7564 7565 u8 reserved_at_40[0x40]; 7566 }; 7567 7568 struct mlx5_ifc_destroy_tir_in_bits { 7569 u8 opcode[0x10]; 7570 u8 uid[0x10]; 7571 7572 u8 reserved_at_20[0x10]; 7573 u8 op_mod[0x10]; 7574 7575 u8 reserved_at_40[0x8]; 7576 u8 tirn[0x18]; 7577 7578 u8 reserved_at_60[0x20]; 7579 }; 7580 7581 struct mlx5_ifc_destroy_srq_out_bits { 7582 u8 status[0x8]; 7583 u8 reserved_at_8[0x18]; 7584 7585 u8 syndrome[0x20]; 7586 7587 u8 reserved_at_40[0x40]; 7588 }; 7589 7590 struct mlx5_ifc_destroy_srq_in_bits { 7591 u8 opcode[0x10]; 7592 u8 uid[0x10]; 7593 7594 u8 reserved_at_20[0x10]; 7595 u8 op_mod[0x10]; 7596 7597 u8 reserved_at_40[0x8]; 7598 u8 srqn[0x18]; 7599 7600 u8 reserved_at_60[0x20]; 7601 }; 7602 7603 struct mlx5_ifc_destroy_sq_out_bits { 7604 u8 status[0x8]; 7605 u8 reserved_at_8[0x18]; 7606 7607 u8 syndrome[0x20]; 7608 7609 u8 reserved_at_40[0x40]; 7610 }; 7611 7612 struct mlx5_ifc_destroy_sq_in_bits { 7613 u8 opcode[0x10]; 7614 u8 uid[0x10]; 7615 7616 u8 reserved_at_20[0x10]; 7617 u8 op_mod[0x10]; 7618 7619 u8 reserved_at_40[0x8]; 7620 u8 sqn[0x18]; 7621 7622 u8 reserved_at_60[0x20]; 7623 }; 7624 7625 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7626 u8 status[0x8]; 7627 u8 reserved_at_8[0x18]; 7628 7629 u8 syndrome[0x20]; 7630 7631 u8 reserved_at_40[0x1c0]; 7632 }; 7633 7634 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7635 u8 opcode[0x10]; 7636 u8 reserved_at_10[0x10]; 7637 7638 u8 reserved_at_20[0x10]; 7639 u8 op_mod[0x10]; 7640 7641 u8 scheduling_hierarchy[0x8]; 7642 u8 reserved_at_48[0x18]; 7643 7644 u8 scheduling_element_id[0x20]; 7645 7646 u8 reserved_at_80[0x180]; 7647 }; 7648 7649 struct mlx5_ifc_destroy_rqt_out_bits { 7650 u8 status[0x8]; 7651 u8 reserved_at_8[0x18]; 7652 7653 u8 syndrome[0x20]; 7654 7655 u8 reserved_at_40[0x40]; 7656 }; 7657 7658 struct mlx5_ifc_destroy_rqt_in_bits { 7659 u8 opcode[0x10]; 7660 u8 uid[0x10]; 7661 7662 u8 reserved_at_20[0x10]; 7663 u8 op_mod[0x10]; 7664 7665 u8 reserved_at_40[0x8]; 7666 u8 rqtn[0x18]; 7667 7668 u8 reserved_at_60[0x20]; 7669 }; 7670 7671 struct mlx5_ifc_destroy_rq_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x40]; 7678 }; 7679 7680 struct mlx5_ifc_destroy_rq_in_bits { 7681 u8 opcode[0x10]; 7682 u8 uid[0x10]; 7683 7684 u8 reserved_at_20[0x10]; 7685 u8 op_mod[0x10]; 7686 7687 u8 reserved_at_40[0x8]; 7688 u8 rqn[0x18]; 7689 7690 u8 reserved_at_60[0x20]; 7691 }; 7692 7693 struct mlx5_ifc_set_delay_drop_params_in_bits { 7694 u8 opcode[0x10]; 7695 u8 reserved_at_10[0x10]; 7696 7697 u8 reserved_at_20[0x10]; 7698 u8 op_mod[0x10]; 7699 7700 u8 reserved_at_40[0x20]; 7701 7702 u8 reserved_at_60[0x10]; 7703 u8 delay_drop_timeout[0x10]; 7704 }; 7705 7706 struct mlx5_ifc_set_delay_drop_params_out_bits { 7707 u8 status[0x8]; 7708 u8 reserved_at_8[0x18]; 7709 7710 u8 syndrome[0x20]; 7711 7712 u8 reserved_at_40[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_destroy_rmp_out_bits { 7716 u8 status[0x8]; 7717 u8 reserved_at_8[0x18]; 7718 7719 u8 syndrome[0x20]; 7720 7721 u8 reserved_at_40[0x40]; 7722 }; 7723 7724 struct mlx5_ifc_destroy_rmp_in_bits { 7725 u8 opcode[0x10]; 7726 u8 uid[0x10]; 7727 7728 u8 reserved_at_20[0x10]; 7729 u8 op_mod[0x10]; 7730 7731 u8 reserved_at_40[0x8]; 7732 u8 rmpn[0x18]; 7733 7734 u8 reserved_at_60[0x20]; 7735 }; 7736 7737 struct mlx5_ifc_destroy_qp_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_at_8[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 reserved_at_40[0x40]; 7744 }; 7745 7746 struct mlx5_ifc_destroy_qp_in_bits { 7747 u8 opcode[0x10]; 7748 u8 uid[0x10]; 7749 7750 u8 reserved_at_20[0x10]; 7751 u8 op_mod[0x10]; 7752 7753 u8 reserved_at_40[0x8]; 7754 u8 qpn[0x18]; 7755 7756 u8 reserved_at_60[0x20]; 7757 }; 7758 7759 struct mlx5_ifc_destroy_psv_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x40]; 7766 }; 7767 7768 struct mlx5_ifc_destroy_psv_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_at_10[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_at_40[0x8]; 7776 u8 psvn[0x18]; 7777 7778 u8 reserved_at_60[0x20]; 7779 }; 7780 7781 struct mlx5_ifc_destroy_mkey_out_bits { 7782 u8 status[0x8]; 7783 u8 reserved_at_8[0x18]; 7784 7785 u8 syndrome[0x20]; 7786 7787 u8 reserved_at_40[0x40]; 7788 }; 7789 7790 struct mlx5_ifc_destroy_mkey_in_bits { 7791 u8 opcode[0x10]; 7792 u8 uid[0x10]; 7793 7794 u8 reserved_at_20[0x10]; 7795 u8 op_mod[0x10]; 7796 7797 u8 reserved_at_40[0x8]; 7798 u8 mkey_index[0x18]; 7799 7800 u8 reserved_at_60[0x20]; 7801 }; 7802 7803 struct mlx5_ifc_destroy_flow_table_out_bits { 7804 u8 status[0x8]; 7805 u8 reserved_at_8[0x18]; 7806 7807 u8 syndrome[0x20]; 7808 7809 u8 reserved_at_40[0x40]; 7810 }; 7811 7812 struct mlx5_ifc_destroy_flow_table_in_bits { 7813 u8 opcode[0x10]; 7814 u8 reserved_at_10[0x10]; 7815 7816 u8 reserved_at_20[0x10]; 7817 u8 op_mod[0x10]; 7818 7819 u8 other_vport[0x1]; 7820 u8 reserved_at_41[0xf]; 7821 u8 vport_number[0x10]; 7822 7823 u8 reserved_at_60[0x20]; 7824 7825 u8 table_type[0x8]; 7826 u8 reserved_at_88[0x18]; 7827 7828 u8 reserved_at_a0[0x8]; 7829 u8 table_id[0x18]; 7830 7831 u8 reserved_at_c0[0x140]; 7832 }; 7833 7834 struct mlx5_ifc_destroy_flow_group_out_bits { 7835 u8 status[0x8]; 7836 u8 reserved_at_8[0x18]; 7837 7838 u8 syndrome[0x20]; 7839 7840 u8 reserved_at_40[0x40]; 7841 }; 7842 7843 struct mlx5_ifc_destroy_flow_group_in_bits { 7844 u8 opcode[0x10]; 7845 u8 reserved_at_10[0x10]; 7846 7847 u8 reserved_at_20[0x10]; 7848 u8 op_mod[0x10]; 7849 7850 u8 other_vport[0x1]; 7851 u8 reserved_at_41[0xf]; 7852 u8 vport_number[0x10]; 7853 7854 u8 reserved_at_60[0x20]; 7855 7856 u8 table_type[0x8]; 7857 u8 reserved_at_88[0x18]; 7858 7859 u8 reserved_at_a0[0x8]; 7860 u8 table_id[0x18]; 7861 7862 u8 group_id[0x20]; 7863 7864 u8 reserved_at_e0[0x120]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_eq_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_destroy_eq_in_bits { 7877 u8 opcode[0x10]; 7878 u8 reserved_at_10[0x10]; 7879 7880 u8 reserved_at_20[0x10]; 7881 u8 op_mod[0x10]; 7882 7883 u8 reserved_at_40[0x18]; 7884 u8 eq_number[0x8]; 7885 7886 u8 reserved_at_60[0x20]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_dct_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_at_8[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_at_40[0x40]; 7896 }; 7897 7898 struct mlx5_ifc_destroy_dct_in_bits { 7899 u8 opcode[0x10]; 7900 u8 uid[0x10]; 7901 7902 u8 reserved_at_20[0x10]; 7903 u8 op_mod[0x10]; 7904 7905 u8 reserved_at_40[0x8]; 7906 u8 dctn[0x18]; 7907 7908 u8 reserved_at_60[0x20]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_cq_out_bits { 7912 u8 status[0x8]; 7913 u8 reserved_at_8[0x18]; 7914 7915 u8 syndrome[0x20]; 7916 7917 u8 reserved_at_40[0x40]; 7918 }; 7919 7920 struct mlx5_ifc_destroy_cq_in_bits { 7921 u8 opcode[0x10]; 7922 u8 uid[0x10]; 7923 7924 u8 reserved_at_20[0x10]; 7925 u8 op_mod[0x10]; 7926 7927 u8 reserved_at_40[0x8]; 7928 u8 cqn[0x18]; 7929 7930 u8 reserved_at_60[0x20]; 7931 }; 7932 7933 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7934 u8 status[0x8]; 7935 u8 reserved_at_8[0x18]; 7936 7937 u8 syndrome[0x20]; 7938 7939 u8 reserved_at_40[0x40]; 7940 }; 7941 7942 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7943 u8 opcode[0x10]; 7944 u8 reserved_at_10[0x10]; 7945 7946 u8 reserved_at_20[0x10]; 7947 u8 op_mod[0x10]; 7948 7949 u8 reserved_at_40[0x20]; 7950 7951 u8 reserved_at_60[0x10]; 7952 u8 vxlan_udp_port[0x10]; 7953 }; 7954 7955 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 }; 7963 7964 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7965 u8 opcode[0x10]; 7966 u8 reserved_at_10[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x60]; 7972 7973 u8 reserved_at_a0[0x8]; 7974 u8 table_index[0x18]; 7975 7976 u8 reserved_at_c0[0x140]; 7977 }; 7978 7979 struct mlx5_ifc_delete_fte_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x40]; 7986 }; 7987 7988 struct mlx5_ifc_delete_fte_in_bits { 7989 u8 opcode[0x10]; 7990 u8 reserved_at_10[0x10]; 7991 7992 u8 reserved_at_20[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 other_vport[0x1]; 7996 u8 reserved_at_41[0xf]; 7997 u8 vport_number[0x10]; 7998 7999 u8 reserved_at_60[0x20]; 8000 8001 u8 table_type[0x8]; 8002 u8 reserved_at_88[0x18]; 8003 8004 u8 reserved_at_a0[0x8]; 8005 u8 table_id[0x18]; 8006 8007 u8 reserved_at_c0[0x40]; 8008 8009 u8 flow_index[0x20]; 8010 8011 u8 reserved_at_120[0xe0]; 8012 }; 8013 8014 struct mlx5_ifc_dealloc_xrcd_out_bits { 8015 u8 status[0x8]; 8016 u8 reserved_at_8[0x18]; 8017 8018 u8 syndrome[0x20]; 8019 8020 u8 reserved_at_40[0x40]; 8021 }; 8022 8023 struct mlx5_ifc_dealloc_xrcd_in_bits { 8024 u8 opcode[0x10]; 8025 u8 uid[0x10]; 8026 8027 u8 reserved_at_20[0x10]; 8028 u8 op_mod[0x10]; 8029 8030 u8 reserved_at_40[0x8]; 8031 u8 xrcd[0x18]; 8032 8033 u8 reserved_at_60[0x20]; 8034 }; 8035 8036 struct mlx5_ifc_dealloc_uar_out_bits { 8037 u8 status[0x8]; 8038 u8 reserved_at_8[0x18]; 8039 8040 u8 syndrome[0x20]; 8041 8042 u8 reserved_at_40[0x40]; 8043 }; 8044 8045 struct mlx5_ifc_dealloc_uar_in_bits { 8046 u8 opcode[0x10]; 8047 u8 uid[0x10]; 8048 8049 u8 reserved_at_20[0x10]; 8050 u8 op_mod[0x10]; 8051 8052 u8 reserved_at_40[0x8]; 8053 u8 uar[0x18]; 8054 8055 u8 reserved_at_60[0x20]; 8056 }; 8057 8058 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8068 u8 opcode[0x10]; 8069 u8 uid[0x10]; 8070 8071 u8 reserved_at_20[0x10]; 8072 u8 op_mod[0x10]; 8073 8074 u8 reserved_at_40[0x8]; 8075 u8 transport_domain[0x18]; 8076 8077 u8 reserved_at_60[0x20]; 8078 }; 8079 8080 struct mlx5_ifc_dealloc_q_counter_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_dealloc_q_counter_in_bits { 8090 u8 opcode[0x10]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x18]; 8097 u8 counter_set_id[0x8]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_dealloc_pd_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 }; 8110 8111 struct mlx5_ifc_dealloc_pd_in_bits { 8112 u8 opcode[0x10]; 8113 u8 uid[0x10]; 8114 8115 u8 reserved_at_20[0x10]; 8116 u8 op_mod[0x10]; 8117 8118 u8 reserved_at_40[0x8]; 8119 u8 pd[0x18]; 8120 8121 u8 reserved_at_60[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x40]; 8131 }; 8132 8133 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8134 u8 opcode[0x10]; 8135 u8 reserved_at_10[0x10]; 8136 8137 u8 reserved_at_20[0x10]; 8138 u8 op_mod[0x10]; 8139 8140 u8 flow_counter_id[0x20]; 8141 8142 u8 reserved_at_60[0x20]; 8143 }; 8144 8145 struct mlx5_ifc_create_xrq_out_bits { 8146 u8 status[0x8]; 8147 u8 reserved_at_8[0x18]; 8148 8149 u8 syndrome[0x20]; 8150 8151 u8 reserved_at_40[0x8]; 8152 u8 xrqn[0x18]; 8153 8154 u8 reserved_at_60[0x20]; 8155 }; 8156 8157 struct mlx5_ifc_create_xrq_in_bits { 8158 u8 opcode[0x10]; 8159 u8 uid[0x10]; 8160 8161 u8 reserved_at_20[0x10]; 8162 u8 op_mod[0x10]; 8163 8164 u8 reserved_at_40[0x40]; 8165 8166 struct mlx5_ifc_xrqc_bits xrq_context; 8167 }; 8168 8169 struct mlx5_ifc_create_xrc_srq_out_bits { 8170 u8 status[0x8]; 8171 u8 reserved_at_8[0x18]; 8172 8173 u8 syndrome[0x20]; 8174 8175 u8 reserved_at_40[0x8]; 8176 u8 xrc_srqn[0x18]; 8177 8178 u8 reserved_at_60[0x20]; 8179 }; 8180 8181 struct mlx5_ifc_create_xrc_srq_in_bits { 8182 u8 opcode[0x10]; 8183 u8 uid[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 reserved_at_40[0x40]; 8189 8190 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8191 8192 u8 reserved_at_280[0x60]; 8193 8194 u8 xrc_srq_umem_valid[0x1]; 8195 u8 reserved_at_2e1[0x1f]; 8196 8197 u8 reserved_at_300[0x580]; 8198 8199 u8 pas[][0x40]; 8200 }; 8201 8202 struct mlx5_ifc_create_tis_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x8]; 8209 u8 tisn[0x18]; 8210 8211 u8 reserved_at_60[0x20]; 8212 }; 8213 8214 struct mlx5_ifc_create_tis_in_bits { 8215 u8 opcode[0x10]; 8216 u8 uid[0x10]; 8217 8218 u8 reserved_at_20[0x10]; 8219 u8 op_mod[0x10]; 8220 8221 u8 reserved_at_40[0xc0]; 8222 8223 struct mlx5_ifc_tisc_bits ctx; 8224 }; 8225 8226 struct mlx5_ifc_create_tir_out_bits { 8227 u8 status[0x8]; 8228 u8 icm_address_63_40[0x18]; 8229 8230 u8 syndrome[0x20]; 8231 8232 u8 icm_address_39_32[0x8]; 8233 u8 tirn[0x18]; 8234 8235 u8 icm_address_31_0[0x20]; 8236 }; 8237 8238 struct mlx5_ifc_create_tir_in_bits { 8239 u8 opcode[0x10]; 8240 u8 uid[0x10]; 8241 8242 u8 reserved_at_20[0x10]; 8243 u8 op_mod[0x10]; 8244 8245 u8 reserved_at_40[0xc0]; 8246 8247 struct mlx5_ifc_tirc_bits ctx; 8248 }; 8249 8250 struct mlx5_ifc_create_srq_out_bits { 8251 u8 status[0x8]; 8252 u8 reserved_at_8[0x18]; 8253 8254 u8 syndrome[0x20]; 8255 8256 u8 reserved_at_40[0x8]; 8257 u8 srqn[0x18]; 8258 8259 u8 reserved_at_60[0x20]; 8260 }; 8261 8262 struct mlx5_ifc_create_srq_in_bits { 8263 u8 opcode[0x10]; 8264 u8 uid[0x10]; 8265 8266 u8 reserved_at_20[0x10]; 8267 u8 op_mod[0x10]; 8268 8269 u8 reserved_at_40[0x40]; 8270 8271 struct mlx5_ifc_srqc_bits srq_context_entry; 8272 8273 u8 reserved_at_280[0x600]; 8274 8275 u8 pas[][0x40]; 8276 }; 8277 8278 struct mlx5_ifc_create_sq_out_bits { 8279 u8 status[0x8]; 8280 u8 reserved_at_8[0x18]; 8281 8282 u8 syndrome[0x20]; 8283 8284 u8 reserved_at_40[0x8]; 8285 u8 sqn[0x18]; 8286 8287 u8 reserved_at_60[0x20]; 8288 }; 8289 8290 struct mlx5_ifc_create_sq_in_bits { 8291 u8 opcode[0x10]; 8292 u8 uid[0x10]; 8293 8294 u8 reserved_at_20[0x10]; 8295 u8 op_mod[0x10]; 8296 8297 u8 reserved_at_40[0xc0]; 8298 8299 struct mlx5_ifc_sqc_bits ctx; 8300 }; 8301 8302 struct mlx5_ifc_create_scheduling_element_out_bits { 8303 u8 status[0x8]; 8304 u8 reserved_at_8[0x18]; 8305 8306 u8 syndrome[0x20]; 8307 8308 u8 reserved_at_40[0x40]; 8309 8310 u8 scheduling_element_id[0x20]; 8311 8312 u8 reserved_at_a0[0x160]; 8313 }; 8314 8315 struct mlx5_ifc_create_scheduling_element_in_bits { 8316 u8 opcode[0x10]; 8317 u8 reserved_at_10[0x10]; 8318 8319 u8 reserved_at_20[0x10]; 8320 u8 op_mod[0x10]; 8321 8322 u8 scheduling_hierarchy[0x8]; 8323 u8 reserved_at_48[0x18]; 8324 8325 u8 reserved_at_60[0xa0]; 8326 8327 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8328 8329 u8 reserved_at_300[0x100]; 8330 }; 8331 8332 struct mlx5_ifc_create_rqt_out_bits { 8333 u8 status[0x8]; 8334 u8 reserved_at_8[0x18]; 8335 8336 u8 syndrome[0x20]; 8337 8338 u8 reserved_at_40[0x8]; 8339 u8 rqtn[0x18]; 8340 8341 u8 reserved_at_60[0x20]; 8342 }; 8343 8344 struct mlx5_ifc_create_rqt_in_bits { 8345 u8 opcode[0x10]; 8346 u8 uid[0x10]; 8347 8348 u8 reserved_at_20[0x10]; 8349 u8 op_mod[0x10]; 8350 8351 u8 reserved_at_40[0xc0]; 8352 8353 struct mlx5_ifc_rqtc_bits rqt_context; 8354 }; 8355 8356 struct mlx5_ifc_create_rq_out_bits { 8357 u8 status[0x8]; 8358 u8 reserved_at_8[0x18]; 8359 8360 u8 syndrome[0x20]; 8361 8362 u8 reserved_at_40[0x8]; 8363 u8 rqn[0x18]; 8364 8365 u8 reserved_at_60[0x20]; 8366 }; 8367 8368 struct mlx5_ifc_create_rq_in_bits { 8369 u8 opcode[0x10]; 8370 u8 uid[0x10]; 8371 8372 u8 reserved_at_20[0x10]; 8373 u8 op_mod[0x10]; 8374 8375 u8 reserved_at_40[0xc0]; 8376 8377 struct mlx5_ifc_rqc_bits ctx; 8378 }; 8379 8380 struct mlx5_ifc_create_rmp_out_bits { 8381 u8 status[0x8]; 8382 u8 reserved_at_8[0x18]; 8383 8384 u8 syndrome[0x20]; 8385 8386 u8 reserved_at_40[0x8]; 8387 u8 rmpn[0x18]; 8388 8389 u8 reserved_at_60[0x20]; 8390 }; 8391 8392 struct mlx5_ifc_create_rmp_in_bits { 8393 u8 opcode[0x10]; 8394 u8 uid[0x10]; 8395 8396 u8 reserved_at_20[0x10]; 8397 u8 op_mod[0x10]; 8398 8399 u8 reserved_at_40[0xc0]; 8400 8401 struct mlx5_ifc_rmpc_bits ctx; 8402 }; 8403 8404 struct mlx5_ifc_create_qp_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x8]; 8411 u8 qpn[0x18]; 8412 8413 u8 ece[0x20]; 8414 }; 8415 8416 struct mlx5_ifc_create_qp_in_bits { 8417 u8 opcode[0x10]; 8418 u8 uid[0x10]; 8419 8420 u8 reserved_at_20[0x10]; 8421 u8 op_mod[0x10]; 8422 8423 u8 reserved_at_40[0x8]; 8424 u8 input_qpn[0x18]; 8425 8426 u8 reserved_at_60[0x20]; 8427 u8 opt_param_mask[0x20]; 8428 8429 u8 ece[0x20]; 8430 8431 struct mlx5_ifc_qpc_bits qpc; 8432 8433 u8 reserved_at_800[0x60]; 8434 8435 u8 wq_umem_valid[0x1]; 8436 u8 reserved_at_861[0x1f]; 8437 8438 u8 pas[][0x40]; 8439 }; 8440 8441 struct mlx5_ifc_create_psv_out_bits { 8442 u8 status[0x8]; 8443 u8 reserved_at_8[0x18]; 8444 8445 u8 syndrome[0x20]; 8446 8447 u8 reserved_at_40[0x40]; 8448 8449 u8 reserved_at_80[0x8]; 8450 u8 psv0_index[0x18]; 8451 8452 u8 reserved_at_a0[0x8]; 8453 u8 psv1_index[0x18]; 8454 8455 u8 reserved_at_c0[0x8]; 8456 u8 psv2_index[0x18]; 8457 8458 u8 reserved_at_e0[0x8]; 8459 u8 psv3_index[0x18]; 8460 }; 8461 8462 struct mlx5_ifc_create_psv_in_bits { 8463 u8 opcode[0x10]; 8464 u8 reserved_at_10[0x10]; 8465 8466 u8 reserved_at_20[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 num_psv[0x4]; 8470 u8 reserved_at_44[0x4]; 8471 u8 pd[0x18]; 8472 8473 u8 reserved_at_60[0x20]; 8474 }; 8475 8476 struct mlx5_ifc_create_mkey_out_bits { 8477 u8 status[0x8]; 8478 u8 reserved_at_8[0x18]; 8479 8480 u8 syndrome[0x20]; 8481 8482 u8 reserved_at_40[0x8]; 8483 u8 mkey_index[0x18]; 8484 8485 u8 reserved_at_60[0x20]; 8486 }; 8487 8488 struct mlx5_ifc_create_mkey_in_bits { 8489 u8 opcode[0x10]; 8490 u8 uid[0x10]; 8491 8492 u8 reserved_at_20[0x10]; 8493 u8 op_mod[0x10]; 8494 8495 u8 reserved_at_40[0x20]; 8496 8497 u8 pg_access[0x1]; 8498 u8 mkey_umem_valid[0x1]; 8499 u8 reserved_at_62[0x1e]; 8500 8501 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8502 8503 u8 reserved_at_280[0x80]; 8504 8505 u8 translations_octword_actual_size[0x20]; 8506 8507 u8 reserved_at_320[0x560]; 8508 8509 u8 klm_pas_mtt[][0x20]; 8510 }; 8511 8512 enum { 8513 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8514 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8515 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8516 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8517 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8518 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8519 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8520 }; 8521 8522 struct mlx5_ifc_create_flow_table_out_bits { 8523 u8 status[0x8]; 8524 u8 icm_address_63_40[0x18]; 8525 8526 u8 syndrome[0x20]; 8527 8528 u8 icm_address_39_32[0x8]; 8529 u8 table_id[0x18]; 8530 8531 u8 icm_address_31_0[0x20]; 8532 }; 8533 8534 struct mlx5_ifc_create_flow_table_in_bits { 8535 u8 opcode[0x10]; 8536 u8 uid[0x10]; 8537 8538 u8 reserved_at_20[0x10]; 8539 u8 op_mod[0x10]; 8540 8541 u8 other_vport[0x1]; 8542 u8 reserved_at_41[0xf]; 8543 u8 vport_number[0x10]; 8544 8545 u8 reserved_at_60[0x20]; 8546 8547 u8 table_type[0x8]; 8548 u8 reserved_at_88[0x18]; 8549 8550 u8 reserved_at_a0[0x20]; 8551 8552 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8553 }; 8554 8555 struct mlx5_ifc_create_flow_group_out_bits { 8556 u8 status[0x8]; 8557 u8 reserved_at_8[0x18]; 8558 8559 u8 syndrome[0x20]; 8560 8561 u8 reserved_at_40[0x8]; 8562 u8 group_id[0x18]; 8563 8564 u8 reserved_at_60[0x20]; 8565 }; 8566 8567 enum { 8568 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8569 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8570 }; 8571 8572 enum { 8573 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8574 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8575 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8576 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8577 }; 8578 8579 struct mlx5_ifc_create_flow_group_in_bits { 8580 u8 opcode[0x10]; 8581 u8 reserved_at_10[0x10]; 8582 8583 u8 reserved_at_20[0x10]; 8584 u8 op_mod[0x10]; 8585 8586 u8 other_vport[0x1]; 8587 u8 reserved_at_41[0xf]; 8588 u8 vport_number[0x10]; 8589 8590 u8 reserved_at_60[0x20]; 8591 8592 u8 table_type[0x8]; 8593 u8 reserved_at_88[0x4]; 8594 u8 group_type[0x4]; 8595 u8 reserved_at_90[0x10]; 8596 8597 u8 reserved_at_a0[0x8]; 8598 u8 table_id[0x18]; 8599 8600 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8601 8602 u8 reserved_at_c1[0x1f]; 8603 8604 u8 start_flow_index[0x20]; 8605 8606 u8 reserved_at_100[0x20]; 8607 8608 u8 end_flow_index[0x20]; 8609 8610 u8 reserved_at_140[0x10]; 8611 u8 match_definer_id[0x10]; 8612 8613 u8 reserved_at_160[0x80]; 8614 8615 u8 reserved_at_1e0[0x18]; 8616 u8 match_criteria_enable[0x8]; 8617 8618 struct mlx5_ifc_fte_match_param_bits match_criteria; 8619 8620 u8 reserved_at_1200[0xe00]; 8621 }; 8622 8623 struct mlx5_ifc_create_eq_out_bits { 8624 u8 status[0x8]; 8625 u8 reserved_at_8[0x18]; 8626 8627 u8 syndrome[0x20]; 8628 8629 u8 reserved_at_40[0x18]; 8630 u8 eq_number[0x8]; 8631 8632 u8 reserved_at_60[0x20]; 8633 }; 8634 8635 struct mlx5_ifc_create_eq_in_bits { 8636 u8 opcode[0x10]; 8637 u8 uid[0x10]; 8638 8639 u8 reserved_at_20[0x10]; 8640 u8 op_mod[0x10]; 8641 8642 u8 reserved_at_40[0x40]; 8643 8644 struct mlx5_ifc_eqc_bits eq_context_entry; 8645 8646 u8 reserved_at_280[0x40]; 8647 8648 u8 event_bitmask[4][0x40]; 8649 8650 u8 reserved_at_3c0[0x4c0]; 8651 8652 u8 pas[][0x40]; 8653 }; 8654 8655 struct mlx5_ifc_create_dct_out_bits { 8656 u8 status[0x8]; 8657 u8 reserved_at_8[0x18]; 8658 8659 u8 syndrome[0x20]; 8660 8661 u8 reserved_at_40[0x8]; 8662 u8 dctn[0x18]; 8663 8664 u8 ece[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_create_dct_in_bits { 8668 u8 opcode[0x10]; 8669 u8 uid[0x10]; 8670 8671 u8 reserved_at_20[0x10]; 8672 u8 op_mod[0x10]; 8673 8674 u8 reserved_at_40[0x40]; 8675 8676 struct mlx5_ifc_dctc_bits dct_context_entry; 8677 8678 u8 reserved_at_280[0x180]; 8679 }; 8680 8681 struct mlx5_ifc_create_cq_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x8]; 8688 u8 cqn[0x18]; 8689 8690 u8 reserved_at_60[0x20]; 8691 }; 8692 8693 struct mlx5_ifc_create_cq_in_bits { 8694 u8 opcode[0x10]; 8695 u8 uid[0x10]; 8696 8697 u8 reserved_at_20[0x10]; 8698 u8 op_mod[0x10]; 8699 8700 u8 reserved_at_40[0x40]; 8701 8702 struct mlx5_ifc_cqc_bits cq_context; 8703 8704 u8 reserved_at_280[0x60]; 8705 8706 u8 cq_umem_valid[0x1]; 8707 u8 reserved_at_2e1[0x59f]; 8708 8709 u8 pas[][0x40]; 8710 }; 8711 8712 struct mlx5_ifc_config_int_moderation_out_bits { 8713 u8 status[0x8]; 8714 u8 reserved_at_8[0x18]; 8715 8716 u8 syndrome[0x20]; 8717 8718 u8 reserved_at_40[0x4]; 8719 u8 min_delay[0xc]; 8720 u8 int_vector[0x10]; 8721 8722 u8 reserved_at_60[0x20]; 8723 }; 8724 8725 enum { 8726 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8727 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8728 }; 8729 8730 struct mlx5_ifc_config_int_moderation_in_bits { 8731 u8 opcode[0x10]; 8732 u8 reserved_at_10[0x10]; 8733 8734 u8 reserved_at_20[0x10]; 8735 u8 op_mod[0x10]; 8736 8737 u8 reserved_at_40[0x4]; 8738 u8 min_delay[0xc]; 8739 u8 int_vector[0x10]; 8740 8741 u8 reserved_at_60[0x20]; 8742 }; 8743 8744 struct mlx5_ifc_attach_to_mcg_out_bits { 8745 u8 status[0x8]; 8746 u8 reserved_at_8[0x18]; 8747 8748 u8 syndrome[0x20]; 8749 8750 u8 reserved_at_40[0x40]; 8751 }; 8752 8753 struct mlx5_ifc_attach_to_mcg_in_bits { 8754 u8 opcode[0x10]; 8755 u8 uid[0x10]; 8756 8757 u8 reserved_at_20[0x10]; 8758 u8 op_mod[0x10]; 8759 8760 u8 reserved_at_40[0x8]; 8761 u8 qpn[0x18]; 8762 8763 u8 reserved_at_60[0x20]; 8764 8765 u8 multicast_gid[16][0x8]; 8766 }; 8767 8768 struct mlx5_ifc_arm_xrq_out_bits { 8769 u8 status[0x8]; 8770 u8 reserved_at_8[0x18]; 8771 8772 u8 syndrome[0x20]; 8773 8774 u8 reserved_at_40[0x40]; 8775 }; 8776 8777 struct mlx5_ifc_arm_xrq_in_bits { 8778 u8 opcode[0x10]; 8779 u8 reserved_at_10[0x10]; 8780 8781 u8 reserved_at_20[0x10]; 8782 u8 op_mod[0x10]; 8783 8784 u8 reserved_at_40[0x8]; 8785 u8 xrqn[0x18]; 8786 8787 u8 reserved_at_60[0x10]; 8788 u8 lwm[0x10]; 8789 }; 8790 8791 struct mlx5_ifc_arm_xrc_srq_out_bits { 8792 u8 status[0x8]; 8793 u8 reserved_at_8[0x18]; 8794 8795 u8 syndrome[0x20]; 8796 8797 u8 reserved_at_40[0x40]; 8798 }; 8799 8800 enum { 8801 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8802 }; 8803 8804 struct mlx5_ifc_arm_xrc_srq_in_bits { 8805 u8 opcode[0x10]; 8806 u8 uid[0x10]; 8807 8808 u8 reserved_at_20[0x10]; 8809 u8 op_mod[0x10]; 8810 8811 u8 reserved_at_40[0x8]; 8812 u8 xrc_srqn[0x18]; 8813 8814 u8 reserved_at_60[0x10]; 8815 u8 lwm[0x10]; 8816 }; 8817 8818 struct mlx5_ifc_arm_rq_out_bits { 8819 u8 status[0x8]; 8820 u8 reserved_at_8[0x18]; 8821 8822 u8 syndrome[0x20]; 8823 8824 u8 reserved_at_40[0x40]; 8825 }; 8826 8827 enum { 8828 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8829 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8830 }; 8831 8832 struct mlx5_ifc_arm_rq_in_bits { 8833 u8 opcode[0x10]; 8834 u8 uid[0x10]; 8835 8836 u8 reserved_at_20[0x10]; 8837 u8 op_mod[0x10]; 8838 8839 u8 reserved_at_40[0x8]; 8840 u8 srq_number[0x18]; 8841 8842 u8 reserved_at_60[0x10]; 8843 u8 lwm[0x10]; 8844 }; 8845 8846 struct mlx5_ifc_arm_dct_out_bits { 8847 u8 status[0x8]; 8848 u8 reserved_at_8[0x18]; 8849 8850 u8 syndrome[0x20]; 8851 8852 u8 reserved_at_40[0x40]; 8853 }; 8854 8855 struct mlx5_ifc_arm_dct_in_bits { 8856 u8 opcode[0x10]; 8857 u8 reserved_at_10[0x10]; 8858 8859 u8 reserved_at_20[0x10]; 8860 u8 op_mod[0x10]; 8861 8862 u8 reserved_at_40[0x8]; 8863 u8 dct_number[0x18]; 8864 8865 u8 reserved_at_60[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_alloc_xrcd_out_bits { 8869 u8 status[0x8]; 8870 u8 reserved_at_8[0x18]; 8871 8872 u8 syndrome[0x20]; 8873 8874 u8 reserved_at_40[0x8]; 8875 u8 xrcd[0x18]; 8876 8877 u8 reserved_at_60[0x20]; 8878 }; 8879 8880 struct mlx5_ifc_alloc_xrcd_in_bits { 8881 u8 opcode[0x10]; 8882 u8 uid[0x10]; 8883 8884 u8 reserved_at_20[0x10]; 8885 u8 op_mod[0x10]; 8886 8887 u8 reserved_at_40[0x40]; 8888 }; 8889 8890 struct mlx5_ifc_alloc_uar_out_bits { 8891 u8 status[0x8]; 8892 u8 reserved_at_8[0x18]; 8893 8894 u8 syndrome[0x20]; 8895 8896 u8 reserved_at_40[0x8]; 8897 u8 uar[0x18]; 8898 8899 u8 reserved_at_60[0x20]; 8900 }; 8901 8902 struct mlx5_ifc_alloc_uar_in_bits { 8903 u8 opcode[0x10]; 8904 u8 uid[0x10]; 8905 8906 u8 reserved_at_20[0x10]; 8907 u8 op_mod[0x10]; 8908 8909 u8 reserved_at_40[0x40]; 8910 }; 8911 8912 struct mlx5_ifc_alloc_transport_domain_out_bits { 8913 u8 status[0x8]; 8914 u8 reserved_at_8[0x18]; 8915 8916 u8 syndrome[0x20]; 8917 8918 u8 reserved_at_40[0x8]; 8919 u8 transport_domain[0x18]; 8920 8921 u8 reserved_at_60[0x20]; 8922 }; 8923 8924 struct mlx5_ifc_alloc_transport_domain_in_bits { 8925 u8 opcode[0x10]; 8926 u8 uid[0x10]; 8927 8928 u8 reserved_at_20[0x10]; 8929 u8 op_mod[0x10]; 8930 8931 u8 reserved_at_40[0x40]; 8932 }; 8933 8934 struct mlx5_ifc_alloc_q_counter_out_bits { 8935 u8 status[0x8]; 8936 u8 reserved_at_8[0x18]; 8937 8938 u8 syndrome[0x20]; 8939 8940 u8 reserved_at_40[0x18]; 8941 u8 counter_set_id[0x8]; 8942 8943 u8 reserved_at_60[0x20]; 8944 }; 8945 8946 struct mlx5_ifc_alloc_q_counter_in_bits { 8947 u8 opcode[0x10]; 8948 u8 uid[0x10]; 8949 8950 u8 reserved_at_20[0x10]; 8951 u8 op_mod[0x10]; 8952 8953 u8 reserved_at_40[0x40]; 8954 }; 8955 8956 struct mlx5_ifc_alloc_pd_out_bits { 8957 u8 status[0x8]; 8958 u8 reserved_at_8[0x18]; 8959 8960 u8 syndrome[0x20]; 8961 8962 u8 reserved_at_40[0x8]; 8963 u8 pd[0x18]; 8964 8965 u8 reserved_at_60[0x20]; 8966 }; 8967 8968 struct mlx5_ifc_alloc_pd_in_bits { 8969 u8 opcode[0x10]; 8970 u8 uid[0x10]; 8971 8972 u8 reserved_at_20[0x10]; 8973 u8 op_mod[0x10]; 8974 8975 u8 reserved_at_40[0x40]; 8976 }; 8977 8978 struct mlx5_ifc_alloc_flow_counter_out_bits { 8979 u8 status[0x8]; 8980 u8 reserved_at_8[0x18]; 8981 8982 u8 syndrome[0x20]; 8983 8984 u8 flow_counter_id[0x20]; 8985 8986 u8 reserved_at_60[0x20]; 8987 }; 8988 8989 struct mlx5_ifc_alloc_flow_counter_in_bits { 8990 u8 opcode[0x10]; 8991 u8 reserved_at_10[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 reserved_at_40[0x38]; 8997 u8 flow_counter_bulk[0x8]; 8998 }; 8999 9000 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9001 u8 status[0x8]; 9002 u8 reserved_at_8[0x18]; 9003 9004 u8 syndrome[0x20]; 9005 9006 u8 reserved_at_40[0x40]; 9007 }; 9008 9009 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9010 u8 opcode[0x10]; 9011 u8 reserved_at_10[0x10]; 9012 9013 u8 reserved_at_20[0x10]; 9014 u8 op_mod[0x10]; 9015 9016 u8 reserved_at_40[0x20]; 9017 9018 u8 reserved_at_60[0x10]; 9019 u8 vxlan_udp_port[0x10]; 9020 }; 9021 9022 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9023 u8 status[0x8]; 9024 u8 reserved_at_8[0x18]; 9025 9026 u8 syndrome[0x20]; 9027 9028 u8 reserved_at_40[0x40]; 9029 }; 9030 9031 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9032 u8 rate_limit[0x20]; 9033 9034 u8 burst_upper_bound[0x20]; 9035 9036 u8 reserved_at_40[0x10]; 9037 u8 typical_packet_size[0x10]; 9038 9039 u8 reserved_at_60[0x120]; 9040 }; 9041 9042 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9043 u8 opcode[0x10]; 9044 u8 uid[0x10]; 9045 9046 u8 reserved_at_20[0x10]; 9047 u8 op_mod[0x10]; 9048 9049 u8 reserved_at_40[0x10]; 9050 u8 rate_limit_index[0x10]; 9051 9052 u8 reserved_at_60[0x20]; 9053 9054 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9055 }; 9056 9057 struct mlx5_ifc_access_register_out_bits { 9058 u8 status[0x8]; 9059 u8 reserved_at_8[0x18]; 9060 9061 u8 syndrome[0x20]; 9062 9063 u8 reserved_at_40[0x40]; 9064 9065 u8 register_data[][0x20]; 9066 }; 9067 9068 enum { 9069 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9070 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9071 }; 9072 9073 struct mlx5_ifc_access_register_in_bits { 9074 u8 opcode[0x10]; 9075 u8 reserved_at_10[0x10]; 9076 9077 u8 reserved_at_20[0x10]; 9078 u8 op_mod[0x10]; 9079 9080 u8 reserved_at_40[0x10]; 9081 u8 register_id[0x10]; 9082 9083 u8 argument[0x20]; 9084 9085 u8 register_data[][0x20]; 9086 }; 9087 9088 struct mlx5_ifc_sltp_reg_bits { 9089 u8 status[0x4]; 9090 u8 version[0x4]; 9091 u8 local_port[0x8]; 9092 u8 pnat[0x2]; 9093 u8 reserved_at_12[0x2]; 9094 u8 lane[0x4]; 9095 u8 reserved_at_18[0x8]; 9096 9097 u8 reserved_at_20[0x20]; 9098 9099 u8 reserved_at_40[0x7]; 9100 u8 polarity[0x1]; 9101 u8 ob_tap0[0x8]; 9102 u8 ob_tap1[0x8]; 9103 u8 ob_tap2[0x8]; 9104 9105 u8 reserved_at_60[0xc]; 9106 u8 ob_preemp_mode[0x4]; 9107 u8 ob_reg[0x8]; 9108 u8 ob_bias[0x8]; 9109 9110 u8 reserved_at_80[0x20]; 9111 }; 9112 9113 struct mlx5_ifc_slrg_reg_bits { 9114 u8 status[0x4]; 9115 u8 version[0x4]; 9116 u8 local_port[0x8]; 9117 u8 pnat[0x2]; 9118 u8 reserved_at_12[0x2]; 9119 u8 lane[0x4]; 9120 u8 reserved_at_18[0x8]; 9121 9122 u8 time_to_link_up[0x10]; 9123 u8 reserved_at_30[0xc]; 9124 u8 grade_lane_speed[0x4]; 9125 9126 u8 grade_version[0x8]; 9127 u8 grade[0x18]; 9128 9129 u8 reserved_at_60[0x4]; 9130 u8 height_grade_type[0x4]; 9131 u8 height_grade[0x18]; 9132 9133 u8 height_dz[0x10]; 9134 u8 height_dv[0x10]; 9135 9136 u8 reserved_at_a0[0x10]; 9137 u8 height_sigma[0x10]; 9138 9139 u8 reserved_at_c0[0x20]; 9140 9141 u8 reserved_at_e0[0x4]; 9142 u8 phase_grade_type[0x4]; 9143 u8 phase_grade[0x18]; 9144 9145 u8 reserved_at_100[0x8]; 9146 u8 phase_eo_pos[0x8]; 9147 u8 reserved_at_110[0x8]; 9148 u8 phase_eo_neg[0x8]; 9149 9150 u8 ffe_set_tested[0x10]; 9151 u8 test_errors_per_lane[0x10]; 9152 }; 9153 9154 struct mlx5_ifc_pvlc_reg_bits { 9155 u8 reserved_at_0[0x8]; 9156 u8 local_port[0x8]; 9157 u8 reserved_at_10[0x10]; 9158 9159 u8 reserved_at_20[0x1c]; 9160 u8 vl_hw_cap[0x4]; 9161 9162 u8 reserved_at_40[0x1c]; 9163 u8 vl_admin[0x4]; 9164 9165 u8 reserved_at_60[0x1c]; 9166 u8 vl_operational[0x4]; 9167 }; 9168 9169 struct mlx5_ifc_pude_reg_bits { 9170 u8 swid[0x8]; 9171 u8 local_port[0x8]; 9172 u8 reserved_at_10[0x4]; 9173 u8 admin_status[0x4]; 9174 u8 reserved_at_18[0x4]; 9175 u8 oper_status[0x4]; 9176 9177 u8 reserved_at_20[0x60]; 9178 }; 9179 9180 struct mlx5_ifc_ptys_reg_bits { 9181 u8 reserved_at_0[0x1]; 9182 u8 an_disable_admin[0x1]; 9183 u8 an_disable_cap[0x1]; 9184 u8 reserved_at_3[0x5]; 9185 u8 local_port[0x8]; 9186 u8 reserved_at_10[0xd]; 9187 u8 proto_mask[0x3]; 9188 9189 u8 an_status[0x4]; 9190 u8 reserved_at_24[0xc]; 9191 u8 data_rate_oper[0x10]; 9192 9193 u8 ext_eth_proto_capability[0x20]; 9194 9195 u8 eth_proto_capability[0x20]; 9196 9197 u8 ib_link_width_capability[0x10]; 9198 u8 ib_proto_capability[0x10]; 9199 9200 u8 ext_eth_proto_admin[0x20]; 9201 9202 u8 eth_proto_admin[0x20]; 9203 9204 u8 ib_link_width_admin[0x10]; 9205 u8 ib_proto_admin[0x10]; 9206 9207 u8 ext_eth_proto_oper[0x20]; 9208 9209 u8 eth_proto_oper[0x20]; 9210 9211 u8 ib_link_width_oper[0x10]; 9212 u8 ib_proto_oper[0x10]; 9213 9214 u8 reserved_at_160[0x1c]; 9215 u8 connector_type[0x4]; 9216 9217 u8 eth_proto_lp_advertise[0x20]; 9218 9219 u8 reserved_at_1a0[0x60]; 9220 }; 9221 9222 struct mlx5_ifc_mlcr_reg_bits { 9223 u8 reserved_at_0[0x8]; 9224 u8 local_port[0x8]; 9225 u8 reserved_at_10[0x20]; 9226 9227 u8 beacon_duration[0x10]; 9228 u8 reserved_at_40[0x10]; 9229 9230 u8 beacon_remain[0x10]; 9231 }; 9232 9233 struct mlx5_ifc_ptas_reg_bits { 9234 u8 reserved_at_0[0x20]; 9235 9236 u8 algorithm_options[0x10]; 9237 u8 reserved_at_30[0x4]; 9238 u8 repetitions_mode[0x4]; 9239 u8 num_of_repetitions[0x8]; 9240 9241 u8 grade_version[0x8]; 9242 u8 height_grade_type[0x4]; 9243 u8 phase_grade_type[0x4]; 9244 u8 height_grade_weight[0x8]; 9245 u8 phase_grade_weight[0x8]; 9246 9247 u8 gisim_measure_bits[0x10]; 9248 u8 adaptive_tap_measure_bits[0x10]; 9249 9250 u8 ber_bath_high_error_threshold[0x10]; 9251 u8 ber_bath_mid_error_threshold[0x10]; 9252 9253 u8 ber_bath_low_error_threshold[0x10]; 9254 u8 one_ratio_high_threshold[0x10]; 9255 9256 u8 one_ratio_high_mid_threshold[0x10]; 9257 u8 one_ratio_low_mid_threshold[0x10]; 9258 9259 u8 one_ratio_low_threshold[0x10]; 9260 u8 ndeo_error_threshold[0x10]; 9261 9262 u8 mixer_offset_step_size[0x10]; 9263 u8 reserved_at_110[0x8]; 9264 u8 mix90_phase_for_voltage_bath[0x8]; 9265 9266 u8 mixer_offset_start[0x10]; 9267 u8 mixer_offset_end[0x10]; 9268 9269 u8 reserved_at_140[0x15]; 9270 u8 ber_test_time[0xb]; 9271 }; 9272 9273 struct mlx5_ifc_pspa_reg_bits { 9274 u8 swid[0x8]; 9275 u8 local_port[0x8]; 9276 u8 sub_port[0x8]; 9277 u8 reserved_at_18[0x8]; 9278 9279 u8 reserved_at_20[0x20]; 9280 }; 9281 9282 struct mlx5_ifc_pqdr_reg_bits { 9283 u8 reserved_at_0[0x8]; 9284 u8 local_port[0x8]; 9285 u8 reserved_at_10[0x5]; 9286 u8 prio[0x3]; 9287 u8 reserved_at_18[0x6]; 9288 u8 mode[0x2]; 9289 9290 u8 reserved_at_20[0x20]; 9291 9292 u8 reserved_at_40[0x10]; 9293 u8 min_threshold[0x10]; 9294 9295 u8 reserved_at_60[0x10]; 9296 u8 max_threshold[0x10]; 9297 9298 u8 reserved_at_80[0x10]; 9299 u8 mark_probability_denominator[0x10]; 9300 9301 u8 reserved_at_a0[0x60]; 9302 }; 9303 9304 struct mlx5_ifc_ppsc_reg_bits { 9305 u8 reserved_at_0[0x8]; 9306 u8 local_port[0x8]; 9307 u8 reserved_at_10[0x10]; 9308 9309 u8 reserved_at_20[0x60]; 9310 9311 u8 reserved_at_80[0x1c]; 9312 u8 wrps_admin[0x4]; 9313 9314 u8 reserved_at_a0[0x1c]; 9315 u8 wrps_status[0x4]; 9316 9317 u8 reserved_at_c0[0x8]; 9318 u8 up_threshold[0x8]; 9319 u8 reserved_at_d0[0x8]; 9320 u8 down_threshold[0x8]; 9321 9322 u8 reserved_at_e0[0x20]; 9323 9324 u8 reserved_at_100[0x1c]; 9325 u8 srps_admin[0x4]; 9326 9327 u8 reserved_at_120[0x1c]; 9328 u8 srps_status[0x4]; 9329 9330 u8 reserved_at_140[0x40]; 9331 }; 9332 9333 struct mlx5_ifc_pplr_reg_bits { 9334 u8 reserved_at_0[0x8]; 9335 u8 local_port[0x8]; 9336 u8 reserved_at_10[0x10]; 9337 9338 u8 reserved_at_20[0x8]; 9339 u8 lb_cap[0x8]; 9340 u8 reserved_at_30[0x8]; 9341 u8 lb_en[0x8]; 9342 }; 9343 9344 struct mlx5_ifc_pplm_reg_bits { 9345 u8 reserved_at_0[0x8]; 9346 u8 local_port[0x8]; 9347 u8 reserved_at_10[0x10]; 9348 9349 u8 reserved_at_20[0x20]; 9350 9351 u8 port_profile_mode[0x8]; 9352 u8 static_port_profile[0x8]; 9353 u8 active_port_profile[0x8]; 9354 u8 reserved_at_58[0x8]; 9355 9356 u8 retransmission_active[0x8]; 9357 u8 fec_mode_active[0x18]; 9358 9359 u8 rs_fec_correction_bypass_cap[0x4]; 9360 u8 reserved_at_84[0x8]; 9361 u8 fec_override_cap_56g[0x4]; 9362 u8 fec_override_cap_100g[0x4]; 9363 u8 fec_override_cap_50g[0x4]; 9364 u8 fec_override_cap_25g[0x4]; 9365 u8 fec_override_cap_10g_40g[0x4]; 9366 9367 u8 rs_fec_correction_bypass_admin[0x4]; 9368 u8 reserved_at_a4[0x8]; 9369 u8 fec_override_admin_56g[0x4]; 9370 u8 fec_override_admin_100g[0x4]; 9371 u8 fec_override_admin_50g[0x4]; 9372 u8 fec_override_admin_25g[0x4]; 9373 u8 fec_override_admin_10g_40g[0x4]; 9374 9375 u8 fec_override_cap_400g_8x[0x10]; 9376 u8 fec_override_cap_200g_4x[0x10]; 9377 9378 u8 fec_override_cap_100g_2x[0x10]; 9379 u8 fec_override_cap_50g_1x[0x10]; 9380 9381 u8 fec_override_admin_400g_8x[0x10]; 9382 u8 fec_override_admin_200g_4x[0x10]; 9383 9384 u8 fec_override_admin_100g_2x[0x10]; 9385 u8 fec_override_admin_50g_1x[0x10]; 9386 9387 u8 reserved_at_140[0x140]; 9388 }; 9389 9390 struct mlx5_ifc_ppcnt_reg_bits { 9391 u8 swid[0x8]; 9392 u8 local_port[0x8]; 9393 u8 pnat[0x2]; 9394 u8 reserved_at_12[0x8]; 9395 u8 grp[0x6]; 9396 9397 u8 clr[0x1]; 9398 u8 reserved_at_21[0x1c]; 9399 u8 prio_tc[0x3]; 9400 9401 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9402 }; 9403 9404 struct mlx5_ifc_mpein_reg_bits { 9405 u8 reserved_at_0[0x2]; 9406 u8 depth[0x6]; 9407 u8 pcie_index[0x8]; 9408 u8 node[0x8]; 9409 u8 reserved_at_18[0x8]; 9410 9411 u8 capability_mask[0x20]; 9412 9413 u8 reserved_at_40[0x8]; 9414 u8 link_width_enabled[0x8]; 9415 u8 link_speed_enabled[0x10]; 9416 9417 u8 lane0_physical_position[0x8]; 9418 u8 link_width_active[0x8]; 9419 u8 link_speed_active[0x10]; 9420 9421 u8 num_of_pfs[0x10]; 9422 u8 num_of_vfs[0x10]; 9423 9424 u8 bdf0[0x10]; 9425 u8 reserved_at_b0[0x10]; 9426 9427 u8 max_read_request_size[0x4]; 9428 u8 max_payload_size[0x4]; 9429 u8 reserved_at_c8[0x5]; 9430 u8 pwr_status[0x3]; 9431 u8 port_type[0x4]; 9432 u8 reserved_at_d4[0xb]; 9433 u8 lane_reversal[0x1]; 9434 9435 u8 reserved_at_e0[0x14]; 9436 u8 pci_power[0xc]; 9437 9438 u8 reserved_at_100[0x20]; 9439 9440 u8 device_status[0x10]; 9441 u8 port_state[0x8]; 9442 u8 reserved_at_138[0x8]; 9443 9444 u8 reserved_at_140[0x10]; 9445 u8 receiver_detect_result[0x10]; 9446 9447 u8 reserved_at_160[0x20]; 9448 }; 9449 9450 struct mlx5_ifc_mpcnt_reg_bits { 9451 u8 reserved_at_0[0x8]; 9452 u8 pcie_index[0x8]; 9453 u8 reserved_at_10[0xa]; 9454 u8 grp[0x6]; 9455 9456 u8 clr[0x1]; 9457 u8 reserved_at_21[0x1f]; 9458 9459 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9460 }; 9461 9462 struct mlx5_ifc_ppad_reg_bits { 9463 u8 reserved_at_0[0x3]; 9464 u8 single_mac[0x1]; 9465 u8 reserved_at_4[0x4]; 9466 u8 local_port[0x8]; 9467 u8 mac_47_32[0x10]; 9468 9469 u8 mac_31_0[0x20]; 9470 9471 u8 reserved_at_40[0x40]; 9472 }; 9473 9474 struct mlx5_ifc_pmtu_reg_bits { 9475 u8 reserved_at_0[0x8]; 9476 u8 local_port[0x8]; 9477 u8 reserved_at_10[0x10]; 9478 9479 u8 max_mtu[0x10]; 9480 u8 reserved_at_30[0x10]; 9481 9482 u8 admin_mtu[0x10]; 9483 u8 reserved_at_50[0x10]; 9484 9485 u8 oper_mtu[0x10]; 9486 u8 reserved_at_70[0x10]; 9487 }; 9488 9489 struct mlx5_ifc_pmpr_reg_bits { 9490 u8 reserved_at_0[0x8]; 9491 u8 module[0x8]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x18]; 9495 u8 attenuation_5g[0x8]; 9496 9497 u8 reserved_at_40[0x18]; 9498 u8 attenuation_7g[0x8]; 9499 9500 u8 reserved_at_60[0x18]; 9501 u8 attenuation_12g[0x8]; 9502 }; 9503 9504 struct mlx5_ifc_pmpe_reg_bits { 9505 u8 reserved_at_0[0x8]; 9506 u8 module[0x8]; 9507 u8 reserved_at_10[0xc]; 9508 u8 module_status[0x4]; 9509 9510 u8 reserved_at_20[0x60]; 9511 }; 9512 9513 struct mlx5_ifc_pmpc_reg_bits { 9514 u8 module_state_updated[32][0x8]; 9515 }; 9516 9517 struct mlx5_ifc_pmlpn_reg_bits { 9518 u8 reserved_at_0[0x4]; 9519 u8 mlpn_status[0x4]; 9520 u8 local_port[0x8]; 9521 u8 reserved_at_10[0x10]; 9522 9523 u8 e[0x1]; 9524 u8 reserved_at_21[0x1f]; 9525 }; 9526 9527 struct mlx5_ifc_pmlp_reg_bits { 9528 u8 rxtx[0x1]; 9529 u8 reserved_at_1[0x7]; 9530 u8 local_port[0x8]; 9531 u8 reserved_at_10[0x8]; 9532 u8 width[0x8]; 9533 9534 u8 lane0_module_mapping[0x20]; 9535 9536 u8 lane1_module_mapping[0x20]; 9537 9538 u8 lane2_module_mapping[0x20]; 9539 9540 u8 lane3_module_mapping[0x20]; 9541 9542 u8 reserved_at_a0[0x160]; 9543 }; 9544 9545 struct mlx5_ifc_pmaos_reg_bits { 9546 u8 reserved_at_0[0x8]; 9547 u8 module[0x8]; 9548 u8 reserved_at_10[0x4]; 9549 u8 admin_status[0x4]; 9550 u8 reserved_at_18[0x4]; 9551 u8 oper_status[0x4]; 9552 9553 u8 ase[0x1]; 9554 u8 ee[0x1]; 9555 u8 reserved_at_22[0x1c]; 9556 u8 e[0x2]; 9557 9558 u8 reserved_at_40[0x40]; 9559 }; 9560 9561 struct mlx5_ifc_plpc_reg_bits { 9562 u8 reserved_at_0[0x4]; 9563 u8 profile_id[0xc]; 9564 u8 reserved_at_10[0x4]; 9565 u8 proto_mask[0x4]; 9566 u8 reserved_at_18[0x8]; 9567 9568 u8 reserved_at_20[0x10]; 9569 u8 lane_speed[0x10]; 9570 9571 u8 reserved_at_40[0x17]; 9572 u8 lpbf[0x1]; 9573 u8 fec_mode_policy[0x8]; 9574 9575 u8 retransmission_capability[0x8]; 9576 u8 fec_mode_capability[0x18]; 9577 9578 u8 retransmission_support_admin[0x8]; 9579 u8 fec_mode_support_admin[0x18]; 9580 9581 u8 retransmission_request_admin[0x8]; 9582 u8 fec_mode_request_admin[0x18]; 9583 9584 u8 reserved_at_c0[0x80]; 9585 }; 9586 9587 struct mlx5_ifc_plib_reg_bits { 9588 u8 reserved_at_0[0x8]; 9589 u8 local_port[0x8]; 9590 u8 reserved_at_10[0x8]; 9591 u8 ib_port[0x8]; 9592 9593 u8 reserved_at_20[0x60]; 9594 }; 9595 9596 struct mlx5_ifc_plbf_reg_bits { 9597 u8 reserved_at_0[0x8]; 9598 u8 local_port[0x8]; 9599 u8 reserved_at_10[0xd]; 9600 u8 lbf_mode[0x3]; 9601 9602 u8 reserved_at_20[0x20]; 9603 }; 9604 9605 struct mlx5_ifc_pipg_reg_bits { 9606 u8 reserved_at_0[0x8]; 9607 u8 local_port[0x8]; 9608 u8 reserved_at_10[0x10]; 9609 9610 u8 dic[0x1]; 9611 u8 reserved_at_21[0x19]; 9612 u8 ipg[0x4]; 9613 u8 reserved_at_3e[0x2]; 9614 }; 9615 9616 struct mlx5_ifc_pifr_reg_bits { 9617 u8 reserved_at_0[0x8]; 9618 u8 local_port[0x8]; 9619 u8 reserved_at_10[0x10]; 9620 9621 u8 reserved_at_20[0xe0]; 9622 9623 u8 port_filter[8][0x20]; 9624 9625 u8 port_filter_update_en[8][0x20]; 9626 }; 9627 9628 struct mlx5_ifc_pfcc_reg_bits { 9629 u8 reserved_at_0[0x8]; 9630 u8 local_port[0x8]; 9631 u8 reserved_at_10[0xb]; 9632 u8 ppan_mask_n[0x1]; 9633 u8 minor_stall_mask[0x1]; 9634 u8 critical_stall_mask[0x1]; 9635 u8 reserved_at_1e[0x2]; 9636 9637 u8 ppan[0x4]; 9638 u8 reserved_at_24[0x4]; 9639 u8 prio_mask_tx[0x8]; 9640 u8 reserved_at_30[0x8]; 9641 u8 prio_mask_rx[0x8]; 9642 9643 u8 pptx[0x1]; 9644 u8 aptx[0x1]; 9645 u8 pptx_mask_n[0x1]; 9646 u8 reserved_at_43[0x5]; 9647 u8 pfctx[0x8]; 9648 u8 reserved_at_50[0x10]; 9649 9650 u8 pprx[0x1]; 9651 u8 aprx[0x1]; 9652 u8 pprx_mask_n[0x1]; 9653 u8 reserved_at_63[0x5]; 9654 u8 pfcrx[0x8]; 9655 u8 reserved_at_70[0x10]; 9656 9657 u8 device_stall_minor_watermark[0x10]; 9658 u8 device_stall_critical_watermark[0x10]; 9659 9660 u8 reserved_at_a0[0x60]; 9661 }; 9662 9663 struct mlx5_ifc_pelc_reg_bits { 9664 u8 op[0x4]; 9665 u8 reserved_at_4[0x4]; 9666 u8 local_port[0x8]; 9667 u8 reserved_at_10[0x10]; 9668 9669 u8 op_admin[0x8]; 9670 u8 op_capability[0x8]; 9671 u8 op_request[0x8]; 9672 u8 op_active[0x8]; 9673 9674 u8 admin[0x40]; 9675 9676 u8 capability[0x40]; 9677 9678 u8 request[0x40]; 9679 9680 u8 active[0x40]; 9681 9682 u8 reserved_at_140[0x80]; 9683 }; 9684 9685 struct mlx5_ifc_peir_reg_bits { 9686 u8 reserved_at_0[0x8]; 9687 u8 local_port[0x8]; 9688 u8 reserved_at_10[0x10]; 9689 9690 u8 reserved_at_20[0xc]; 9691 u8 error_count[0x4]; 9692 u8 reserved_at_30[0x10]; 9693 9694 u8 reserved_at_40[0xc]; 9695 u8 lane[0x4]; 9696 u8 reserved_at_50[0x8]; 9697 u8 error_type[0x8]; 9698 }; 9699 9700 struct mlx5_ifc_mpegc_reg_bits { 9701 u8 reserved_at_0[0x30]; 9702 u8 field_select[0x10]; 9703 9704 u8 tx_overflow_sense[0x1]; 9705 u8 mark_cqe[0x1]; 9706 u8 mark_cnp[0x1]; 9707 u8 reserved_at_43[0x1b]; 9708 u8 tx_lossy_overflow_oper[0x2]; 9709 9710 u8 reserved_at_60[0x100]; 9711 }; 9712 9713 enum { 9714 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9715 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9716 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9717 }; 9718 9719 struct mlx5_ifc_mtutc_reg_bits { 9720 u8 reserved_at_0[0x1c]; 9721 u8 operation[0x4]; 9722 9723 u8 freq_adjustment[0x20]; 9724 9725 u8 reserved_at_40[0x40]; 9726 9727 u8 utc_sec[0x20]; 9728 9729 u8 reserved_at_a0[0x2]; 9730 u8 utc_nsec[0x1e]; 9731 9732 u8 time_adjustment[0x20]; 9733 }; 9734 9735 struct mlx5_ifc_pcam_enhanced_features_bits { 9736 u8 reserved_at_0[0x68]; 9737 u8 fec_50G_per_lane_in_pplm[0x1]; 9738 u8 reserved_at_69[0x4]; 9739 u8 rx_icrc_encapsulated_counter[0x1]; 9740 u8 reserved_at_6e[0x4]; 9741 u8 ptys_extended_ethernet[0x1]; 9742 u8 reserved_at_73[0x3]; 9743 u8 pfcc_mask[0x1]; 9744 u8 reserved_at_77[0x3]; 9745 u8 per_lane_error_counters[0x1]; 9746 u8 rx_buffer_fullness_counters[0x1]; 9747 u8 ptys_connector_type[0x1]; 9748 u8 reserved_at_7d[0x1]; 9749 u8 ppcnt_discard_group[0x1]; 9750 u8 ppcnt_statistical_group[0x1]; 9751 }; 9752 9753 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9754 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9755 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9756 9757 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9758 u8 pplm[0x1]; 9759 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9760 9761 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9762 u8 pbmc[0x1]; 9763 u8 pptb[0x1]; 9764 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9765 u8 ppcnt[0x1]; 9766 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9767 }; 9768 9769 struct mlx5_ifc_pcam_reg_bits { 9770 u8 reserved_at_0[0x8]; 9771 u8 feature_group[0x8]; 9772 u8 reserved_at_10[0x8]; 9773 u8 access_reg_group[0x8]; 9774 9775 u8 reserved_at_20[0x20]; 9776 9777 union { 9778 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9779 u8 reserved_at_0[0x80]; 9780 } port_access_reg_cap_mask; 9781 9782 u8 reserved_at_c0[0x80]; 9783 9784 union { 9785 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9786 u8 reserved_at_0[0x80]; 9787 } feature_cap_mask; 9788 9789 u8 reserved_at_1c0[0xc0]; 9790 }; 9791 9792 struct mlx5_ifc_mcam_enhanced_features_bits { 9793 u8 reserved_at_0[0x5d]; 9794 u8 mcia_32dwords[0x1]; 9795 u8 reserved_at_5e[0xc]; 9796 u8 reset_state[0x1]; 9797 u8 ptpcyc2realtime_modify[0x1]; 9798 u8 reserved_at_6c[0x2]; 9799 u8 pci_status_and_power[0x1]; 9800 u8 reserved_at_6f[0x5]; 9801 u8 mark_tx_action_cnp[0x1]; 9802 u8 mark_tx_action_cqe[0x1]; 9803 u8 dynamic_tx_overflow[0x1]; 9804 u8 reserved_at_77[0x4]; 9805 u8 pcie_outbound_stalled[0x1]; 9806 u8 tx_overflow_buffer_pkt[0x1]; 9807 u8 mtpps_enh_out_per_adj[0x1]; 9808 u8 mtpps_fs[0x1]; 9809 u8 pcie_performance_group[0x1]; 9810 }; 9811 9812 struct mlx5_ifc_mcam_access_reg_bits { 9813 u8 reserved_at_0[0x1c]; 9814 u8 mcda[0x1]; 9815 u8 mcc[0x1]; 9816 u8 mcqi[0x1]; 9817 u8 mcqs[0x1]; 9818 9819 u8 regs_95_to_87[0x9]; 9820 u8 mpegc[0x1]; 9821 u8 mtutc[0x1]; 9822 u8 regs_84_to_68[0x11]; 9823 u8 tracer_registers[0x4]; 9824 9825 u8 regs_63_to_46[0x12]; 9826 u8 mrtc[0x1]; 9827 u8 regs_44_to_32[0xd]; 9828 9829 u8 regs_31_to_0[0x20]; 9830 }; 9831 9832 struct mlx5_ifc_mcam_access_reg_bits1 { 9833 u8 regs_127_to_96[0x20]; 9834 9835 u8 regs_95_to_64[0x20]; 9836 9837 u8 regs_63_to_32[0x20]; 9838 9839 u8 regs_31_to_0[0x20]; 9840 }; 9841 9842 struct mlx5_ifc_mcam_access_reg_bits2 { 9843 u8 regs_127_to_99[0x1d]; 9844 u8 mirc[0x1]; 9845 u8 regs_97_to_96[0x2]; 9846 9847 u8 regs_95_to_64[0x20]; 9848 9849 u8 regs_63_to_32[0x20]; 9850 9851 u8 regs_31_to_0[0x20]; 9852 }; 9853 9854 struct mlx5_ifc_mcam_reg_bits { 9855 u8 reserved_at_0[0x8]; 9856 u8 feature_group[0x8]; 9857 u8 reserved_at_10[0x8]; 9858 u8 access_reg_group[0x8]; 9859 9860 u8 reserved_at_20[0x20]; 9861 9862 union { 9863 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9864 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9865 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9866 u8 reserved_at_0[0x80]; 9867 } mng_access_reg_cap_mask; 9868 9869 u8 reserved_at_c0[0x80]; 9870 9871 union { 9872 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9873 u8 reserved_at_0[0x80]; 9874 } mng_feature_cap_mask; 9875 9876 u8 reserved_at_1c0[0x80]; 9877 }; 9878 9879 struct mlx5_ifc_qcam_access_reg_cap_mask { 9880 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9881 u8 qpdpm[0x1]; 9882 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9883 u8 qdpm[0x1]; 9884 u8 qpts[0x1]; 9885 u8 qcap[0x1]; 9886 u8 qcam_access_reg_cap_mask_0[0x1]; 9887 }; 9888 9889 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9890 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9891 u8 qpts_trust_both[0x1]; 9892 }; 9893 9894 struct mlx5_ifc_qcam_reg_bits { 9895 u8 reserved_at_0[0x8]; 9896 u8 feature_group[0x8]; 9897 u8 reserved_at_10[0x8]; 9898 u8 access_reg_group[0x8]; 9899 u8 reserved_at_20[0x20]; 9900 9901 union { 9902 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9903 u8 reserved_at_0[0x80]; 9904 } qos_access_reg_cap_mask; 9905 9906 u8 reserved_at_c0[0x80]; 9907 9908 union { 9909 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9910 u8 reserved_at_0[0x80]; 9911 } qos_feature_cap_mask; 9912 9913 u8 reserved_at_1c0[0x80]; 9914 }; 9915 9916 struct mlx5_ifc_core_dump_reg_bits { 9917 u8 reserved_at_0[0x18]; 9918 u8 core_dump_type[0x8]; 9919 9920 u8 reserved_at_20[0x30]; 9921 u8 vhca_id[0x10]; 9922 9923 u8 reserved_at_60[0x8]; 9924 u8 qpn[0x18]; 9925 u8 reserved_at_80[0x180]; 9926 }; 9927 9928 struct mlx5_ifc_pcap_reg_bits { 9929 u8 reserved_at_0[0x8]; 9930 u8 local_port[0x8]; 9931 u8 reserved_at_10[0x10]; 9932 9933 u8 port_capability_mask[4][0x20]; 9934 }; 9935 9936 struct mlx5_ifc_paos_reg_bits { 9937 u8 swid[0x8]; 9938 u8 local_port[0x8]; 9939 u8 reserved_at_10[0x4]; 9940 u8 admin_status[0x4]; 9941 u8 reserved_at_18[0x4]; 9942 u8 oper_status[0x4]; 9943 9944 u8 ase[0x1]; 9945 u8 ee[0x1]; 9946 u8 reserved_at_22[0x1c]; 9947 u8 e[0x2]; 9948 9949 u8 reserved_at_40[0x40]; 9950 }; 9951 9952 struct mlx5_ifc_pamp_reg_bits { 9953 u8 reserved_at_0[0x8]; 9954 u8 opamp_group[0x8]; 9955 u8 reserved_at_10[0xc]; 9956 u8 opamp_group_type[0x4]; 9957 9958 u8 start_index[0x10]; 9959 u8 reserved_at_30[0x4]; 9960 u8 num_of_indices[0xc]; 9961 9962 u8 index_data[18][0x10]; 9963 }; 9964 9965 struct mlx5_ifc_pcmr_reg_bits { 9966 u8 reserved_at_0[0x8]; 9967 u8 local_port[0x8]; 9968 u8 reserved_at_10[0x10]; 9969 9970 u8 entropy_force_cap[0x1]; 9971 u8 entropy_calc_cap[0x1]; 9972 u8 entropy_gre_calc_cap[0x1]; 9973 u8 reserved_at_23[0xf]; 9974 u8 rx_ts_over_crc_cap[0x1]; 9975 u8 reserved_at_33[0xb]; 9976 u8 fcs_cap[0x1]; 9977 u8 reserved_at_3f[0x1]; 9978 9979 u8 entropy_force[0x1]; 9980 u8 entropy_calc[0x1]; 9981 u8 entropy_gre_calc[0x1]; 9982 u8 reserved_at_43[0xf]; 9983 u8 rx_ts_over_crc[0x1]; 9984 u8 reserved_at_53[0xb]; 9985 u8 fcs_chk[0x1]; 9986 u8 reserved_at_5f[0x1]; 9987 }; 9988 9989 struct mlx5_ifc_lane_2_module_mapping_bits { 9990 u8 reserved_at_0[0x4]; 9991 u8 rx_lane[0x4]; 9992 u8 reserved_at_8[0x4]; 9993 u8 tx_lane[0x4]; 9994 u8 reserved_at_10[0x8]; 9995 u8 module[0x8]; 9996 }; 9997 9998 struct mlx5_ifc_bufferx_reg_bits { 9999 u8 reserved_at_0[0x6]; 10000 u8 lossy[0x1]; 10001 u8 epsb[0x1]; 10002 u8 reserved_at_8[0x8]; 10003 u8 size[0x10]; 10004 10005 u8 xoff_threshold[0x10]; 10006 u8 xon_threshold[0x10]; 10007 }; 10008 10009 struct mlx5_ifc_set_node_in_bits { 10010 u8 node_description[64][0x8]; 10011 }; 10012 10013 struct mlx5_ifc_register_power_settings_bits { 10014 u8 reserved_at_0[0x18]; 10015 u8 power_settings_level[0x8]; 10016 10017 u8 reserved_at_20[0x60]; 10018 }; 10019 10020 struct mlx5_ifc_register_host_endianness_bits { 10021 u8 he[0x1]; 10022 u8 reserved_at_1[0x1f]; 10023 10024 u8 reserved_at_20[0x60]; 10025 }; 10026 10027 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10028 u8 reserved_at_0[0x20]; 10029 10030 u8 mkey[0x20]; 10031 10032 u8 addressh_63_32[0x20]; 10033 10034 u8 addressl_31_0[0x20]; 10035 }; 10036 10037 struct mlx5_ifc_ud_adrs_vector_bits { 10038 u8 dc_key[0x40]; 10039 10040 u8 ext[0x1]; 10041 u8 reserved_at_41[0x7]; 10042 u8 destination_qp_dct[0x18]; 10043 10044 u8 static_rate[0x4]; 10045 u8 sl_eth_prio[0x4]; 10046 u8 fl[0x1]; 10047 u8 mlid[0x7]; 10048 u8 rlid_udp_sport[0x10]; 10049 10050 u8 reserved_at_80[0x20]; 10051 10052 u8 rmac_47_16[0x20]; 10053 10054 u8 rmac_15_0[0x10]; 10055 u8 tclass[0x8]; 10056 u8 hop_limit[0x8]; 10057 10058 u8 reserved_at_e0[0x1]; 10059 u8 grh[0x1]; 10060 u8 reserved_at_e2[0x2]; 10061 u8 src_addr_index[0x8]; 10062 u8 flow_label[0x14]; 10063 10064 u8 rgid_rip[16][0x8]; 10065 }; 10066 10067 struct mlx5_ifc_pages_req_event_bits { 10068 u8 reserved_at_0[0x10]; 10069 u8 function_id[0x10]; 10070 10071 u8 num_pages[0x20]; 10072 10073 u8 reserved_at_40[0xa0]; 10074 }; 10075 10076 struct mlx5_ifc_eqe_bits { 10077 u8 reserved_at_0[0x8]; 10078 u8 event_type[0x8]; 10079 u8 reserved_at_10[0x8]; 10080 u8 event_sub_type[0x8]; 10081 10082 u8 reserved_at_20[0xe0]; 10083 10084 union mlx5_ifc_event_auto_bits event_data; 10085 10086 u8 reserved_at_1e0[0x10]; 10087 u8 signature[0x8]; 10088 u8 reserved_at_1f8[0x7]; 10089 u8 owner[0x1]; 10090 }; 10091 10092 enum { 10093 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10094 }; 10095 10096 struct mlx5_ifc_cmd_queue_entry_bits { 10097 u8 type[0x8]; 10098 u8 reserved_at_8[0x18]; 10099 10100 u8 input_length[0x20]; 10101 10102 u8 input_mailbox_pointer_63_32[0x20]; 10103 10104 u8 input_mailbox_pointer_31_9[0x17]; 10105 u8 reserved_at_77[0x9]; 10106 10107 u8 command_input_inline_data[16][0x8]; 10108 10109 u8 command_output_inline_data[16][0x8]; 10110 10111 u8 output_mailbox_pointer_63_32[0x20]; 10112 10113 u8 output_mailbox_pointer_31_9[0x17]; 10114 u8 reserved_at_1b7[0x9]; 10115 10116 u8 output_length[0x20]; 10117 10118 u8 token[0x8]; 10119 u8 signature[0x8]; 10120 u8 reserved_at_1f0[0x8]; 10121 u8 status[0x7]; 10122 u8 ownership[0x1]; 10123 }; 10124 10125 struct mlx5_ifc_cmd_out_bits { 10126 u8 status[0x8]; 10127 u8 reserved_at_8[0x18]; 10128 10129 u8 syndrome[0x20]; 10130 10131 u8 command_output[0x20]; 10132 }; 10133 10134 struct mlx5_ifc_cmd_in_bits { 10135 u8 opcode[0x10]; 10136 u8 reserved_at_10[0x10]; 10137 10138 u8 reserved_at_20[0x10]; 10139 u8 op_mod[0x10]; 10140 10141 u8 command[][0x20]; 10142 }; 10143 10144 struct mlx5_ifc_cmd_if_box_bits { 10145 u8 mailbox_data[512][0x8]; 10146 10147 u8 reserved_at_1000[0x180]; 10148 10149 u8 next_pointer_63_32[0x20]; 10150 10151 u8 next_pointer_31_10[0x16]; 10152 u8 reserved_at_11b6[0xa]; 10153 10154 u8 block_number[0x20]; 10155 10156 u8 reserved_at_11e0[0x8]; 10157 u8 token[0x8]; 10158 u8 ctrl_signature[0x8]; 10159 u8 signature[0x8]; 10160 }; 10161 10162 struct mlx5_ifc_mtt_bits { 10163 u8 ptag_63_32[0x20]; 10164 10165 u8 ptag_31_8[0x18]; 10166 u8 reserved_at_38[0x6]; 10167 u8 wr_en[0x1]; 10168 u8 rd_en[0x1]; 10169 }; 10170 10171 struct mlx5_ifc_query_wol_rol_out_bits { 10172 u8 status[0x8]; 10173 u8 reserved_at_8[0x18]; 10174 10175 u8 syndrome[0x20]; 10176 10177 u8 reserved_at_40[0x10]; 10178 u8 rol_mode[0x8]; 10179 u8 wol_mode[0x8]; 10180 10181 u8 reserved_at_60[0x20]; 10182 }; 10183 10184 struct mlx5_ifc_query_wol_rol_in_bits { 10185 u8 opcode[0x10]; 10186 u8 reserved_at_10[0x10]; 10187 10188 u8 reserved_at_20[0x10]; 10189 u8 op_mod[0x10]; 10190 10191 u8 reserved_at_40[0x40]; 10192 }; 10193 10194 struct mlx5_ifc_set_wol_rol_out_bits { 10195 u8 status[0x8]; 10196 u8 reserved_at_8[0x18]; 10197 10198 u8 syndrome[0x20]; 10199 10200 u8 reserved_at_40[0x40]; 10201 }; 10202 10203 struct mlx5_ifc_set_wol_rol_in_bits { 10204 u8 opcode[0x10]; 10205 u8 reserved_at_10[0x10]; 10206 10207 u8 reserved_at_20[0x10]; 10208 u8 op_mod[0x10]; 10209 10210 u8 rol_mode_valid[0x1]; 10211 u8 wol_mode_valid[0x1]; 10212 u8 reserved_at_42[0xe]; 10213 u8 rol_mode[0x8]; 10214 u8 wol_mode[0x8]; 10215 10216 u8 reserved_at_60[0x20]; 10217 }; 10218 10219 enum { 10220 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10221 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10222 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10223 }; 10224 10225 enum { 10226 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10227 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10228 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10229 }; 10230 10231 enum { 10232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10240 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10241 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10242 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10243 }; 10244 10245 struct mlx5_ifc_initial_seg_bits { 10246 u8 fw_rev_minor[0x10]; 10247 u8 fw_rev_major[0x10]; 10248 10249 u8 cmd_interface_rev[0x10]; 10250 u8 fw_rev_subminor[0x10]; 10251 10252 u8 reserved_at_40[0x40]; 10253 10254 u8 cmdq_phy_addr_63_32[0x20]; 10255 10256 u8 cmdq_phy_addr_31_12[0x14]; 10257 u8 reserved_at_b4[0x2]; 10258 u8 nic_interface[0x2]; 10259 u8 log_cmdq_size[0x4]; 10260 u8 log_cmdq_stride[0x4]; 10261 10262 u8 command_doorbell_vector[0x20]; 10263 10264 u8 reserved_at_e0[0xf00]; 10265 10266 u8 initializing[0x1]; 10267 u8 reserved_at_fe1[0x4]; 10268 u8 nic_interface_supported[0x3]; 10269 u8 embedded_cpu[0x1]; 10270 u8 reserved_at_fe9[0x17]; 10271 10272 struct mlx5_ifc_health_buffer_bits health_buffer; 10273 10274 u8 no_dram_nic_offset[0x20]; 10275 10276 u8 reserved_at_1220[0x6e40]; 10277 10278 u8 reserved_at_8060[0x1f]; 10279 u8 clear_int[0x1]; 10280 10281 u8 health_syndrome[0x8]; 10282 u8 health_counter[0x18]; 10283 10284 u8 reserved_at_80a0[0x17fc0]; 10285 }; 10286 10287 struct mlx5_ifc_mtpps_reg_bits { 10288 u8 reserved_at_0[0xc]; 10289 u8 cap_number_of_pps_pins[0x4]; 10290 u8 reserved_at_10[0x4]; 10291 u8 cap_max_num_of_pps_in_pins[0x4]; 10292 u8 reserved_at_18[0x4]; 10293 u8 cap_max_num_of_pps_out_pins[0x4]; 10294 10295 u8 reserved_at_20[0x24]; 10296 u8 cap_pin_3_mode[0x4]; 10297 u8 reserved_at_48[0x4]; 10298 u8 cap_pin_2_mode[0x4]; 10299 u8 reserved_at_50[0x4]; 10300 u8 cap_pin_1_mode[0x4]; 10301 u8 reserved_at_58[0x4]; 10302 u8 cap_pin_0_mode[0x4]; 10303 10304 u8 reserved_at_60[0x4]; 10305 u8 cap_pin_7_mode[0x4]; 10306 u8 reserved_at_68[0x4]; 10307 u8 cap_pin_6_mode[0x4]; 10308 u8 reserved_at_70[0x4]; 10309 u8 cap_pin_5_mode[0x4]; 10310 u8 reserved_at_78[0x4]; 10311 u8 cap_pin_4_mode[0x4]; 10312 10313 u8 field_select[0x20]; 10314 u8 reserved_at_a0[0x60]; 10315 10316 u8 enable[0x1]; 10317 u8 reserved_at_101[0xb]; 10318 u8 pattern[0x4]; 10319 u8 reserved_at_110[0x4]; 10320 u8 pin_mode[0x4]; 10321 u8 pin[0x8]; 10322 10323 u8 reserved_at_120[0x20]; 10324 10325 u8 time_stamp[0x40]; 10326 10327 u8 out_pulse_duration[0x10]; 10328 u8 out_periodic_adjustment[0x10]; 10329 u8 enhanced_out_periodic_adjustment[0x20]; 10330 10331 u8 reserved_at_1c0[0x20]; 10332 }; 10333 10334 struct mlx5_ifc_mtppse_reg_bits { 10335 u8 reserved_at_0[0x18]; 10336 u8 pin[0x8]; 10337 u8 event_arm[0x1]; 10338 u8 reserved_at_21[0x1b]; 10339 u8 event_generation_mode[0x4]; 10340 u8 reserved_at_40[0x40]; 10341 }; 10342 10343 struct mlx5_ifc_mcqs_reg_bits { 10344 u8 last_index_flag[0x1]; 10345 u8 reserved_at_1[0x7]; 10346 u8 fw_device[0x8]; 10347 u8 component_index[0x10]; 10348 10349 u8 reserved_at_20[0x10]; 10350 u8 identifier[0x10]; 10351 10352 u8 reserved_at_40[0x17]; 10353 u8 component_status[0x5]; 10354 u8 component_update_state[0x4]; 10355 10356 u8 last_update_state_changer_type[0x4]; 10357 u8 last_update_state_changer_host_id[0x4]; 10358 u8 reserved_at_68[0x18]; 10359 }; 10360 10361 struct mlx5_ifc_mcqi_cap_bits { 10362 u8 supported_info_bitmask[0x20]; 10363 10364 u8 component_size[0x20]; 10365 10366 u8 max_component_size[0x20]; 10367 10368 u8 log_mcda_word_size[0x4]; 10369 u8 reserved_at_64[0xc]; 10370 u8 mcda_max_write_size[0x10]; 10371 10372 u8 rd_en[0x1]; 10373 u8 reserved_at_81[0x1]; 10374 u8 match_chip_id[0x1]; 10375 u8 match_psid[0x1]; 10376 u8 check_user_timestamp[0x1]; 10377 u8 match_base_guid_mac[0x1]; 10378 u8 reserved_at_86[0x1a]; 10379 }; 10380 10381 struct mlx5_ifc_mcqi_version_bits { 10382 u8 reserved_at_0[0x2]; 10383 u8 build_time_valid[0x1]; 10384 u8 user_defined_time_valid[0x1]; 10385 u8 reserved_at_4[0x14]; 10386 u8 version_string_length[0x8]; 10387 10388 u8 version[0x20]; 10389 10390 u8 build_time[0x40]; 10391 10392 u8 user_defined_time[0x40]; 10393 10394 u8 build_tool_version[0x20]; 10395 10396 u8 reserved_at_e0[0x20]; 10397 10398 u8 version_string[92][0x8]; 10399 }; 10400 10401 struct mlx5_ifc_mcqi_activation_method_bits { 10402 u8 pending_server_ac_power_cycle[0x1]; 10403 u8 pending_server_dc_power_cycle[0x1]; 10404 u8 pending_server_reboot[0x1]; 10405 u8 pending_fw_reset[0x1]; 10406 u8 auto_activate[0x1]; 10407 u8 all_hosts_sync[0x1]; 10408 u8 device_hw_reset[0x1]; 10409 u8 reserved_at_7[0x19]; 10410 }; 10411 10412 union mlx5_ifc_mcqi_reg_data_bits { 10413 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10414 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10415 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10416 }; 10417 10418 struct mlx5_ifc_mcqi_reg_bits { 10419 u8 read_pending_component[0x1]; 10420 u8 reserved_at_1[0xf]; 10421 u8 component_index[0x10]; 10422 10423 u8 reserved_at_20[0x20]; 10424 10425 u8 reserved_at_40[0x1b]; 10426 u8 info_type[0x5]; 10427 10428 u8 info_size[0x20]; 10429 10430 u8 offset[0x20]; 10431 10432 u8 reserved_at_a0[0x10]; 10433 u8 data_size[0x10]; 10434 10435 union mlx5_ifc_mcqi_reg_data_bits data[]; 10436 }; 10437 10438 struct mlx5_ifc_mcc_reg_bits { 10439 u8 reserved_at_0[0x4]; 10440 u8 time_elapsed_since_last_cmd[0xc]; 10441 u8 reserved_at_10[0x8]; 10442 u8 instruction[0x8]; 10443 10444 u8 reserved_at_20[0x10]; 10445 u8 component_index[0x10]; 10446 10447 u8 reserved_at_40[0x8]; 10448 u8 update_handle[0x18]; 10449 10450 u8 handle_owner_type[0x4]; 10451 u8 handle_owner_host_id[0x4]; 10452 u8 reserved_at_68[0x1]; 10453 u8 control_progress[0x7]; 10454 u8 error_code[0x8]; 10455 u8 reserved_at_78[0x4]; 10456 u8 control_state[0x4]; 10457 10458 u8 component_size[0x20]; 10459 10460 u8 reserved_at_a0[0x60]; 10461 }; 10462 10463 struct mlx5_ifc_mcda_reg_bits { 10464 u8 reserved_at_0[0x8]; 10465 u8 update_handle[0x18]; 10466 10467 u8 offset[0x20]; 10468 10469 u8 reserved_at_40[0x10]; 10470 u8 size[0x10]; 10471 10472 u8 reserved_at_60[0x20]; 10473 10474 u8 data[][0x20]; 10475 }; 10476 10477 enum { 10478 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10479 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10480 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10481 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10482 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10483 }; 10484 10485 enum { 10486 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10487 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10488 }; 10489 10490 enum { 10491 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10492 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10493 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10494 }; 10495 10496 struct mlx5_ifc_mfrl_reg_bits { 10497 u8 reserved_at_0[0x20]; 10498 10499 u8 reserved_at_20[0x2]; 10500 u8 pci_sync_for_fw_update_start[0x1]; 10501 u8 pci_sync_for_fw_update_resp[0x2]; 10502 u8 rst_type_sel[0x3]; 10503 u8 reserved_at_28[0x4]; 10504 u8 reset_state[0x4]; 10505 u8 reset_type[0x8]; 10506 u8 reset_level[0x8]; 10507 }; 10508 10509 struct mlx5_ifc_mirc_reg_bits { 10510 u8 reserved_at_0[0x18]; 10511 u8 status_code[0x8]; 10512 10513 u8 reserved_at_20[0x20]; 10514 }; 10515 10516 struct mlx5_ifc_pddr_monitor_opcode_bits { 10517 u8 reserved_at_0[0x10]; 10518 u8 monitor_opcode[0x10]; 10519 }; 10520 10521 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10522 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10523 u8 reserved_at_0[0x20]; 10524 }; 10525 10526 enum { 10527 /* Monitor opcodes */ 10528 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10529 }; 10530 10531 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10532 u8 reserved_at_0[0x10]; 10533 u8 group_opcode[0x10]; 10534 10535 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10536 10537 u8 reserved_at_40[0x20]; 10538 10539 u8 status_message[59][0x20]; 10540 }; 10541 10542 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10543 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10544 u8 reserved_at_0[0x7c0]; 10545 }; 10546 10547 enum { 10548 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10549 }; 10550 10551 struct mlx5_ifc_pddr_reg_bits { 10552 u8 reserved_at_0[0x8]; 10553 u8 local_port[0x8]; 10554 u8 pnat[0x2]; 10555 u8 reserved_at_12[0xe]; 10556 10557 u8 reserved_at_20[0x18]; 10558 u8 page_select[0x8]; 10559 10560 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10561 }; 10562 10563 struct mlx5_ifc_mrtc_reg_bits { 10564 u8 time_synced[0x1]; 10565 u8 reserved_at_1[0x1f]; 10566 10567 u8 reserved_at_20[0x20]; 10568 10569 u8 time_h[0x20]; 10570 10571 u8 time_l[0x20]; 10572 }; 10573 10574 union mlx5_ifc_ports_control_registers_document_bits { 10575 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10576 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10577 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10578 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10579 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10580 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10581 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10582 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10583 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10584 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10585 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10586 struct mlx5_ifc_paos_reg_bits paos_reg; 10587 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10588 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10589 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10590 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10591 struct mlx5_ifc_peir_reg_bits peir_reg; 10592 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10593 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10594 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10595 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10596 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10597 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10598 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10599 struct mlx5_ifc_plib_reg_bits plib_reg; 10600 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10601 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10602 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10603 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10604 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10605 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10606 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10607 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10608 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10609 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10610 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10611 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10612 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10613 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10614 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10615 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10616 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10617 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10618 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10619 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10620 struct mlx5_ifc_pude_reg_bits pude_reg; 10621 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10622 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10623 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10624 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10625 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10626 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10627 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10628 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10629 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10630 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10631 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10632 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10633 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10634 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10635 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10636 u8 reserved_at_0[0x60e0]; 10637 }; 10638 10639 union mlx5_ifc_debug_enhancements_document_bits { 10640 struct mlx5_ifc_health_buffer_bits health_buffer; 10641 u8 reserved_at_0[0x200]; 10642 }; 10643 10644 union mlx5_ifc_uplink_pci_interface_document_bits { 10645 struct mlx5_ifc_initial_seg_bits initial_seg; 10646 u8 reserved_at_0[0x20060]; 10647 }; 10648 10649 struct mlx5_ifc_set_flow_table_root_out_bits { 10650 u8 status[0x8]; 10651 u8 reserved_at_8[0x18]; 10652 10653 u8 syndrome[0x20]; 10654 10655 u8 reserved_at_40[0x40]; 10656 }; 10657 10658 struct mlx5_ifc_set_flow_table_root_in_bits { 10659 u8 opcode[0x10]; 10660 u8 reserved_at_10[0x10]; 10661 10662 u8 reserved_at_20[0x10]; 10663 u8 op_mod[0x10]; 10664 10665 u8 other_vport[0x1]; 10666 u8 reserved_at_41[0xf]; 10667 u8 vport_number[0x10]; 10668 10669 u8 reserved_at_60[0x20]; 10670 10671 u8 table_type[0x8]; 10672 u8 reserved_at_88[0x7]; 10673 u8 table_of_other_vport[0x1]; 10674 u8 table_vport_number[0x10]; 10675 10676 u8 reserved_at_a0[0x8]; 10677 u8 table_id[0x18]; 10678 10679 u8 reserved_at_c0[0x8]; 10680 u8 underlay_qpn[0x18]; 10681 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10682 u8 reserved_at_e1[0xf]; 10683 u8 table_eswitch_owner_vhca_id[0x10]; 10684 u8 reserved_at_100[0x100]; 10685 }; 10686 10687 enum { 10688 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10689 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10690 }; 10691 10692 struct mlx5_ifc_modify_flow_table_out_bits { 10693 u8 status[0x8]; 10694 u8 reserved_at_8[0x18]; 10695 10696 u8 syndrome[0x20]; 10697 10698 u8 reserved_at_40[0x40]; 10699 }; 10700 10701 struct mlx5_ifc_modify_flow_table_in_bits { 10702 u8 opcode[0x10]; 10703 u8 reserved_at_10[0x10]; 10704 10705 u8 reserved_at_20[0x10]; 10706 u8 op_mod[0x10]; 10707 10708 u8 other_vport[0x1]; 10709 u8 reserved_at_41[0xf]; 10710 u8 vport_number[0x10]; 10711 10712 u8 reserved_at_60[0x10]; 10713 u8 modify_field_select[0x10]; 10714 10715 u8 table_type[0x8]; 10716 u8 reserved_at_88[0x18]; 10717 10718 u8 reserved_at_a0[0x8]; 10719 u8 table_id[0x18]; 10720 10721 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10722 }; 10723 10724 struct mlx5_ifc_ets_tcn_config_reg_bits { 10725 u8 g[0x1]; 10726 u8 b[0x1]; 10727 u8 r[0x1]; 10728 u8 reserved_at_3[0x9]; 10729 u8 group[0x4]; 10730 u8 reserved_at_10[0x9]; 10731 u8 bw_allocation[0x7]; 10732 10733 u8 reserved_at_20[0xc]; 10734 u8 max_bw_units[0x4]; 10735 u8 reserved_at_30[0x8]; 10736 u8 max_bw_value[0x8]; 10737 }; 10738 10739 struct mlx5_ifc_ets_global_config_reg_bits { 10740 u8 reserved_at_0[0x2]; 10741 u8 r[0x1]; 10742 u8 reserved_at_3[0x1d]; 10743 10744 u8 reserved_at_20[0xc]; 10745 u8 max_bw_units[0x4]; 10746 u8 reserved_at_30[0x8]; 10747 u8 max_bw_value[0x8]; 10748 }; 10749 10750 struct mlx5_ifc_qetc_reg_bits { 10751 u8 reserved_at_0[0x8]; 10752 u8 port_number[0x8]; 10753 u8 reserved_at_10[0x30]; 10754 10755 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10756 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10757 }; 10758 10759 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10760 u8 e[0x1]; 10761 u8 reserved_at_01[0x0b]; 10762 u8 prio[0x04]; 10763 }; 10764 10765 struct mlx5_ifc_qpdpm_reg_bits { 10766 u8 reserved_at_0[0x8]; 10767 u8 local_port[0x8]; 10768 u8 reserved_at_10[0x10]; 10769 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10770 }; 10771 10772 struct mlx5_ifc_qpts_reg_bits { 10773 u8 reserved_at_0[0x8]; 10774 u8 local_port[0x8]; 10775 u8 reserved_at_10[0x2d]; 10776 u8 trust_state[0x3]; 10777 }; 10778 10779 struct mlx5_ifc_pptb_reg_bits { 10780 u8 reserved_at_0[0x2]; 10781 u8 mm[0x2]; 10782 u8 reserved_at_4[0x4]; 10783 u8 local_port[0x8]; 10784 u8 reserved_at_10[0x6]; 10785 u8 cm[0x1]; 10786 u8 um[0x1]; 10787 u8 pm[0x8]; 10788 10789 u8 prio_x_buff[0x20]; 10790 10791 u8 pm_msb[0x8]; 10792 u8 reserved_at_48[0x10]; 10793 u8 ctrl_buff[0x4]; 10794 u8 untagged_buff[0x4]; 10795 }; 10796 10797 struct mlx5_ifc_sbcam_reg_bits { 10798 u8 reserved_at_0[0x8]; 10799 u8 feature_group[0x8]; 10800 u8 reserved_at_10[0x8]; 10801 u8 access_reg_group[0x8]; 10802 10803 u8 reserved_at_20[0x20]; 10804 10805 u8 sb_access_reg_cap_mask[4][0x20]; 10806 10807 u8 reserved_at_c0[0x80]; 10808 10809 u8 sb_feature_cap_mask[4][0x20]; 10810 10811 u8 reserved_at_1c0[0x40]; 10812 10813 u8 cap_total_buffer_size[0x20]; 10814 10815 u8 cap_cell_size[0x10]; 10816 u8 cap_max_pg_buffers[0x8]; 10817 u8 cap_num_pool_supported[0x8]; 10818 10819 u8 reserved_at_240[0x8]; 10820 u8 cap_sbsr_stat_size[0x8]; 10821 u8 cap_max_tclass_data[0x8]; 10822 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10823 }; 10824 10825 struct mlx5_ifc_pbmc_reg_bits { 10826 u8 reserved_at_0[0x8]; 10827 u8 local_port[0x8]; 10828 u8 reserved_at_10[0x10]; 10829 10830 u8 xoff_timer_value[0x10]; 10831 u8 xoff_refresh[0x10]; 10832 10833 u8 reserved_at_40[0x9]; 10834 u8 fullness_threshold[0x7]; 10835 u8 port_buffer_size[0x10]; 10836 10837 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10838 10839 u8 reserved_at_2e0[0x80]; 10840 }; 10841 10842 struct mlx5_ifc_qtct_reg_bits { 10843 u8 reserved_at_0[0x8]; 10844 u8 port_number[0x8]; 10845 u8 reserved_at_10[0xd]; 10846 u8 prio[0x3]; 10847 10848 u8 reserved_at_20[0x1d]; 10849 u8 tclass[0x3]; 10850 }; 10851 10852 struct mlx5_ifc_mcia_reg_bits { 10853 u8 l[0x1]; 10854 u8 reserved_at_1[0x7]; 10855 u8 module[0x8]; 10856 u8 reserved_at_10[0x8]; 10857 u8 status[0x8]; 10858 10859 u8 i2c_device_address[0x8]; 10860 u8 page_number[0x8]; 10861 u8 device_address[0x10]; 10862 10863 u8 reserved_at_40[0x10]; 10864 u8 size[0x10]; 10865 10866 u8 reserved_at_60[0x20]; 10867 10868 u8 dword_0[0x20]; 10869 u8 dword_1[0x20]; 10870 u8 dword_2[0x20]; 10871 u8 dword_3[0x20]; 10872 u8 dword_4[0x20]; 10873 u8 dword_5[0x20]; 10874 u8 dword_6[0x20]; 10875 u8 dword_7[0x20]; 10876 u8 dword_8[0x20]; 10877 u8 dword_9[0x20]; 10878 u8 dword_10[0x20]; 10879 u8 dword_11[0x20]; 10880 }; 10881 10882 struct mlx5_ifc_dcbx_param_bits { 10883 u8 dcbx_cee_cap[0x1]; 10884 u8 dcbx_ieee_cap[0x1]; 10885 u8 dcbx_standby_cap[0x1]; 10886 u8 reserved_at_3[0x5]; 10887 u8 port_number[0x8]; 10888 u8 reserved_at_10[0xa]; 10889 u8 max_application_table_size[6]; 10890 u8 reserved_at_20[0x15]; 10891 u8 version_oper[0x3]; 10892 u8 reserved_at_38[5]; 10893 u8 version_admin[0x3]; 10894 u8 willing_admin[0x1]; 10895 u8 reserved_at_41[0x3]; 10896 u8 pfc_cap_oper[0x4]; 10897 u8 reserved_at_48[0x4]; 10898 u8 pfc_cap_admin[0x4]; 10899 u8 reserved_at_50[0x4]; 10900 u8 num_of_tc_oper[0x4]; 10901 u8 reserved_at_58[0x4]; 10902 u8 num_of_tc_admin[0x4]; 10903 u8 remote_willing[0x1]; 10904 u8 reserved_at_61[3]; 10905 u8 remote_pfc_cap[4]; 10906 u8 reserved_at_68[0x14]; 10907 u8 remote_num_of_tc[0x4]; 10908 u8 reserved_at_80[0x18]; 10909 u8 error[0x8]; 10910 u8 reserved_at_a0[0x160]; 10911 }; 10912 10913 enum { 10914 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10915 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10916 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10917 }; 10918 10919 struct mlx5_ifc_lagc_bits { 10920 u8 fdb_selection_mode[0x1]; 10921 u8 reserved_at_1[0x14]; 10922 u8 port_select_mode[0x3]; 10923 u8 reserved_at_18[0x5]; 10924 u8 lag_state[0x3]; 10925 10926 u8 reserved_at_20[0x14]; 10927 u8 tx_remap_affinity_2[0x4]; 10928 u8 reserved_at_38[0x4]; 10929 u8 tx_remap_affinity_1[0x4]; 10930 }; 10931 10932 struct mlx5_ifc_create_lag_out_bits { 10933 u8 status[0x8]; 10934 u8 reserved_at_8[0x18]; 10935 10936 u8 syndrome[0x20]; 10937 10938 u8 reserved_at_40[0x40]; 10939 }; 10940 10941 struct mlx5_ifc_create_lag_in_bits { 10942 u8 opcode[0x10]; 10943 u8 reserved_at_10[0x10]; 10944 10945 u8 reserved_at_20[0x10]; 10946 u8 op_mod[0x10]; 10947 10948 struct mlx5_ifc_lagc_bits ctx; 10949 }; 10950 10951 struct mlx5_ifc_modify_lag_out_bits { 10952 u8 status[0x8]; 10953 u8 reserved_at_8[0x18]; 10954 10955 u8 syndrome[0x20]; 10956 10957 u8 reserved_at_40[0x40]; 10958 }; 10959 10960 struct mlx5_ifc_modify_lag_in_bits { 10961 u8 opcode[0x10]; 10962 u8 reserved_at_10[0x10]; 10963 10964 u8 reserved_at_20[0x10]; 10965 u8 op_mod[0x10]; 10966 10967 u8 reserved_at_40[0x20]; 10968 u8 field_select[0x20]; 10969 10970 struct mlx5_ifc_lagc_bits ctx; 10971 }; 10972 10973 struct mlx5_ifc_query_lag_out_bits { 10974 u8 status[0x8]; 10975 u8 reserved_at_8[0x18]; 10976 10977 u8 syndrome[0x20]; 10978 10979 struct mlx5_ifc_lagc_bits ctx; 10980 }; 10981 10982 struct mlx5_ifc_query_lag_in_bits { 10983 u8 opcode[0x10]; 10984 u8 reserved_at_10[0x10]; 10985 10986 u8 reserved_at_20[0x10]; 10987 u8 op_mod[0x10]; 10988 10989 u8 reserved_at_40[0x40]; 10990 }; 10991 10992 struct mlx5_ifc_destroy_lag_out_bits { 10993 u8 status[0x8]; 10994 u8 reserved_at_8[0x18]; 10995 10996 u8 syndrome[0x20]; 10997 10998 u8 reserved_at_40[0x40]; 10999 }; 11000 11001 struct mlx5_ifc_destroy_lag_in_bits { 11002 u8 opcode[0x10]; 11003 u8 reserved_at_10[0x10]; 11004 11005 u8 reserved_at_20[0x10]; 11006 u8 op_mod[0x10]; 11007 11008 u8 reserved_at_40[0x40]; 11009 }; 11010 11011 struct mlx5_ifc_create_vport_lag_out_bits { 11012 u8 status[0x8]; 11013 u8 reserved_at_8[0x18]; 11014 11015 u8 syndrome[0x20]; 11016 11017 u8 reserved_at_40[0x40]; 11018 }; 11019 11020 struct mlx5_ifc_create_vport_lag_in_bits { 11021 u8 opcode[0x10]; 11022 u8 reserved_at_10[0x10]; 11023 11024 u8 reserved_at_20[0x10]; 11025 u8 op_mod[0x10]; 11026 11027 u8 reserved_at_40[0x40]; 11028 }; 11029 11030 struct mlx5_ifc_destroy_vport_lag_out_bits { 11031 u8 status[0x8]; 11032 u8 reserved_at_8[0x18]; 11033 11034 u8 syndrome[0x20]; 11035 11036 u8 reserved_at_40[0x40]; 11037 }; 11038 11039 struct mlx5_ifc_destroy_vport_lag_in_bits { 11040 u8 opcode[0x10]; 11041 u8 reserved_at_10[0x10]; 11042 11043 u8 reserved_at_20[0x10]; 11044 u8 op_mod[0x10]; 11045 11046 u8 reserved_at_40[0x40]; 11047 }; 11048 11049 enum { 11050 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11051 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11052 }; 11053 11054 struct mlx5_ifc_modify_memic_in_bits { 11055 u8 opcode[0x10]; 11056 u8 uid[0x10]; 11057 11058 u8 reserved_at_20[0x10]; 11059 u8 op_mod[0x10]; 11060 11061 u8 reserved_at_40[0x20]; 11062 11063 u8 reserved_at_60[0x18]; 11064 u8 memic_operation_type[0x8]; 11065 11066 u8 memic_start_addr[0x40]; 11067 11068 u8 reserved_at_c0[0x140]; 11069 }; 11070 11071 struct mlx5_ifc_modify_memic_out_bits { 11072 u8 status[0x8]; 11073 u8 reserved_at_8[0x18]; 11074 11075 u8 syndrome[0x20]; 11076 11077 u8 reserved_at_40[0x40]; 11078 11079 u8 memic_operation_addr[0x40]; 11080 11081 u8 reserved_at_c0[0x140]; 11082 }; 11083 11084 struct mlx5_ifc_alloc_memic_in_bits { 11085 u8 opcode[0x10]; 11086 u8 reserved_at_10[0x10]; 11087 11088 u8 reserved_at_20[0x10]; 11089 u8 op_mod[0x10]; 11090 11091 u8 reserved_at_30[0x20]; 11092 11093 u8 reserved_at_40[0x18]; 11094 u8 log_memic_addr_alignment[0x8]; 11095 11096 u8 range_start_addr[0x40]; 11097 11098 u8 range_size[0x20]; 11099 11100 u8 memic_size[0x20]; 11101 }; 11102 11103 struct mlx5_ifc_alloc_memic_out_bits { 11104 u8 status[0x8]; 11105 u8 reserved_at_8[0x18]; 11106 11107 u8 syndrome[0x20]; 11108 11109 u8 memic_start_addr[0x40]; 11110 }; 11111 11112 struct mlx5_ifc_dealloc_memic_in_bits { 11113 u8 opcode[0x10]; 11114 u8 reserved_at_10[0x10]; 11115 11116 u8 reserved_at_20[0x10]; 11117 u8 op_mod[0x10]; 11118 11119 u8 reserved_at_40[0x40]; 11120 11121 u8 memic_start_addr[0x40]; 11122 11123 u8 memic_size[0x20]; 11124 11125 u8 reserved_at_e0[0x20]; 11126 }; 11127 11128 struct mlx5_ifc_dealloc_memic_out_bits { 11129 u8 status[0x8]; 11130 u8 reserved_at_8[0x18]; 11131 11132 u8 syndrome[0x20]; 11133 11134 u8 reserved_at_40[0x40]; 11135 }; 11136 11137 struct mlx5_ifc_umem_bits { 11138 u8 reserved_at_0[0x80]; 11139 11140 u8 reserved_at_80[0x1b]; 11141 u8 log_page_size[0x5]; 11142 11143 u8 page_offset[0x20]; 11144 11145 u8 num_of_mtt[0x40]; 11146 11147 struct mlx5_ifc_mtt_bits mtt[]; 11148 }; 11149 11150 struct mlx5_ifc_uctx_bits { 11151 u8 cap[0x20]; 11152 11153 u8 reserved_at_20[0x160]; 11154 }; 11155 11156 struct mlx5_ifc_sw_icm_bits { 11157 u8 modify_field_select[0x40]; 11158 11159 u8 reserved_at_40[0x18]; 11160 u8 log_sw_icm_size[0x8]; 11161 11162 u8 reserved_at_60[0x20]; 11163 11164 u8 sw_icm_start_addr[0x40]; 11165 11166 u8 reserved_at_c0[0x140]; 11167 }; 11168 11169 struct mlx5_ifc_geneve_tlv_option_bits { 11170 u8 modify_field_select[0x40]; 11171 11172 u8 reserved_at_40[0x18]; 11173 u8 geneve_option_fte_index[0x8]; 11174 11175 u8 option_class[0x10]; 11176 u8 option_type[0x8]; 11177 u8 reserved_at_78[0x3]; 11178 u8 option_data_length[0x5]; 11179 11180 u8 reserved_at_80[0x180]; 11181 }; 11182 11183 struct mlx5_ifc_create_umem_in_bits { 11184 u8 opcode[0x10]; 11185 u8 uid[0x10]; 11186 11187 u8 reserved_at_20[0x10]; 11188 u8 op_mod[0x10]; 11189 11190 u8 reserved_at_40[0x40]; 11191 11192 struct mlx5_ifc_umem_bits umem; 11193 }; 11194 11195 struct mlx5_ifc_create_umem_out_bits { 11196 u8 status[0x8]; 11197 u8 reserved_at_8[0x18]; 11198 11199 u8 syndrome[0x20]; 11200 11201 u8 reserved_at_40[0x8]; 11202 u8 umem_id[0x18]; 11203 11204 u8 reserved_at_60[0x20]; 11205 }; 11206 11207 struct mlx5_ifc_destroy_umem_in_bits { 11208 u8 opcode[0x10]; 11209 u8 uid[0x10]; 11210 11211 u8 reserved_at_20[0x10]; 11212 u8 op_mod[0x10]; 11213 11214 u8 reserved_at_40[0x8]; 11215 u8 umem_id[0x18]; 11216 11217 u8 reserved_at_60[0x20]; 11218 }; 11219 11220 struct mlx5_ifc_destroy_umem_out_bits { 11221 u8 status[0x8]; 11222 u8 reserved_at_8[0x18]; 11223 11224 u8 syndrome[0x20]; 11225 11226 u8 reserved_at_40[0x40]; 11227 }; 11228 11229 struct mlx5_ifc_create_uctx_in_bits { 11230 u8 opcode[0x10]; 11231 u8 reserved_at_10[0x10]; 11232 11233 u8 reserved_at_20[0x10]; 11234 u8 op_mod[0x10]; 11235 11236 u8 reserved_at_40[0x40]; 11237 11238 struct mlx5_ifc_uctx_bits uctx; 11239 }; 11240 11241 struct mlx5_ifc_create_uctx_out_bits { 11242 u8 status[0x8]; 11243 u8 reserved_at_8[0x18]; 11244 11245 u8 syndrome[0x20]; 11246 11247 u8 reserved_at_40[0x10]; 11248 u8 uid[0x10]; 11249 11250 u8 reserved_at_60[0x20]; 11251 }; 11252 11253 struct mlx5_ifc_destroy_uctx_in_bits { 11254 u8 opcode[0x10]; 11255 u8 reserved_at_10[0x10]; 11256 11257 u8 reserved_at_20[0x10]; 11258 u8 op_mod[0x10]; 11259 11260 u8 reserved_at_40[0x10]; 11261 u8 uid[0x10]; 11262 11263 u8 reserved_at_60[0x20]; 11264 }; 11265 11266 struct mlx5_ifc_destroy_uctx_out_bits { 11267 u8 status[0x8]; 11268 u8 reserved_at_8[0x18]; 11269 11270 u8 syndrome[0x20]; 11271 11272 u8 reserved_at_40[0x40]; 11273 }; 11274 11275 struct mlx5_ifc_create_sw_icm_in_bits { 11276 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11277 struct mlx5_ifc_sw_icm_bits sw_icm; 11278 }; 11279 11280 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11281 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11282 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11283 }; 11284 11285 struct mlx5_ifc_mtrc_string_db_param_bits { 11286 u8 string_db_base_address[0x20]; 11287 11288 u8 reserved_at_20[0x8]; 11289 u8 string_db_size[0x18]; 11290 }; 11291 11292 struct mlx5_ifc_mtrc_cap_bits { 11293 u8 trace_owner[0x1]; 11294 u8 trace_to_memory[0x1]; 11295 u8 reserved_at_2[0x4]; 11296 u8 trc_ver[0x2]; 11297 u8 reserved_at_8[0x14]; 11298 u8 num_string_db[0x4]; 11299 11300 u8 first_string_trace[0x8]; 11301 u8 num_string_trace[0x8]; 11302 u8 reserved_at_30[0x28]; 11303 11304 u8 log_max_trace_buffer_size[0x8]; 11305 11306 u8 reserved_at_60[0x20]; 11307 11308 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11309 11310 u8 reserved_at_280[0x180]; 11311 }; 11312 11313 struct mlx5_ifc_mtrc_conf_bits { 11314 u8 reserved_at_0[0x1c]; 11315 u8 trace_mode[0x4]; 11316 u8 reserved_at_20[0x18]; 11317 u8 log_trace_buffer_size[0x8]; 11318 u8 trace_mkey[0x20]; 11319 u8 reserved_at_60[0x3a0]; 11320 }; 11321 11322 struct mlx5_ifc_mtrc_stdb_bits { 11323 u8 string_db_index[0x4]; 11324 u8 reserved_at_4[0x4]; 11325 u8 read_size[0x18]; 11326 u8 start_offset[0x20]; 11327 u8 string_db_data[]; 11328 }; 11329 11330 struct mlx5_ifc_mtrc_ctrl_bits { 11331 u8 trace_status[0x2]; 11332 u8 reserved_at_2[0x2]; 11333 u8 arm_event[0x1]; 11334 u8 reserved_at_5[0xb]; 11335 u8 modify_field_select[0x10]; 11336 u8 reserved_at_20[0x2b]; 11337 u8 current_timestamp52_32[0x15]; 11338 u8 current_timestamp31_0[0x20]; 11339 u8 reserved_at_80[0x180]; 11340 }; 11341 11342 struct mlx5_ifc_host_params_context_bits { 11343 u8 host_number[0x8]; 11344 u8 reserved_at_8[0x7]; 11345 u8 host_pf_disabled[0x1]; 11346 u8 host_num_of_vfs[0x10]; 11347 11348 u8 host_total_vfs[0x10]; 11349 u8 host_pci_bus[0x10]; 11350 11351 u8 reserved_at_40[0x10]; 11352 u8 host_pci_device[0x10]; 11353 11354 u8 reserved_at_60[0x10]; 11355 u8 host_pci_function[0x10]; 11356 11357 u8 reserved_at_80[0x180]; 11358 }; 11359 11360 struct mlx5_ifc_query_esw_functions_in_bits { 11361 u8 opcode[0x10]; 11362 u8 reserved_at_10[0x10]; 11363 11364 u8 reserved_at_20[0x10]; 11365 u8 op_mod[0x10]; 11366 11367 u8 reserved_at_40[0x40]; 11368 }; 11369 11370 struct mlx5_ifc_query_esw_functions_out_bits { 11371 u8 status[0x8]; 11372 u8 reserved_at_8[0x18]; 11373 11374 u8 syndrome[0x20]; 11375 11376 u8 reserved_at_40[0x40]; 11377 11378 struct mlx5_ifc_host_params_context_bits host_params_context; 11379 11380 u8 reserved_at_280[0x180]; 11381 u8 host_sf_enable[][0x40]; 11382 }; 11383 11384 struct mlx5_ifc_sf_partition_bits { 11385 u8 reserved_at_0[0x10]; 11386 u8 log_num_sf[0x8]; 11387 u8 log_sf_bar_size[0x8]; 11388 }; 11389 11390 struct mlx5_ifc_query_sf_partitions_out_bits { 11391 u8 status[0x8]; 11392 u8 reserved_at_8[0x18]; 11393 11394 u8 syndrome[0x20]; 11395 11396 u8 reserved_at_40[0x18]; 11397 u8 num_sf_partitions[0x8]; 11398 11399 u8 reserved_at_60[0x20]; 11400 11401 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11402 }; 11403 11404 struct mlx5_ifc_query_sf_partitions_in_bits { 11405 u8 opcode[0x10]; 11406 u8 reserved_at_10[0x10]; 11407 11408 u8 reserved_at_20[0x10]; 11409 u8 op_mod[0x10]; 11410 11411 u8 reserved_at_40[0x40]; 11412 }; 11413 11414 struct mlx5_ifc_dealloc_sf_out_bits { 11415 u8 status[0x8]; 11416 u8 reserved_at_8[0x18]; 11417 11418 u8 syndrome[0x20]; 11419 11420 u8 reserved_at_40[0x40]; 11421 }; 11422 11423 struct mlx5_ifc_dealloc_sf_in_bits { 11424 u8 opcode[0x10]; 11425 u8 reserved_at_10[0x10]; 11426 11427 u8 reserved_at_20[0x10]; 11428 u8 op_mod[0x10]; 11429 11430 u8 reserved_at_40[0x10]; 11431 u8 function_id[0x10]; 11432 11433 u8 reserved_at_60[0x20]; 11434 }; 11435 11436 struct mlx5_ifc_alloc_sf_out_bits { 11437 u8 status[0x8]; 11438 u8 reserved_at_8[0x18]; 11439 11440 u8 syndrome[0x20]; 11441 11442 u8 reserved_at_40[0x40]; 11443 }; 11444 11445 struct mlx5_ifc_alloc_sf_in_bits { 11446 u8 opcode[0x10]; 11447 u8 reserved_at_10[0x10]; 11448 11449 u8 reserved_at_20[0x10]; 11450 u8 op_mod[0x10]; 11451 11452 u8 reserved_at_40[0x10]; 11453 u8 function_id[0x10]; 11454 11455 u8 reserved_at_60[0x20]; 11456 }; 11457 11458 struct mlx5_ifc_affiliated_event_header_bits { 11459 u8 reserved_at_0[0x10]; 11460 u8 obj_type[0x10]; 11461 11462 u8 obj_id[0x20]; 11463 }; 11464 11465 enum { 11466 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11467 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11468 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11469 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11470 }; 11471 11472 enum { 11473 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11474 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11475 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11476 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11477 }; 11478 11479 enum { 11480 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11481 }; 11482 11483 struct mlx5_ifc_ipsec_obj_bits { 11484 u8 modify_field_select[0x40]; 11485 u8 full_offload[0x1]; 11486 u8 reserved_at_41[0x1]; 11487 u8 esn_en[0x1]; 11488 u8 esn_overlap[0x1]; 11489 u8 reserved_at_44[0x2]; 11490 u8 icv_length[0x2]; 11491 u8 reserved_at_48[0x4]; 11492 u8 aso_return_reg[0x4]; 11493 u8 reserved_at_50[0x10]; 11494 11495 u8 esn_msb[0x20]; 11496 11497 u8 reserved_at_80[0x8]; 11498 u8 dekn[0x18]; 11499 11500 u8 salt[0x20]; 11501 11502 u8 implicit_iv[0x40]; 11503 11504 u8 reserved_at_100[0x700]; 11505 }; 11506 11507 struct mlx5_ifc_create_ipsec_obj_in_bits { 11508 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11509 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11510 }; 11511 11512 enum { 11513 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11514 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11515 }; 11516 11517 struct mlx5_ifc_query_ipsec_obj_out_bits { 11518 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11519 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11520 }; 11521 11522 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11523 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11524 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11525 }; 11526 11527 struct mlx5_ifc_encryption_key_obj_bits { 11528 u8 modify_field_select[0x40]; 11529 11530 u8 reserved_at_40[0x14]; 11531 u8 key_size[0x4]; 11532 u8 reserved_at_58[0x4]; 11533 u8 key_type[0x4]; 11534 11535 u8 reserved_at_60[0x8]; 11536 u8 pd[0x18]; 11537 11538 u8 reserved_at_80[0x180]; 11539 u8 key[8][0x20]; 11540 11541 u8 reserved_at_300[0x500]; 11542 }; 11543 11544 struct mlx5_ifc_create_encryption_key_in_bits { 11545 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11546 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11547 }; 11548 11549 enum { 11550 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11551 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11552 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11553 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11554 }; 11555 11556 struct mlx5_ifc_flow_meter_parameters_bits { 11557 u8 valid[0x1]; 11558 u8 bucket_overflow[0x1]; 11559 u8 start_color[0x2]; 11560 u8 both_buckets_on_green[0x1]; 11561 u8 reserved_at_5[0x1]; 11562 u8 meter_mode[0x2]; 11563 u8 reserved_at_8[0x18]; 11564 11565 u8 reserved_at_20[0x20]; 11566 11567 u8 reserved_at_40[0x3]; 11568 u8 cbs_exponent[0x5]; 11569 u8 cbs_mantissa[0x8]; 11570 u8 reserved_at_50[0x3]; 11571 u8 cir_exponent[0x5]; 11572 u8 cir_mantissa[0x8]; 11573 11574 u8 reserved_at_60[0x20]; 11575 11576 u8 reserved_at_80[0x3]; 11577 u8 ebs_exponent[0x5]; 11578 u8 ebs_mantissa[0x8]; 11579 u8 reserved_at_90[0x3]; 11580 u8 eir_exponent[0x5]; 11581 u8 eir_mantissa[0x8]; 11582 11583 u8 reserved_at_a0[0x60]; 11584 }; 11585 11586 struct mlx5_ifc_flow_meter_aso_obj_bits { 11587 u8 modify_field_select[0x40]; 11588 11589 u8 reserved_at_40[0x40]; 11590 11591 u8 reserved_at_80[0x8]; 11592 u8 meter_aso_access_pd[0x18]; 11593 11594 u8 reserved_at_a0[0x160]; 11595 11596 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11597 }; 11598 11599 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11600 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11601 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11602 }; 11603 11604 struct mlx5_ifc_sampler_obj_bits { 11605 u8 modify_field_select[0x40]; 11606 11607 u8 table_type[0x8]; 11608 u8 level[0x8]; 11609 u8 reserved_at_50[0xf]; 11610 u8 ignore_flow_level[0x1]; 11611 11612 u8 sample_ratio[0x20]; 11613 11614 u8 reserved_at_80[0x8]; 11615 u8 sample_table_id[0x18]; 11616 11617 u8 reserved_at_a0[0x8]; 11618 u8 default_table_id[0x18]; 11619 11620 u8 sw_steering_icm_address_rx[0x40]; 11621 u8 sw_steering_icm_address_tx[0x40]; 11622 11623 u8 reserved_at_140[0xa0]; 11624 }; 11625 11626 struct mlx5_ifc_create_sampler_obj_in_bits { 11627 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11628 struct mlx5_ifc_sampler_obj_bits sampler_object; 11629 }; 11630 11631 struct mlx5_ifc_query_sampler_obj_out_bits { 11632 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11633 struct mlx5_ifc_sampler_obj_bits sampler_object; 11634 }; 11635 11636 enum { 11637 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11638 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11639 }; 11640 11641 enum { 11642 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11643 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11644 }; 11645 11646 struct mlx5_ifc_tls_static_params_bits { 11647 u8 const_2[0x2]; 11648 u8 tls_version[0x4]; 11649 u8 const_1[0x2]; 11650 u8 reserved_at_8[0x14]; 11651 u8 encryption_standard[0x4]; 11652 11653 u8 reserved_at_20[0x20]; 11654 11655 u8 initial_record_number[0x40]; 11656 11657 u8 resync_tcp_sn[0x20]; 11658 11659 u8 gcm_iv[0x20]; 11660 11661 u8 implicit_iv[0x40]; 11662 11663 u8 reserved_at_100[0x8]; 11664 u8 dek_index[0x18]; 11665 11666 u8 reserved_at_120[0xe0]; 11667 }; 11668 11669 struct mlx5_ifc_tls_progress_params_bits { 11670 u8 next_record_tcp_sn[0x20]; 11671 11672 u8 hw_resync_tcp_sn[0x20]; 11673 11674 u8 record_tracker_state[0x2]; 11675 u8 auth_state[0x2]; 11676 u8 reserved_at_44[0x4]; 11677 u8 hw_offset_record_number[0x18]; 11678 }; 11679 11680 enum { 11681 MLX5_MTT_PERM_READ = 1 << 0, 11682 MLX5_MTT_PERM_WRITE = 1 << 1, 11683 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11684 }; 11685 11686 enum { 11687 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11688 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11689 }; 11690 11691 struct mlx5_ifc_suspend_vhca_in_bits { 11692 u8 opcode[0x10]; 11693 u8 uid[0x10]; 11694 11695 u8 reserved_at_20[0x10]; 11696 u8 op_mod[0x10]; 11697 11698 u8 reserved_at_40[0x10]; 11699 u8 vhca_id[0x10]; 11700 11701 u8 reserved_at_60[0x20]; 11702 }; 11703 11704 struct mlx5_ifc_suspend_vhca_out_bits { 11705 u8 status[0x8]; 11706 u8 reserved_at_8[0x18]; 11707 11708 u8 syndrome[0x20]; 11709 11710 u8 reserved_at_40[0x40]; 11711 }; 11712 11713 enum { 11714 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11715 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11716 }; 11717 11718 struct mlx5_ifc_resume_vhca_in_bits { 11719 u8 opcode[0x10]; 11720 u8 uid[0x10]; 11721 11722 u8 reserved_at_20[0x10]; 11723 u8 op_mod[0x10]; 11724 11725 u8 reserved_at_40[0x10]; 11726 u8 vhca_id[0x10]; 11727 11728 u8 reserved_at_60[0x20]; 11729 }; 11730 11731 struct mlx5_ifc_resume_vhca_out_bits { 11732 u8 status[0x8]; 11733 u8 reserved_at_8[0x18]; 11734 11735 u8 syndrome[0x20]; 11736 11737 u8 reserved_at_40[0x40]; 11738 }; 11739 11740 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11741 u8 opcode[0x10]; 11742 u8 uid[0x10]; 11743 11744 u8 reserved_at_20[0x10]; 11745 u8 op_mod[0x10]; 11746 11747 u8 reserved_at_40[0x10]; 11748 u8 vhca_id[0x10]; 11749 11750 u8 reserved_at_60[0x20]; 11751 }; 11752 11753 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11754 u8 status[0x8]; 11755 u8 reserved_at_8[0x18]; 11756 11757 u8 syndrome[0x20]; 11758 11759 u8 reserved_at_40[0x40]; 11760 11761 u8 required_umem_size[0x20]; 11762 11763 u8 reserved_at_a0[0x160]; 11764 }; 11765 11766 struct mlx5_ifc_save_vhca_state_in_bits { 11767 u8 opcode[0x10]; 11768 u8 uid[0x10]; 11769 11770 u8 reserved_at_20[0x10]; 11771 u8 op_mod[0x10]; 11772 11773 u8 reserved_at_40[0x10]; 11774 u8 vhca_id[0x10]; 11775 11776 u8 reserved_at_60[0x20]; 11777 11778 u8 va[0x40]; 11779 11780 u8 mkey[0x20]; 11781 11782 u8 size[0x20]; 11783 }; 11784 11785 struct mlx5_ifc_save_vhca_state_out_bits { 11786 u8 status[0x8]; 11787 u8 reserved_at_8[0x18]; 11788 11789 u8 syndrome[0x20]; 11790 11791 u8 actual_image_size[0x20]; 11792 11793 u8 reserved_at_60[0x20]; 11794 }; 11795 11796 struct mlx5_ifc_load_vhca_state_in_bits { 11797 u8 opcode[0x10]; 11798 u8 uid[0x10]; 11799 11800 u8 reserved_at_20[0x10]; 11801 u8 op_mod[0x10]; 11802 11803 u8 reserved_at_40[0x10]; 11804 u8 vhca_id[0x10]; 11805 11806 u8 reserved_at_60[0x20]; 11807 11808 u8 va[0x40]; 11809 11810 u8 mkey[0x20]; 11811 11812 u8 size[0x20]; 11813 }; 11814 11815 struct mlx5_ifc_load_vhca_state_out_bits { 11816 u8 status[0x8]; 11817 u8 reserved_at_8[0x18]; 11818 11819 u8 syndrome[0x20]; 11820 11821 u8 reserved_at_40[0x40]; 11822 }; 11823 11824 struct mlx5_ifc_adv_virtualization_cap_bits { 11825 u8 reserved_at_0[0x3]; 11826 u8 pg_track_log_max_num[0x5]; 11827 u8 pg_track_max_num_range[0x8]; 11828 u8 pg_track_log_min_addr_space[0x8]; 11829 u8 pg_track_log_max_addr_space[0x8]; 11830 11831 u8 reserved_at_20[0x3]; 11832 u8 pg_track_log_min_msg_size[0x5]; 11833 u8 reserved_at_28[0x3]; 11834 u8 pg_track_log_max_msg_size[0x5]; 11835 u8 reserved_at_30[0x3]; 11836 u8 pg_track_log_min_page_size[0x5]; 11837 u8 reserved_at_38[0x3]; 11838 u8 pg_track_log_max_page_size[0x5]; 11839 11840 u8 reserved_at_40[0x7c0]; 11841 }; 11842 11843 struct mlx5_ifc_page_track_report_entry_bits { 11844 u8 dirty_address_high[0x20]; 11845 11846 u8 dirty_address_low[0x20]; 11847 }; 11848 11849 enum { 11850 MLX5_PAGE_TRACK_STATE_TRACKING, 11851 MLX5_PAGE_TRACK_STATE_REPORTING, 11852 MLX5_PAGE_TRACK_STATE_ERROR, 11853 }; 11854 11855 struct mlx5_ifc_page_track_range_bits { 11856 u8 start_address[0x40]; 11857 11858 u8 length[0x40]; 11859 }; 11860 11861 struct mlx5_ifc_page_track_bits { 11862 u8 modify_field_select[0x40]; 11863 11864 u8 reserved_at_40[0x10]; 11865 u8 vhca_id[0x10]; 11866 11867 u8 reserved_at_60[0x20]; 11868 11869 u8 state[0x4]; 11870 u8 track_type[0x4]; 11871 u8 log_addr_space_size[0x8]; 11872 u8 reserved_at_90[0x3]; 11873 u8 log_page_size[0x5]; 11874 u8 reserved_at_98[0x3]; 11875 u8 log_msg_size[0x5]; 11876 11877 u8 reserved_at_a0[0x8]; 11878 u8 reporting_qpn[0x18]; 11879 11880 u8 reserved_at_c0[0x18]; 11881 u8 num_ranges[0x8]; 11882 11883 u8 reserved_at_e0[0x20]; 11884 11885 u8 range_start_address[0x40]; 11886 11887 u8 length[0x40]; 11888 11889 struct mlx5_ifc_page_track_range_bits track_range[0]; 11890 }; 11891 11892 struct mlx5_ifc_create_page_track_obj_in_bits { 11893 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11894 struct mlx5_ifc_page_track_bits obj_context; 11895 }; 11896 11897 struct mlx5_ifc_modify_page_track_obj_in_bits { 11898 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11899 struct mlx5_ifc_page_track_bits obj_context; 11900 }; 11901 11902 #endif /* MLX5_IFC_H */ 11903