1*ac7ea1c7SPatrisious Haddad /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2*ac7ea1c7SPatrisious Haddad /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */ 3*ac7ea1c7SPatrisious Haddad 4*ac7ea1c7SPatrisious Haddad #ifndef MLX5_MACSEC_H 5*ac7ea1c7SPatrisious Haddad #define MLX5_MACSEC_H 6*ac7ea1c7SPatrisious Haddad 7*ac7ea1c7SPatrisious Haddad #ifdef CONFIG_MLX5_MACSEC 8*ac7ea1c7SPatrisious Haddad struct mlx5_macsec_event_data { 9*ac7ea1c7SPatrisious Haddad struct mlx5_macsec_fs *macsec_fs; 10*ac7ea1c7SPatrisious Haddad void *macdev; 11*ac7ea1c7SPatrisious Haddad u32 fs_id; 12*ac7ea1c7SPatrisious Haddad bool is_tx; 13*ac7ea1c7SPatrisious Haddad }; 14*ac7ea1c7SPatrisious Haddad 15*ac7ea1c7SPatrisious Haddad int mlx5_macsec_add_roce_rule(void *macdev, const struct sockaddr *addr, u16 gid_idx, 16*ac7ea1c7SPatrisious Haddad struct list_head *tx_rules_list, struct list_head *rx_rules_list, 17*ac7ea1c7SPatrisious Haddad struct mlx5_macsec_fs *macsec_fs); 18*ac7ea1c7SPatrisious Haddad 19*ac7ea1c7SPatrisious Haddad void mlx5_macsec_del_roce_rule(u16 gid_idx, struct mlx5_macsec_fs *macsec_fs, 20*ac7ea1c7SPatrisious Haddad struct list_head *tx_rules_list, struct list_head *rx_rules_list); 21*ac7ea1c7SPatrisious Haddad 22*ac7ea1c7SPatrisious Haddad void mlx5_macsec_add_roce_sa_rules(u32 fs_id, const struct sockaddr *addr, u16 gid_idx, 23*ac7ea1c7SPatrisious Haddad struct list_head *tx_rules_list, 24*ac7ea1c7SPatrisious Haddad struct list_head *rx_rules_list, 25*ac7ea1c7SPatrisious Haddad struct mlx5_macsec_fs *macsec_fs, bool is_tx); 26*ac7ea1c7SPatrisious Haddad 27*ac7ea1c7SPatrisious Haddad void mlx5_macsec_del_roce_sa_rules(u32 fs_id, struct mlx5_macsec_fs *macsec_fs, 28*ac7ea1c7SPatrisious Haddad struct list_head *tx_rules_list, 29*ac7ea1c7SPatrisious Haddad struct list_head *rx_rules_list, bool is_tx); 30*ac7ea1c7SPatrisious Haddad 31*ac7ea1c7SPatrisious Haddad #endif 32*ac7ea1c7SPatrisious Haddad #endif /* MLX5_MACSEC_H */ 33