xref: /linux-6.15/include/linux/mlx5/driver.h (revision ffbd0c8c) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53 
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <linux/ptp_clock_kernel.h>
59 #include <net/devlink.h>
60 
61 #define MLX5_ADEV_NAME "mlx5_core"
62 
63 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
64 
65 enum {
66 	MLX5_BOARD_ID_LEN = 64,
67 };
68 
69 enum {
70 	MLX5_CMD_WQ_MAX_NAME	= 32,
71 };
72 
73 enum {
74 	CMD_OWNER_SW		= 0x0,
75 	CMD_OWNER_HW		= 0x1,
76 	CMD_STATUS_SUCCESS	= 0,
77 };
78 
79 enum mlx5_sqp_t {
80 	MLX5_SQP_SMI		= 0,
81 	MLX5_SQP_GSI		= 1,
82 	MLX5_SQP_IEEE_1588	= 2,
83 	MLX5_SQP_SNIFFER	= 3,
84 	MLX5_SQP_SYNC_UMR	= 4,
85 };
86 
87 enum {
88 	MLX5_MAX_PORTS	= 4,
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFFSET = 16,
93 	MLX5_ATOMIC_MODE_IB_COMP = 1,
94 	MLX5_ATOMIC_MODE_CX = 2,
95 	MLX5_ATOMIC_MODE_8B = 3,
96 	MLX5_ATOMIC_MODE_16B = 4,
97 	MLX5_ATOMIC_MODE_32B = 5,
98 	MLX5_ATOMIC_MODE_64B = 6,
99 	MLX5_ATOMIC_MODE_128B = 7,
100 	MLX5_ATOMIC_MODE_256B = 8,
101 };
102 
103 enum {
104 	MLX5_REG_SBPR            = 0xb001,
105 	MLX5_REG_SBCM            = 0xb002,
106 	MLX5_REG_QPTS            = 0x4002,
107 	MLX5_REG_QETCR		 = 0x4005,
108 	MLX5_REG_QTCT		 = 0x400a,
109 	MLX5_REG_QPDPM           = 0x4013,
110 	MLX5_REG_QCAM            = 0x4019,
111 	MLX5_REG_DCBX_PARAM      = 0x4020,
112 	MLX5_REG_DCBX_APP        = 0x4021,
113 	MLX5_REG_FPGA_CAP	 = 0x4022,
114 	MLX5_REG_FPGA_CTRL	 = 0x4023,
115 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 	MLX5_REG_CORE_DUMP	 = 0x402e,
117 	MLX5_REG_PCAP		 = 0x5001,
118 	MLX5_REG_PMTU		 = 0x5003,
119 	MLX5_REG_PTYS		 = 0x5004,
120 	MLX5_REG_PAOS		 = 0x5006,
121 	MLX5_REG_PFCC            = 0x5007,
122 	MLX5_REG_PPCNT		 = 0x5008,
123 	MLX5_REG_PPTB            = 0x500b,
124 	MLX5_REG_PBMC            = 0x500c,
125 	MLX5_REG_PMAOS		 = 0x5012,
126 	MLX5_REG_PUDE		 = 0x5009,
127 	MLX5_REG_PMPE		 = 0x5010,
128 	MLX5_REG_PELC		 = 0x500e,
129 	MLX5_REG_PVLC		 = 0x500f,
130 	MLX5_REG_PCMR		 = 0x5041,
131 	MLX5_REG_PDDR		 = 0x5031,
132 	MLX5_REG_PMLP		 = 0x5002,
133 	MLX5_REG_PPLM		 = 0x5023,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MTCAP		 = 0x9009,
138 	MLX5_REG_MTMP		 = 0x900A,
139 	MLX5_REG_MCIA		 = 0x9014,
140 	MLX5_REG_MFRL		 = 0x9028,
141 	MLX5_REG_MLCR		 = 0x902b,
142 	MLX5_REG_MRTC		 = 0x902d,
143 	MLX5_REG_MTRC_CAP	 = 0x9040,
144 	MLX5_REG_MTRC_CONF	 = 0x9041,
145 	MLX5_REG_MTRC_STDB	 = 0x9042,
146 	MLX5_REG_MTRC_CTRL	 = 0x9043,
147 	MLX5_REG_MPEIN		 = 0x9050,
148 	MLX5_REG_MPCNT		 = 0x9051,
149 	MLX5_REG_MTPPS		 = 0x9053,
150 	MLX5_REG_MTPPSE		 = 0x9054,
151 	MLX5_REG_MTUTC		 = 0x9055,
152 	MLX5_REG_MPEGC		 = 0x9056,
153 	MLX5_REG_MCQS		 = 0x9060,
154 	MLX5_REG_MCQI		 = 0x9061,
155 	MLX5_REG_MCC		 = 0x9062,
156 	MLX5_REG_MCDA		 = 0x9063,
157 	MLX5_REG_MCAM		 = 0x907f,
158 	MLX5_REG_MIRC		 = 0x9162,
159 	MLX5_REG_SBCAM		 = 0xB01F,
160 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
161 	MLX5_REG_DTOR            = 0xC00E,
162 };
163 
164 enum mlx5_qpts_trust_state {
165 	MLX5_QPTS_TRUST_PCP  = 1,
166 	MLX5_QPTS_TRUST_DSCP = 2,
167 };
168 
169 enum mlx5_dcbx_oper_mode {
170 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
171 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
172 };
173 
174 enum {
175 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
176 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
177 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
178 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
179 };
180 
181 enum mlx5_page_fault_resume_flags {
182 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
183 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
184 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
185 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
186 };
187 
188 enum dbg_rsc_type {
189 	MLX5_DBG_RSC_QP,
190 	MLX5_DBG_RSC_EQ,
191 	MLX5_DBG_RSC_CQ,
192 };
193 
194 enum port_state_policy {
195 	MLX5_POLICY_DOWN	= 0,
196 	MLX5_POLICY_UP		= 1,
197 	MLX5_POLICY_FOLLOW	= 2,
198 	MLX5_POLICY_INVALID	= 0xffffffff
199 };
200 
201 enum mlx5_coredev_type {
202 	MLX5_COREDEV_PF,
203 	MLX5_COREDEV_VF,
204 	MLX5_COREDEV_SF,
205 };
206 
207 struct mlx5_field_desc {
208 	int			i;
209 };
210 
211 struct mlx5_rsc_debug {
212 	struct mlx5_core_dev   *dev;
213 	void		       *object;
214 	enum dbg_rsc_type	type;
215 	struct dentry	       *root;
216 	struct mlx5_field_desc	fields[];
217 };
218 
219 enum mlx5_dev_event {
220 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
221 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
222 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
223 };
224 
225 enum mlx5_port_status {
226 	MLX5_PORT_UP        = 1,
227 	MLX5_PORT_DOWN      = 2,
228 };
229 
230 enum mlx5_cmdif_state {
231 	MLX5_CMDIF_STATE_UNINITIALIZED,
232 	MLX5_CMDIF_STATE_UP,
233 	MLX5_CMDIF_STATE_DOWN,
234 };
235 
236 struct mlx5_cmd_first {
237 	__be32		data[4];
238 };
239 
240 struct mlx5_cmd_msg {
241 	struct list_head		list;
242 	struct cmd_msg_cache	       *parent;
243 	u32				len;
244 	struct mlx5_cmd_first		first;
245 	struct mlx5_cmd_mailbox	       *next;
246 };
247 
248 struct mlx5_cmd_debug {
249 	struct dentry	       *dbg_root;
250 	void		       *in_msg;
251 	void		       *out_msg;
252 	u8			status;
253 	u16			inlen;
254 	u16			outlen;
255 };
256 
257 struct cmd_msg_cache {
258 	/* protect block chain allocations
259 	 */
260 	spinlock_t		lock;
261 	struct list_head	head;
262 	unsigned int		max_inbox_size;
263 	unsigned int		num_ent;
264 };
265 
266 enum {
267 	MLX5_NUM_COMMAND_CACHES = 5,
268 };
269 
270 struct mlx5_cmd_stats {
271 	u64		sum;
272 	u64		n;
273 	/* number of times command failed */
274 	u64		failed;
275 	/* number of times command failed on bad status returned by FW */
276 	u64		failed_mbox_status;
277 	/* last command failed returned errno */
278 	u32		last_failed_errno;
279 	/* last bad status returned by FW */
280 	u8		last_failed_mbox_status;
281 	/* last command failed syndrome returned by FW */
282 	u32		last_failed_syndrome;
283 	struct dentry  *root;
284 	/* protect command average calculations */
285 	spinlock_t	lock;
286 };
287 
288 struct mlx5_cmd {
289 	struct mlx5_nb    nb;
290 
291 	/* members which needs to be queried or reinitialized each reload */
292 	struct {
293 		u16		cmdif_rev;
294 		u8		log_sz;
295 		u8		log_stride;
296 		int		max_reg_cmds;
297 		unsigned long	bitmask;
298 		struct semaphore sem;
299 		struct semaphore pages_sem;
300 		struct semaphore throttle_sem;
301 	} vars;
302 	enum mlx5_cmdif_state	state;
303 	void	       *cmd_alloc_buf;
304 	dma_addr_t	alloc_dma;
305 	int		alloc_size;
306 	void	       *cmd_buf;
307 	dma_addr_t	dma;
308 
309 	/* protect command queue allocations
310 	 */
311 	spinlock_t	alloc_lock;
312 
313 	/* protect token allocations
314 	 */
315 	spinlock_t	token_lock;
316 	u8		token;
317 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
318 	struct workqueue_struct *wq;
319 	int	mode;
320 	u16     allowed_opcode;
321 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
322 	struct dma_pool *pool;
323 	struct mlx5_cmd_debug dbg;
324 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
325 	int checksum_disabled;
326 	struct xarray stats;
327 };
328 
329 struct mlx5_cmd_mailbox {
330 	void	       *buf;
331 	dma_addr_t	dma;
332 	struct mlx5_cmd_mailbox *next;
333 };
334 
335 struct mlx5_buf_list {
336 	void		       *buf;
337 	dma_addr_t		map;
338 };
339 
340 struct mlx5_frag_buf {
341 	struct mlx5_buf_list	*frags;
342 	int			npages;
343 	int			size;
344 	u8			page_shift;
345 };
346 
347 struct mlx5_frag_buf_ctrl {
348 	struct mlx5_buf_list   *frags;
349 	u32			sz_m1;
350 	u16			frag_sz_m1;
351 	u16			strides_offset;
352 	u8			log_sz;
353 	u8			log_stride;
354 	u8			log_frag_strides;
355 };
356 
357 struct mlx5_core_psv {
358 	u32	psv_idx;
359 	struct psv_layout {
360 		u32	pd;
361 		u16	syndrome;
362 		u16	reserved;
363 		u16	bg;
364 		u16	app_tag;
365 		u32	ref_tag;
366 	} psv;
367 };
368 
369 struct mlx5_core_sig_ctx {
370 	struct mlx5_core_psv	psv_memory;
371 	struct mlx5_core_psv	psv_wire;
372 	struct ib_sig_err       err_item;
373 	bool			sig_status_checked;
374 	bool			sig_err_exists;
375 	u32			sigerr_count;
376 };
377 
378 #define MLX5_24BIT_MASK		((1 << 24) - 1)
379 
380 enum mlx5_res_type {
381 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
382 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
383 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
384 	MLX5_RES_SRQ	= 3,
385 	MLX5_RES_XSRQ	= 4,
386 	MLX5_RES_XRQ	= 5,
387 };
388 
389 struct mlx5_core_rsc_common {
390 	enum mlx5_res_type	res;
391 	refcount_t		refcount;
392 	struct completion	free;
393 };
394 
395 struct mlx5_uars_page {
396 	void __iomem	       *map;
397 	bool			wc;
398 	u32			index;
399 	struct list_head	list;
400 	unsigned int		bfregs;
401 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
402 	unsigned long	       *fp_bitmap;
403 	unsigned int		reg_avail;
404 	unsigned int		fp_avail;
405 	struct kref		ref_count;
406 	struct mlx5_core_dev   *mdev;
407 };
408 
409 struct mlx5_bfreg_head {
410 	/* protect blue flame registers allocations */
411 	struct mutex		lock;
412 	struct list_head	list;
413 };
414 
415 struct mlx5_bfreg_data {
416 	struct mlx5_bfreg_head	reg_head;
417 	struct mlx5_bfreg_head	wc_head;
418 };
419 
420 struct mlx5_sq_bfreg {
421 	void __iomem	       *map;
422 	struct mlx5_uars_page  *up;
423 	bool			wc;
424 	u32			index;
425 	unsigned int		offset;
426 };
427 
428 struct mlx5_core_health {
429 	struct health_buffer __iomem   *health;
430 	__be32 __iomem		       *health_counter;
431 	struct timer_list		timer;
432 	u32				prev;
433 	int				miss_counter;
434 	u8				synd;
435 	u32				fatal_error;
436 	u32				crdump_size;
437 	struct workqueue_struct	       *wq;
438 	unsigned long			flags;
439 	struct work_struct		fatal_report_work;
440 	struct work_struct		report_work;
441 	struct devlink_health_reporter *fw_reporter;
442 	struct devlink_health_reporter *fw_fatal_reporter;
443 	struct devlink_health_reporter *vnic_reporter;
444 	struct delayed_work		update_fw_log_ts_work;
445 };
446 
447 enum {
448 	MLX5_PF_NOTIFY_DISABLE_VF,
449 	MLX5_PF_NOTIFY_ENABLE_VF,
450 };
451 
452 struct mlx5_vf_context {
453 	int	enabled;
454 	u64	port_guid;
455 	u64	node_guid;
456 	/* Valid bits are used to validate administrative guid only.
457 	 * Enabled after ndo_set_vf_guid
458 	 */
459 	u8	port_guid_valid:1;
460 	u8	node_guid_valid:1;
461 	enum port_state_policy	policy;
462 	struct blocking_notifier_head notifier;
463 };
464 
465 struct mlx5_core_sriov {
466 	struct mlx5_vf_context	*vfs_ctx;
467 	int			num_vfs;
468 	u16			max_vfs;
469 	u16			max_ec_vfs;
470 };
471 
472 struct mlx5_fc_pool {
473 	struct mlx5_core_dev *dev;
474 	struct mutex pool_lock; /* protects pool lists */
475 	struct list_head fully_used;
476 	struct list_head partially_used;
477 	struct list_head unused;
478 	int available_fcs;
479 	int used_fcs;
480 	int threshold;
481 };
482 
483 struct mlx5_fc_stats {
484 	spinlock_t counters_idr_lock; /* protects counters_idr */
485 	struct idr counters_idr;
486 	struct list_head counters;
487 	struct llist_head addlist;
488 	struct llist_head dellist;
489 
490 	struct workqueue_struct *wq;
491 	struct delayed_work work;
492 	unsigned long next_query;
493 	unsigned long sampling_interval; /* jiffies */
494 	u32 *bulk_query_out;
495 	int bulk_query_len;
496 	size_t num_counters;
497 	bool bulk_query_alloc_failed;
498 	unsigned long next_bulk_query_alloc;
499 	struct mlx5_fc_pool fc_pool;
500 };
501 
502 struct mlx5_events;
503 struct mlx5_mpfs;
504 struct mlx5_eswitch;
505 struct mlx5_lag;
506 struct mlx5_devcom_dev;
507 struct mlx5_fw_reset;
508 struct mlx5_eq_table;
509 struct mlx5_irq_table;
510 struct mlx5_vhca_state_notifier;
511 struct mlx5_sf_dev_table;
512 struct mlx5_sf_hw_table;
513 struct mlx5_sf_table;
514 struct mlx5_crypto_dek_priv;
515 
516 struct mlx5_rate_limit {
517 	u32			rate;
518 	u32			max_burst_sz;
519 	u16			typical_pkt_sz;
520 };
521 
522 struct mlx5_rl_entry {
523 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
524 	u64 refcount;
525 	u16 index;
526 	u16 uid;
527 	u8 dedicated : 1;
528 };
529 
530 struct mlx5_rl_table {
531 	/* protect rate limit table */
532 	struct mutex            rl_lock;
533 	u16                     max_size;
534 	u32                     max_rate;
535 	u32                     min_rate;
536 	struct mlx5_rl_entry   *rl_entry;
537 	u64 refcount;
538 };
539 
540 struct mlx5_core_roce {
541 	struct mlx5_flow_table *ft;
542 	struct mlx5_flow_group *fg;
543 	struct mlx5_flow_handle *allow_rule;
544 };
545 
546 enum {
547 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
548 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
549 	/* Set during device detach to block any further devices
550 	 * creation/deletion on drivers rescan. Unset during device attach.
551 	 */
552 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
553 };
554 
555 struct mlx5_adev {
556 	struct auxiliary_device adev;
557 	struct mlx5_core_dev *mdev;
558 	int idx;
559 };
560 
561 struct mlx5_debugfs_entries {
562 	struct dentry *dbg_root;
563 	struct dentry *qp_debugfs;
564 	struct dentry *eq_debugfs;
565 	struct dentry *cq_debugfs;
566 	struct dentry *cmdif_debugfs;
567 	struct dentry *pages_debugfs;
568 	struct dentry *lag_debugfs;
569 };
570 
571 enum mlx5_func_type {
572 	MLX5_PF,
573 	MLX5_VF,
574 	MLX5_SF,
575 	MLX5_HOST_PF,
576 	MLX5_EC_VF,
577 	MLX5_FUNC_TYPE_NUM,
578 };
579 
580 struct mlx5_ft_pool;
581 struct mlx5_priv {
582 	/* IRQ table valid only for real pci devices PF or VF */
583 	struct mlx5_irq_table   *irq_table;
584 	struct mlx5_eq_table	*eq_table;
585 
586 	/* pages stuff */
587 	struct mlx5_nb          pg_nb;
588 	struct workqueue_struct *pg_wq;
589 	struct xarray           page_root_xa;
590 	atomic_t		reg_pages;
591 	struct list_head	free_list;
592 	u32			fw_pages;
593 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
594 	u32			fw_pages_alloc_failed;
595 	u32			give_pages_dropped;
596 	u32			reclaim_pages_discard;
597 
598 	struct mlx5_core_health health;
599 	struct list_head	traps;
600 
601 	struct mlx5_debugfs_entries dbg;
602 
603 	/* start: alloc staff */
604 	/* protect buffer allocation according to numa node */
605 	struct mutex            alloc_mutex;
606 	int                     numa_node;
607 
608 	struct mutex            pgdir_mutex;
609 	struct list_head        pgdir_list;
610 	/* end: alloc staff */
611 
612 	struct mlx5_adev       **adev;
613 	int			adev_idx;
614 	int			sw_vhca_id;
615 	struct mlx5_events      *events;
616 
617 	struct mlx5_flow_steering *steering;
618 	struct mlx5_mpfs        *mpfs;
619 	struct mlx5_eswitch     *eswitch;
620 	struct mlx5_core_sriov	sriov;
621 	struct mlx5_lag		*lag;
622 	u32			flags;
623 	struct mlx5_devcom_dev	*devc;
624 	struct mlx5_fw_reset	*fw_reset;
625 	struct mlx5_core_roce	roce;
626 	struct mlx5_fc_stats		fc_stats;
627 	struct mlx5_rl_table            rl_table;
628 	struct mlx5_ft_pool		*ft_pool;
629 
630 	struct mlx5_bfreg_data		bfregs;
631 	struct mlx5_uars_page	       *uar;
632 #ifdef CONFIG_MLX5_SF
633 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
634 	struct mlx5_sf_dev_table *sf_dev_table;
635 	struct mlx5_core_dev *parent_mdev;
636 #endif
637 #ifdef CONFIG_MLX5_SF_MANAGER
638 	struct mlx5_sf_hw_table *sf_hw_table;
639 	struct mlx5_sf_table *sf_table;
640 #endif
641 };
642 
643 enum mlx5_device_state {
644 	MLX5_DEVICE_STATE_UP = 1,
645 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
646 };
647 
648 enum mlx5_interface_state {
649 	MLX5_INTERFACE_STATE_UP = BIT(0),
650 	MLX5_BREAK_FW_WAIT = BIT(1),
651 };
652 
653 enum mlx5_pci_status {
654 	MLX5_PCI_STATUS_DISABLED,
655 	MLX5_PCI_STATUS_ENABLED,
656 };
657 
658 enum mlx5_pagefault_type_flags {
659 	MLX5_PFAULT_REQUESTOR = 1 << 0,
660 	MLX5_PFAULT_WRITE     = 1 << 1,
661 	MLX5_PFAULT_RDMA      = 1 << 2,
662 };
663 
664 struct mlx5_td {
665 	/* protects tirs list changes while tirs refresh */
666 	struct mutex     list_lock;
667 	struct list_head tirs_list;
668 	u32              tdn;
669 };
670 
671 struct mlx5e_resources {
672 	struct mlx5e_hw_objs {
673 		u32                        pdn;
674 		struct mlx5_td             td;
675 		u32			   mkey;
676 		struct mlx5_sq_bfreg       bfreg;
677 	} hw_objs;
678 	struct net_device *uplink_netdev;
679 	struct mutex uplink_netdev_lock;
680 	struct mlx5_crypto_dek_priv *dek_priv;
681 };
682 
683 enum mlx5_sw_icm_type {
684 	MLX5_SW_ICM_TYPE_STEERING,
685 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
686 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
687 };
688 
689 #define MLX5_MAX_RESERVED_GIDS 8
690 
691 struct mlx5_rsvd_gids {
692 	unsigned int start;
693 	unsigned int count;
694 	struct ida ida;
695 };
696 
697 #define MAX_PIN_NUM	8
698 struct mlx5_pps {
699 	u8                         pin_caps[MAX_PIN_NUM];
700 	struct work_struct         out_work;
701 	u64                        start[MAX_PIN_NUM];
702 	u8                         enabled;
703 	u64                        min_npps_period;
704 	u64                        min_out_pulse_duration_ns;
705 };
706 
707 struct mlx5_timer {
708 	struct cyclecounter        cycles;
709 	struct timecounter         tc;
710 	u32                        nominal_c_mult;
711 	unsigned long              overflow_period;
712 	struct delayed_work        overflow_work;
713 };
714 
715 struct mlx5_clock {
716 	struct mlx5_nb             pps_nb;
717 	seqlock_t                  lock;
718 	struct hwtstamp_config     hwtstamp_config;
719 	struct ptp_clock          *ptp;
720 	struct ptp_clock_info      ptp_info;
721 	struct mlx5_pps            pps_info;
722 	struct mlx5_timer          timer;
723 };
724 
725 struct mlx5_dm;
726 struct mlx5_fw_tracer;
727 struct mlx5_vxlan;
728 struct mlx5_geneve;
729 struct mlx5_hv_vhca;
730 
731 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
732 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
733 
734 enum {
735 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
736 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
737 };
738 
739 enum {
740 	MKEY_CACHE_LAST_STD_ENTRY = 20,
741 	MLX5_IMR_KSM_CACHE_ENTRY,
742 	MAX_MKEY_CACHE_ENTRIES
743 };
744 
745 struct mlx5_profile {
746 	u64	mask;
747 	u8	log_max_qp;
748 	u8	num_cmd_caches;
749 	struct {
750 		int	size;
751 		int	limit;
752 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
753 };
754 
755 struct mlx5_hca_cap {
756 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
757 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
758 };
759 
760 struct mlx5_core_dev {
761 	struct device *device;
762 	enum mlx5_coredev_type coredev_type;
763 	struct pci_dev	       *pdev;
764 	/* sync pci state */
765 	struct mutex		pci_status_mutex;
766 	enum mlx5_pci_status	pci_status;
767 	u8			rev_id;
768 	char			board_id[MLX5_BOARD_ID_LEN];
769 	struct mlx5_cmd		cmd;
770 	struct {
771 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
772 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
773 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
774 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
775 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
776 		u8  embedded_cpu;
777 	} caps;
778 	struct mlx5_timeouts	*timeouts;
779 	u64			sys_image_guid;
780 	phys_addr_t		iseg_base;
781 	struct mlx5_init_seg __iomem *iseg;
782 	phys_addr_t             bar_addr;
783 	enum mlx5_device_state	state;
784 	/* sync interface state */
785 	struct mutex		intf_state_mutex;
786 	struct lock_class_key	lock_key;
787 	unsigned long		intf_state;
788 	struct mlx5_priv	priv;
789 	struct mlx5_profile	profile;
790 	u32			issi;
791 	struct mlx5e_resources  mlx5e_res;
792 	struct mlx5_dm          *dm;
793 	struct mlx5_vxlan       *vxlan;
794 	struct mlx5_geneve      *geneve;
795 	struct {
796 		struct mlx5_rsvd_gids	reserved_gids;
797 		u32			roce_en;
798 	} roce;
799 #ifdef CONFIG_MLX5_FPGA
800 	struct mlx5_fpga_device *fpga;
801 #endif
802 	struct mlx5_clock        clock;
803 	struct mlx5_ib_clock_info  *clock_info;
804 	struct mlx5_fw_tracer   *tracer;
805 	struct mlx5_rsc_dump    *rsc_dump;
806 	u32                      vsc_addr;
807 	struct mlx5_hv_vhca	*hv_vhca;
808 	struct mlx5_hwmon	*hwmon;
809 	u64			num_block_tc;
810 	u64			num_block_ipsec;
811 #ifdef CONFIG_MLX5_MACSEC
812 	struct mlx5_macsec_fs *macsec_fs;
813 	/* MACsec notifier chain to sync MACsec core and IB database */
814 	struct blocking_notifier_head macsec_nh;
815 #endif
816 };
817 
818 struct mlx5_db {
819 	__be32			*db;
820 	union {
821 		struct mlx5_db_pgdir		*pgdir;
822 		struct mlx5_ib_user_db_page	*user_page;
823 	}			u;
824 	dma_addr_t		dma;
825 	int			index;
826 };
827 
828 enum {
829 	MLX5_COMP_EQ_SIZE = 1024,
830 };
831 
832 enum {
833 	MLX5_PTYS_IB = 1 << 0,
834 	MLX5_PTYS_EN = 1 << 2,
835 };
836 
837 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
838 
839 enum {
840 	MLX5_CMD_ENT_STATE_PENDING_COMP,
841 };
842 
843 struct mlx5_cmd_work_ent {
844 	unsigned long		state;
845 	struct mlx5_cmd_msg    *in;
846 	struct mlx5_cmd_msg    *out;
847 	void		       *uout;
848 	int			uout_size;
849 	mlx5_cmd_cbk_t		callback;
850 	struct delayed_work	cb_timeout_work;
851 	void		       *context;
852 	int			idx;
853 	struct completion	handling;
854 	struct completion	done;
855 	struct mlx5_cmd        *cmd;
856 	struct work_struct	work;
857 	struct mlx5_cmd_layout *lay;
858 	int			ret;
859 	int			page_queue;
860 	u8			status;
861 	u8			token;
862 	u64			ts1;
863 	u64			ts2;
864 	u16			op;
865 	bool			polling;
866 	/* Track the max comp handlers */
867 	refcount_t              refcnt;
868 };
869 
870 enum phy_port_state {
871 	MLX5_AAA_111
872 };
873 
874 struct mlx5_hca_vport_context {
875 	u32			field_select;
876 	bool			sm_virt_aware;
877 	bool			has_smi;
878 	bool			has_raw;
879 	enum port_state_policy	policy;
880 	enum phy_port_state	phys_state;
881 	enum ib_port_state	vport_state;
882 	u8			port_physical_state;
883 	u64			sys_image_guid;
884 	u64			port_guid;
885 	u64			node_guid;
886 	u32			cap_mask1;
887 	u32			cap_mask1_perm;
888 	u16			cap_mask2;
889 	u16			cap_mask2_perm;
890 	u16			lid;
891 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
892 	u8			lmc;
893 	u8			subnet_timeout;
894 	u16			sm_lid;
895 	u8			sm_sl;
896 	u16			qkey_violation_counter;
897 	u16			pkey_violation_counter;
898 	bool			grh_required;
899 };
900 
901 #define STRUCT_FIELD(header, field) \
902 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
903 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
904 
905 extern struct dentry *mlx5_debugfs_root;
906 
907 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
908 {
909 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
910 }
911 
912 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
913 {
914 	return ioread32be(&dev->iseg->fw_rev) >> 16;
915 }
916 
917 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
918 {
919 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
920 }
921 
922 static inline u32 mlx5_base_mkey(const u32 key)
923 {
924 	return key & 0xffffff00u;
925 }
926 
927 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
928 {
929 	return ((u32)1 << log_sz) << log_stride;
930 }
931 
932 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
933 					u8 log_stride, u8 log_sz,
934 					u16 strides_offset,
935 					struct mlx5_frag_buf_ctrl *fbc)
936 {
937 	fbc->frags      = frags;
938 	fbc->log_stride = log_stride;
939 	fbc->log_sz     = log_sz;
940 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
941 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
942 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
943 	fbc->strides_offset = strides_offset;
944 }
945 
946 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
947 				 u8 log_stride, u8 log_sz,
948 				 struct mlx5_frag_buf_ctrl *fbc)
949 {
950 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
951 }
952 
953 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
954 					  u32 ix)
955 {
956 	unsigned int frag;
957 
958 	ix  += fbc->strides_offset;
959 	frag = ix >> fbc->log_frag_strides;
960 
961 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
962 }
963 
964 static inline u32
965 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
966 {
967 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
968 
969 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
970 }
971 
972 enum {
973 	CMD_ALLOWED_OPCODE_ALL,
974 };
975 
976 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
977 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
978 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
979 
980 struct mlx5_async_ctx {
981 	struct mlx5_core_dev *dev;
982 	atomic_t num_inflight;
983 	struct completion inflight_done;
984 };
985 
986 struct mlx5_async_work;
987 
988 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
989 
990 struct mlx5_async_work {
991 	struct mlx5_async_ctx *ctx;
992 	mlx5_async_cbk_t user_callback;
993 	u16 opcode; /* cmd opcode */
994 	u16 op_mod; /* cmd op_mod */
995 	void *out; /* pointer to the cmd output buffer */
996 };
997 
998 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
999 			     struct mlx5_async_ctx *ctx);
1000 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1001 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1002 		     void *out, int out_size, mlx5_async_cbk_t callback,
1003 		     struct mlx5_async_work *work);
1004 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1005 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1006 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1007 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1008 		  int out_size);
1009 
1010 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1011 	({                                                                     \
1012 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1013 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1014 	})
1015 
1016 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1017 	({                                                                     \
1018 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1019 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1020 	})
1021 
1022 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1023 			  void *out, int out_size);
1024 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1025 
1026 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1027 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1028 
1029 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1030 int mlx5_health_init(struct mlx5_core_dev *dev);
1031 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1032 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1033 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1034 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1035 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1036 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1037 			     struct mlx5_frag_buf *buf, int node);
1038 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1039 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1040 						      gfp_t flags, int npages);
1041 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1042 				 struct mlx5_cmd_mailbox *head);
1043 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1044 			  int inlen);
1045 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1046 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1047 			 int outlen);
1048 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1049 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1050 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1051 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1052 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1053 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1054 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1055 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1056 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1057 				 s32 npages, bool ec_function);
1058 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1059 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1060 void mlx5_register_debugfs(void);
1061 void mlx5_unregister_debugfs(void);
1062 
1063 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1064 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1065 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1066 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1067 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1068 
1069 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1070 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1071 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1072 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1073 		    void *data_out, int size_out, u16 reg_id, int arg,
1074 		    int write, bool verbose);
1075 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1076 			 int size_in, void *data_out, int size_out,
1077 			 u16 reg_num, int arg, int write);
1078 
1079 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1080 		       int node);
1081 
1082 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1083 {
1084 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1085 }
1086 
1087 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1088 
1089 const char *mlx5_command_str(int command);
1090 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1091 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1092 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1093 			 int npsvs, u32 *sig_index);
1094 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1095 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1096 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1097 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1098 			struct mlx5_odp_caps *odp_caps);
1099 
1100 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1101 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1102 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1103 		     struct mlx5_rate_limit *rl);
1104 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1105 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1106 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1107 			 bool dedicated_entry, u16 *index);
1108 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1109 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1110 		       struct mlx5_rate_limit *rl_1);
1111 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1112 		     bool map_wc, bool fast_path);
1113 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1114 
1115 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1116 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1117 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1118 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1119 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1120 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1121 
1122 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1123 {
1124 	return mkey >> 8;
1125 }
1126 
1127 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1128 {
1129 	return mkey_idx << 8;
1130 }
1131 
1132 static inline u8 mlx5_mkey_variant(u32 mkey)
1133 {
1134 	return mkey & 0xff;
1135 }
1136 
1137 /* Async-atomic event notifier used by mlx5 core to forward FW
1138  * evetns received from event queue to mlx5 consumers.
1139  * Optimise event queue dipatching.
1140  */
1141 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1143 
1144 /* Async-atomic event notifier used for forwarding
1145  * evetns from the event queue into the to mlx5 events dispatcher,
1146  * eswitch, clock and others.
1147  */
1148 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1149 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1150 
1151 /* Blocking event notifier used to forward SW events, used for slow path */
1152 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1153 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1154 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1155 				      void *data);
1156 
1157 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1158 
1159 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1160 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1161 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1162 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1163 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1164 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1165 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1166 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1167 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1168 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1169 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1170 			   struct net_device *slave);
1171 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1172 				 u64 *values,
1173 				 int num_counters,
1174 				 size_t *offsets);
1175 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1176 
1177 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1178 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1179 	     peer;								\
1180 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1181 
1182 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1183 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1184 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1185 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1186 			 u64 length, u32 log_alignment, u16 uid,
1187 			 phys_addr_t *addr, u32 *obj_id);
1188 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1189 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1190 
1191 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1192 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1193 
1194 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1195 					  int vf_id,
1196 					  struct notifier_block *nb);
1197 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1198 					     int vf_id,
1199 					     struct notifier_block *nb);
1200 #ifdef CONFIG_MLX5_CORE_IPOIB
1201 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1202 					  struct ib_device *ibdev,
1203 					  const char *name,
1204 					  void (*setup)(struct net_device *));
1205 #endif /* CONFIG_MLX5_CORE_IPOIB */
1206 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1207 			    struct ib_device *device,
1208 			    struct rdma_netdev_alloc_params *params);
1209 
1210 enum {
1211 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1212 };
1213 
1214 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1215 {
1216 	return dev->coredev_type == MLX5_COREDEV_PF;
1217 }
1218 
1219 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1220 {
1221 	return dev->coredev_type == MLX5_COREDEV_VF;
1222 }
1223 
1224 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1225 {
1226 	return dev->caps.embedded_cpu;
1227 }
1228 
1229 static inline bool
1230 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1231 {
1232 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1233 }
1234 
1235 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1236 {
1237 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1238 }
1239 
1240 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1241 {
1242 	return dev->priv.sriov.max_vfs;
1243 }
1244 
1245 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1246 {
1247 	/* LACP owner conditions:
1248 	 * 1) Function is physical.
1249 	 * 2) LAG is supported by FW.
1250 	 * 3) LAG is managed by driver (currently the only option).
1251 	 */
1252 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1253 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1254 		    MLX5_CAP_GEN(dev, lag_master);
1255 }
1256 
1257 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1258 {
1259 	return dev->priv.sriov.max_ec_vfs;
1260 }
1261 
1262 static inline int mlx5_get_gid_table_len(u16 param)
1263 {
1264 	if (param > 4) {
1265 		pr_warn("gid table length is zero\n");
1266 		return 0;
1267 	}
1268 
1269 	return 8 * (1 << param);
1270 }
1271 
1272 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1273 {
1274 	return !!(dev->priv.rl_table.max_size);
1275 }
1276 
1277 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1278 {
1279 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1280 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1281 }
1282 
1283 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1284 {
1285 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1286 }
1287 
1288 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1289 {
1290 	return mlx5_core_is_mp_slave(dev) ||
1291 	       mlx5_core_is_mp_master(dev);
1292 }
1293 
1294 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1295 {
1296 	if (!mlx5_core_mp_enabled(dev))
1297 		return 1;
1298 
1299 	return MLX5_CAP_GEN(dev, native_port_num);
1300 }
1301 
1302 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1303 {
1304 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1305 
1306 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1307 		return idx - 1;
1308 	else
1309 		return PCI_FUNC(dev->pdev->devfn);
1310 }
1311 
1312 enum {
1313 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1314 };
1315 
1316 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1317 
1318 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1319 {
1320 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1321 		return MLX5_CAP_GEN(dev, roce);
1322 
1323 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1324 	 * in order to support RoCE enable/disable feature
1325 	 */
1326 	return mlx5_is_roce_on(dev);
1327 }
1328 
1329 #ifdef CONFIG_MLX5_MACSEC
1330 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1331 {
1332 	if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1333 	    MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1334 		return false;
1335 
1336 	if (!MLX5_CAP_GEN(mdev, log_max_dek))
1337 		return false;
1338 
1339 	if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1340 		return false;
1341 
1342 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1343 	    !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1344 		return false;
1345 
1346 	if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1347 	    !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1348 		return false;
1349 
1350 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1351 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1352 		return false;
1353 
1354 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1355 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1356 		return false;
1357 
1358 	return true;
1359 }
1360 
1361 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1362 
1363 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1364 {
1365 	if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1366 	     NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1367 	     !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1368 	     !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1369 		return false;
1370 
1371 	return true;
1372 }
1373 #endif
1374 
1375 enum {
1376 	MLX5_OCTWORD = 16,
1377 };
1378 
1379 struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev,
1380 			       irqreturn_t (*handler)(int, void *),
1381 			       const struct irq_affinity_desc *affdesc,
1382 			       const char *name);
1383 void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map);
1384 
1385 #endif /* MLX5_DRIVER_H */
1386