1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 51 #include <linux/mlx5/device.h> 52 #include <linux/mlx5/doorbell.h> 53 #include <linux/mlx5/eq.h> 54 #include <linux/timecounter.h> 55 #include <linux/ptp_clock_kernel.h> 56 57 enum { 58 MLX5_BOARD_ID_LEN = 64, 59 MLX5_MAX_NAME_LEN = 16, 60 }; 61 62 enum { 63 /* one minute for the sake of bringup. Generally, commands must always 64 * complete and we may need to increase this timeout value 65 */ 66 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 67 MLX5_CMD_WQ_MAX_NAME = 32, 68 }; 69 70 enum { 71 CMD_OWNER_SW = 0x0, 72 CMD_OWNER_HW = 0x1, 73 CMD_STATUS_SUCCESS = 0, 74 }; 75 76 enum mlx5_sqp_t { 77 MLX5_SQP_SMI = 0, 78 MLX5_SQP_GSI = 1, 79 MLX5_SQP_IEEE_1588 = 2, 80 MLX5_SQP_SNIFFER = 3, 81 MLX5_SQP_SYNC_UMR = 4, 82 }; 83 84 enum { 85 MLX5_MAX_PORTS = 2, 86 }; 87 88 enum { 89 MLX5_ATOMIC_MODE_OFFSET = 16, 90 MLX5_ATOMIC_MODE_IB_COMP = 1, 91 MLX5_ATOMIC_MODE_CX = 2, 92 MLX5_ATOMIC_MODE_8B = 3, 93 MLX5_ATOMIC_MODE_16B = 4, 94 MLX5_ATOMIC_MODE_32B = 5, 95 MLX5_ATOMIC_MODE_64B = 6, 96 MLX5_ATOMIC_MODE_128B = 7, 97 MLX5_ATOMIC_MODE_256B = 8, 98 }; 99 100 enum { 101 MLX5_REG_QPTS = 0x4002, 102 MLX5_REG_QETCR = 0x4005, 103 MLX5_REG_QTCT = 0x400a, 104 MLX5_REG_QPDPM = 0x4013, 105 MLX5_REG_QCAM = 0x4019, 106 MLX5_REG_DCBX_PARAM = 0x4020, 107 MLX5_REG_DCBX_APP = 0x4021, 108 MLX5_REG_FPGA_CAP = 0x4022, 109 MLX5_REG_FPGA_CTRL = 0x4023, 110 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 111 MLX5_REG_PCAP = 0x5001, 112 MLX5_REG_PMTU = 0x5003, 113 MLX5_REG_PTYS = 0x5004, 114 MLX5_REG_PAOS = 0x5006, 115 MLX5_REG_PFCC = 0x5007, 116 MLX5_REG_PPCNT = 0x5008, 117 MLX5_REG_PPTB = 0x500b, 118 MLX5_REG_PBMC = 0x500c, 119 MLX5_REG_PMAOS = 0x5012, 120 MLX5_REG_PUDE = 0x5009, 121 MLX5_REG_PMPE = 0x5010, 122 MLX5_REG_PELC = 0x500e, 123 MLX5_REG_PVLC = 0x500f, 124 MLX5_REG_PCMR = 0x5041, 125 MLX5_REG_PMLP = 0x5002, 126 MLX5_REG_PPLM = 0x5023, 127 MLX5_REG_PCAM = 0x507f, 128 MLX5_REG_NODE_DESC = 0x6001, 129 MLX5_REG_HOST_ENDIANNESS = 0x7004, 130 MLX5_REG_MCIA = 0x9014, 131 MLX5_REG_MLCR = 0x902b, 132 MLX5_REG_MTRC_CAP = 0x9040, 133 MLX5_REG_MTRC_CONF = 0x9041, 134 MLX5_REG_MTRC_STDB = 0x9042, 135 MLX5_REG_MTRC_CTRL = 0x9043, 136 MLX5_REG_MPCNT = 0x9051, 137 MLX5_REG_MTPPS = 0x9053, 138 MLX5_REG_MTPPSE = 0x9054, 139 MLX5_REG_MPEGC = 0x9056, 140 MLX5_REG_MCQI = 0x9061, 141 MLX5_REG_MCC = 0x9062, 142 MLX5_REG_MCDA = 0x9063, 143 MLX5_REG_MCAM = 0x907f, 144 }; 145 146 enum mlx5_qpts_trust_state { 147 MLX5_QPTS_TRUST_PCP = 1, 148 MLX5_QPTS_TRUST_DSCP = 2, 149 }; 150 151 enum mlx5_dcbx_oper_mode { 152 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 153 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 154 }; 155 156 enum { 157 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 158 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 159 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 160 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 161 }; 162 163 enum mlx5_page_fault_resume_flags { 164 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 165 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 166 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 167 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 168 }; 169 170 enum dbg_rsc_type { 171 MLX5_DBG_RSC_QP, 172 MLX5_DBG_RSC_EQ, 173 MLX5_DBG_RSC_CQ, 174 }; 175 176 enum port_state_policy { 177 MLX5_POLICY_DOWN = 0, 178 MLX5_POLICY_UP = 1, 179 MLX5_POLICY_FOLLOW = 2, 180 MLX5_POLICY_INVALID = 0xffffffff 181 }; 182 183 struct mlx5_field_desc { 184 struct dentry *dent; 185 int i; 186 }; 187 188 struct mlx5_rsc_debug { 189 struct mlx5_core_dev *dev; 190 void *object; 191 enum dbg_rsc_type type; 192 struct dentry *root; 193 struct mlx5_field_desc fields[0]; 194 }; 195 196 enum mlx5_dev_event { 197 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 198 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 199 }; 200 201 enum mlx5_port_status { 202 MLX5_PORT_UP = 1, 203 MLX5_PORT_DOWN = 2, 204 }; 205 206 struct mlx5_bfreg_info { 207 u32 *sys_pages; 208 int num_low_latency_bfregs; 209 unsigned int *count; 210 211 /* 212 * protect bfreg allocation data structs 213 */ 214 struct mutex lock; 215 u32 ver; 216 bool lib_uar_4k; 217 u32 num_sys_pages; 218 u32 num_static_sys_pages; 219 u32 total_num_bfregs; 220 u32 num_dyn_bfregs; 221 }; 222 223 struct mlx5_cmd_first { 224 __be32 data[4]; 225 }; 226 227 struct mlx5_cmd_msg { 228 struct list_head list; 229 struct cmd_msg_cache *parent; 230 u32 len; 231 struct mlx5_cmd_first first; 232 struct mlx5_cmd_mailbox *next; 233 }; 234 235 struct mlx5_cmd_debug { 236 struct dentry *dbg_root; 237 struct dentry *dbg_in; 238 struct dentry *dbg_out; 239 struct dentry *dbg_outlen; 240 struct dentry *dbg_status; 241 struct dentry *dbg_run; 242 void *in_msg; 243 void *out_msg; 244 u8 status; 245 u16 inlen; 246 u16 outlen; 247 }; 248 249 struct cmd_msg_cache { 250 /* protect block chain allocations 251 */ 252 spinlock_t lock; 253 struct list_head head; 254 unsigned int max_inbox_size; 255 unsigned int num_ent; 256 }; 257 258 enum { 259 MLX5_NUM_COMMAND_CACHES = 5, 260 }; 261 262 struct mlx5_cmd_stats { 263 u64 sum; 264 u64 n; 265 struct dentry *root; 266 struct dentry *avg; 267 struct dentry *count; 268 /* protect command average calculations */ 269 spinlock_t lock; 270 }; 271 272 struct mlx5_cmd { 273 struct mlx5_nb nb; 274 275 void *cmd_alloc_buf; 276 dma_addr_t alloc_dma; 277 int alloc_size; 278 void *cmd_buf; 279 dma_addr_t dma; 280 u16 cmdif_rev; 281 u8 log_sz; 282 u8 log_stride; 283 int max_reg_cmds; 284 int events; 285 u32 __iomem *vector; 286 287 /* protect command queue allocations 288 */ 289 spinlock_t alloc_lock; 290 291 /* protect token allocations 292 */ 293 spinlock_t token_lock; 294 u8 token; 295 unsigned long bitmask; 296 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 297 struct workqueue_struct *wq; 298 struct semaphore sem; 299 struct semaphore pages_sem; 300 int mode; 301 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 302 struct dma_pool *pool; 303 struct mlx5_cmd_debug dbg; 304 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 305 int checksum_disabled; 306 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 307 }; 308 309 struct mlx5_port_caps { 310 int gid_table_len; 311 int pkey_table_len; 312 u8 ext_port_cap; 313 bool has_smi; 314 }; 315 316 struct mlx5_cmd_mailbox { 317 void *buf; 318 dma_addr_t dma; 319 struct mlx5_cmd_mailbox *next; 320 }; 321 322 struct mlx5_buf_list { 323 void *buf; 324 dma_addr_t map; 325 }; 326 327 struct mlx5_frag_buf { 328 struct mlx5_buf_list *frags; 329 int npages; 330 int size; 331 u8 page_shift; 332 }; 333 334 struct mlx5_frag_buf_ctrl { 335 struct mlx5_buf_list *frags; 336 u32 sz_m1; 337 u16 frag_sz_m1; 338 u16 strides_offset; 339 u8 log_sz; 340 u8 log_stride; 341 u8 log_frag_strides; 342 }; 343 344 struct mlx5_core_psv { 345 u32 psv_idx; 346 struct psv_layout { 347 u32 pd; 348 u16 syndrome; 349 u16 reserved; 350 u16 bg; 351 u16 app_tag; 352 u32 ref_tag; 353 } psv; 354 }; 355 356 struct mlx5_core_sig_ctx { 357 struct mlx5_core_psv psv_memory; 358 struct mlx5_core_psv psv_wire; 359 struct ib_sig_err err_item; 360 bool sig_status_checked; 361 bool sig_err_exists; 362 u32 sigerr_count; 363 }; 364 365 enum { 366 MLX5_MKEY_MR = 1, 367 MLX5_MKEY_MW, 368 MLX5_MKEY_INDIRECT_DEVX, 369 }; 370 371 struct mlx5_core_mkey { 372 u64 iova; 373 u64 size; 374 u32 key; 375 u32 pd; 376 u32 type; 377 }; 378 379 #define MLX5_24BIT_MASK ((1 << 24) - 1) 380 381 enum mlx5_res_type { 382 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 383 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 384 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 385 MLX5_RES_SRQ = 3, 386 MLX5_RES_XSRQ = 4, 387 MLX5_RES_XRQ = 5, 388 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 389 }; 390 391 struct mlx5_core_rsc_common { 392 enum mlx5_res_type res; 393 atomic_t refcount; 394 struct completion free; 395 }; 396 397 struct mlx5_uars_page { 398 void __iomem *map; 399 bool wc; 400 u32 index; 401 struct list_head list; 402 unsigned int bfregs; 403 unsigned long *reg_bitmap; /* for non fast path bf regs */ 404 unsigned long *fp_bitmap; 405 unsigned int reg_avail; 406 unsigned int fp_avail; 407 struct kref ref_count; 408 struct mlx5_core_dev *mdev; 409 }; 410 411 struct mlx5_bfreg_head { 412 /* protect blue flame registers allocations */ 413 struct mutex lock; 414 struct list_head list; 415 }; 416 417 struct mlx5_bfreg_data { 418 struct mlx5_bfreg_head reg_head; 419 struct mlx5_bfreg_head wc_head; 420 }; 421 422 struct mlx5_sq_bfreg { 423 void __iomem *map; 424 struct mlx5_uars_page *up; 425 bool wc; 426 u32 index; 427 unsigned int offset; 428 }; 429 430 struct mlx5_core_health { 431 struct health_buffer __iomem *health; 432 __be32 __iomem *health_counter; 433 struct timer_list timer; 434 u32 prev; 435 int miss_counter; 436 bool sick; 437 /* wq spinlock to synchronize draining */ 438 spinlock_t wq_lock; 439 struct workqueue_struct *wq; 440 unsigned long flags; 441 struct work_struct work; 442 struct delayed_work recover_work; 443 }; 444 445 struct mlx5_qp_table { 446 struct notifier_block nb; 447 448 /* protect radix tree 449 */ 450 spinlock_t lock; 451 struct radix_tree_root tree; 452 }; 453 454 struct mlx5_mkey_table { 455 /* protect radix tree 456 */ 457 rwlock_t lock; 458 struct radix_tree_root tree; 459 }; 460 461 struct mlx5_vf_context { 462 int enabled; 463 u64 port_guid; 464 u64 node_guid; 465 enum port_state_policy policy; 466 }; 467 468 struct mlx5_core_sriov { 469 struct mlx5_vf_context *vfs_ctx; 470 int num_vfs; 471 int enabled_vfs; 472 }; 473 474 struct mlx5_fc_stats { 475 spinlock_t counters_idr_lock; /* protects counters_idr */ 476 struct idr counters_idr; 477 struct list_head counters; 478 struct llist_head addlist; 479 struct llist_head dellist; 480 481 struct workqueue_struct *wq; 482 struct delayed_work work; 483 unsigned long next_query; 484 unsigned long sampling_interval; /* jiffies */ 485 }; 486 487 struct mlx5_events; 488 struct mlx5_mpfs; 489 struct mlx5_eswitch; 490 struct mlx5_lag; 491 struct mlx5_devcom; 492 struct mlx5_eq_table; 493 494 struct mlx5_rate_limit { 495 u32 rate; 496 u32 max_burst_sz; 497 u16 typical_pkt_sz; 498 }; 499 500 struct mlx5_rl_entry { 501 struct mlx5_rate_limit rl; 502 u16 index; 503 u16 refcount; 504 }; 505 506 struct mlx5_rl_table { 507 /* protect rate limit table */ 508 struct mutex rl_lock; 509 u16 max_size; 510 u32 max_rate; 511 u32 min_rate; 512 struct mlx5_rl_entry *rl_entry; 513 }; 514 515 struct mlx5_priv { 516 char name[MLX5_MAX_NAME_LEN]; 517 struct mlx5_eq_table *eq_table; 518 519 /* pages stuff */ 520 struct mlx5_nb pg_nb; 521 struct workqueue_struct *pg_wq; 522 struct rb_root page_root; 523 int fw_pages; 524 atomic_t reg_pages; 525 struct list_head free_list; 526 int vfs_pages; 527 int peer_pf_pages; 528 529 struct mlx5_core_health health; 530 531 /* start: qp staff */ 532 struct mlx5_qp_table qp_table; 533 struct dentry *qp_debugfs; 534 struct dentry *eq_debugfs; 535 struct dentry *cq_debugfs; 536 struct dentry *cmdif_debugfs; 537 /* end: qp staff */ 538 539 /* start: mkey staff */ 540 struct mlx5_mkey_table mkey_table; 541 /* end: mkey staff */ 542 543 /* start: alloc staff */ 544 /* protect buffer alocation according to numa node */ 545 struct mutex alloc_mutex; 546 int numa_node; 547 548 struct mutex pgdir_mutex; 549 struct list_head pgdir_list; 550 /* end: alloc staff */ 551 struct dentry *dbg_root; 552 553 /* protect mkey key part */ 554 spinlock_t mkey_lock; 555 u8 mkey_key; 556 557 struct list_head dev_list; 558 struct list_head ctx_list; 559 spinlock_t ctx_lock; 560 struct mlx5_events *events; 561 562 struct mlx5_flow_steering *steering; 563 struct mlx5_mpfs *mpfs; 564 struct mlx5_eswitch *eswitch; 565 struct mlx5_core_sriov sriov; 566 struct mlx5_lag *lag; 567 struct mlx5_devcom *devcom; 568 unsigned long pci_dev_data; 569 struct mlx5_fc_stats fc_stats; 570 struct mlx5_rl_table rl_table; 571 572 struct mlx5_bfreg_data bfregs; 573 struct mlx5_uars_page *uar; 574 }; 575 576 enum mlx5_device_state { 577 MLX5_DEVICE_STATE_UP, 578 MLX5_DEVICE_STATE_INTERNAL_ERROR, 579 }; 580 581 enum mlx5_interface_state { 582 MLX5_INTERFACE_STATE_UP = BIT(0), 583 }; 584 585 enum mlx5_pci_status { 586 MLX5_PCI_STATUS_DISABLED, 587 MLX5_PCI_STATUS_ENABLED, 588 }; 589 590 enum mlx5_pagefault_type_flags { 591 MLX5_PFAULT_REQUESTOR = 1 << 0, 592 MLX5_PFAULT_WRITE = 1 << 1, 593 MLX5_PFAULT_RDMA = 1 << 2, 594 }; 595 596 struct mlx5_td { 597 /* protects tirs list changes while tirs refresh */ 598 struct mutex list_lock; 599 struct list_head tirs_list; 600 u32 tdn; 601 }; 602 603 struct mlx5e_resources { 604 u32 pdn; 605 struct mlx5_td td; 606 struct mlx5_core_mkey mkey; 607 struct mlx5_sq_bfreg bfreg; 608 }; 609 610 #define MLX5_MAX_RESERVED_GIDS 8 611 612 struct mlx5_rsvd_gids { 613 unsigned int start; 614 unsigned int count; 615 struct ida ida; 616 }; 617 618 #define MAX_PIN_NUM 8 619 struct mlx5_pps { 620 u8 pin_caps[MAX_PIN_NUM]; 621 struct work_struct out_work; 622 u64 start[MAX_PIN_NUM]; 623 u8 enabled; 624 }; 625 626 struct mlx5_clock { 627 struct mlx5_core_dev *mdev; 628 struct mlx5_nb pps_nb; 629 seqlock_t lock; 630 struct cyclecounter cycles; 631 struct timecounter tc; 632 struct hwtstamp_config hwtstamp_config; 633 u32 nominal_c_mult; 634 unsigned long overflow_period; 635 struct delayed_work overflow_work; 636 struct ptp_clock *ptp; 637 struct ptp_clock_info ptp_info; 638 struct mlx5_pps pps_info; 639 }; 640 641 struct mlx5_fw_tracer; 642 struct mlx5_vxlan; 643 644 struct mlx5_core_dev { 645 struct pci_dev *pdev; 646 /* sync pci state */ 647 struct mutex pci_status_mutex; 648 enum mlx5_pci_status pci_status; 649 u8 rev_id; 650 char board_id[MLX5_BOARD_ID_LEN]; 651 struct mlx5_cmd cmd; 652 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 653 struct { 654 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 655 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 656 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 657 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 658 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 659 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 660 u8 embedded_cpu; 661 } caps; 662 u64 sys_image_guid; 663 phys_addr_t iseg_base; 664 struct mlx5_init_seg __iomem *iseg; 665 enum mlx5_device_state state; 666 /* sync interface state */ 667 struct mutex intf_state_mutex; 668 unsigned long intf_state; 669 struct mlx5_priv priv; 670 struct mlx5_profile *profile; 671 atomic_t num_qps; 672 u32 issi; 673 struct mlx5e_resources mlx5e_res; 674 struct mlx5_vxlan *vxlan; 675 struct { 676 struct mlx5_rsvd_gids reserved_gids; 677 u32 roce_en; 678 } roce; 679 #ifdef CONFIG_MLX5_FPGA 680 struct mlx5_fpga_device *fpga; 681 #endif 682 struct mlx5_clock clock; 683 struct mlx5_ib_clock_info *clock_info; 684 struct page *clock_info_page; 685 struct mlx5_fw_tracer *tracer; 686 }; 687 688 struct mlx5_db { 689 __be32 *db; 690 union { 691 struct mlx5_db_pgdir *pgdir; 692 struct mlx5_ib_user_db_page *user_page; 693 } u; 694 dma_addr_t dma; 695 int index; 696 }; 697 698 enum { 699 MLX5_COMP_EQ_SIZE = 1024, 700 }; 701 702 enum { 703 MLX5_PTYS_IB = 1 << 0, 704 MLX5_PTYS_EN = 1 << 2, 705 }; 706 707 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 708 709 enum { 710 MLX5_CMD_ENT_STATE_PENDING_COMP, 711 }; 712 713 struct mlx5_cmd_work_ent { 714 unsigned long state; 715 struct mlx5_cmd_msg *in; 716 struct mlx5_cmd_msg *out; 717 void *uout; 718 int uout_size; 719 mlx5_cmd_cbk_t callback; 720 struct delayed_work cb_timeout_work; 721 void *context; 722 int idx; 723 struct completion done; 724 struct mlx5_cmd *cmd; 725 struct work_struct work; 726 struct mlx5_cmd_layout *lay; 727 int ret; 728 int page_queue; 729 u8 status; 730 u8 token; 731 u64 ts1; 732 u64 ts2; 733 u16 op; 734 bool polling; 735 }; 736 737 struct mlx5_pas { 738 u64 pa; 739 u8 log_sz; 740 }; 741 742 enum phy_port_state { 743 MLX5_AAA_111 744 }; 745 746 struct mlx5_hca_vport_context { 747 u32 field_select; 748 bool sm_virt_aware; 749 bool has_smi; 750 bool has_raw; 751 enum port_state_policy policy; 752 enum phy_port_state phys_state; 753 enum ib_port_state vport_state; 754 u8 port_physical_state; 755 u64 sys_image_guid; 756 u64 port_guid; 757 u64 node_guid; 758 u32 cap_mask1; 759 u32 cap_mask1_perm; 760 u16 cap_mask2; 761 u16 cap_mask2_perm; 762 u16 lid; 763 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 764 u8 lmc; 765 u8 subnet_timeout; 766 u16 sm_lid; 767 u8 sm_sl; 768 u16 qkey_violation_counter; 769 u16 pkey_violation_counter; 770 bool grh_required; 771 }; 772 773 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 774 { 775 return buf->frags->buf + offset; 776 } 777 778 #define STRUCT_FIELD(header, field) \ 779 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 780 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 781 782 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 783 { 784 return pci_get_drvdata(pdev); 785 } 786 787 extern struct dentry *mlx5_debugfs_root; 788 789 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 790 { 791 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 792 } 793 794 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 795 { 796 return ioread32be(&dev->iseg->fw_rev) >> 16; 797 } 798 799 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 800 { 801 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 802 } 803 804 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 805 { 806 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 807 } 808 809 static inline u32 mlx5_base_mkey(const u32 key) 810 { 811 return key & 0xffffff00u; 812 } 813 814 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 815 u8 log_stride, u8 log_sz, 816 u16 strides_offset, 817 struct mlx5_frag_buf_ctrl *fbc) 818 { 819 fbc->frags = frags; 820 fbc->log_stride = log_stride; 821 fbc->log_sz = log_sz; 822 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 823 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 824 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 825 fbc->strides_offset = strides_offset; 826 } 827 828 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 829 u8 log_stride, u8 log_sz, 830 struct mlx5_frag_buf_ctrl *fbc) 831 { 832 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 833 } 834 835 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 836 u32 ix) 837 { 838 unsigned int frag; 839 840 ix += fbc->strides_offset; 841 frag = ix >> fbc->log_frag_strides; 842 843 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 844 } 845 846 static inline u32 847 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 848 { 849 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 850 851 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 852 } 853 854 int mlx5_cmd_init(struct mlx5_core_dev *dev); 855 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 856 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 857 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 858 859 struct mlx5_async_ctx { 860 struct mlx5_core_dev *dev; 861 atomic_t num_inflight; 862 struct wait_queue_head wait; 863 }; 864 865 struct mlx5_async_work; 866 867 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 868 869 struct mlx5_async_work { 870 struct mlx5_async_ctx *ctx; 871 mlx5_async_cbk_t user_callback; 872 }; 873 874 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 875 struct mlx5_async_ctx *ctx); 876 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 877 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 878 void *out, int out_size, mlx5_async_cbk_t callback, 879 struct mlx5_async_work *work); 880 881 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 882 int out_size); 883 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 884 void *out, int out_size); 885 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 886 887 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 888 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 889 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 890 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 891 int mlx5_health_init(struct mlx5_core_dev *dev); 892 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 893 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 894 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 895 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 896 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 897 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 898 struct mlx5_frag_buf *buf, int node); 899 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 900 int size, struct mlx5_frag_buf *buf); 901 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 902 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 903 struct mlx5_frag_buf *buf, int node); 904 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 905 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 906 gfp_t flags, int npages); 907 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 908 struct mlx5_cmd_mailbox *head); 909 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 910 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 911 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 912 struct mlx5_core_mkey *mkey, 913 struct mlx5_async_ctx *async_ctx, u32 *in, 914 int inlen, u32 *out, int outlen, 915 mlx5_async_cbk_t callback, 916 struct mlx5_async_work *context); 917 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 918 struct mlx5_core_mkey *mkey, 919 u32 *in, int inlen); 920 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 921 struct mlx5_core_mkey *mkey); 922 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 923 u32 *out, int outlen); 924 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 925 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 926 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 927 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 928 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 929 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 930 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 931 s32 npages, bool ec_function); 932 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 933 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 934 void mlx5_register_debugfs(void); 935 void mlx5_unregister_debugfs(void); 936 937 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 938 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 939 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 940 unsigned int *irqn); 941 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 942 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 943 944 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 945 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 946 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 947 int size_in, void *data_out, int size_out, 948 u16 reg_num, int arg, int write); 949 950 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 951 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 952 int node); 953 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 954 955 const char *mlx5_command_str(int command); 956 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 957 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 958 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 959 int npsvs, u32 *sig_index); 960 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 961 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 962 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 963 struct mlx5_odp_caps *odp_caps); 964 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 965 u8 port_num, void *out, size_t sz); 966 967 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 968 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 969 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 970 struct mlx5_rate_limit *rl); 971 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 972 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 973 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 974 struct mlx5_rate_limit *rl_1); 975 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 976 bool map_wc, bool fast_path); 977 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 978 979 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 980 struct cpumask * 981 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 982 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 983 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 984 u8 roce_version, u8 roce_l3_type, const u8 *gid, 985 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 986 987 static inline int fw_initializing(struct mlx5_core_dev *dev) 988 { 989 return ioread32be(&dev->iseg->initializing) >> 31; 990 } 991 992 static inline u32 mlx5_mkey_to_idx(u32 mkey) 993 { 994 return mkey >> 8; 995 } 996 997 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 998 { 999 return mkey_idx << 8; 1000 } 1001 1002 static inline u8 mlx5_mkey_variant(u32 mkey) 1003 { 1004 return mkey & 0xff; 1005 } 1006 1007 enum { 1008 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1009 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1010 }; 1011 1012 enum { 1013 MR_CACHE_LAST_STD_ENTRY = 20, 1014 MLX5_IMR_MTT_CACHE_ENTRY, 1015 MLX5_IMR_KSM_CACHE_ENTRY, 1016 MAX_MR_CACHE_ENTRIES 1017 }; 1018 1019 enum { 1020 MLX5_INTERFACE_PROTOCOL_IB = 0, 1021 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1022 }; 1023 1024 struct mlx5_interface { 1025 void * (*add)(struct mlx5_core_dev *dev); 1026 void (*remove)(struct mlx5_core_dev *dev, void *context); 1027 int (*attach)(struct mlx5_core_dev *dev, void *context); 1028 void (*detach)(struct mlx5_core_dev *dev, void *context); 1029 int protocol; 1030 struct list_head list; 1031 }; 1032 1033 int mlx5_register_interface(struct mlx5_interface *intf); 1034 void mlx5_unregister_interface(struct mlx5_interface *intf); 1035 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1036 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1037 1038 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1039 1040 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1041 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1042 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1043 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1044 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1045 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1046 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1047 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1048 u64 *values, 1049 int num_counters, 1050 size_t *offsets); 1051 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1052 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1053 1054 #ifdef CONFIG_MLX5_CORE_IPOIB 1055 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1056 struct ib_device *ibdev, 1057 const char *name, 1058 void (*setup)(struct net_device *)); 1059 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1060 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1061 struct ib_device *device, 1062 struct rdma_netdev_alloc_params *params); 1063 1064 struct mlx5_profile { 1065 u64 mask; 1066 u8 log_max_qp; 1067 struct { 1068 int size; 1069 int limit; 1070 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1071 }; 1072 1073 enum { 1074 MLX5_PCI_DEV_IS_VF = 1 << 0, 1075 }; 1076 1077 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1078 { 1079 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1080 } 1081 1082 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1083 { 1084 return dev->caps.embedded_cpu; 1085 } 1086 1087 static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev) 1088 { 1089 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1090 } 1091 1092 static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev) 1093 { 1094 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1095 } 1096 1097 #define MLX5_HOST_PF_MAX_VFS (127u) 1098 static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev) 1099 { 1100 if (mlx5_core_is_ecpf_esw_manager(dev)) 1101 return MLX5_HOST_PF_MAX_VFS; 1102 else 1103 return pci_sriov_get_totalvfs(dev->pdev); 1104 } 1105 1106 static inline int mlx5_get_gid_table_len(u16 param) 1107 { 1108 if (param > 4) { 1109 pr_warn("gid table length is zero\n"); 1110 return 0; 1111 } 1112 1113 return 8 * (1 << param); 1114 } 1115 1116 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1117 { 1118 return !!(dev->priv.rl_table.max_size); 1119 } 1120 1121 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1122 { 1123 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1124 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1125 } 1126 1127 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1128 { 1129 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1130 } 1131 1132 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1133 { 1134 return mlx5_core_is_mp_slave(dev) || 1135 mlx5_core_is_mp_master(dev); 1136 } 1137 1138 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1139 { 1140 if (!mlx5_core_mp_enabled(dev)) 1141 return 1; 1142 1143 return MLX5_CAP_GEN(dev, native_port_num); 1144 } 1145 1146 enum { 1147 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1148 }; 1149 1150 #endif /* MLX5_DRIVER_H */ 1151