xref: /linux-6.15/include/linux/mlx5/driver.h (revision f9beaf4f) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <net/devlink.h>
58 
59 #define MLX5_ADEV_NAME "mlx5_core"
60 
61 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
62 
63 enum {
64 	MLX5_BOARD_ID_LEN = 64,
65 };
66 
67 enum {
68 	MLX5_CMD_WQ_MAX_NAME	= 32,
69 };
70 
71 enum {
72 	CMD_OWNER_SW		= 0x0,
73 	CMD_OWNER_HW		= 0x1,
74 	CMD_STATUS_SUCCESS	= 0,
75 };
76 
77 enum mlx5_sqp_t {
78 	MLX5_SQP_SMI		= 0,
79 	MLX5_SQP_GSI		= 1,
80 	MLX5_SQP_IEEE_1588	= 2,
81 	MLX5_SQP_SNIFFER	= 3,
82 	MLX5_SQP_SYNC_UMR	= 4,
83 };
84 
85 enum {
86 	MLX5_MAX_PORTS	= 8,
87 };
88 
89 enum {
90 	MLX5_ATOMIC_MODE_OFFSET = 16,
91 	MLX5_ATOMIC_MODE_IB_COMP = 1,
92 	MLX5_ATOMIC_MODE_CX = 2,
93 	MLX5_ATOMIC_MODE_8B = 3,
94 	MLX5_ATOMIC_MODE_16B = 4,
95 	MLX5_ATOMIC_MODE_32B = 5,
96 	MLX5_ATOMIC_MODE_64B = 6,
97 	MLX5_ATOMIC_MODE_128B = 7,
98 	MLX5_ATOMIC_MODE_256B = 8,
99 };
100 
101 enum {
102 	MLX5_REG_SBPR            = 0xb001,
103 	MLX5_REG_SBCM            = 0xb002,
104 	MLX5_REG_QPTS            = 0x4002,
105 	MLX5_REG_QETCR		 = 0x4005,
106 	MLX5_REG_QTCT		 = 0x400a,
107 	MLX5_REG_QPDPM           = 0x4013,
108 	MLX5_REG_QCAM            = 0x4019,
109 	MLX5_REG_DCBX_PARAM      = 0x4020,
110 	MLX5_REG_DCBX_APP        = 0x4021,
111 	MLX5_REG_FPGA_CAP	 = 0x4022,
112 	MLX5_REG_FPGA_CTRL	 = 0x4023,
113 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
114 	MLX5_REG_CORE_DUMP	 = 0x402e,
115 	MLX5_REG_PCAP		 = 0x5001,
116 	MLX5_REG_PMTU		 = 0x5003,
117 	MLX5_REG_PTYS		 = 0x5004,
118 	MLX5_REG_PAOS		 = 0x5006,
119 	MLX5_REG_PFCC            = 0x5007,
120 	MLX5_REG_PPCNT		 = 0x5008,
121 	MLX5_REG_PPTB            = 0x500b,
122 	MLX5_REG_PBMC            = 0x500c,
123 	MLX5_REG_PMAOS		 = 0x5012,
124 	MLX5_REG_PUDE		 = 0x5009,
125 	MLX5_REG_PMPE		 = 0x5010,
126 	MLX5_REG_PELC		 = 0x500e,
127 	MLX5_REG_PVLC		 = 0x500f,
128 	MLX5_REG_PCMR		 = 0x5041,
129 	MLX5_REG_PDDR		 = 0x5031,
130 	MLX5_REG_PMLP		 = 0x5002,
131 	MLX5_REG_PPLM		 = 0x5023,
132 	MLX5_REG_PCAM		 = 0x507f,
133 	MLX5_REG_NODE_DESC	 = 0x6001,
134 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 	MLX5_REG_MTCAP		 = 0x9009,
136 	MLX5_REG_MTMP		 = 0x900A,
137 	MLX5_REG_MCIA		 = 0x9014,
138 	MLX5_REG_MFRL		 = 0x9028,
139 	MLX5_REG_MLCR		 = 0x902b,
140 	MLX5_REG_MRTC		 = 0x902d,
141 	MLX5_REG_MTRC_CAP	 = 0x9040,
142 	MLX5_REG_MTRC_CONF	 = 0x9041,
143 	MLX5_REG_MTRC_STDB	 = 0x9042,
144 	MLX5_REG_MTRC_CTRL	 = 0x9043,
145 	MLX5_REG_MPEIN		 = 0x9050,
146 	MLX5_REG_MPCNT		 = 0x9051,
147 	MLX5_REG_MTPPS		 = 0x9053,
148 	MLX5_REG_MTPPSE		 = 0x9054,
149 	MLX5_REG_MTUTC		 = 0x9055,
150 	MLX5_REG_MPEGC		 = 0x9056,
151 	MLX5_REG_MPIR		 = 0x9059,
152 	MLX5_REG_MCQS		 = 0x9060,
153 	MLX5_REG_MCQI		 = 0x9061,
154 	MLX5_REG_MCC		 = 0x9062,
155 	MLX5_REG_MCDA		 = 0x9063,
156 	MLX5_REG_MCAM		 = 0x907f,
157 	MLX5_REG_MSECQ		 = 0x9155,
158 	MLX5_REG_MSEES		 = 0x9156,
159 	MLX5_REG_MIRC		 = 0x9162,
160 	MLX5_REG_MTPTM		 = 0x9180,
161 	MLX5_REG_MTCTR		 = 0x9181,
162 	MLX5_REG_MRTCQ		 = 0x9182,
163 	MLX5_REG_SBCAM		 = 0xB01F,
164 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
165 	MLX5_REG_NIC_CAP	 = 0xC00D,
166 	MLX5_REG_DTOR            = 0xC00E,
167 	MLX5_REG_VHCA_ICM_CTRL	 = 0xC010,
168 };
169 
170 enum mlx5_qpts_trust_state {
171 	MLX5_QPTS_TRUST_PCP  = 1,
172 	MLX5_QPTS_TRUST_DSCP = 2,
173 };
174 
175 enum mlx5_dcbx_oper_mode {
176 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
177 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
178 };
179 
180 enum {
181 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
182 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
183 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
184 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
185 };
186 
187 enum mlx5_page_fault_resume_flags {
188 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
189 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
190 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
191 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
192 };
193 
194 enum dbg_rsc_type {
195 	MLX5_DBG_RSC_QP,
196 	MLX5_DBG_RSC_EQ,
197 	MLX5_DBG_RSC_CQ,
198 };
199 
200 enum port_state_policy {
201 	MLX5_POLICY_DOWN	= 0,
202 	MLX5_POLICY_UP		= 1,
203 	MLX5_POLICY_FOLLOW	= 2,
204 	MLX5_POLICY_INVALID	= 0xffffffff
205 };
206 
207 enum mlx5_coredev_type {
208 	MLX5_COREDEV_PF,
209 	MLX5_COREDEV_VF,
210 	MLX5_COREDEV_SF,
211 };
212 
213 struct mlx5_field_desc {
214 	int			i;
215 };
216 
217 struct mlx5_rsc_debug {
218 	struct mlx5_core_dev   *dev;
219 	void		       *object;
220 	enum dbg_rsc_type	type;
221 	struct dentry	       *root;
222 	struct mlx5_field_desc	fields[];
223 };
224 
225 enum mlx5_dev_event {
226 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
227 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
228 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
229 };
230 
231 enum mlx5_port_status {
232 	MLX5_PORT_UP        = 1,
233 	MLX5_PORT_DOWN      = 2,
234 };
235 
236 enum mlx5_cmdif_state {
237 	MLX5_CMDIF_STATE_UNINITIALIZED,
238 	MLX5_CMDIF_STATE_UP,
239 	MLX5_CMDIF_STATE_DOWN,
240 };
241 
242 struct mlx5_cmd_first {
243 	__be32		data[4];
244 };
245 
246 struct mlx5_cmd_msg {
247 	struct list_head		list;
248 	struct cmd_msg_cache	       *parent;
249 	u32				len;
250 	struct mlx5_cmd_first		first;
251 	struct mlx5_cmd_mailbox	       *next;
252 };
253 
254 struct mlx5_cmd_debug {
255 	struct dentry	       *dbg_root;
256 	void		       *in_msg;
257 	void		       *out_msg;
258 	u8			status;
259 	u16			inlen;
260 	u16			outlen;
261 };
262 
263 struct cmd_msg_cache {
264 	/* protect block chain allocations
265 	 */
266 	spinlock_t		lock;
267 	struct list_head	head;
268 	unsigned int		max_inbox_size;
269 	unsigned int		num_ent;
270 };
271 
272 enum {
273 	MLX5_NUM_COMMAND_CACHES = 5,
274 };
275 
276 struct mlx5_cmd_stats {
277 	u64		sum;
278 	u64		n;
279 	/* number of times command failed */
280 	u64		failed;
281 	/* number of times command failed on bad status returned by FW */
282 	u64		failed_mbox_status;
283 	/* last command failed returned errno */
284 	u32		last_failed_errno;
285 	/* last bad status returned by FW */
286 	u8		last_failed_mbox_status;
287 	/* last command failed syndrome returned by FW */
288 	u32		last_failed_syndrome;
289 	struct dentry  *root;
290 	/* protect command average calculations */
291 	spinlock_t	lock;
292 };
293 
294 struct mlx5_cmd {
295 	struct mlx5_nb    nb;
296 
297 	/* members which needs to be queried or reinitialized each reload */
298 	struct {
299 		u16		cmdif_rev;
300 		u8		log_sz;
301 		u8		log_stride;
302 		int		max_reg_cmds;
303 		unsigned long	bitmask;
304 		struct semaphore sem;
305 		struct semaphore pages_sem;
306 		struct semaphore throttle_sem;
307 	} vars;
308 	enum mlx5_cmdif_state	state;
309 	void	       *cmd_alloc_buf;
310 	dma_addr_t	alloc_dma;
311 	int		alloc_size;
312 	void	       *cmd_buf;
313 	dma_addr_t	dma;
314 
315 	/* protect command queue allocations
316 	 */
317 	spinlock_t	alloc_lock;
318 
319 	/* protect token allocations
320 	 */
321 	spinlock_t	token_lock;
322 	u8		token;
323 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
324 	struct workqueue_struct *wq;
325 	int	mode;
326 	u16     allowed_opcode;
327 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
328 	struct dma_pool *pool;
329 	struct mlx5_cmd_debug dbg;
330 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
331 	int checksum_disabled;
332 	struct xarray stats;
333 };
334 
335 struct mlx5_cmd_mailbox {
336 	void	       *buf;
337 	dma_addr_t	dma;
338 	struct mlx5_cmd_mailbox *next;
339 };
340 
341 struct mlx5_buf_list {
342 	void		       *buf;
343 	dma_addr_t		map;
344 };
345 
346 struct mlx5_frag_buf {
347 	struct mlx5_buf_list	*frags;
348 	int			npages;
349 	int			size;
350 	u8			page_shift;
351 };
352 
353 struct mlx5_frag_buf_ctrl {
354 	struct mlx5_buf_list   *frags;
355 	u32			sz_m1;
356 	u16			frag_sz_m1;
357 	u16			strides_offset;
358 	u8			log_sz;
359 	u8			log_stride;
360 	u8			log_frag_strides;
361 };
362 
363 struct mlx5_core_psv {
364 	u32	psv_idx;
365 	struct psv_layout {
366 		u32	pd;
367 		u16	syndrome;
368 		u16	reserved;
369 		u16	bg;
370 		u16	app_tag;
371 		u32	ref_tag;
372 	} psv;
373 };
374 
375 struct mlx5_core_sig_ctx {
376 	struct mlx5_core_psv	psv_memory;
377 	struct mlx5_core_psv	psv_wire;
378 	struct ib_sig_err       err_item;
379 	bool			sig_status_checked;
380 	bool			sig_err_exists;
381 	u32			sigerr_count;
382 };
383 
384 #define MLX5_24BIT_MASK		((1 << 24) - 1)
385 
386 enum mlx5_res_type {
387 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
388 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
389 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
390 	MLX5_RES_SRQ	= 3,
391 	MLX5_RES_XSRQ	= 4,
392 	MLX5_RES_XRQ	= 5,
393 };
394 
395 struct mlx5_core_rsc_common {
396 	enum mlx5_res_type	res;
397 	refcount_t		refcount;
398 	struct completion	free;
399 };
400 
401 struct mlx5_uars_page {
402 	void __iomem	       *map;
403 	bool			wc;
404 	u32			index;
405 	struct list_head	list;
406 	unsigned int		bfregs;
407 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
408 	unsigned long	       *fp_bitmap;
409 	unsigned int		reg_avail;
410 	unsigned int		fp_avail;
411 	struct kref		ref_count;
412 	struct mlx5_core_dev   *mdev;
413 };
414 
415 struct mlx5_bfreg_head {
416 	/* protect blue flame registers allocations */
417 	struct mutex		lock;
418 	struct list_head	list;
419 };
420 
421 struct mlx5_bfreg_data {
422 	struct mlx5_bfreg_head	reg_head;
423 	struct mlx5_bfreg_head	wc_head;
424 };
425 
426 struct mlx5_sq_bfreg {
427 	void __iomem	       *map;
428 	struct mlx5_uars_page  *up;
429 	bool			wc;
430 	u32			index;
431 	unsigned int		offset;
432 };
433 
434 struct mlx5_core_health {
435 	struct health_buffer __iomem   *health;
436 	__be32 __iomem		       *health_counter;
437 	struct timer_list		timer;
438 	u32				prev;
439 	int				miss_counter;
440 	u8				synd;
441 	u32				fatal_error;
442 	u32				crdump_size;
443 	struct workqueue_struct	       *wq;
444 	unsigned long			flags;
445 	struct work_struct		fatal_report_work;
446 	struct work_struct		report_work;
447 	struct devlink_health_reporter *fw_reporter;
448 	struct devlink_health_reporter *fw_fatal_reporter;
449 	struct devlink_health_reporter *vnic_reporter;
450 	struct delayed_work		update_fw_log_ts_work;
451 };
452 
453 enum {
454 	MLX5_PF_NOTIFY_DISABLE_VF,
455 	MLX5_PF_NOTIFY_ENABLE_VF,
456 };
457 
458 struct mlx5_vf_context {
459 	int	enabled;
460 	u64	port_guid;
461 	u64	node_guid;
462 	/* Valid bits are used to validate administrative guid only.
463 	 * Enabled after ndo_set_vf_guid
464 	 */
465 	u8	port_guid_valid:1;
466 	u8	node_guid_valid:1;
467 	enum port_state_policy	policy;
468 	struct blocking_notifier_head notifier;
469 };
470 
471 struct mlx5_core_sriov {
472 	struct mlx5_vf_context	*vfs_ctx;
473 	int			num_vfs;
474 	u16			max_vfs;
475 	u16			max_ec_vfs;
476 };
477 
478 struct mlx5_events;
479 struct mlx5_mpfs;
480 struct mlx5_eswitch;
481 struct mlx5_lag;
482 struct mlx5_devcom_dev;
483 struct mlx5_fw_reset;
484 struct mlx5_eq_table;
485 struct mlx5_irq_table;
486 struct mlx5_vhca_state_notifier;
487 struct mlx5_sf_dev_table;
488 struct mlx5_sf_hw_table;
489 struct mlx5_sf_table;
490 struct mlx5_crypto_dek_priv;
491 
492 struct mlx5_rate_limit {
493 	u32			rate;
494 	u32			max_burst_sz;
495 	u16			typical_pkt_sz;
496 };
497 
498 struct mlx5_rl_entry {
499 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
500 	u64 refcount;
501 	u16 index;
502 	u16 uid;
503 	u8 dedicated : 1;
504 };
505 
506 struct mlx5_rl_table {
507 	/* protect rate limit table */
508 	struct mutex            rl_lock;
509 	u16                     max_size;
510 	u32                     max_rate;
511 	u32                     min_rate;
512 	struct mlx5_rl_entry   *rl_entry;
513 	u64 refcount;
514 };
515 
516 struct mlx5_core_roce {
517 	struct mlx5_flow_table *ft;
518 	struct mlx5_flow_group *fg;
519 	struct mlx5_flow_handle *allow_rule;
520 };
521 
522 enum {
523 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
524 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
525 	/* Set during device detach to block any further devices
526 	 * creation/deletion on drivers rescan. Unset during device attach.
527 	 */
528 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
529 	MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
530 };
531 
532 struct mlx5_adev {
533 	struct auxiliary_device adev;
534 	struct mlx5_core_dev *mdev;
535 	int idx;
536 };
537 
538 struct mlx5_debugfs_entries {
539 	struct dentry *dbg_root;
540 	struct dentry *qp_debugfs;
541 	struct dentry *eq_debugfs;
542 	struct dentry *cq_debugfs;
543 	struct dentry *cmdif_debugfs;
544 	struct dentry *pages_debugfs;
545 	struct dentry *lag_debugfs;
546 };
547 
548 enum mlx5_func_type {
549 	MLX5_PF,
550 	MLX5_VF,
551 	MLX5_SF,
552 	MLX5_HOST_PF,
553 	MLX5_EC_VF,
554 	MLX5_FUNC_TYPE_NUM,
555 };
556 
557 struct mlx5_ft_pool;
558 struct mlx5_priv {
559 	/* IRQ table valid only for real pci devices PF or VF */
560 	struct mlx5_irq_table   *irq_table;
561 	struct mlx5_eq_table	*eq_table;
562 
563 	/* pages stuff */
564 	struct mlx5_nb          pg_nb;
565 	struct workqueue_struct *pg_wq;
566 	struct xarray           page_root_xa;
567 	atomic_t		reg_pages;
568 	struct list_head	free_list;
569 	u32			fw_pages;
570 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
571 	u32			fw_pages_alloc_failed;
572 	u32			give_pages_dropped;
573 	u32			reclaim_pages_discard;
574 
575 	struct mlx5_core_health health;
576 	struct list_head	traps;
577 
578 	struct mlx5_debugfs_entries dbg;
579 
580 	/* start: alloc staff */
581 	/* protect buffer allocation according to numa node */
582 	struct mutex            alloc_mutex;
583 	int                     numa_node;
584 
585 	struct mutex            pgdir_mutex;
586 	struct list_head        pgdir_list;
587 	/* end: alloc staff */
588 
589 	struct mlx5_adev       **adev;
590 	int			adev_idx;
591 	int			sw_vhca_id;
592 	struct mlx5_events      *events;
593 	struct mlx5_vhca_events *vhca_events;
594 
595 	struct mlx5_flow_steering *steering;
596 	struct mlx5_mpfs        *mpfs;
597 	struct mlx5_eswitch     *eswitch;
598 	struct mlx5_core_sriov	sriov;
599 	struct mlx5_lag		*lag;
600 	u32			flags;
601 	struct mlx5_devcom_dev	*devc;
602 	struct mlx5_devcom_comp_dev *hca_devcom_comp;
603 	struct mlx5_fw_reset	*fw_reset;
604 	struct mlx5_core_roce	roce;
605 	struct mlx5_fc_stats		*fc_stats;
606 	struct mlx5_rl_table            rl_table;
607 	struct mlx5_ft_pool		*ft_pool;
608 
609 	struct mlx5_bfreg_data		bfregs;
610 	struct mlx5_uars_page	       *uar;
611 #ifdef CONFIG_MLX5_SF
612 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
613 	struct mlx5_sf_dev_table *sf_dev_table;
614 	struct mlx5_core_dev *parent_mdev;
615 #endif
616 #ifdef CONFIG_MLX5_SF_MANAGER
617 	struct mlx5_sf_hw_table *sf_hw_table;
618 	struct mlx5_sf_table *sf_table;
619 #endif
620 	struct blocking_notifier_head lag_nh;
621 };
622 
623 enum mlx5_device_state {
624 	MLX5_DEVICE_STATE_UP = 1,
625 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
626 };
627 
628 enum mlx5_interface_state {
629 	MLX5_INTERFACE_STATE_UP = BIT(0),
630 	MLX5_BREAK_FW_WAIT = BIT(1),
631 };
632 
633 enum mlx5_pci_status {
634 	MLX5_PCI_STATUS_DISABLED,
635 	MLX5_PCI_STATUS_ENABLED,
636 };
637 
638 enum mlx5_pagefault_type_flags {
639 	MLX5_PFAULT_REQUESTOR = 1 << 0,
640 	MLX5_PFAULT_WRITE     = 1 << 1,
641 	MLX5_PFAULT_RDMA      = 1 << 2,
642 };
643 
644 struct mlx5_td {
645 	/* protects tirs list changes while tirs refresh */
646 	struct mutex     list_lock;
647 	struct list_head tirs_list;
648 	u32              tdn;
649 };
650 
651 struct mlx5e_resources {
652 	struct mlx5e_hw_objs {
653 		u32                        pdn;
654 		struct mlx5_td             td;
655 		u32			   mkey;
656 		struct mlx5_sq_bfreg       bfreg;
657 #define MLX5_MAX_NUM_TC 8
658 		u32                        tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
659 		bool			   tisn_valid;
660 	} hw_objs;
661 	struct net_device *uplink_netdev;
662 	struct mutex uplink_netdev_lock;
663 	struct mlx5_crypto_dek_priv *dek_priv;
664 };
665 
666 enum mlx5_sw_icm_type {
667 	MLX5_SW_ICM_TYPE_STEERING,
668 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
669 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
670 	MLX5_SW_ICM_TYPE_SW_ENCAP,
671 };
672 
673 #define MLX5_MAX_RESERVED_GIDS 8
674 
675 struct mlx5_rsvd_gids {
676 	unsigned int start;
677 	unsigned int count;
678 	struct ida ida;
679 };
680 
681 struct mlx5_clock;
682 struct mlx5_dm;
683 struct mlx5_fw_tracer;
684 struct mlx5_vxlan;
685 struct mlx5_geneve;
686 struct mlx5_hv_vhca;
687 
688 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
689 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
690 
691 enum {
692 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
693 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
694 };
695 
696 enum {
697 	MKEY_CACHE_LAST_STD_ENTRY = 20,
698 	MLX5_IMR_KSM_CACHE_ENTRY,
699 	MAX_MKEY_CACHE_ENTRIES
700 };
701 
702 struct mlx5_profile {
703 	u64	mask;
704 	u8	log_max_qp;
705 	u8	num_cmd_caches;
706 	struct {
707 		int	size;
708 		int	limit;
709 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
710 };
711 
712 struct mlx5_hca_cap {
713 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
714 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
715 };
716 
717 enum mlx5_wc_state {
718 	MLX5_WC_STATE_UNINITIALIZED,
719 	MLX5_WC_STATE_UNSUPPORTED,
720 	MLX5_WC_STATE_SUPPORTED,
721 };
722 
723 struct mlx5_core_dev {
724 	struct device *device;
725 	enum mlx5_coredev_type coredev_type;
726 	struct pci_dev	       *pdev;
727 	/* sync pci state */
728 	struct mutex		pci_status_mutex;
729 	enum mlx5_pci_status	pci_status;
730 	u8			rev_id;
731 	char			board_id[MLX5_BOARD_ID_LEN];
732 	struct mlx5_cmd		cmd;
733 	struct {
734 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
735 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
736 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
737 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
738 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
739 		u8  embedded_cpu;
740 	} caps;
741 	struct mlx5_timeouts	*timeouts;
742 	u64			sys_image_guid;
743 	phys_addr_t		iseg_base;
744 	struct mlx5_init_seg __iomem *iseg;
745 	phys_addr_t             bar_addr;
746 	enum mlx5_device_state	state;
747 	/* sync interface state */
748 	struct mutex		intf_state_mutex;
749 	struct lock_class_key	lock_key;
750 	unsigned long		intf_state;
751 	struct mlx5_priv	priv;
752 	struct mlx5_profile	profile;
753 	u32			issi;
754 	struct mlx5e_resources  mlx5e_res;
755 	struct mlx5_dm          *dm;
756 	struct mlx5_vxlan       *vxlan;
757 	struct mlx5_geneve      *geneve;
758 	struct {
759 		struct mlx5_rsvd_gids	reserved_gids;
760 		u32			roce_en;
761 	} roce;
762 #ifdef CONFIG_MLX5_FPGA
763 	struct mlx5_fpga_device *fpga;
764 #endif
765 	struct mlx5_clock       *clock;
766 	struct mlx5_ib_clock_info  *clock_info;
767 	struct mlx5_fw_tracer   *tracer;
768 	struct mlx5_rsc_dump    *rsc_dump;
769 	u32                      vsc_addr;
770 	struct mlx5_hv_vhca	*hv_vhca;
771 	struct mlx5_hwmon	*hwmon;
772 	u64			num_block_tc;
773 	u64			num_block_ipsec;
774 #ifdef CONFIG_MLX5_MACSEC
775 	struct mlx5_macsec_fs *macsec_fs;
776 	/* MACsec notifier chain to sync MACsec core and IB database */
777 	struct blocking_notifier_head macsec_nh;
778 #endif
779 	u64 num_ipsec_offloads;
780 	struct mlx5_sd          *sd;
781 	enum mlx5_wc_state wc_state;
782 	/* sync write combining state */
783 	struct mutex wc_state_lock;
784 };
785 
786 struct mlx5_db {
787 	__be32			*db;
788 	union {
789 		struct mlx5_db_pgdir		*pgdir;
790 		struct mlx5_ib_user_db_page	*user_page;
791 	}			u;
792 	dma_addr_t		dma;
793 	int			index;
794 };
795 
796 enum {
797 	MLX5_COMP_EQ_SIZE = 1024,
798 };
799 
800 enum {
801 	MLX5_PTYS_IB = 1 << 0,
802 	MLX5_PTYS_EN = 1 << 2,
803 };
804 
805 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
806 
807 enum {
808 	MLX5_CMD_ENT_STATE_PENDING_COMP,
809 };
810 
811 struct mlx5_cmd_work_ent {
812 	unsigned long		state;
813 	struct mlx5_cmd_msg    *in;
814 	struct mlx5_cmd_msg    *out;
815 	void		       *uout;
816 	int			uout_size;
817 	mlx5_cmd_cbk_t		callback;
818 	struct delayed_work	cb_timeout_work;
819 	void		       *context;
820 	int			idx;
821 	struct completion	handling;
822 	struct completion	slotted;
823 	struct completion	done;
824 	struct mlx5_cmd        *cmd;
825 	struct work_struct	work;
826 	struct mlx5_cmd_layout *lay;
827 	int			ret;
828 	int			page_queue;
829 	u8			status;
830 	u8			token;
831 	u64			ts1;
832 	u64			ts2;
833 	u16			op;
834 	bool			polling;
835 	/* Track the max comp handlers */
836 	refcount_t              refcnt;
837 };
838 
839 enum phy_port_state {
840 	MLX5_AAA_111
841 };
842 
843 struct mlx5_hca_vport_context {
844 	u32			field_select;
845 	bool			sm_virt_aware;
846 	bool			has_smi;
847 	bool			has_raw;
848 	enum port_state_policy	policy;
849 	enum phy_port_state	phys_state;
850 	enum ib_port_state	vport_state;
851 	u8			port_physical_state;
852 	u64			sys_image_guid;
853 	u64			port_guid;
854 	u64			node_guid;
855 	u32			cap_mask1;
856 	u32			cap_mask1_perm;
857 	u16			cap_mask2;
858 	u16			cap_mask2_perm;
859 	u16			lid;
860 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
861 	u8			lmc;
862 	u8			subnet_timeout;
863 	u16			sm_lid;
864 	u8			sm_sl;
865 	u16			qkey_violation_counter;
866 	u16			pkey_violation_counter;
867 	bool			grh_required;
868 	u8			num_plane;
869 };
870 
871 #define STRUCT_FIELD(header, field) \
872 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
873 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
874 
875 extern struct dentry *mlx5_debugfs_root;
876 
877 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
878 {
879 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
880 }
881 
882 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
883 {
884 	return ioread32be(&dev->iseg->fw_rev) >> 16;
885 }
886 
887 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
888 {
889 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
890 }
891 
892 static inline u32 mlx5_base_mkey(const u32 key)
893 {
894 	return key & 0xffffff00u;
895 }
896 
897 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
898 {
899 	return ((u32)1 << log_sz) << log_stride;
900 }
901 
902 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
903 					u8 log_stride, u8 log_sz,
904 					u16 strides_offset,
905 					struct mlx5_frag_buf_ctrl *fbc)
906 {
907 	fbc->frags      = frags;
908 	fbc->log_stride = log_stride;
909 	fbc->log_sz     = log_sz;
910 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
911 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
912 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
913 	fbc->strides_offset = strides_offset;
914 }
915 
916 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
917 				 u8 log_stride, u8 log_sz,
918 				 struct mlx5_frag_buf_ctrl *fbc)
919 {
920 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
921 }
922 
923 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
924 					  u32 ix)
925 {
926 	unsigned int frag;
927 
928 	ix  += fbc->strides_offset;
929 	frag = ix >> fbc->log_frag_strides;
930 
931 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
932 }
933 
934 static inline u32
935 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
936 {
937 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
938 
939 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
940 }
941 
942 enum {
943 	CMD_ALLOWED_OPCODE_ALL,
944 };
945 
946 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
947 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
948 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
949 
950 struct mlx5_async_ctx {
951 	struct mlx5_core_dev *dev;
952 	atomic_t num_inflight;
953 	struct completion inflight_done;
954 };
955 
956 struct mlx5_async_work;
957 
958 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
959 
960 struct mlx5_async_work {
961 	struct mlx5_async_ctx *ctx;
962 	mlx5_async_cbk_t user_callback;
963 	u16 opcode; /* cmd opcode */
964 	u16 op_mod; /* cmd op_mod */
965 	void *out; /* pointer to the cmd output buffer */
966 };
967 
968 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
969 			     struct mlx5_async_ctx *ctx);
970 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
971 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
972 		     void *out, int out_size, mlx5_async_cbk_t callback,
973 		     struct mlx5_async_work *work);
974 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
975 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
976 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
977 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
978 		  int out_size);
979 
980 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
981 	({                                                                     \
982 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
983 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
984 	})
985 
986 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
987 	({                                                                     \
988 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
989 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
990 	})
991 
992 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
993 			  void *out, int out_size);
994 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
995 
996 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
997 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
998 
999 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1000 
1001 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1002 int mlx5_health_init(struct mlx5_core_dev *dev);
1003 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1004 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1005 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1006 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1007 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1008 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1009 			     struct mlx5_frag_buf *buf, int node);
1010 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1011 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1012 			  int inlen);
1013 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1014 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1015 			 int outlen);
1016 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1017 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1018 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1019 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1020 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1021 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1022 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1023 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1024 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1025 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1026 void mlx5_register_debugfs(void);
1027 void mlx5_unregister_debugfs(void);
1028 
1029 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1030 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1031 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1032 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1033 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1034 
1035 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1036 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1037 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1038 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1039 		    void *data_out, int size_out, u16 reg_id, int arg,
1040 		    int write, bool verbose);
1041 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1042 			 int size_in, void *data_out, int size_out,
1043 			 u16 reg_num, int arg, int write);
1044 
1045 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1046 		       int node);
1047 
1048 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1049 {
1050 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1051 }
1052 
1053 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1054 
1055 const char *mlx5_command_str(int command);
1056 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1057 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1058 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1059 			 int npsvs, u32 *sig_index);
1060 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1061 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1062 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1063 
1064 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1065 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1066 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1067 		     struct mlx5_rate_limit *rl);
1068 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1069 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1070 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1071 			 bool dedicated_entry, u16 *index);
1072 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1073 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1074 		       struct mlx5_rate_limit *rl_1);
1075 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1076 		     bool map_wc, bool fast_path);
1077 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1078 
1079 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1080 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1081 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1082 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1083 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1084 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1085 
1086 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1087 {
1088 	return mkey >> 8;
1089 }
1090 
1091 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1092 {
1093 	return mkey_idx << 8;
1094 }
1095 
1096 static inline u8 mlx5_mkey_variant(u32 mkey)
1097 {
1098 	return mkey & 0xff;
1099 }
1100 
1101 /* Async-atomic event notifier used by mlx5 core to forward FW
1102  * evetns received from event queue to mlx5 consumers.
1103  * Optimise event queue dipatching.
1104  */
1105 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1106 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1107 
1108 /* Async-atomic event notifier used for forwarding
1109  * evetns from the event queue into the to mlx5 events dispatcher,
1110  * eswitch, clock and others.
1111  */
1112 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1113 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1114 
1115 /* Blocking event notifier used to forward SW events, used for slow path */
1116 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1117 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1118 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1119 				      void *data);
1120 
1121 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1122 
1123 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1124 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1125 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1126 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1127 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1128 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1129 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1130 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1131 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1132 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1133 			   struct net_device *slave);
1134 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1135 				 u64 *values,
1136 				 int num_counters,
1137 				 size_t *offsets);
1138 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1139 
1140 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1141 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1142 	     peer;								\
1143 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1144 
1145 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1146 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1147 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1148 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1149 			 u64 length, u32 log_alignment, u16 uid,
1150 			 phys_addr_t *addr, u32 *obj_id);
1151 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1152 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1153 
1154 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1155 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1156 
1157 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1158 					  int vf_id,
1159 					  struct notifier_block *nb);
1160 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1161 					     int vf_id,
1162 					     struct notifier_block *nb);
1163 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1164 			    struct ib_device *device,
1165 			    struct rdma_netdev_alloc_params *params);
1166 
1167 enum {
1168 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1169 };
1170 
1171 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1172 {
1173 	return dev->coredev_type == MLX5_COREDEV_PF;
1174 }
1175 
1176 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1177 {
1178 	return dev->coredev_type == MLX5_COREDEV_VF;
1179 }
1180 
1181 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1182 					       const struct mlx5_core_dev *dev2)
1183 {
1184 	return dev1->coredev_type == dev2->coredev_type;
1185 }
1186 
1187 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1188 {
1189 	return dev->caps.embedded_cpu;
1190 }
1191 
1192 static inline bool
1193 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1194 {
1195 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1196 }
1197 
1198 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1199 {
1200 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1201 }
1202 
1203 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1204 {
1205 	return dev->priv.sriov.max_vfs;
1206 }
1207 
1208 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1209 {
1210 	/* LACP owner conditions:
1211 	 * 1) Function is physical.
1212 	 * 2) LAG is supported by FW.
1213 	 * 3) LAG is managed by driver (currently the only option).
1214 	 */
1215 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1216 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1217 		    MLX5_CAP_GEN(dev, lag_master);
1218 }
1219 
1220 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1221 {
1222 	return dev->priv.sriov.max_ec_vfs;
1223 }
1224 
1225 static inline int mlx5_get_gid_table_len(u16 param)
1226 {
1227 	if (param > 4) {
1228 		pr_warn("gid table length is zero\n");
1229 		return 0;
1230 	}
1231 
1232 	return 8 * (1 << param);
1233 }
1234 
1235 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1236 {
1237 	return !!(dev->priv.rl_table.max_size);
1238 }
1239 
1240 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1241 {
1242 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1243 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1244 }
1245 
1246 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1247 {
1248 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1249 }
1250 
1251 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1252 {
1253 	return mlx5_core_is_mp_slave(dev) ||
1254 	       mlx5_core_is_mp_master(dev);
1255 }
1256 
1257 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1258 {
1259 	if (!mlx5_core_mp_enabled(dev))
1260 		return 1;
1261 
1262 	return MLX5_CAP_GEN(dev, native_port_num);
1263 }
1264 
1265 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1266 {
1267 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1268 
1269 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1270 		return idx - 1;
1271 	else
1272 		return PCI_FUNC(dev->pdev->devfn);
1273 }
1274 
1275 enum {
1276 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1277 };
1278 
1279 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1280 
1281 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1282 {
1283 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1284 		return MLX5_CAP_GEN(dev, roce);
1285 
1286 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1287 	 * in order to support RoCE enable/disable feature
1288 	 */
1289 	return mlx5_is_roce_on(dev);
1290 }
1291 
1292 #ifdef CONFIG_MLX5_MACSEC
1293 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1294 {
1295 	if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1296 	    MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1297 		return false;
1298 
1299 	if (!MLX5_CAP_GEN(mdev, log_max_dek))
1300 		return false;
1301 
1302 	if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1303 		return false;
1304 
1305 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1306 	    !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1307 		return false;
1308 
1309 	if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1310 	    !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1311 		return false;
1312 
1313 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1314 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1315 		return false;
1316 
1317 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1318 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1319 		return false;
1320 
1321 	return true;
1322 }
1323 
1324 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1325 
1326 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1327 {
1328 	if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1329 	     NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1330 	     !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1331 	     !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1332 		return false;
1333 
1334 	return true;
1335 }
1336 #endif
1337 
1338 enum {
1339 	MLX5_OCTWORD = 16,
1340 };
1341 
1342 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1343 #endif /* MLX5_DRIVER_H */
1344