xref: /linux-6.15/include/linux/mlx5/driver.h (revision efe4a1ac) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/mempool.h>
46 #include <linux/interrupt.h>
47 
48 #include <linux/mlx5/device.h>
49 #include <linux/mlx5/doorbell.h>
50 #include <linux/mlx5/srq.h>
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	/* one minute for the sake of bringup. Generally, commands must always
59 	 * complete and we may need to increase this timeout value
60 	 */
61 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
62 	MLX5_CMD_WQ_MAX_NAME	= 32,
63 };
64 
65 enum {
66 	CMD_OWNER_SW		= 0x0,
67 	CMD_OWNER_HW		= 0x1,
68 	CMD_STATUS_SUCCESS	= 0,
69 };
70 
71 enum mlx5_sqp_t {
72 	MLX5_SQP_SMI		= 0,
73 	MLX5_SQP_GSI		= 1,
74 	MLX5_SQP_IEEE_1588	= 2,
75 	MLX5_SQP_SNIFFER	= 3,
76 	MLX5_SQP_SYNC_UMR	= 4,
77 };
78 
79 enum {
80 	MLX5_MAX_PORTS	= 2,
81 };
82 
83 enum {
84 	MLX5_EQ_VEC_PAGES	 = 0,
85 	MLX5_EQ_VEC_CMD		 = 1,
86 	MLX5_EQ_VEC_ASYNC	 = 2,
87 	MLX5_EQ_VEC_PFAULT	 = 3,
88 	MLX5_EQ_VEC_COMP_BASE,
89 };
90 
91 enum {
92 	MLX5_MAX_IRQ_NAME	= 32
93 };
94 
95 enum {
96 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << 16,
97 	MLX5_ATOMIC_MODE_CX		= 2 << 16,
98 	MLX5_ATOMIC_MODE_8B		= 3 << 16,
99 	MLX5_ATOMIC_MODE_16B		= 4 << 16,
100 	MLX5_ATOMIC_MODE_32B		= 5 << 16,
101 	MLX5_ATOMIC_MODE_64B		= 6 << 16,
102 	MLX5_ATOMIC_MODE_128B		= 7 << 16,
103 	MLX5_ATOMIC_MODE_256B		= 8 << 16,
104 };
105 
106 enum {
107 	MLX5_REG_QETCR		 = 0x4005,
108 	MLX5_REG_QTCT		 = 0x400a,
109 	MLX5_REG_DCBX_PARAM      = 0x4020,
110 	MLX5_REG_DCBX_APP        = 0x4021,
111 	MLX5_REG_PCAP		 = 0x5001,
112 	MLX5_REG_PMTU		 = 0x5003,
113 	MLX5_REG_PTYS		 = 0x5004,
114 	MLX5_REG_PAOS		 = 0x5006,
115 	MLX5_REG_PFCC            = 0x5007,
116 	MLX5_REG_PPCNT		 = 0x5008,
117 	MLX5_REG_PMAOS		 = 0x5012,
118 	MLX5_REG_PUDE		 = 0x5009,
119 	MLX5_REG_PMPE		 = 0x5010,
120 	MLX5_REG_PELC		 = 0x500e,
121 	MLX5_REG_PVLC		 = 0x500f,
122 	MLX5_REG_PCMR		 = 0x5041,
123 	MLX5_REG_PMLP		 = 0x5002,
124 	MLX5_REG_PCAM		 = 0x507f,
125 	MLX5_REG_NODE_DESC	 = 0x6001,
126 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
127 	MLX5_REG_MCIA		 = 0x9014,
128 	MLX5_REG_MLCR		 = 0x902b,
129 	MLX5_REG_MPCNT		 = 0x9051,
130 	MLX5_REG_MTPPS		 = 0x9053,
131 	MLX5_REG_MTPPSE		 = 0x9054,
132 	MLX5_REG_MCAM		 = 0x907f,
133 };
134 
135 enum mlx5_dcbx_oper_mode {
136 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
137 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
138 };
139 
140 enum {
141 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
142 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
143 };
144 
145 enum mlx5_page_fault_resume_flags {
146 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
147 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
148 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
149 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
150 };
151 
152 enum dbg_rsc_type {
153 	MLX5_DBG_RSC_QP,
154 	MLX5_DBG_RSC_EQ,
155 	MLX5_DBG_RSC_CQ,
156 };
157 
158 struct mlx5_field_desc {
159 	struct dentry	       *dent;
160 	int			i;
161 };
162 
163 struct mlx5_rsc_debug {
164 	struct mlx5_core_dev   *dev;
165 	void		       *object;
166 	enum dbg_rsc_type	type;
167 	struct dentry	       *root;
168 	struct mlx5_field_desc	fields[0];
169 };
170 
171 enum mlx5_dev_event {
172 	MLX5_DEV_EVENT_SYS_ERROR,
173 	MLX5_DEV_EVENT_PORT_UP,
174 	MLX5_DEV_EVENT_PORT_DOWN,
175 	MLX5_DEV_EVENT_PORT_INITIALIZED,
176 	MLX5_DEV_EVENT_LID_CHANGE,
177 	MLX5_DEV_EVENT_PKEY_CHANGE,
178 	MLX5_DEV_EVENT_GUID_CHANGE,
179 	MLX5_DEV_EVENT_CLIENT_REREG,
180 	MLX5_DEV_EVENT_PPS,
181 };
182 
183 enum mlx5_port_status {
184 	MLX5_PORT_UP        = 1,
185 	MLX5_PORT_DOWN      = 2,
186 };
187 
188 enum mlx5_eq_type {
189 	MLX5_EQ_TYPE_COMP,
190 	MLX5_EQ_TYPE_ASYNC,
191 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
192 	MLX5_EQ_TYPE_PF,
193 #endif
194 };
195 
196 struct mlx5_bfreg_info {
197 	u32		       *sys_pages;
198 	int			num_low_latency_bfregs;
199 	unsigned int	       *count;
200 
201 	/*
202 	 * protect bfreg allocation data structs
203 	 */
204 	struct mutex		lock;
205 	u32			ver;
206 	bool			lib_uar_4k;
207 	u32			num_sys_pages;
208 };
209 
210 struct mlx5_cmd_first {
211 	__be32		data[4];
212 };
213 
214 struct mlx5_cmd_msg {
215 	struct list_head		list;
216 	struct cmd_msg_cache	       *parent;
217 	u32				len;
218 	struct mlx5_cmd_first		first;
219 	struct mlx5_cmd_mailbox	       *next;
220 };
221 
222 struct mlx5_cmd_debug {
223 	struct dentry	       *dbg_root;
224 	struct dentry	       *dbg_in;
225 	struct dentry	       *dbg_out;
226 	struct dentry	       *dbg_outlen;
227 	struct dentry	       *dbg_status;
228 	struct dentry	       *dbg_run;
229 	void		       *in_msg;
230 	void		       *out_msg;
231 	u8			status;
232 	u16			inlen;
233 	u16			outlen;
234 };
235 
236 struct cmd_msg_cache {
237 	/* protect block chain allocations
238 	 */
239 	spinlock_t		lock;
240 	struct list_head	head;
241 	unsigned int		max_inbox_size;
242 	unsigned int		num_ent;
243 };
244 
245 enum {
246 	MLX5_NUM_COMMAND_CACHES = 5,
247 };
248 
249 struct mlx5_cmd_stats {
250 	u64		sum;
251 	u64		n;
252 	struct dentry  *root;
253 	struct dentry  *avg;
254 	struct dentry  *count;
255 	/* protect command average calculations */
256 	spinlock_t	lock;
257 };
258 
259 struct mlx5_cmd {
260 	void	       *cmd_alloc_buf;
261 	dma_addr_t	alloc_dma;
262 	int		alloc_size;
263 	void	       *cmd_buf;
264 	dma_addr_t	dma;
265 	u16		cmdif_rev;
266 	u8		log_sz;
267 	u8		log_stride;
268 	int		max_reg_cmds;
269 	int		events;
270 	u32 __iomem    *vector;
271 
272 	/* protect command queue allocations
273 	 */
274 	spinlock_t	alloc_lock;
275 
276 	/* protect token allocations
277 	 */
278 	spinlock_t	token_lock;
279 	u8		token;
280 	unsigned long	bitmask;
281 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
282 	struct workqueue_struct *wq;
283 	struct semaphore sem;
284 	struct semaphore pages_sem;
285 	int	mode;
286 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
287 	struct pci_pool *pool;
288 	struct mlx5_cmd_debug dbg;
289 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
290 	int checksum_disabled;
291 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
292 };
293 
294 struct mlx5_port_caps {
295 	int	gid_table_len;
296 	int	pkey_table_len;
297 	u8	ext_port_cap;
298 	bool	has_smi;
299 };
300 
301 struct mlx5_cmd_mailbox {
302 	void	       *buf;
303 	dma_addr_t	dma;
304 	struct mlx5_cmd_mailbox *next;
305 };
306 
307 struct mlx5_buf_list {
308 	void		       *buf;
309 	dma_addr_t		map;
310 };
311 
312 struct mlx5_buf {
313 	struct mlx5_buf_list	direct;
314 	int			npages;
315 	int			size;
316 	u8			page_shift;
317 };
318 
319 struct mlx5_frag_buf {
320 	struct mlx5_buf_list	*frags;
321 	int			npages;
322 	int			size;
323 	u8			page_shift;
324 };
325 
326 struct mlx5_eq_tasklet {
327 	struct list_head list;
328 	struct list_head process_list;
329 	struct tasklet_struct task;
330 	/* lock on completion tasklet list */
331 	spinlock_t lock;
332 };
333 
334 struct mlx5_eq_pagefault {
335 	struct work_struct       work;
336 	/* Pagefaults lock */
337 	spinlock_t		 lock;
338 	struct workqueue_struct *wq;
339 	mempool_t		*pool;
340 };
341 
342 struct mlx5_eq {
343 	struct mlx5_core_dev   *dev;
344 	__be32 __iomem	       *doorbell;
345 	u32			cons_index;
346 	struct mlx5_buf		buf;
347 	int			size;
348 	unsigned int		irqn;
349 	u8			eqn;
350 	int			nent;
351 	u64			mask;
352 	struct list_head	list;
353 	int			index;
354 	struct mlx5_rsc_debug	*dbg;
355 	enum mlx5_eq_type	type;
356 	union {
357 		struct mlx5_eq_tasklet   tasklet_ctx;
358 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
359 		struct mlx5_eq_pagefault pf_ctx;
360 #endif
361 	};
362 };
363 
364 struct mlx5_core_psv {
365 	u32	psv_idx;
366 	struct psv_layout {
367 		u32	pd;
368 		u16	syndrome;
369 		u16	reserved;
370 		u16	bg;
371 		u16	app_tag;
372 		u32	ref_tag;
373 	} psv;
374 };
375 
376 struct mlx5_core_sig_ctx {
377 	struct mlx5_core_psv	psv_memory;
378 	struct mlx5_core_psv	psv_wire;
379 	struct ib_sig_err       err_item;
380 	bool			sig_status_checked;
381 	bool			sig_err_exists;
382 	u32			sigerr_count;
383 };
384 
385 enum {
386 	MLX5_MKEY_MR = 1,
387 	MLX5_MKEY_MW,
388 };
389 
390 struct mlx5_core_mkey {
391 	u64			iova;
392 	u64			size;
393 	u32			key;
394 	u32			pd;
395 	u32			type;
396 };
397 
398 #define MLX5_24BIT_MASK		((1 << 24) - 1)
399 
400 enum mlx5_res_type {
401 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
402 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
403 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
404 	MLX5_RES_SRQ	= 3,
405 	MLX5_RES_XSRQ	= 4,
406 };
407 
408 struct mlx5_core_rsc_common {
409 	enum mlx5_res_type	res;
410 	atomic_t		refcount;
411 	struct completion	free;
412 };
413 
414 struct mlx5_core_srq {
415 	struct mlx5_core_rsc_common	common; /* must be first */
416 	u32		srqn;
417 	int		max;
418 	int		max_gs;
419 	int		max_avail_gather;
420 	int		wqe_shift;
421 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
422 
423 	atomic_t		refcount;
424 	struct completion	free;
425 };
426 
427 struct mlx5_eq_table {
428 	void __iomem	       *update_ci;
429 	void __iomem	       *update_arm_ci;
430 	struct list_head	comp_eqs_list;
431 	struct mlx5_eq		pages_eq;
432 	struct mlx5_eq		async_eq;
433 	struct mlx5_eq		cmd_eq;
434 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
435 	struct mlx5_eq		pfault_eq;
436 #endif
437 	int			num_comp_vectors;
438 	/* protect EQs list
439 	 */
440 	spinlock_t		lock;
441 };
442 
443 struct mlx5_uars_page {
444 	void __iomem	       *map;
445 	bool			wc;
446 	u32			index;
447 	struct list_head	list;
448 	unsigned int		bfregs;
449 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
450 	unsigned long	       *fp_bitmap;
451 	unsigned int		reg_avail;
452 	unsigned int		fp_avail;
453 	struct kref		ref_count;
454 	struct mlx5_core_dev   *mdev;
455 };
456 
457 struct mlx5_bfreg_head {
458 	/* protect blue flame registers allocations */
459 	struct mutex		lock;
460 	struct list_head	list;
461 };
462 
463 struct mlx5_bfreg_data {
464 	struct mlx5_bfreg_head	reg_head;
465 	struct mlx5_bfreg_head	wc_head;
466 };
467 
468 struct mlx5_sq_bfreg {
469 	void __iomem	       *map;
470 	struct mlx5_uars_page  *up;
471 	bool			wc;
472 	u32			index;
473 	unsigned int		offset;
474 };
475 
476 struct mlx5_core_health {
477 	struct health_buffer __iomem   *health;
478 	__be32 __iomem		       *health_counter;
479 	struct timer_list		timer;
480 	u32				prev;
481 	int				miss_counter;
482 	bool				sick;
483 	/* wq spinlock to synchronize draining */
484 	spinlock_t			wq_lock;
485 	struct workqueue_struct	       *wq;
486 	unsigned long			flags;
487 	struct work_struct		work;
488 	struct delayed_work		recover_work;
489 };
490 
491 struct mlx5_cq_table {
492 	/* protect radix tree
493 	 */
494 	spinlock_t		lock;
495 	struct radix_tree_root	tree;
496 };
497 
498 struct mlx5_qp_table {
499 	/* protect radix tree
500 	 */
501 	spinlock_t		lock;
502 	struct radix_tree_root	tree;
503 };
504 
505 struct mlx5_srq_table {
506 	/* protect radix tree
507 	 */
508 	spinlock_t		lock;
509 	struct radix_tree_root	tree;
510 };
511 
512 struct mlx5_mkey_table {
513 	/* protect radix tree
514 	 */
515 	rwlock_t		lock;
516 	struct radix_tree_root	tree;
517 };
518 
519 struct mlx5_vf_context {
520 	int	enabled;
521 };
522 
523 struct mlx5_core_sriov {
524 	struct mlx5_vf_context	*vfs_ctx;
525 	int			num_vfs;
526 	int			enabled_vfs;
527 };
528 
529 struct mlx5_irq_info {
530 	cpumask_var_t mask;
531 	char name[MLX5_MAX_IRQ_NAME];
532 };
533 
534 struct mlx5_fc_stats {
535 	struct rb_root counters;
536 	struct list_head addlist;
537 	/* protect addlist add/splice operations */
538 	spinlock_t addlist_lock;
539 
540 	struct workqueue_struct *wq;
541 	struct delayed_work work;
542 	unsigned long next_query;
543 	unsigned long sampling_interval; /* jiffies */
544 };
545 
546 struct mlx5_eswitch;
547 struct mlx5_lag;
548 struct mlx5_pagefault;
549 
550 struct mlx5_rl_entry {
551 	u32                     rate;
552 	u16                     index;
553 	u16                     refcount;
554 };
555 
556 struct mlx5_rl_table {
557 	/* protect rate limit table */
558 	struct mutex            rl_lock;
559 	u16                     max_size;
560 	u32                     max_rate;
561 	u32                     min_rate;
562 	struct mlx5_rl_entry   *rl_entry;
563 };
564 
565 enum port_module_event_status_type {
566 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
567 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
568 	MLX5_MODULE_STATUS_ERROR     = 0x3,
569 	MLX5_MODULE_STATUS_NUM       = 0x3,
570 };
571 
572 enum  port_module_event_error_type {
573 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
574 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
575 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
576 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
577 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
578 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
579 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
580 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
581 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
582 	MLX5_MODULE_EVENT_ERROR_NUM,
583 };
584 
585 struct mlx5_port_module_event_stats {
586 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
587 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
588 };
589 
590 struct mlx5_priv {
591 	char			name[MLX5_MAX_NAME_LEN];
592 	struct mlx5_eq_table	eq_table;
593 	struct msix_entry	*msix_arr;
594 	struct mlx5_irq_info	*irq_info;
595 
596 	/* pages stuff */
597 	struct workqueue_struct *pg_wq;
598 	struct rb_root		page_root;
599 	int			fw_pages;
600 	atomic_t		reg_pages;
601 	struct list_head	free_list;
602 	int			vfs_pages;
603 
604 	struct mlx5_core_health health;
605 
606 	struct mlx5_srq_table	srq_table;
607 
608 	/* start: qp staff */
609 	struct mlx5_qp_table	qp_table;
610 	struct dentry	       *qp_debugfs;
611 	struct dentry	       *eq_debugfs;
612 	struct dentry	       *cq_debugfs;
613 	struct dentry	       *cmdif_debugfs;
614 	/* end: qp staff */
615 
616 	/* start: cq staff */
617 	struct mlx5_cq_table	cq_table;
618 	/* end: cq staff */
619 
620 	/* start: mkey staff */
621 	struct mlx5_mkey_table	mkey_table;
622 	/* end: mkey staff */
623 
624 	/* start: alloc staff */
625 	/* protect buffer alocation according to numa node */
626 	struct mutex            alloc_mutex;
627 	int                     numa_node;
628 
629 	struct mutex            pgdir_mutex;
630 	struct list_head        pgdir_list;
631 	/* end: alloc staff */
632 	struct dentry	       *dbg_root;
633 
634 	/* protect mkey key part */
635 	spinlock_t		mkey_lock;
636 	u8			mkey_key;
637 
638 	struct list_head        dev_list;
639 	struct list_head        ctx_list;
640 	spinlock_t              ctx_lock;
641 
642 	struct mlx5_flow_steering *steering;
643 	struct mlx5_eswitch     *eswitch;
644 	struct mlx5_core_sriov	sriov;
645 	struct mlx5_lag		*lag;
646 	unsigned long		pci_dev_data;
647 	struct mlx5_fc_stats		fc_stats;
648 	struct mlx5_rl_table            rl_table;
649 
650 	struct mlx5_port_module_event_stats  pme_stats;
651 
652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
653 	void		      (*pfault)(struct mlx5_core_dev *dev,
654 					void *context,
655 					struct mlx5_pagefault *pfault);
656 	void		       *pfault_ctx;
657 	struct srcu_struct      pfault_srcu;
658 #endif
659 	struct mlx5_bfreg_data		bfregs;
660 	struct mlx5_uars_page	       *uar;
661 };
662 
663 enum mlx5_device_state {
664 	MLX5_DEVICE_STATE_UP,
665 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
666 };
667 
668 enum mlx5_interface_state {
669 	MLX5_INTERFACE_STATE_DOWN = BIT(0),
670 	MLX5_INTERFACE_STATE_UP = BIT(1),
671 	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
672 };
673 
674 enum mlx5_pci_status {
675 	MLX5_PCI_STATUS_DISABLED,
676 	MLX5_PCI_STATUS_ENABLED,
677 };
678 
679 enum mlx5_pagefault_type_flags {
680 	MLX5_PFAULT_REQUESTOR = 1 << 0,
681 	MLX5_PFAULT_WRITE     = 1 << 1,
682 	MLX5_PFAULT_RDMA      = 1 << 2,
683 };
684 
685 /* Contains the details of a pagefault. */
686 struct mlx5_pagefault {
687 	u32			bytes_committed;
688 	u32			token;
689 	u8			event_subtype;
690 	u8			type;
691 	union {
692 		/* Initiator or send message responder pagefault details. */
693 		struct {
694 			/* Received packet size, only valid for responders. */
695 			u32	packet_size;
696 			/*
697 			 * Number of resource holding WQE, depends on type.
698 			 */
699 			u32	wq_num;
700 			/*
701 			 * WQE index. Refers to either the send queue or
702 			 * receive queue, according to event_subtype.
703 			 */
704 			u16	wqe_index;
705 		} wqe;
706 		/* RDMA responder pagefault details */
707 		struct {
708 			u32	r_key;
709 			/*
710 			 * Received packet size, minimal size page fault
711 			 * resolution required for forward progress.
712 			 */
713 			u32	packet_size;
714 			u32	rdma_op_len;
715 			u64	rdma_va;
716 		} rdma;
717 	};
718 
719 	struct mlx5_eq	       *eq;
720 	struct work_struct	work;
721 };
722 
723 struct mlx5_td {
724 	struct list_head tirs_list;
725 	u32              tdn;
726 };
727 
728 struct mlx5e_resources {
729 	u32                        pdn;
730 	struct mlx5_td             td;
731 	struct mlx5_core_mkey      mkey;
732 	struct mlx5_sq_bfreg       bfreg;
733 };
734 
735 struct mlx5_core_dev {
736 	struct pci_dev	       *pdev;
737 	/* sync pci state */
738 	struct mutex		pci_status_mutex;
739 	enum mlx5_pci_status	pci_status;
740 	u8			rev_id;
741 	char			board_id[MLX5_BOARD_ID_LEN];
742 	struct mlx5_cmd		cmd;
743 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
744 	struct {
745 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
746 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
747 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
748 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
749 	} caps;
750 	phys_addr_t		iseg_base;
751 	struct mlx5_init_seg __iomem *iseg;
752 	enum mlx5_device_state	state;
753 	/* sync interface state */
754 	struct mutex		intf_state_mutex;
755 	unsigned long		intf_state;
756 	void			(*event) (struct mlx5_core_dev *dev,
757 					  enum mlx5_dev_event event,
758 					  unsigned long param);
759 	struct mlx5_priv	priv;
760 	struct mlx5_profile	*profile;
761 	atomic_t		num_qps;
762 	u32			issi;
763 	struct mlx5e_resources  mlx5e_res;
764 #ifdef CONFIG_RFS_ACCEL
765 	struct cpu_rmap         *rmap;
766 #endif
767 };
768 
769 struct mlx5_db {
770 	__be32			*db;
771 	union {
772 		struct mlx5_db_pgdir		*pgdir;
773 		struct mlx5_ib_user_db_page	*user_page;
774 	}			u;
775 	dma_addr_t		dma;
776 	int			index;
777 };
778 
779 enum {
780 	MLX5_COMP_EQ_SIZE = 1024,
781 };
782 
783 enum {
784 	MLX5_PTYS_IB = 1 << 0,
785 	MLX5_PTYS_EN = 1 << 2,
786 };
787 
788 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
789 
790 enum {
791 	MLX5_CMD_ENT_STATE_PENDING_COMP,
792 };
793 
794 struct mlx5_cmd_work_ent {
795 	unsigned long		state;
796 	struct mlx5_cmd_msg    *in;
797 	struct mlx5_cmd_msg    *out;
798 	void		       *uout;
799 	int			uout_size;
800 	mlx5_cmd_cbk_t		callback;
801 	struct delayed_work	cb_timeout_work;
802 	void		       *context;
803 	int			idx;
804 	struct completion	done;
805 	struct mlx5_cmd        *cmd;
806 	struct work_struct	work;
807 	struct mlx5_cmd_layout *lay;
808 	int			ret;
809 	int			page_queue;
810 	u8			status;
811 	u8			token;
812 	u64			ts1;
813 	u64			ts2;
814 	u16			op;
815 };
816 
817 struct mlx5_pas {
818 	u64	pa;
819 	u8	log_sz;
820 };
821 
822 enum port_state_policy {
823 	MLX5_POLICY_DOWN	= 0,
824 	MLX5_POLICY_UP		= 1,
825 	MLX5_POLICY_FOLLOW	= 2,
826 	MLX5_POLICY_INVALID	= 0xffffffff
827 };
828 
829 enum phy_port_state {
830 	MLX5_AAA_111
831 };
832 
833 struct mlx5_hca_vport_context {
834 	u32			field_select;
835 	bool			sm_virt_aware;
836 	bool			has_smi;
837 	bool			has_raw;
838 	enum port_state_policy	policy;
839 	enum phy_port_state	phys_state;
840 	enum ib_port_state	vport_state;
841 	u8			port_physical_state;
842 	u64			sys_image_guid;
843 	u64			port_guid;
844 	u64			node_guid;
845 	u32			cap_mask1;
846 	u32			cap_mask1_perm;
847 	u32			cap_mask2;
848 	u32			cap_mask2_perm;
849 	u16			lid;
850 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
851 	u8			lmc;
852 	u8			subnet_timeout;
853 	u16			sm_lid;
854 	u8			sm_sl;
855 	u16			qkey_violation_counter;
856 	u16			pkey_violation_counter;
857 	bool			grh_required;
858 };
859 
860 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
861 {
862 		return buf->direct.buf + offset;
863 }
864 
865 extern struct workqueue_struct *mlx5_core_wq;
866 
867 #define STRUCT_FIELD(header, field) \
868 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
869 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
870 
871 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
872 {
873 	return pci_get_drvdata(pdev);
874 }
875 
876 extern struct dentry *mlx5_debugfs_root;
877 
878 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
879 {
880 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
881 }
882 
883 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
884 {
885 	return ioread32be(&dev->iseg->fw_rev) >> 16;
886 }
887 
888 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
889 {
890 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
891 }
892 
893 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
894 {
895 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
896 }
897 
898 static inline void *mlx5_vzalloc(unsigned long size)
899 {
900 	return kvzalloc(size, GFP_KERNEL);
901 }
902 
903 static inline u32 mlx5_base_mkey(const u32 key)
904 {
905 	return key & 0xffffff00u;
906 }
907 
908 int mlx5_cmd_init(struct mlx5_core_dev *dev);
909 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
910 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
911 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
912 
913 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
914 		  int out_size);
915 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
916 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
917 		     void *context);
918 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
919 
920 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
921 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
922 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
923 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
924 int mlx5_health_init(struct mlx5_core_dev *dev);
925 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
926 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
927 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
928 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
929 			struct mlx5_buf *buf, int node);
930 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
931 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
932 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
933 			     struct mlx5_frag_buf *buf, int node);
934 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
935 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
936 						      gfp_t flags, int npages);
937 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
938 				 struct mlx5_cmd_mailbox *head);
939 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
940 			 struct mlx5_srq_attr *in);
941 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
942 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
943 			struct mlx5_srq_attr *out);
944 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
945 		      u16 lwm, int is_srq);
946 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
947 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
948 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
949 			     struct mlx5_core_mkey *mkey,
950 			     u32 *in, int inlen,
951 			     u32 *out, int outlen,
952 			     mlx5_cmd_cbk_t callback, void *context);
953 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
954 			  struct mlx5_core_mkey *mkey,
955 			  u32 *in, int inlen);
956 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
957 			   struct mlx5_core_mkey *mkey);
958 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
959 			 u32 *out, int outlen);
960 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
961 			     u32 *mkey);
962 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
963 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
964 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
965 		      u16 opmod, u8 port);
966 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
967 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
968 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
969 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
970 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
971 				 s32 npages);
972 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
973 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
974 void mlx5_register_debugfs(void);
975 void mlx5_unregister_debugfs(void);
976 int mlx5_eq_init(struct mlx5_core_dev *dev);
977 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
978 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
979 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
980 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
981 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
982 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
983 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
984 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
985 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
986 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
987 		       int nent, u64 mask, const char *name,
988 		       enum mlx5_eq_type type);
989 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
990 int mlx5_start_eqs(struct mlx5_core_dev *dev);
991 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
992 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
993 		    unsigned int *irqn);
994 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
995 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
996 
997 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
998 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
999 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1000 			 int size_in, void *data_out, int size_out,
1001 			 u16 reg_num, int arg, int write);
1002 
1003 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1004 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1005 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1006 		       u32 *out, int outlen);
1007 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1008 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1009 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1010 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1011 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1012 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1013 		       int node);
1014 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1015 
1016 const char *mlx5_command_str(int command);
1017 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1018 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1019 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1020 			 int npsvs, u32 *sig_index);
1021 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1022 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1023 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1024 			struct mlx5_odp_caps *odp_caps);
1025 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1026 			     u8 port_num, void *out, size_t sz);
1027 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1028 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1029 				u32 wq_num, u8 type, int error);
1030 #endif
1031 
1032 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1033 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1034 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1035 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1036 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1037 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1038 		     bool map_wc, bool fast_path);
1039 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1040 
1041 static inline int fw_initializing(struct mlx5_core_dev *dev)
1042 {
1043 	return ioread32be(&dev->iseg->initializing) >> 31;
1044 }
1045 
1046 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1047 {
1048 	return mkey >> 8;
1049 }
1050 
1051 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1052 {
1053 	return mkey_idx << 8;
1054 }
1055 
1056 static inline u8 mlx5_mkey_variant(u32 mkey)
1057 {
1058 	return mkey & 0xff;
1059 }
1060 
1061 enum {
1062 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1063 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1064 };
1065 
1066 enum {
1067 	MAX_UMR_CACHE_ENTRY = 20,
1068 	MLX5_IMR_MTT_CACHE_ENTRY,
1069 	MLX5_IMR_KSM_CACHE_ENTRY,
1070 	MAX_MR_CACHE_ENTRIES
1071 };
1072 
1073 enum {
1074 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1075 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1076 };
1077 
1078 struct mlx5_interface {
1079 	void *			(*add)(struct mlx5_core_dev *dev);
1080 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1081 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1082 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1083 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1084 					 enum mlx5_dev_event event, unsigned long param);
1085 	void			(*pfault)(struct mlx5_core_dev *dev,
1086 					  void *context,
1087 					  struct mlx5_pagefault *pfault);
1088 	void *                  (*get_dev)(void *context);
1089 	int			protocol;
1090 	struct list_head	list;
1091 };
1092 
1093 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1094 int mlx5_register_interface(struct mlx5_interface *intf);
1095 void mlx5_unregister_interface(struct mlx5_interface *intf);
1096 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1097 
1098 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1099 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1100 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1101 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1102 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1103 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1104 
1105 #ifndef CONFIG_MLX5_CORE_IPOIB
1106 static inline
1107 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1108 					  struct ib_device *ibdev,
1109 					  const char *name,
1110 					  void (*setup)(struct net_device *))
1111 {
1112 	return ERR_PTR(-EOPNOTSUPP);
1113 }
1114 
1115 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1116 #else
1117 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1118 					  struct ib_device *ibdev,
1119 					  const char *name,
1120 					  void (*setup)(struct net_device *));
1121 void mlx5_rdma_netdev_free(struct net_device *netdev);
1122 #endif /* CONFIG_MLX5_CORE_IPOIB */
1123 
1124 struct mlx5_profile {
1125 	u64	mask;
1126 	u8	log_max_qp;
1127 	struct {
1128 		int	size;
1129 		int	limit;
1130 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1131 };
1132 
1133 enum {
1134 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1135 };
1136 
1137 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1138 {
1139 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1140 }
1141 
1142 static inline int mlx5_get_gid_table_len(u16 param)
1143 {
1144 	if (param > 4) {
1145 		pr_warn("gid table length is zero\n");
1146 		return 0;
1147 	}
1148 
1149 	return 8 * (1 << param);
1150 }
1151 
1152 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1153 {
1154 	return !!(dev->priv.rl_table.max_size);
1155 }
1156 
1157 enum {
1158 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1159 };
1160 
1161 #endif /* MLX5_DRIVER_H */
1162