1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 51 #include <linux/mlx5/device.h> 52 #include <linux/mlx5/doorbell.h> 53 #include <linux/mlx5/eq.h> 54 #include <linux/timecounter.h> 55 #include <linux/ptp_clock_kernel.h> 56 57 enum { 58 MLX5_BOARD_ID_LEN = 64, 59 MLX5_MAX_NAME_LEN = 16, 60 }; 61 62 enum { 63 /* one minute for the sake of bringup. Generally, commands must always 64 * complete and we may need to increase this timeout value 65 */ 66 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 67 MLX5_CMD_WQ_MAX_NAME = 32, 68 }; 69 70 enum { 71 CMD_OWNER_SW = 0x0, 72 CMD_OWNER_HW = 0x1, 73 CMD_STATUS_SUCCESS = 0, 74 }; 75 76 enum mlx5_sqp_t { 77 MLX5_SQP_SMI = 0, 78 MLX5_SQP_GSI = 1, 79 MLX5_SQP_IEEE_1588 = 2, 80 MLX5_SQP_SNIFFER = 3, 81 MLX5_SQP_SYNC_UMR = 4, 82 }; 83 84 enum { 85 MLX5_MAX_PORTS = 2, 86 }; 87 88 enum { 89 MLX5_ATOMIC_MODE_OFFSET = 16, 90 MLX5_ATOMIC_MODE_IB_COMP = 1, 91 MLX5_ATOMIC_MODE_CX = 2, 92 MLX5_ATOMIC_MODE_8B = 3, 93 MLX5_ATOMIC_MODE_16B = 4, 94 MLX5_ATOMIC_MODE_32B = 5, 95 MLX5_ATOMIC_MODE_64B = 6, 96 MLX5_ATOMIC_MODE_128B = 7, 97 MLX5_ATOMIC_MODE_256B = 8, 98 }; 99 100 enum { 101 MLX5_REG_QPTS = 0x4002, 102 MLX5_REG_QETCR = 0x4005, 103 MLX5_REG_QTCT = 0x400a, 104 MLX5_REG_QPDPM = 0x4013, 105 MLX5_REG_QCAM = 0x4019, 106 MLX5_REG_DCBX_PARAM = 0x4020, 107 MLX5_REG_DCBX_APP = 0x4021, 108 MLX5_REG_FPGA_CAP = 0x4022, 109 MLX5_REG_FPGA_CTRL = 0x4023, 110 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 111 MLX5_REG_PCAP = 0x5001, 112 MLX5_REG_PMTU = 0x5003, 113 MLX5_REG_PTYS = 0x5004, 114 MLX5_REG_PAOS = 0x5006, 115 MLX5_REG_PFCC = 0x5007, 116 MLX5_REG_PPCNT = 0x5008, 117 MLX5_REG_PPTB = 0x500b, 118 MLX5_REG_PBMC = 0x500c, 119 MLX5_REG_PMAOS = 0x5012, 120 MLX5_REG_PUDE = 0x5009, 121 MLX5_REG_PMPE = 0x5010, 122 MLX5_REG_PELC = 0x500e, 123 MLX5_REG_PVLC = 0x500f, 124 MLX5_REG_PCMR = 0x5041, 125 MLX5_REG_PMLP = 0x5002, 126 MLX5_REG_PPLM = 0x5023, 127 MLX5_REG_PCAM = 0x507f, 128 MLX5_REG_NODE_DESC = 0x6001, 129 MLX5_REG_HOST_ENDIANNESS = 0x7004, 130 MLX5_REG_MCIA = 0x9014, 131 MLX5_REG_MLCR = 0x902b, 132 MLX5_REG_MTRC_CAP = 0x9040, 133 MLX5_REG_MTRC_CONF = 0x9041, 134 MLX5_REG_MTRC_STDB = 0x9042, 135 MLX5_REG_MTRC_CTRL = 0x9043, 136 MLX5_REG_MPEIN = 0x9050, 137 MLX5_REG_MPCNT = 0x9051, 138 MLX5_REG_MTPPS = 0x9053, 139 MLX5_REG_MTPPSE = 0x9054, 140 MLX5_REG_MPEGC = 0x9056, 141 MLX5_REG_MCQI = 0x9061, 142 MLX5_REG_MCC = 0x9062, 143 MLX5_REG_MCDA = 0x9063, 144 MLX5_REG_MCAM = 0x907f, 145 }; 146 147 enum mlx5_qpts_trust_state { 148 MLX5_QPTS_TRUST_PCP = 1, 149 MLX5_QPTS_TRUST_DSCP = 2, 150 }; 151 152 enum mlx5_dcbx_oper_mode { 153 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 154 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 155 }; 156 157 enum { 158 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 159 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 160 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 161 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 162 }; 163 164 enum mlx5_page_fault_resume_flags { 165 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 166 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 167 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 168 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 169 }; 170 171 enum dbg_rsc_type { 172 MLX5_DBG_RSC_QP, 173 MLX5_DBG_RSC_EQ, 174 MLX5_DBG_RSC_CQ, 175 }; 176 177 enum port_state_policy { 178 MLX5_POLICY_DOWN = 0, 179 MLX5_POLICY_UP = 1, 180 MLX5_POLICY_FOLLOW = 2, 181 MLX5_POLICY_INVALID = 0xffffffff 182 }; 183 184 struct mlx5_field_desc { 185 struct dentry *dent; 186 int i; 187 }; 188 189 struct mlx5_rsc_debug { 190 struct mlx5_core_dev *dev; 191 void *object; 192 enum dbg_rsc_type type; 193 struct dentry *root; 194 struct mlx5_field_desc fields[0]; 195 }; 196 197 enum mlx5_dev_event { 198 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 199 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 200 }; 201 202 enum mlx5_port_status { 203 MLX5_PORT_UP = 1, 204 MLX5_PORT_DOWN = 2, 205 }; 206 207 struct mlx5_bfreg_info { 208 u32 *sys_pages; 209 int num_low_latency_bfregs; 210 unsigned int *count; 211 212 /* 213 * protect bfreg allocation data structs 214 */ 215 struct mutex lock; 216 u32 ver; 217 bool lib_uar_4k; 218 u32 num_sys_pages; 219 u32 num_static_sys_pages; 220 u32 total_num_bfregs; 221 u32 num_dyn_bfregs; 222 }; 223 224 struct mlx5_cmd_first { 225 __be32 data[4]; 226 }; 227 228 struct mlx5_cmd_msg { 229 struct list_head list; 230 struct cmd_msg_cache *parent; 231 u32 len; 232 struct mlx5_cmd_first first; 233 struct mlx5_cmd_mailbox *next; 234 }; 235 236 struct mlx5_cmd_debug { 237 struct dentry *dbg_root; 238 struct dentry *dbg_in; 239 struct dentry *dbg_out; 240 struct dentry *dbg_outlen; 241 struct dentry *dbg_status; 242 struct dentry *dbg_run; 243 void *in_msg; 244 void *out_msg; 245 u8 status; 246 u16 inlen; 247 u16 outlen; 248 }; 249 250 struct cmd_msg_cache { 251 /* protect block chain allocations 252 */ 253 spinlock_t lock; 254 struct list_head head; 255 unsigned int max_inbox_size; 256 unsigned int num_ent; 257 }; 258 259 enum { 260 MLX5_NUM_COMMAND_CACHES = 5, 261 }; 262 263 struct mlx5_cmd_stats { 264 u64 sum; 265 u64 n; 266 struct dentry *root; 267 struct dentry *avg; 268 struct dentry *count; 269 /* protect command average calculations */ 270 spinlock_t lock; 271 }; 272 273 struct mlx5_cmd { 274 struct mlx5_nb nb; 275 276 void *cmd_alloc_buf; 277 dma_addr_t alloc_dma; 278 int alloc_size; 279 void *cmd_buf; 280 dma_addr_t dma; 281 u16 cmdif_rev; 282 u8 log_sz; 283 u8 log_stride; 284 int max_reg_cmds; 285 int events; 286 u32 __iomem *vector; 287 288 /* protect command queue allocations 289 */ 290 spinlock_t alloc_lock; 291 292 /* protect token allocations 293 */ 294 spinlock_t token_lock; 295 u8 token; 296 unsigned long bitmask; 297 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 298 struct workqueue_struct *wq; 299 struct semaphore sem; 300 struct semaphore pages_sem; 301 int mode; 302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 303 struct dma_pool *pool; 304 struct mlx5_cmd_debug dbg; 305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 306 int checksum_disabled; 307 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 308 }; 309 310 struct mlx5_port_caps { 311 int gid_table_len; 312 int pkey_table_len; 313 u8 ext_port_cap; 314 bool has_smi; 315 }; 316 317 struct mlx5_cmd_mailbox { 318 void *buf; 319 dma_addr_t dma; 320 struct mlx5_cmd_mailbox *next; 321 }; 322 323 struct mlx5_buf_list { 324 void *buf; 325 dma_addr_t map; 326 }; 327 328 struct mlx5_frag_buf { 329 struct mlx5_buf_list *frags; 330 int npages; 331 int size; 332 u8 page_shift; 333 }; 334 335 struct mlx5_frag_buf_ctrl { 336 struct mlx5_buf_list *frags; 337 u32 sz_m1; 338 u16 frag_sz_m1; 339 u16 strides_offset; 340 u8 log_sz; 341 u8 log_stride; 342 u8 log_frag_strides; 343 }; 344 345 struct mlx5_core_psv { 346 u32 psv_idx; 347 struct psv_layout { 348 u32 pd; 349 u16 syndrome; 350 u16 reserved; 351 u16 bg; 352 u16 app_tag; 353 u32 ref_tag; 354 } psv; 355 }; 356 357 struct mlx5_core_sig_ctx { 358 struct mlx5_core_psv psv_memory; 359 struct mlx5_core_psv psv_wire; 360 struct ib_sig_err err_item; 361 bool sig_status_checked; 362 bool sig_err_exists; 363 u32 sigerr_count; 364 }; 365 366 enum { 367 MLX5_MKEY_MR = 1, 368 MLX5_MKEY_MW, 369 MLX5_MKEY_INDIRECT_DEVX, 370 }; 371 372 struct mlx5_core_mkey { 373 u64 iova; 374 u64 size; 375 u32 key; 376 u32 pd; 377 u32 type; 378 }; 379 380 #define MLX5_24BIT_MASK ((1 << 24) - 1) 381 382 enum mlx5_res_type { 383 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 384 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 385 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 386 MLX5_RES_SRQ = 3, 387 MLX5_RES_XSRQ = 4, 388 MLX5_RES_XRQ = 5, 389 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 390 }; 391 392 struct mlx5_core_rsc_common { 393 enum mlx5_res_type res; 394 atomic_t refcount; 395 struct completion free; 396 }; 397 398 struct mlx5_uars_page { 399 void __iomem *map; 400 bool wc; 401 u32 index; 402 struct list_head list; 403 unsigned int bfregs; 404 unsigned long *reg_bitmap; /* for non fast path bf regs */ 405 unsigned long *fp_bitmap; 406 unsigned int reg_avail; 407 unsigned int fp_avail; 408 struct kref ref_count; 409 struct mlx5_core_dev *mdev; 410 }; 411 412 struct mlx5_bfreg_head { 413 /* protect blue flame registers allocations */ 414 struct mutex lock; 415 struct list_head list; 416 }; 417 418 struct mlx5_bfreg_data { 419 struct mlx5_bfreg_head reg_head; 420 struct mlx5_bfreg_head wc_head; 421 }; 422 423 struct mlx5_sq_bfreg { 424 void __iomem *map; 425 struct mlx5_uars_page *up; 426 bool wc; 427 u32 index; 428 unsigned int offset; 429 }; 430 431 struct mlx5_core_health { 432 struct health_buffer __iomem *health; 433 __be32 __iomem *health_counter; 434 struct timer_list timer; 435 u32 prev; 436 int miss_counter; 437 bool sick; 438 /* wq spinlock to synchronize draining */ 439 spinlock_t wq_lock; 440 struct workqueue_struct *wq; 441 unsigned long flags; 442 struct work_struct work; 443 struct delayed_work recover_work; 444 }; 445 446 struct mlx5_qp_table { 447 struct notifier_block nb; 448 449 /* protect radix tree 450 */ 451 spinlock_t lock; 452 struct radix_tree_root tree; 453 }; 454 455 struct mlx5_mkey_table { 456 /* protect radix tree 457 */ 458 rwlock_t lock; 459 struct radix_tree_root tree; 460 }; 461 462 struct mlx5_vf_context { 463 int enabled; 464 u64 port_guid; 465 u64 node_guid; 466 enum port_state_policy policy; 467 }; 468 469 struct mlx5_core_sriov { 470 struct mlx5_vf_context *vfs_ctx; 471 int num_vfs; 472 int enabled_vfs; 473 }; 474 475 struct mlx5_fc_stats { 476 spinlock_t counters_idr_lock; /* protects counters_idr */ 477 struct idr counters_idr; 478 struct list_head counters; 479 struct llist_head addlist; 480 struct llist_head dellist; 481 482 struct workqueue_struct *wq; 483 struct delayed_work work; 484 unsigned long next_query; 485 unsigned long sampling_interval; /* jiffies */ 486 }; 487 488 struct mlx5_events; 489 struct mlx5_mpfs; 490 struct mlx5_eswitch; 491 struct mlx5_lag; 492 struct mlx5_devcom; 493 struct mlx5_eq_table; 494 495 struct mlx5_rate_limit { 496 u32 rate; 497 u32 max_burst_sz; 498 u16 typical_pkt_sz; 499 }; 500 501 struct mlx5_rl_entry { 502 struct mlx5_rate_limit rl; 503 u16 index; 504 u16 refcount; 505 }; 506 507 struct mlx5_rl_table { 508 /* protect rate limit table */ 509 struct mutex rl_lock; 510 u16 max_size; 511 u32 max_rate; 512 u32 min_rate; 513 struct mlx5_rl_entry *rl_entry; 514 }; 515 516 struct mlx5_priv { 517 char name[MLX5_MAX_NAME_LEN]; 518 struct mlx5_eq_table *eq_table; 519 520 /* pages stuff */ 521 struct mlx5_nb pg_nb; 522 struct workqueue_struct *pg_wq; 523 struct rb_root page_root; 524 int fw_pages; 525 atomic_t reg_pages; 526 struct list_head free_list; 527 int vfs_pages; 528 int peer_pf_pages; 529 530 struct mlx5_core_health health; 531 532 /* start: qp staff */ 533 struct mlx5_qp_table qp_table; 534 struct dentry *qp_debugfs; 535 struct dentry *eq_debugfs; 536 struct dentry *cq_debugfs; 537 struct dentry *cmdif_debugfs; 538 /* end: qp staff */ 539 540 /* start: mkey staff */ 541 struct mlx5_mkey_table mkey_table; 542 /* end: mkey staff */ 543 544 /* start: alloc staff */ 545 /* protect buffer alocation according to numa node */ 546 struct mutex alloc_mutex; 547 int numa_node; 548 549 struct mutex pgdir_mutex; 550 struct list_head pgdir_list; 551 /* end: alloc staff */ 552 struct dentry *dbg_root; 553 554 /* protect mkey key part */ 555 spinlock_t mkey_lock; 556 u8 mkey_key; 557 558 struct list_head dev_list; 559 struct list_head ctx_list; 560 spinlock_t ctx_lock; 561 struct mlx5_events *events; 562 563 struct mlx5_flow_steering *steering; 564 struct mlx5_mpfs *mpfs; 565 struct mlx5_eswitch *eswitch; 566 struct mlx5_core_sriov sriov; 567 struct mlx5_lag *lag; 568 struct mlx5_devcom *devcom; 569 unsigned long pci_dev_data; 570 struct mlx5_fc_stats fc_stats; 571 struct mlx5_rl_table rl_table; 572 573 struct mlx5_bfreg_data bfregs; 574 struct mlx5_uars_page *uar; 575 }; 576 577 enum mlx5_device_state { 578 MLX5_DEVICE_STATE_UP, 579 MLX5_DEVICE_STATE_INTERNAL_ERROR, 580 }; 581 582 enum mlx5_interface_state { 583 MLX5_INTERFACE_STATE_UP = BIT(0), 584 }; 585 586 enum mlx5_pci_status { 587 MLX5_PCI_STATUS_DISABLED, 588 MLX5_PCI_STATUS_ENABLED, 589 }; 590 591 enum mlx5_pagefault_type_flags { 592 MLX5_PFAULT_REQUESTOR = 1 << 0, 593 MLX5_PFAULT_WRITE = 1 << 1, 594 MLX5_PFAULT_RDMA = 1 << 2, 595 }; 596 597 struct mlx5_td { 598 /* protects tirs list changes while tirs refresh */ 599 struct mutex list_lock; 600 struct list_head tirs_list; 601 u32 tdn; 602 }; 603 604 struct mlx5e_resources { 605 u32 pdn; 606 struct mlx5_td td; 607 struct mlx5_core_mkey mkey; 608 struct mlx5_sq_bfreg bfreg; 609 }; 610 611 #define MLX5_MAX_RESERVED_GIDS 8 612 613 struct mlx5_rsvd_gids { 614 unsigned int start; 615 unsigned int count; 616 struct ida ida; 617 }; 618 619 #define MAX_PIN_NUM 8 620 struct mlx5_pps { 621 u8 pin_caps[MAX_PIN_NUM]; 622 struct work_struct out_work; 623 u64 start[MAX_PIN_NUM]; 624 u8 enabled; 625 }; 626 627 struct mlx5_clock { 628 struct mlx5_core_dev *mdev; 629 struct mlx5_nb pps_nb; 630 seqlock_t lock; 631 struct cyclecounter cycles; 632 struct timecounter tc; 633 struct hwtstamp_config hwtstamp_config; 634 u32 nominal_c_mult; 635 unsigned long overflow_period; 636 struct delayed_work overflow_work; 637 struct ptp_clock *ptp; 638 struct ptp_clock_info ptp_info; 639 struct mlx5_pps pps_info; 640 }; 641 642 struct mlx5_fw_tracer; 643 struct mlx5_vxlan; 644 645 struct mlx5_core_dev { 646 struct pci_dev *pdev; 647 /* sync pci state */ 648 struct mutex pci_status_mutex; 649 enum mlx5_pci_status pci_status; 650 u8 rev_id; 651 char board_id[MLX5_BOARD_ID_LEN]; 652 struct mlx5_cmd cmd; 653 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 654 struct { 655 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 656 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 657 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 658 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 659 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 660 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 661 u8 embedded_cpu; 662 } caps; 663 u64 sys_image_guid; 664 phys_addr_t iseg_base; 665 struct mlx5_init_seg __iomem *iseg; 666 phys_addr_t bar_addr; 667 enum mlx5_device_state state; 668 /* sync interface state */ 669 struct mutex intf_state_mutex; 670 unsigned long intf_state; 671 struct mlx5_priv priv; 672 struct mlx5_profile *profile; 673 atomic_t num_qps; 674 u32 issi; 675 struct mlx5e_resources mlx5e_res; 676 struct mlx5_vxlan *vxlan; 677 struct { 678 struct mlx5_rsvd_gids reserved_gids; 679 u32 roce_en; 680 } roce; 681 #ifdef CONFIG_MLX5_FPGA 682 struct mlx5_fpga_device *fpga; 683 #endif 684 struct mlx5_clock clock; 685 struct mlx5_ib_clock_info *clock_info; 686 struct page *clock_info_page; 687 struct mlx5_fw_tracer *tracer; 688 }; 689 690 struct mlx5_db { 691 __be32 *db; 692 union { 693 struct mlx5_db_pgdir *pgdir; 694 struct mlx5_ib_user_db_page *user_page; 695 } u; 696 dma_addr_t dma; 697 int index; 698 }; 699 700 enum { 701 MLX5_COMP_EQ_SIZE = 1024, 702 }; 703 704 enum { 705 MLX5_PTYS_IB = 1 << 0, 706 MLX5_PTYS_EN = 1 << 2, 707 }; 708 709 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 710 711 enum { 712 MLX5_CMD_ENT_STATE_PENDING_COMP, 713 }; 714 715 struct mlx5_cmd_work_ent { 716 unsigned long state; 717 struct mlx5_cmd_msg *in; 718 struct mlx5_cmd_msg *out; 719 void *uout; 720 int uout_size; 721 mlx5_cmd_cbk_t callback; 722 struct delayed_work cb_timeout_work; 723 void *context; 724 int idx; 725 struct completion done; 726 struct mlx5_cmd *cmd; 727 struct work_struct work; 728 struct mlx5_cmd_layout *lay; 729 int ret; 730 int page_queue; 731 u8 status; 732 u8 token; 733 u64 ts1; 734 u64 ts2; 735 u16 op; 736 bool polling; 737 }; 738 739 struct mlx5_pas { 740 u64 pa; 741 u8 log_sz; 742 }; 743 744 enum phy_port_state { 745 MLX5_AAA_111 746 }; 747 748 struct mlx5_hca_vport_context { 749 u32 field_select; 750 bool sm_virt_aware; 751 bool has_smi; 752 bool has_raw; 753 enum port_state_policy policy; 754 enum phy_port_state phys_state; 755 enum ib_port_state vport_state; 756 u8 port_physical_state; 757 u64 sys_image_guid; 758 u64 port_guid; 759 u64 node_guid; 760 u32 cap_mask1; 761 u32 cap_mask1_perm; 762 u16 cap_mask2; 763 u16 cap_mask2_perm; 764 u16 lid; 765 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 766 u8 lmc; 767 u8 subnet_timeout; 768 u16 sm_lid; 769 u8 sm_sl; 770 u16 qkey_violation_counter; 771 u16 pkey_violation_counter; 772 bool grh_required; 773 }; 774 775 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 776 { 777 return buf->frags->buf + offset; 778 } 779 780 #define STRUCT_FIELD(header, field) \ 781 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 782 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 783 784 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 785 { 786 return pci_get_drvdata(pdev); 787 } 788 789 extern struct dentry *mlx5_debugfs_root; 790 791 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 792 { 793 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 794 } 795 796 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 797 { 798 return ioread32be(&dev->iseg->fw_rev) >> 16; 799 } 800 801 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 802 { 803 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 804 } 805 806 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 807 { 808 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 809 } 810 811 static inline u32 mlx5_base_mkey(const u32 key) 812 { 813 return key & 0xffffff00u; 814 } 815 816 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 817 u8 log_stride, u8 log_sz, 818 u16 strides_offset, 819 struct mlx5_frag_buf_ctrl *fbc) 820 { 821 fbc->frags = frags; 822 fbc->log_stride = log_stride; 823 fbc->log_sz = log_sz; 824 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 825 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 826 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 827 fbc->strides_offset = strides_offset; 828 } 829 830 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 831 u8 log_stride, u8 log_sz, 832 struct mlx5_frag_buf_ctrl *fbc) 833 { 834 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 835 } 836 837 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 838 u32 ix) 839 { 840 unsigned int frag; 841 842 ix += fbc->strides_offset; 843 frag = ix >> fbc->log_frag_strides; 844 845 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 846 } 847 848 static inline u32 849 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 850 { 851 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 852 853 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 854 } 855 856 int mlx5_cmd_init(struct mlx5_core_dev *dev); 857 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 858 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 859 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 860 861 struct mlx5_async_ctx { 862 struct mlx5_core_dev *dev; 863 atomic_t num_inflight; 864 struct wait_queue_head wait; 865 }; 866 867 struct mlx5_async_work; 868 869 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 870 871 struct mlx5_async_work { 872 struct mlx5_async_ctx *ctx; 873 mlx5_async_cbk_t user_callback; 874 }; 875 876 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 877 struct mlx5_async_ctx *ctx); 878 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 879 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 880 void *out, int out_size, mlx5_async_cbk_t callback, 881 struct mlx5_async_work *work); 882 883 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 884 int out_size); 885 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 886 void *out, int out_size); 887 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 888 889 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 890 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 891 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 892 void mlx5_health_flush(struct mlx5_core_dev *dev); 893 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 894 int mlx5_health_init(struct mlx5_core_dev *dev); 895 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 896 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 897 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 898 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 899 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 900 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 901 struct mlx5_frag_buf *buf, int node); 902 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 903 int size, struct mlx5_frag_buf *buf); 904 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 905 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 906 struct mlx5_frag_buf *buf, int node); 907 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 908 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 909 gfp_t flags, int npages); 910 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 911 struct mlx5_cmd_mailbox *head); 912 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 913 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 914 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 915 struct mlx5_core_mkey *mkey, 916 struct mlx5_async_ctx *async_ctx, u32 *in, 917 int inlen, u32 *out, int outlen, 918 mlx5_async_cbk_t callback, 919 struct mlx5_async_work *context); 920 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 921 struct mlx5_core_mkey *mkey, 922 u32 *in, int inlen); 923 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 924 struct mlx5_core_mkey *mkey); 925 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 926 u32 *out, int outlen); 927 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 928 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 929 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 930 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 931 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 932 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 933 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 934 s32 npages, bool ec_function); 935 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 936 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 937 void mlx5_register_debugfs(void); 938 void mlx5_unregister_debugfs(void); 939 940 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 941 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 942 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 943 unsigned int *irqn); 944 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 945 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 946 947 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 948 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 949 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 950 int size_in, void *data_out, int size_out, 951 u16 reg_num, int arg, int write); 952 953 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 954 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 955 int node); 956 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 957 958 const char *mlx5_command_str(int command); 959 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 960 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 961 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 962 int npsvs, u32 *sig_index); 963 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 964 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 965 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 966 struct mlx5_odp_caps *odp_caps); 967 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 968 u8 port_num, void *out, size_t sz); 969 970 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 971 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 972 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 973 struct mlx5_rate_limit *rl); 974 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 975 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 976 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 977 struct mlx5_rate_limit *rl_1); 978 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 979 bool map_wc, bool fast_path); 980 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 981 982 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 983 struct cpumask * 984 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 985 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 986 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 987 u8 roce_version, u8 roce_l3_type, const u8 *gid, 988 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 989 990 static inline int fw_initializing(struct mlx5_core_dev *dev) 991 { 992 return ioread32be(&dev->iseg->initializing) >> 31; 993 } 994 995 static inline u32 mlx5_mkey_to_idx(u32 mkey) 996 { 997 return mkey >> 8; 998 } 999 1000 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1001 { 1002 return mkey_idx << 8; 1003 } 1004 1005 static inline u8 mlx5_mkey_variant(u32 mkey) 1006 { 1007 return mkey & 0xff; 1008 } 1009 1010 enum { 1011 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1012 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1013 }; 1014 1015 enum { 1016 MR_CACHE_LAST_STD_ENTRY = 20, 1017 MLX5_IMR_MTT_CACHE_ENTRY, 1018 MLX5_IMR_KSM_CACHE_ENTRY, 1019 MAX_MR_CACHE_ENTRIES 1020 }; 1021 1022 enum { 1023 MLX5_INTERFACE_PROTOCOL_IB = 0, 1024 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1025 }; 1026 1027 struct mlx5_interface { 1028 void * (*add)(struct mlx5_core_dev *dev); 1029 void (*remove)(struct mlx5_core_dev *dev, void *context); 1030 int (*attach)(struct mlx5_core_dev *dev, void *context); 1031 void (*detach)(struct mlx5_core_dev *dev, void *context); 1032 int protocol; 1033 struct list_head list; 1034 }; 1035 1036 int mlx5_register_interface(struct mlx5_interface *intf); 1037 void mlx5_unregister_interface(struct mlx5_interface *intf); 1038 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1039 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1040 1041 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1042 1043 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1044 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1045 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1046 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1047 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1048 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1049 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1050 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1051 u64 *values, 1052 int num_counters, 1053 size_t *offsets); 1054 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1055 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1056 1057 #ifdef CONFIG_MLX5_CORE_IPOIB 1058 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1059 struct ib_device *ibdev, 1060 const char *name, 1061 void (*setup)(struct net_device *)); 1062 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1063 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1064 struct ib_device *device, 1065 struct rdma_netdev_alloc_params *params); 1066 1067 struct mlx5_profile { 1068 u64 mask; 1069 u8 log_max_qp; 1070 struct { 1071 int size; 1072 int limit; 1073 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1074 }; 1075 1076 enum { 1077 MLX5_PCI_DEV_IS_VF = 1 << 0, 1078 }; 1079 1080 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1081 { 1082 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1083 } 1084 1085 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1086 { 1087 return dev->caps.embedded_cpu; 1088 } 1089 1090 static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev) 1091 { 1092 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1093 } 1094 1095 static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev) 1096 { 1097 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1098 } 1099 1100 #define MLX5_HOST_PF_MAX_VFS (127u) 1101 static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev) 1102 { 1103 if (mlx5_core_is_ecpf_esw_manager(dev)) 1104 return MLX5_HOST_PF_MAX_VFS; 1105 else 1106 return pci_sriov_get_totalvfs(dev->pdev); 1107 } 1108 1109 static inline int mlx5_get_gid_table_len(u16 param) 1110 { 1111 if (param > 4) { 1112 pr_warn("gid table length is zero\n"); 1113 return 0; 1114 } 1115 1116 return 8 * (1 << param); 1117 } 1118 1119 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1120 { 1121 return !!(dev->priv.rl_table.max_size); 1122 } 1123 1124 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1125 { 1126 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1127 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1128 } 1129 1130 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1131 { 1132 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1133 } 1134 1135 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1136 { 1137 return mlx5_core_is_mp_slave(dev) || 1138 mlx5_core_is_mp_master(dev); 1139 } 1140 1141 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1142 { 1143 if (!mlx5_core_mp_enabled(dev)) 1144 return 1; 1145 1146 return MLX5_CAP_GEN(dev, native_port_num); 1147 } 1148 1149 enum { 1150 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1151 }; 1152 1153 #endif /* MLX5_DRIVER_H */ 1154