xref: /linux-6.15/include/linux/mlx5/driver.h (revision e2f5cb72) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 
52 #include <linux/mlx5/device.h>
53 #include <linux/mlx5/doorbell.h>
54 #include <linux/mlx5/eq.h>
55 #include <linux/timecounter.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/devlink.h>
58 
59 enum {
60 	MLX5_BOARD_ID_LEN = 64,
61 };
62 
63 enum {
64 	/* one minute for the sake of bringup. Generally, commands must always
65 	 * complete and we may need to increase this timeout value
66 	 */
67 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
68 	MLX5_CMD_WQ_MAX_NAME	= 32,
69 };
70 
71 enum {
72 	CMD_OWNER_SW		= 0x0,
73 	CMD_OWNER_HW		= 0x1,
74 	CMD_STATUS_SUCCESS	= 0,
75 };
76 
77 enum mlx5_sqp_t {
78 	MLX5_SQP_SMI		= 0,
79 	MLX5_SQP_GSI		= 1,
80 	MLX5_SQP_IEEE_1588	= 2,
81 	MLX5_SQP_SNIFFER	= 3,
82 	MLX5_SQP_SYNC_UMR	= 4,
83 };
84 
85 enum {
86 	MLX5_MAX_PORTS	= 2,
87 };
88 
89 enum {
90 	MLX5_ATOMIC_MODE_OFFSET = 16,
91 	MLX5_ATOMIC_MODE_IB_COMP = 1,
92 	MLX5_ATOMIC_MODE_CX = 2,
93 	MLX5_ATOMIC_MODE_8B = 3,
94 	MLX5_ATOMIC_MODE_16B = 4,
95 	MLX5_ATOMIC_MODE_32B = 5,
96 	MLX5_ATOMIC_MODE_64B = 6,
97 	MLX5_ATOMIC_MODE_128B = 7,
98 	MLX5_ATOMIC_MODE_256B = 8,
99 };
100 
101 enum {
102 	MLX5_REG_QPTS            = 0x4002,
103 	MLX5_REG_QETCR		 = 0x4005,
104 	MLX5_REG_QTCT		 = 0x400a,
105 	MLX5_REG_QPDPM           = 0x4013,
106 	MLX5_REG_QCAM            = 0x4019,
107 	MLX5_REG_DCBX_PARAM      = 0x4020,
108 	MLX5_REG_DCBX_APP        = 0x4021,
109 	MLX5_REG_FPGA_CAP	 = 0x4022,
110 	MLX5_REG_FPGA_CTRL	 = 0x4023,
111 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
112 	MLX5_REG_CORE_DUMP	 = 0x402e,
113 	MLX5_REG_PCAP		 = 0x5001,
114 	MLX5_REG_PMTU		 = 0x5003,
115 	MLX5_REG_PTYS		 = 0x5004,
116 	MLX5_REG_PAOS		 = 0x5006,
117 	MLX5_REG_PFCC            = 0x5007,
118 	MLX5_REG_PPCNT		 = 0x5008,
119 	MLX5_REG_PPTB            = 0x500b,
120 	MLX5_REG_PBMC            = 0x500c,
121 	MLX5_REG_PMAOS		 = 0x5012,
122 	MLX5_REG_PUDE		 = 0x5009,
123 	MLX5_REG_PMPE		 = 0x5010,
124 	MLX5_REG_PELC		 = 0x500e,
125 	MLX5_REG_PVLC		 = 0x500f,
126 	MLX5_REG_PCMR		 = 0x5041,
127 	MLX5_REG_PMLP		 = 0x5002,
128 	MLX5_REG_PPLM		 = 0x5023,
129 	MLX5_REG_PCAM		 = 0x507f,
130 	MLX5_REG_NODE_DESC	 = 0x6001,
131 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 	MLX5_REG_MCIA		 = 0x9014,
133 	MLX5_REG_MLCR		 = 0x902b,
134 	MLX5_REG_MTRC_CAP	 = 0x9040,
135 	MLX5_REG_MTRC_CONF	 = 0x9041,
136 	MLX5_REG_MTRC_STDB	 = 0x9042,
137 	MLX5_REG_MTRC_CTRL	 = 0x9043,
138 	MLX5_REG_MPEIN		 = 0x9050,
139 	MLX5_REG_MPCNT		 = 0x9051,
140 	MLX5_REG_MTPPS		 = 0x9053,
141 	MLX5_REG_MTPPSE		 = 0x9054,
142 	MLX5_REG_MPEGC		 = 0x9056,
143 	MLX5_REG_MCQS		 = 0x9060,
144 	MLX5_REG_MCQI		 = 0x9061,
145 	MLX5_REG_MCC		 = 0x9062,
146 	MLX5_REG_MCDA		 = 0x9063,
147 	MLX5_REG_MCAM		 = 0x907f,
148 	MLX5_REG_MIRC		 = 0x9162,
149 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
150 };
151 
152 enum mlx5_qpts_trust_state {
153 	MLX5_QPTS_TRUST_PCP  = 1,
154 	MLX5_QPTS_TRUST_DSCP = 2,
155 };
156 
157 enum mlx5_dcbx_oper_mode {
158 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
159 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
160 };
161 
162 enum {
163 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
164 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
165 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
166 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
167 };
168 
169 enum mlx5_page_fault_resume_flags {
170 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
171 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
172 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
173 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
174 };
175 
176 enum dbg_rsc_type {
177 	MLX5_DBG_RSC_QP,
178 	MLX5_DBG_RSC_EQ,
179 	MLX5_DBG_RSC_CQ,
180 };
181 
182 enum port_state_policy {
183 	MLX5_POLICY_DOWN	= 0,
184 	MLX5_POLICY_UP		= 1,
185 	MLX5_POLICY_FOLLOW	= 2,
186 	MLX5_POLICY_INVALID	= 0xffffffff
187 };
188 
189 enum mlx5_coredev_type {
190 	MLX5_COREDEV_PF,
191 	MLX5_COREDEV_VF
192 };
193 
194 struct mlx5_field_desc {
195 	int			i;
196 };
197 
198 struct mlx5_rsc_debug {
199 	struct mlx5_core_dev   *dev;
200 	void		       *object;
201 	enum dbg_rsc_type	type;
202 	struct dentry	       *root;
203 	struct mlx5_field_desc	fields[0];
204 };
205 
206 enum mlx5_dev_event {
207 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
208 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
209 };
210 
211 enum mlx5_port_status {
212 	MLX5_PORT_UP        = 1,
213 	MLX5_PORT_DOWN      = 2,
214 };
215 
216 struct mlx5_bfreg_info {
217 	u32		       *sys_pages;
218 	int			num_low_latency_bfregs;
219 	unsigned int	       *count;
220 
221 	/*
222 	 * protect bfreg allocation data structs
223 	 */
224 	struct mutex		lock;
225 	u32			ver;
226 	bool			lib_uar_4k;
227 	u32			num_sys_pages;
228 	u32			num_static_sys_pages;
229 	u32			total_num_bfregs;
230 	u32			num_dyn_bfregs;
231 };
232 
233 struct mlx5_cmd_first {
234 	__be32		data[4];
235 };
236 
237 struct mlx5_cmd_msg {
238 	struct list_head		list;
239 	struct cmd_msg_cache	       *parent;
240 	u32				len;
241 	struct mlx5_cmd_first		first;
242 	struct mlx5_cmd_mailbox	       *next;
243 };
244 
245 struct mlx5_cmd_debug {
246 	struct dentry	       *dbg_root;
247 	void		       *in_msg;
248 	void		       *out_msg;
249 	u8			status;
250 	u16			inlen;
251 	u16			outlen;
252 };
253 
254 struct cmd_msg_cache {
255 	/* protect block chain allocations
256 	 */
257 	spinlock_t		lock;
258 	struct list_head	head;
259 	unsigned int		max_inbox_size;
260 	unsigned int		num_ent;
261 };
262 
263 enum {
264 	MLX5_NUM_COMMAND_CACHES = 5,
265 };
266 
267 struct mlx5_cmd_stats {
268 	u64		sum;
269 	u64		n;
270 	struct dentry  *root;
271 	/* protect command average calculations */
272 	spinlock_t	lock;
273 };
274 
275 struct mlx5_cmd {
276 	struct mlx5_nb    nb;
277 
278 	void	       *cmd_alloc_buf;
279 	dma_addr_t	alloc_dma;
280 	int		alloc_size;
281 	void	       *cmd_buf;
282 	dma_addr_t	dma;
283 	u16		cmdif_rev;
284 	u8		log_sz;
285 	u8		log_stride;
286 	int		max_reg_cmds;
287 	int		events;
288 	u32 __iomem    *vector;
289 
290 	/* protect command queue allocations
291 	 */
292 	spinlock_t	alloc_lock;
293 
294 	/* protect token allocations
295 	 */
296 	spinlock_t	token_lock;
297 	u8		token;
298 	unsigned long	bitmask;
299 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
300 	struct workqueue_struct *wq;
301 	struct semaphore sem;
302 	struct semaphore pages_sem;
303 	int	mode;
304 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
305 	struct dma_pool *pool;
306 	struct mlx5_cmd_debug dbg;
307 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
308 	int checksum_disabled;
309 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
310 };
311 
312 struct mlx5_port_caps {
313 	int	gid_table_len;
314 	int	pkey_table_len;
315 	u8	ext_port_cap;
316 	bool	has_smi;
317 };
318 
319 struct mlx5_cmd_mailbox {
320 	void	       *buf;
321 	dma_addr_t	dma;
322 	struct mlx5_cmd_mailbox *next;
323 };
324 
325 struct mlx5_buf_list {
326 	void		       *buf;
327 	dma_addr_t		map;
328 };
329 
330 struct mlx5_frag_buf {
331 	struct mlx5_buf_list	*frags;
332 	int			npages;
333 	int			size;
334 	u8			page_shift;
335 };
336 
337 struct mlx5_frag_buf_ctrl {
338 	struct mlx5_buf_list   *frags;
339 	u32			sz_m1;
340 	u16			frag_sz_m1;
341 	u16			strides_offset;
342 	u8			log_sz;
343 	u8			log_stride;
344 	u8			log_frag_strides;
345 };
346 
347 struct mlx5_core_psv {
348 	u32	psv_idx;
349 	struct psv_layout {
350 		u32	pd;
351 		u16	syndrome;
352 		u16	reserved;
353 		u16	bg;
354 		u16	app_tag;
355 		u32	ref_tag;
356 	} psv;
357 };
358 
359 struct mlx5_core_sig_ctx {
360 	struct mlx5_core_psv	psv_memory;
361 	struct mlx5_core_psv	psv_wire;
362 	struct ib_sig_err       err_item;
363 	bool			sig_status_checked;
364 	bool			sig_err_exists;
365 	u32			sigerr_count;
366 };
367 
368 enum {
369 	MLX5_MKEY_MR = 1,
370 	MLX5_MKEY_MW,
371 	MLX5_MKEY_INDIRECT_DEVX,
372 };
373 
374 struct mlx5_core_mkey {
375 	u64			iova;
376 	u64			size;
377 	u32			key;
378 	u32			pd;
379 	u32			type;
380 };
381 
382 #define MLX5_24BIT_MASK		((1 << 24) - 1)
383 
384 enum mlx5_res_type {
385 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
386 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
387 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
388 	MLX5_RES_SRQ	= 3,
389 	MLX5_RES_XSRQ	= 4,
390 	MLX5_RES_XRQ	= 5,
391 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
392 };
393 
394 struct mlx5_core_rsc_common {
395 	enum mlx5_res_type	res;
396 	refcount_t		refcount;
397 	struct completion	free;
398 };
399 
400 struct mlx5_uars_page {
401 	void __iomem	       *map;
402 	bool			wc;
403 	u32			index;
404 	struct list_head	list;
405 	unsigned int		bfregs;
406 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
407 	unsigned long	       *fp_bitmap;
408 	unsigned int		reg_avail;
409 	unsigned int		fp_avail;
410 	struct kref		ref_count;
411 	struct mlx5_core_dev   *mdev;
412 };
413 
414 struct mlx5_bfreg_head {
415 	/* protect blue flame registers allocations */
416 	struct mutex		lock;
417 	struct list_head	list;
418 };
419 
420 struct mlx5_bfreg_data {
421 	struct mlx5_bfreg_head	reg_head;
422 	struct mlx5_bfreg_head	wc_head;
423 };
424 
425 struct mlx5_sq_bfreg {
426 	void __iomem	       *map;
427 	struct mlx5_uars_page  *up;
428 	bool			wc;
429 	u32			index;
430 	unsigned int		offset;
431 };
432 
433 struct mlx5_core_health {
434 	struct health_buffer __iomem   *health;
435 	__be32 __iomem		       *health_counter;
436 	struct timer_list		timer;
437 	u32				prev;
438 	int				miss_counter;
439 	u8				synd;
440 	u32				fatal_error;
441 	u32				crdump_size;
442 	/* wq spinlock to synchronize draining */
443 	spinlock_t			wq_lock;
444 	struct workqueue_struct	       *wq;
445 	unsigned long			flags;
446 	struct work_struct		fatal_report_work;
447 	struct work_struct		report_work;
448 	struct delayed_work		recover_work;
449 	struct devlink_health_reporter *fw_reporter;
450 	struct devlink_health_reporter *fw_fatal_reporter;
451 };
452 
453 struct mlx5_qp_table {
454 	struct notifier_block   nb;
455 
456 	/* protect radix tree
457 	 */
458 	spinlock_t		lock;
459 	struct radix_tree_root	tree;
460 };
461 
462 struct mlx5_vf_context {
463 	int	enabled;
464 	u64	port_guid;
465 	u64	node_guid;
466 	/* Valid bits are used to validate administrative guid only.
467 	 * Enabled after ndo_set_vf_guid
468 	 */
469 	u8	port_guid_valid:1;
470 	u8	node_guid_valid:1;
471 	enum port_state_policy	policy;
472 };
473 
474 struct mlx5_core_sriov {
475 	struct mlx5_vf_context	*vfs_ctx;
476 	int			num_vfs;
477 	u16			max_vfs;
478 };
479 
480 struct mlx5_fc_pool {
481 	struct mlx5_core_dev *dev;
482 	struct mutex pool_lock; /* protects pool lists */
483 	struct list_head fully_used;
484 	struct list_head partially_used;
485 	struct list_head unused;
486 	int available_fcs;
487 	int used_fcs;
488 	int threshold;
489 };
490 
491 struct mlx5_fc_stats {
492 	spinlock_t counters_idr_lock; /* protects counters_idr */
493 	struct idr counters_idr;
494 	struct list_head counters;
495 	struct llist_head addlist;
496 	struct llist_head dellist;
497 
498 	struct workqueue_struct *wq;
499 	struct delayed_work work;
500 	unsigned long next_query;
501 	unsigned long sampling_interval; /* jiffies */
502 	u32 *bulk_query_out;
503 	struct mlx5_fc_pool fc_pool;
504 };
505 
506 struct mlx5_events;
507 struct mlx5_mpfs;
508 struct mlx5_eswitch;
509 struct mlx5_lag;
510 struct mlx5_devcom;
511 struct mlx5_eq_table;
512 struct mlx5_irq_table;
513 
514 struct mlx5_rate_limit {
515 	u32			rate;
516 	u32			max_burst_sz;
517 	u16			typical_pkt_sz;
518 };
519 
520 struct mlx5_rl_entry {
521 	struct mlx5_rate_limit	rl;
522 	u16                     index;
523 	u16                     refcount;
524 };
525 
526 struct mlx5_rl_table {
527 	/* protect rate limit table */
528 	struct mutex            rl_lock;
529 	u16                     max_size;
530 	u32                     max_rate;
531 	u32                     min_rate;
532 	struct mlx5_rl_entry   *rl_entry;
533 };
534 
535 struct mlx5_core_roce {
536 	struct mlx5_flow_table *ft;
537 	struct mlx5_flow_group *fg;
538 	struct mlx5_flow_handle *allow_rule;
539 };
540 
541 struct mlx5_priv {
542 	/* IRQ table valid only for real pci devices PF or VF */
543 	struct mlx5_irq_table   *irq_table;
544 	struct mlx5_eq_table	*eq_table;
545 
546 	/* pages stuff */
547 	struct mlx5_nb          pg_nb;
548 	struct workqueue_struct *pg_wq;
549 	struct rb_root		page_root;
550 	int			fw_pages;
551 	atomic_t		reg_pages;
552 	struct list_head	free_list;
553 	int			vfs_pages;
554 	int			peer_pf_pages;
555 
556 	struct mlx5_core_health health;
557 
558 	/* start: qp staff */
559 	struct mlx5_qp_table	qp_table;
560 	struct dentry	       *qp_debugfs;
561 	struct dentry	       *eq_debugfs;
562 	struct dentry	       *cq_debugfs;
563 	struct dentry	       *cmdif_debugfs;
564 	/* end: qp staff */
565 
566 	/* start: alloc staff */
567 	/* protect buffer alocation according to numa node */
568 	struct mutex            alloc_mutex;
569 	int                     numa_node;
570 
571 	struct mutex            pgdir_mutex;
572 	struct list_head        pgdir_list;
573 	/* end: alloc staff */
574 	struct dentry	       *dbg_root;
575 
576 	/* protect mkey key part */
577 	spinlock_t		mkey_lock;
578 	u8			mkey_key;
579 
580 	struct list_head        dev_list;
581 	struct list_head        ctx_list;
582 	spinlock_t              ctx_lock;
583 	struct mlx5_events      *events;
584 
585 	struct mlx5_flow_steering *steering;
586 	struct mlx5_mpfs        *mpfs;
587 	struct mlx5_eswitch     *eswitch;
588 	struct mlx5_core_sriov	sriov;
589 	struct mlx5_lag		*lag;
590 	struct mlx5_devcom	*devcom;
591 	struct mlx5_core_roce	roce;
592 	struct mlx5_fc_stats		fc_stats;
593 	struct mlx5_rl_table            rl_table;
594 
595 	struct mlx5_bfreg_data		bfregs;
596 	struct mlx5_uars_page	       *uar;
597 };
598 
599 enum mlx5_device_state {
600 	MLX5_DEVICE_STATE_UNINITIALIZED,
601 	MLX5_DEVICE_STATE_UP,
602 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
603 };
604 
605 enum mlx5_interface_state {
606 	MLX5_INTERFACE_STATE_UP = BIT(0),
607 };
608 
609 enum mlx5_pci_status {
610 	MLX5_PCI_STATUS_DISABLED,
611 	MLX5_PCI_STATUS_ENABLED,
612 };
613 
614 enum mlx5_pagefault_type_flags {
615 	MLX5_PFAULT_REQUESTOR = 1 << 0,
616 	MLX5_PFAULT_WRITE     = 1 << 1,
617 	MLX5_PFAULT_RDMA      = 1 << 2,
618 };
619 
620 struct mlx5_td {
621 	/* protects tirs list changes while tirs refresh */
622 	struct mutex     list_lock;
623 	struct list_head tirs_list;
624 	u32              tdn;
625 };
626 
627 struct mlx5e_resources {
628 	u32                        pdn;
629 	struct mlx5_td             td;
630 	struct mlx5_core_mkey      mkey;
631 	struct mlx5_sq_bfreg       bfreg;
632 };
633 
634 enum mlx5_sw_icm_type {
635 	MLX5_SW_ICM_TYPE_STEERING,
636 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
637 };
638 
639 #define MLX5_MAX_RESERVED_GIDS 8
640 
641 struct mlx5_rsvd_gids {
642 	unsigned int start;
643 	unsigned int count;
644 	struct ida ida;
645 };
646 
647 #define MAX_PIN_NUM	8
648 struct mlx5_pps {
649 	u8                         pin_caps[MAX_PIN_NUM];
650 	struct work_struct         out_work;
651 	u64                        start[MAX_PIN_NUM];
652 	u8                         enabled;
653 };
654 
655 struct mlx5_clock {
656 	struct mlx5_core_dev      *mdev;
657 	struct mlx5_nb             pps_nb;
658 	seqlock_t                  lock;
659 	struct cyclecounter        cycles;
660 	struct timecounter         tc;
661 	struct hwtstamp_config     hwtstamp_config;
662 	u32                        nominal_c_mult;
663 	unsigned long              overflow_period;
664 	struct delayed_work        overflow_work;
665 	struct ptp_clock          *ptp;
666 	struct ptp_clock_info      ptp_info;
667 	struct mlx5_pps            pps_info;
668 };
669 
670 struct mlx5_dm;
671 struct mlx5_fw_tracer;
672 struct mlx5_vxlan;
673 struct mlx5_geneve;
674 struct mlx5_hv_vhca;
675 
676 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
677 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
678 
679 struct mlx5_core_dev {
680 	struct device *device;
681 	enum mlx5_coredev_type coredev_type;
682 	struct pci_dev	       *pdev;
683 	/* sync pci state */
684 	struct mutex		pci_status_mutex;
685 	enum mlx5_pci_status	pci_status;
686 	u8			rev_id;
687 	char			board_id[MLX5_BOARD_ID_LEN];
688 	struct mlx5_cmd		cmd;
689 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
690 	struct {
691 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
692 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
693 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
694 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
695 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
696 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
697 		u8  embedded_cpu;
698 	} caps;
699 	u64			sys_image_guid;
700 	phys_addr_t		iseg_base;
701 	struct mlx5_init_seg __iomem *iseg;
702 	phys_addr_t             bar_addr;
703 	enum mlx5_device_state	state;
704 	/* sync interface state */
705 	struct mutex		intf_state_mutex;
706 	unsigned long		intf_state;
707 	struct mlx5_priv	priv;
708 	struct mlx5_profile	*profile;
709 	atomic_t		num_qps;
710 	u32			issi;
711 	struct mlx5e_resources  mlx5e_res;
712 	struct mlx5_dm          *dm;
713 	struct mlx5_vxlan       *vxlan;
714 	struct mlx5_geneve      *geneve;
715 	struct {
716 		struct mlx5_rsvd_gids	reserved_gids;
717 		u32			roce_en;
718 	} roce;
719 #ifdef CONFIG_MLX5_FPGA
720 	struct mlx5_fpga_device *fpga;
721 #endif
722 	struct mlx5_clock        clock;
723 	struct mlx5_ib_clock_info  *clock_info;
724 	struct mlx5_fw_tracer   *tracer;
725 	struct mlx5_rsc_dump    *rsc_dump;
726 	u32                      vsc_addr;
727 	struct mlx5_hv_vhca	*hv_vhca;
728 };
729 
730 struct mlx5_db {
731 	__be32			*db;
732 	union {
733 		struct mlx5_db_pgdir		*pgdir;
734 		struct mlx5_ib_user_db_page	*user_page;
735 	}			u;
736 	dma_addr_t		dma;
737 	int			index;
738 };
739 
740 enum {
741 	MLX5_COMP_EQ_SIZE = 1024,
742 };
743 
744 enum {
745 	MLX5_PTYS_IB = 1 << 0,
746 	MLX5_PTYS_EN = 1 << 2,
747 };
748 
749 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
750 
751 enum {
752 	MLX5_CMD_ENT_STATE_PENDING_COMP,
753 };
754 
755 struct mlx5_cmd_work_ent {
756 	unsigned long		state;
757 	struct mlx5_cmd_msg    *in;
758 	struct mlx5_cmd_msg    *out;
759 	void		       *uout;
760 	int			uout_size;
761 	mlx5_cmd_cbk_t		callback;
762 	struct delayed_work	cb_timeout_work;
763 	void		       *context;
764 	int			idx;
765 	struct completion	done;
766 	struct mlx5_cmd        *cmd;
767 	struct work_struct	work;
768 	struct mlx5_cmd_layout *lay;
769 	int			ret;
770 	int			page_queue;
771 	u8			status;
772 	u8			token;
773 	u64			ts1;
774 	u64			ts2;
775 	u16			op;
776 	bool			polling;
777 };
778 
779 struct mlx5_pas {
780 	u64	pa;
781 	u8	log_sz;
782 };
783 
784 enum phy_port_state {
785 	MLX5_AAA_111
786 };
787 
788 struct mlx5_hca_vport_context {
789 	u32			field_select;
790 	bool			sm_virt_aware;
791 	bool			has_smi;
792 	bool			has_raw;
793 	enum port_state_policy	policy;
794 	enum phy_port_state	phys_state;
795 	enum ib_port_state	vport_state;
796 	u8			port_physical_state;
797 	u64			sys_image_guid;
798 	u64			port_guid;
799 	u64			node_guid;
800 	u32			cap_mask1;
801 	u32			cap_mask1_perm;
802 	u16			cap_mask2;
803 	u16			cap_mask2_perm;
804 	u16			lid;
805 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
806 	u8			lmc;
807 	u8			subnet_timeout;
808 	u16			sm_lid;
809 	u8			sm_sl;
810 	u16			qkey_violation_counter;
811 	u16			pkey_violation_counter;
812 	bool			grh_required;
813 };
814 
815 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
816 {
817 		return buf->frags->buf + offset;
818 }
819 
820 #define STRUCT_FIELD(header, field) \
821 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
822 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
823 
824 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
825 {
826 	return pci_get_drvdata(pdev);
827 }
828 
829 extern struct dentry *mlx5_debugfs_root;
830 
831 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
832 {
833 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
834 }
835 
836 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
837 {
838 	return ioread32be(&dev->iseg->fw_rev) >> 16;
839 }
840 
841 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
842 {
843 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
844 }
845 
846 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
847 {
848 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
849 }
850 
851 static inline u32 mlx5_base_mkey(const u32 key)
852 {
853 	return key & 0xffffff00u;
854 }
855 
856 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
857 					u8 log_stride, u8 log_sz,
858 					u16 strides_offset,
859 					struct mlx5_frag_buf_ctrl *fbc)
860 {
861 	fbc->frags      = frags;
862 	fbc->log_stride = log_stride;
863 	fbc->log_sz     = log_sz;
864 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
865 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
866 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
867 	fbc->strides_offset = strides_offset;
868 }
869 
870 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
871 				 u8 log_stride, u8 log_sz,
872 				 struct mlx5_frag_buf_ctrl *fbc)
873 {
874 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
875 }
876 
877 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
878 					  u32 ix)
879 {
880 	unsigned int frag;
881 
882 	ix  += fbc->strides_offset;
883 	frag = ix >> fbc->log_frag_strides;
884 
885 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
886 }
887 
888 static inline u32
889 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
890 {
891 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
892 
893 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
894 }
895 
896 int mlx5_cmd_init(struct mlx5_core_dev *dev);
897 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
898 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
899 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
900 
901 struct mlx5_async_ctx {
902 	struct mlx5_core_dev *dev;
903 	atomic_t num_inflight;
904 	struct wait_queue_head wait;
905 };
906 
907 struct mlx5_async_work;
908 
909 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
910 
911 struct mlx5_async_work {
912 	struct mlx5_async_ctx *ctx;
913 	mlx5_async_cbk_t user_callback;
914 };
915 
916 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
917 			     struct mlx5_async_ctx *ctx);
918 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
919 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
920 		     void *out, int out_size, mlx5_async_cbk_t callback,
921 		     struct mlx5_async_work *work);
922 
923 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
924 		  int out_size);
925 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
926 			  void *out, int out_size);
927 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
928 
929 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
930 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
931 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
932 void mlx5_health_flush(struct mlx5_core_dev *dev);
933 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
934 int mlx5_health_init(struct mlx5_core_dev *dev);
935 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
936 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
937 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
938 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
939 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
940 		   int size, struct mlx5_frag_buf *buf);
941 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
942 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
943 			     struct mlx5_frag_buf *buf, int node);
944 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
945 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
946 						      gfp_t flags, int npages);
947 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
948 				 struct mlx5_cmd_mailbox *head);
949 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
950 			     struct mlx5_core_mkey *mkey,
951 			     struct mlx5_async_ctx *async_ctx, u32 *in,
952 			     int inlen, u32 *out, int outlen,
953 			     mlx5_async_cbk_t callback,
954 			     struct mlx5_async_work *context);
955 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
956 			  struct mlx5_core_mkey *mkey,
957 			  u32 *in, int inlen);
958 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
959 			   struct mlx5_core_mkey *mkey);
960 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
961 			 u32 *out, int outlen);
962 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
963 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
964 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
965 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
966 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
967 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
968 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
969 				 s32 npages, bool ec_function);
970 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
971 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
972 void mlx5_register_debugfs(void);
973 void mlx5_unregister_debugfs(void);
974 
975 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
976 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
977 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
978 		    unsigned int *irqn);
979 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
980 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
981 
982 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
983 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
984 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
985 			 int size_in, void *data_out, int size_out,
986 			 u16 reg_num, int arg, int write);
987 
988 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
989 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
990 		       int node);
991 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
992 
993 const char *mlx5_command_str(int command);
994 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
995 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
996 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
997 			 int npsvs, u32 *sig_index);
998 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
999 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1000 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1001 			struct mlx5_odp_caps *odp_caps);
1002 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1003 			     u8 port_num, void *out, size_t sz);
1004 
1005 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1006 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1007 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1008 		     struct mlx5_rate_limit *rl);
1009 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1010 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1011 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1012 		       struct mlx5_rate_limit *rl_1);
1013 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1014 		     bool map_wc, bool fast_path);
1015 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1016 
1017 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1018 struct cpumask *
1019 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1020 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1021 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1022 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1023 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1024 
1025 static inline int fw_initializing(struct mlx5_core_dev *dev)
1026 {
1027 	return ioread32be(&dev->iseg->initializing) >> 31;
1028 }
1029 
1030 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1031 {
1032 	return mkey >> 8;
1033 }
1034 
1035 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1036 {
1037 	return mkey_idx << 8;
1038 }
1039 
1040 static inline u8 mlx5_mkey_variant(u32 mkey)
1041 {
1042 	return mkey & 0xff;
1043 }
1044 
1045 enum {
1046 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1047 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1048 };
1049 
1050 enum {
1051 	MR_CACHE_LAST_STD_ENTRY = 20,
1052 	MLX5_IMR_MTT_CACHE_ENTRY,
1053 	MLX5_IMR_KSM_CACHE_ENTRY,
1054 	MAX_MR_CACHE_ENTRIES
1055 };
1056 
1057 enum {
1058 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1059 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1060 };
1061 
1062 struct mlx5_interface {
1063 	void *			(*add)(struct mlx5_core_dev *dev);
1064 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1065 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1066 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1067 	int			protocol;
1068 	struct list_head	list;
1069 };
1070 
1071 int mlx5_register_interface(struct mlx5_interface *intf);
1072 void mlx5_unregister_interface(struct mlx5_interface *intf);
1073 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1074 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1075 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1076 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1077 
1078 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1079 
1080 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1081 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1082 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1083 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1084 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1085 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1086 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1087 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1088 				 u64 *values,
1089 				 int num_counters,
1090 				 size_t *offsets);
1091 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1092 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1093 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1094 			 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
1095 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1096 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1097 
1098 #ifdef CONFIG_MLX5_CORE_IPOIB
1099 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1100 					  struct ib_device *ibdev,
1101 					  const char *name,
1102 					  void (*setup)(struct net_device *));
1103 #endif /* CONFIG_MLX5_CORE_IPOIB */
1104 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1105 			    struct ib_device *device,
1106 			    struct rdma_netdev_alloc_params *params);
1107 
1108 struct mlx5_profile {
1109 	u64	mask;
1110 	u8	log_max_qp;
1111 	struct {
1112 		int	size;
1113 		int	limit;
1114 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1115 };
1116 
1117 enum {
1118 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1119 };
1120 
1121 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1122 {
1123 	return dev->coredev_type == MLX5_COREDEV_PF;
1124 }
1125 
1126 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1127 {
1128 	return dev->coredev_type == MLX5_COREDEV_VF;
1129 }
1130 
1131 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1132 {
1133 	return dev->caps.embedded_cpu;
1134 }
1135 
1136 static inline bool
1137 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1138 {
1139 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1140 }
1141 
1142 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1143 {
1144 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1145 }
1146 
1147 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1148 {
1149 	return dev->priv.sriov.max_vfs;
1150 }
1151 
1152 static inline int mlx5_get_gid_table_len(u16 param)
1153 {
1154 	if (param > 4) {
1155 		pr_warn("gid table length is zero\n");
1156 		return 0;
1157 	}
1158 
1159 	return 8 * (1 << param);
1160 }
1161 
1162 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1163 {
1164 	return !!(dev->priv.rl_table.max_size);
1165 }
1166 
1167 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1168 {
1169 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1170 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1171 }
1172 
1173 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1174 {
1175 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1176 }
1177 
1178 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1179 {
1180 	return mlx5_core_is_mp_slave(dev) ||
1181 	       mlx5_core_is_mp_master(dev);
1182 }
1183 
1184 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1185 {
1186 	if (!mlx5_core_mp_enabled(dev))
1187 		return 1;
1188 
1189 	return MLX5_CAP_GEN(dev, native_port_num);
1190 }
1191 
1192 enum {
1193 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1194 };
1195 
1196 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1197 {
1198 	struct devlink *devlink = priv_to_devlink(dev);
1199 	union devlink_param_value val;
1200 
1201 	devlink_param_driverinit_value_get(devlink,
1202 					   DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1203 					   &val);
1204 	return val.vbool;
1205 }
1206 
1207 #endif /* MLX5_DRIVER_H */
1208