1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 51 #include <linux/mlx5/device.h> 52 #include <linux/mlx5/doorbell.h> 53 #include <linux/mlx5/eq.h> 54 #include <linux/timecounter.h> 55 #include <linux/ptp_clock_kernel.h> 56 57 enum { 58 MLX5_BOARD_ID_LEN = 64, 59 MLX5_MAX_NAME_LEN = 16, 60 }; 61 62 enum { 63 /* one minute for the sake of bringup. Generally, commands must always 64 * complete and we may need to increase this timeout value 65 */ 66 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 67 MLX5_CMD_WQ_MAX_NAME = 32, 68 }; 69 70 enum { 71 CMD_OWNER_SW = 0x0, 72 CMD_OWNER_HW = 0x1, 73 CMD_STATUS_SUCCESS = 0, 74 }; 75 76 enum mlx5_sqp_t { 77 MLX5_SQP_SMI = 0, 78 MLX5_SQP_GSI = 1, 79 MLX5_SQP_IEEE_1588 = 2, 80 MLX5_SQP_SNIFFER = 3, 81 MLX5_SQP_SYNC_UMR = 4, 82 }; 83 84 enum { 85 MLX5_MAX_PORTS = 2, 86 }; 87 88 enum { 89 MLX5_ATOMIC_MODE_OFFSET = 16, 90 MLX5_ATOMIC_MODE_IB_COMP = 1, 91 MLX5_ATOMIC_MODE_CX = 2, 92 MLX5_ATOMIC_MODE_8B = 3, 93 MLX5_ATOMIC_MODE_16B = 4, 94 MLX5_ATOMIC_MODE_32B = 5, 95 MLX5_ATOMIC_MODE_64B = 6, 96 MLX5_ATOMIC_MODE_128B = 7, 97 MLX5_ATOMIC_MODE_256B = 8, 98 }; 99 100 enum { 101 MLX5_REG_QPTS = 0x4002, 102 MLX5_REG_QETCR = 0x4005, 103 MLX5_REG_QTCT = 0x400a, 104 MLX5_REG_QPDPM = 0x4013, 105 MLX5_REG_QCAM = 0x4019, 106 MLX5_REG_DCBX_PARAM = 0x4020, 107 MLX5_REG_DCBX_APP = 0x4021, 108 MLX5_REG_FPGA_CAP = 0x4022, 109 MLX5_REG_FPGA_CTRL = 0x4023, 110 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 111 MLX5_REG_PCAP = 0x5001, 112 MLX5_REG_PMTU = 0x5003, 113 MLX5_REG_PTYS = 0x5004, 114 MLX5_REG_PAOS = 0x5006, 115 MLX5_REG_PFCC = 0x5007, 116 MLX5_REG_PPCNT = 0x5008, 117 MLX5_REG_PPTB = 0x500b, 118 MLX5_REG_PBMC = 0x500c, 119 MLX5_REG_PMAOS = 0x5012, 120 MLX5_REG_PUDE = 0x5009, 121 MLX5_REG_PMPE = 0x5010, 122 MLX5_REG_PELC = 0x500e, 123 MLX5_REG_PVLC = 0x500f, 124 MLX5_REG_PCMR = 0x5041, 125 MLX5_REG_PMLP = 0x5002, 126 MLX5_REG_PPLM = 0x5023, 127 MLX5_REG_PCAM = 0x507f, 128 MLX5_REG_NODE_DESC = 0x6001, 129 MLX5_REG_HOST_ENDIANNESS = 0x7004, 130 MLX5_REG_MCIA = 0x9014, 131 MLX5_REG_MLCR = 0x902b, 132 MLX5_REG_MTRC_CAP = 0x9040, 133 MLX5_REG_MTRC_CONF = 0x9041, 134 MLX5_REG_MTRC_STDB = 0x9042, 135 MLX5_REG_MTRC_CTRL = 0x9043, 136 MLX5_REG_MPCNT = 0x9051, 137 MLX5_REG_MTPPS = 0x9053, 138 MLX5_REG_MTPPSE = 0x9054, 139 MLX5_REG_MPEGC = 0x9056, 140 MLX5_REG_MCQI = 0x9061, 141 MLX5_REG_MCC = 0x9062, 142 MLX5_REG_MCDA = 0x9063, 143 MLX5_REG_MCAM = 0x907f, 144 }; 145 146 enum mlx5_qpts_trust_state { 147 MLX5_QPTS_TRUST_PCP = 1, 148 MLX5_QPTS_TRUST_DSCP = 2, 149 }; 150 151 enum mlx5_dcbx_oper_mode { 152 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 153 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 154 }; 155 156 enum { 157 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 158 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 159 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 160 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 161 }; 162 163 enum mlx5_page_fault_resume_flags { 164 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 165 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 166 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 167 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 168 }; 169 170 enum dbg_rsc_type { 171 MLX5_DBG_RSC_QP, 172 MLX5_DBG_RSC_EQ, 173 MLX5_DBG_RSC_CQ, 174 }; 175 176 enum port_state_policy { 177 MLX5_POLICY_DOWN = 0, 178 MLX5_POLICY_UP = 1, 179 MLX5_POLICY_FOLLOW = 2, 180 MLX5_POLICY_INVALID = 0xffffffff 181 }; 182 183 struct mlx5_field_desc { 184 struct dentry *dent; 185 int i; 186 }; 187 188 struct mlx5_rsc_debug { 189 struct mlx5_core_dev *dev; 190 void *object; 191 enum dbg_rsc_type type; 192 struct dentry *root; 193 struct mlx5_field_desc fields[0]; 194 }; 195 196 enum mlx5_dev_event { 197 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 198 }; 199 200 enum mlx5_port_status { 201 MLX5_PORT_UP = 1, 202 MLX5_PORT_DOWN = 2, 203 }; 204 205 struct mlx5_bfreg_info { 206 u32 *sys_pages; 207 int num_low_latency_bfregs; 208 unsigned int *count; 209 210 /* 211 * protect bfreg allocation data structs 212 */ 213 struct mutex lock; 214 u32 ver; 215 bool lib_uar_4k; 216 u32 num_sys_pages; 217 u32 num_static_sys_pages; 218 u32 total_num_bfregs; 219 u32 num_dyn_bfregs; 220 }; 221 222 struct mlx5_cmd_first { 223 __be32 data[4]; 224 }; 225 226 struct mlx5_cmd_msg { 227 struct list_head list; 228 struct cmd_msg_cache *parent; 229 u32 len; 230 struct mlx5_cmd_first first; 231 struct mlx5_cmd_mailbox *next; 232 }; 233 234 struct mlx5_cmd_debug { 235 struct dentry *dbg_root; 236 struct dentry *dbg_in; 237 struct dentry *dbg_out; 238 struct dentry *dbg_outlen; 239 struct dentry *dbg_status; 240 struct dentry *dbg_run; 241 void *in_msg; 242 void *out_msg; 243 u8 status; 244 u16 inlen; 245 u16 outlen; 246 }; 247 248 struct cmd_msg_cache { 249 /* protect block chain allocations 250 */ 251 spinlock_t lock; 252 struct list_head head; 253 unsigned int max_inbox_size; 254 unsigned int num_ent; 255 }; 256 257 enum { 258 MLX5_NUM_COMMAND_CACHES = 5, 259 }; 260 261 struct mlx5_cmd_stats { 262 u64 sum; 263 u64 n; 264 struct dentry *root; 265 struct dentry *avg; 266 struct dentry *count; 267 /* protect command average calculations */ 268 spinlock_t lock; 269 }; 270 271 struct mlx5_cmd { 272 struct mlx5_nb nb; 273 274 void *cmd_alloc_buf; 275 dma_addr_t alloc_dma; 276 int alloc_size; 277 void *cmd_buf; 278 dma_addr_t dma; 279 u16 cmdif_rev; 280 u8 log_sz; 281 u8 log_stride; 282 int max_reg_cmds; 283 int events; 284 u32 __iomem *vector; 285 286 /* protect command queue allocations 287 */ 288 spinlock_t alloc_lock; 289 290 /* protect token allocations 291 */ 292 spinlock_t token_lock; 293 u8 token; 294 unsigned long bitmask; 295 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 296 struct workqueue_struct *wq; 297 struct semaphore sem; 298 struct semaphore pages_sem; 299 int mode; 300 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 301 struct dma_pool *pool; 302 struct mlx5_cmd_debug dbg; 303 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 304 int checksum_disabled; 305 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 306 }; 307 308 struct mlx5_port_caps { 309 int gid_table_len; 310 int pkey_table_len; 311 u8 ext_port_cap; 312 bool has_smi; 313 }; 314 315 struct mlx5_cmd_mailbox { 316 void *buf; 317 dma_addr_t dma; 318 struct mlx5_cmd_mailbox *next; 319 }; 320 321 struct mlx5_buf_list { 322 void *buf; 323 dma_addr_t map; 324 }; 325 326 struct mlx5_frag_buf { 327 struct mlx5_buf_list *frags; 328 int npages; 329 int size; 330 u8 page_shift; 331 }; 332 333 struct mlx5_frag_buf_ctrl { 334 struct mlx5_buf_list *frags; 335 u32 sz_m1; 336 u16 frag_sz_m1; 337 u16 strides_offset; 338 u8 log_sz; 339 u8 log_stride; 340 u8 log_frag_strides; 341 }; 342 343 struct mlx5_core_psv { 344 u32 psv_idx; 345 struct psv_layout { 346 u32 pd; 347 u16 syndrome; 348 u16 reserved; 349 u16 bg; 350 u16 app_tag; 351 u32 ref_tag; 352 } psv; 353 }; 354 355 struct mlx5_core_sig_ctx { 356 struct mlx5_core_psv psv_memory; 357 struct mlx5_core_psv psv_wire; 358 struct ib_sig_err err_item; 359 bool sig_status_checked; 360 bool sig_err_exists; 361 u32 sigerr_count; 362 }; 363 364 enum { 365 MLX5_MKEY_MR = 1, 366 MLX5_MKEY_MW, 367 }; 368 369 struct mlx5_core_mkey { 370 u64 iova; 371 u64 size; 372 u32 key; 373 u32 pd; 374 u32 type; 375 }; 376 377 #define MLX5_24BIT_MASK ((1 << 24) - 1) 378 379 enum mlx5_res_type { 380 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 381 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 382 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 383 MLX5_RES_SRQ = 3, 384 MLX5_RES_XSRQ = 4, 385 MLX5_RES_XRQ = 5, 386 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 387 }; 388 389 struct mlx5_core_rsc_common { 390 enum mlx5_res_type res; 391 atomic_t refcount; 392 struct completion free; 393 }; 394 395 struct mlx5_uars_page { 396 void __iomem *map; 397 bool wc; 398 u32 index; 399 struct list_head list; 400 unsigned int bfregs; 401 unsigned long *reg_bitmap; /* for non fast path bf regs */ 402 unsigned long *fp_bitmap; 403 unsigned int reg_avail; 404 unsigned int fp_avail; 405 struct kref ref_count; 406 struct mlx5_core_dev *mdev; 407 }; 408 409 struct mlx5_bfreg_head { 410 /* protect blue flame registers allocations */ 411 struct mutex lock; 412 struct list_head list; 413 }; 414 415 struct mlx5_bfreg_data { 416 struct mlx5_bfreg_head reg_head; 417 struct mlx5_bfreg_head wc_head; 418 }; 419 420 struct mlx5_sq_bfreg { 421 void __iomem *map; 422 struct mlx5_uars_page *up; 423 bool wc; 424 u32 index; 425 unsigned int offset; 426 }; 427 428 struct mlx5_core_health { 429 struct health_buffer __iomem *health; 430 __be32 __iomem *health_counter; 431 struct timer_list timer; 432 u32 prev; 433 int miss_counter; 434 bool sick; 435 /* wq spinlock to synchronize draining */ 436 spinlock_t wq_lock; 437 struct workqueue_struct *wq; 438 unsigned long flags; 439 struct work_struct work; 440 struct delayed_work recover_work; 441 }; 442 443 struct mlx5_qp_table { 444 struct notifier_block nb; 445 446 /* protect radix tree 447 */ 448 spinlock_t lock; 449 struct radix_tree_root tree; 450 }; 451 452 struct mlx5_mkey_table { 453 /* protect radix tree 454 */ 455 rwlock_t lock; 456 struct radix_tree_root tree; 457 }; 458 459 struct mlx5_vf_context { 460 int enabled; 461 u64 port_guid; 462 u64 node_guid; 463 enum port_state_policy policy; 464 }; 465 466 struct mlx5_core_sriov { 467 struct mlx5_vf_context *vfs_ctx; 468 int num_vfs; 469 int enabled_vfs; 470 }; 471 472 struct mlx5_fc_stats { 473 spinlock_t counters_idr_lock; /* protects counters_idr */ 474 struct idr counters_idr; 475 struct list_head counters; 476 struct llist_head addlist; 477 struct llist_head dellist; 478 479 struct workqueue_struct *wq; 480 struct delayed_work work; 481 unsigned long next_query; 482 unsigned long sampling_interval; /* jiffies */ 483 }; 484 485 struct mlx5_events; 486 struct mlx5_mpfs; 487 struct mlx5_eswitch; 488 struct mlx5_lag; 489 struct mlx5_devcom; 490 struct mlx5_eq_table; 491 492 struct mlx5_rate_limit { 493 u32 rate; 494 u32 max_burst_sz; 495 u16 typical_pkt_sz; 496 }; 497 498 struct mlx5_rl_entry { 499 struct mlx5_rate_limit rl; 500 u16 index; 501 u16 refcount; 502 }; 503 504 struct mlx5_rl_table { 505 /* protect rate limit table */ 506 struct mutex rl_lock; 507 u16 max_size; 508 u32 max_rate; 509 u32 min_rate; 510 struct mlx5_rl_entry *rl_entry; 511 }; 512 513 struct mlx5_priv { 514 char name[MLX5_MAX_NAME_LEN]; 515 struct mlx5_eq_table *eq_table; 516 517 /* pages stuff */ 518 struct mlx5_nb pg_nb; 519 struct workqueue_struct *pg_wq; 520 struct rb_root page_root; 521 int fw_pages; 522 atomic_t reg_pages; 523 struct list_head free_list; 524 int vfs_pages; 525 526 struct mlx5_core_health health; 527 528 /* start: qp staff */ 529 struct mlx5_qp_table qp_table; 530 struct dentry *qp_debugfs; 531 struct dentry *eq_debugfs; 532 struct dentry *cq_debugfs; 533 struct dentry *cmdif_debugfs; 534 /* end: qp staff */ 535 536 /* start: mkey staff */ 537 struct mlx5_mkey_table mkey_table; 538 /* end: mkey staff */ 539 540 /* start: alloc staff */ 541 /* protect buffer alocation according to numa node */ 542 struct mutex alloc_mutex; 543 int numa_node; 544 545 struct mutex pgdir_mutex; 546 struct list_head pgdir_list; 547 /* end: alloc staff */ 548 struct dentry *dbg_root; 549 550 /* protect mkey key part */ 551 spinlock_t mkey_lock; 552 u8 mkey_key; 553 554 struct list_head dev_list; 555 struct list_head ctx_list; 556 spinlock_t ctx_lock; 557 struct mlx5_events *events; 558 559 struct mlx5_flow_steering *steering; 560 struct mlx5_mpfs *mpfs; 561 struct mlx5_eswitch *eswitch; 562 struct mlx5_core_sriov sriov; 563 struct mlx5_lag *lag; 564 struct mlx5_devcom *devcom; 565 unsigned long pci_dev_data; 566 struct mlx5_fc_stats fc_stats; 567 struct mlx5_rl_table rl_table; 568 569 struct mlx5_bfreg_data bfregs; 570 struct mlx5_uars_page *uar; 571 }; 572 573 enum mlx5_device_state { 574 MLX5_DEVICE_STATE_UP, 575 MLX5_DEVICE_STATE_INTERNAL_ERROR, 576 }; 577 578 enum mlx5_interface_state { 579 MLX5_INTERFACE_STATE_UP = BIT(0), 580 }; 581 582 enum mlx5_pci_status { 583 MLX5_PCI_STATUS_DISABLED, 584 MLX5_PCI_STATUS_ENABLED, 585 }; 586 587 enum mlx5_pagefault_type_flags { 588 MLX5_PFAULT_REQUESTOR = 1 << 0, 589 MLX5_PFAULT_WRITE = 1 << 1, 590 MLX5_PFAULT_RDMA = 1 << 2, 591 }; 592 593 struct mlx5_td { 594 struct list_head tirs_list; 595 u32 tdn; 596 }; 597 598 struct mlx5e_resources { 599 u32 pdn; 600 struct mlx5_td td; 601 struct mlx5_core_mkey mkey; 602 struct mlx5_sq_bfreg bfreg; 603 }; 604 605 #define MLX5_MAX_RESERVED_GIDS 8 606 607 struct mlx5_rsvd_gids { 608 unsigned int start; 609 unsigned int count; 610 struct ida ida; 611 }; 612 613 #define MAX_PIN_NUM 8 614 struct mlx5_pps { 615 u8 pin_caps[MAX_PIN_NUM]; 616 struct work_struct out_work; 617 u64 start[MAX_PIN_NUM]; 618 u8 enabled; 619 }; 620 621 struct mlx5_clock { 622 struct mlx5_core_dev *mdev; 623 struct mlx5_nb pps_nb; 624 seqlock_t lock; 625 struct cyclecounter cycles; 626 struct timecounter tc; 627 struct hwtstamp_config hwtstamp_config; 628 u32 nominal_c_mult; 629 unsigned long overflow_period; 630 struct delayed_work overflow_work; 631 struct ptp_clock *ptp; 632 struct ptp_clock_info ptp_info; 633 struct mlx5_pps pps_info; 634 }; 635 636 struct mlx5_fw_tracer; 637 struct mlx5_vxlan; 638 639 struct mlx5_core_dev { 640 struct pci_dev *pdev; 641 /* sync pci state */ 642 struct mutex pci_status_mutex; 643 enum mlx5_pci_status pci_status; 644 u8 rev_id; 645 char board_id[MLX5_BOARD_ID_LEN]; 646 struct mlx5_cmd cmd; 647 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 648 struct { 649 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 650 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 651 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 652 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 653 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 654 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 655 } caps; 656 u64 sys_image_guid; 657 phys_addr_t iseg_base; 658 struct mlx5_init_seg __iomem *iseg; 659 enum mlx5_device_state state; 660 /* sync interface state */ 661 struct mutex intf_state_mutex; 662 unsigned long intf_state; 663 struct mlx5_priv priv; 664 struct mlx5_profile *profile; 665 atomic_t num_qps; 666 u32 issi; 667 struct mlx5e_resources mlx5e_res; 668 struct mlx5_vxlan *vxlan; 669 struct { 670 struct mlx5_rsvd_gids reserved_gids; 671 u32 roce_en; 672 } roce; 673 #ifdef CONFIG_MLX5_FPGA 674 struct mlx5_fpga_device *fpga; 675 #endif 676 struct mlx5_clock clock; 677 struct mlx5_ib_clock_info *clock_info; 678 struct page *clock_info_page; 679 struct mlx5_fw_tracer *tracer; 680 }; 681 682 struct mlx5_db { 683 __be32 *db; 684 union { 685 struct mlx5_db_pgdir *pgdir; 686 struct mlx5_ib_user_db_page *user_page; 687 } u; 688 dma_addr_t dma; 689 int index; 690 }; 691 692 enum { 693 MLX5_COMP_EQ_SIZE = 1024, 694 }; 695 696 enum { 697 MLX5_PTYS_IB = 1 << 0, 698 MLX5_PTYS_EN = 1 << 2, 699 }; 700 701 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 702 703 enum { 704 MLX5_CMD_ENT_STATE_PENDING_COMP, 705 }; 706 707 struct mlx5_cmd_work_ent { 708 unsigned long state; 709 struct mlx5_cmd_msg *in; 710 struct mlx5_cmd_msg *out; 711 void *uout; 712 int uout_size; 713 mlx5_cmd_cbk_t callback; 714 struct delayed_work cb_timeout_work; 715 void *context; 716 int idx; 717 struct completion done; 718 struct mlx5_cmd *cmd; 719 struct work_struct work; 720 struct mlx5_cmd_layout *lay; 721 int ret; 722 int page_queue; 723 u8 status; 724 u8 token; 725 u64 ts1; 726 u64 ts2; 727 u16 op; 728 bool polling; 729 }; 730 731 struct mlx5_pas { 732 u64 pa; 733 u8 log_sz; 734 }; 735 736 enum phy_port_state { 737 MLX5_AAA_111 738 }; 739 740 struct mlx5_hca_vport_context { 741 u32 field_select; 742 bool sm_virt_aware; 743 bool has_smi; 744 bool has_raw; 745 enum port_state_policy policy; 746 enum phy_port_state phys_state; 747 enum ib_port_state vport_state; 748 u8 port_physical_state; 749 u64 sys_image_guid; 750 u64 port_guid; 751 u64 node_guid; 752 u32 cap_mask1; 753 u32 cap_mask1_perm; 754 u16 cap_mask2; 755 u16 cap_mask2_perm; 756 u16 lid; 757 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 758 u8 lmc; 759 u8 subnet_timeout; 760 u16 sm_lid; 761 u8 sm_sl; 762 u16 qkey_violation_counter; 763 u16 pkey_violation_counter; 764 bool grh_required; 765 }; 766 767 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 768 { 769 return buf->frags->buf + offset; 770 } 771 772 #define STRUCT_FIELD(header, field) \ 773 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 774 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 775 776 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 777 { 778 return pci_get_drvdata(pdev); 779 } 780 781 extern struct dentry *mlx5_debugfs_root; 782 783 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 784 { 785 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 786 } 787 788 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 789 { 790 return ioread32be(&dev->iseg->fw_rev) >> 16; 791 } 792 793 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 794 { 795 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 796 } 797 798 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 799 { 800 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 801 } 802 803 static inline u32 mlx5_base_mkey(const u32 key) 804 { 805 return key & 0xffffff00u; 806 } 807 808 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 809 u8 log_stride, u8 log_sz, 810 u16 strides_offset, 811 struct mlx5_frag_buf_ctrl *fbc) 812 { 813 fbc->frags = frags; 814 fbc->log_stride = log_stride; 815 fbc->log_sz = log_sz; 816 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 817 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 818 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 819 fbc->strides_offset = strides_offset; 820 } 821 822 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 823 u8 log_stride, u8 log_sz, 824 struct mlx5_frag_buf_ctrl *fbc) 825 { 826 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 827 } 828 829 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 830 u32 ix) 831 { 832 unsigned int frag; 833 834 ix += fbc->strides_offset; 835 frag = ix >> fbc->log_frag_strides; 836 837 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 838 } 839 840 static inline u32 841 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 842 { 843 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 844 845 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 846 } 847 848 int mlx5_cmd_init(struct mlx5_core_dev *dev); 849 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 850 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 851 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 852 853 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 854 int out_size); 855 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 856 void *out, int out_size, mlx5_cmd_cbk_t callback, 857 void *context); 858 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 859 void *out, int out_size); 860 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 861 862 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 863 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 864 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 865 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 866 int mlx5_health_init(struct mlx5_core_dev *dev); 867 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 868 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 869 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 870 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 871 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 872 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 873 struct mlx5_frag_buf *buf, int node); 874 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 875 int size, struct mlx5_frag_buf *buf); 876 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 877 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 878 struct mlx5_frag_buf *buf, int node); 879 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 880 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 881 gfp_t flags, int npages); 882 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 883 struct mlx5_cmd_mailbox *head); 884 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 885 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 886 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 887 struct mlx5_core_mkey *mkey, 888 u32 *in, int inlen, 889 u32 *out, int outlen, 890 mlx5_cmd_cbk_t callback, void *context); 891 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 892 struct mlx5_core_mkey *mkey, 893 u32 *in, int inlen); 894 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 895 struct mlx5_core_mkey *mkey); 896 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 897 u32 *out, int outlen); 898 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 899 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 900 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 901 u16 opmod, u8 port); 902 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 903 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 904 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 905 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 906 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 907 s32 npages); 908 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 909 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 910 void mlx5_register_debugfs(void); 911 void mlx5_unregister_debugfs(void); 912 913 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 914 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 915 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 916 unsigned int *irqn); 917 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 918 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 919 920 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 921 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 922 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 923 int size_in, void *data_out, int size_out, 924 u16 reg_num, int arg, int write); 925 926 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 927 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 928 int node); 929 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 930 931 const char *mlx5_command_str(int command); 932 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 933 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 934 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 935 int npsvs, u32 *sig_index); 936 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 937 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 938 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 939 struct mlx5_odp_caps *odp_caps); 940 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 941 u8 port_num, void *out, size_t sz); 942 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 943 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 944 u32 wq_num, u8 type, int error); 945 #endif 946 947 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 948 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 949 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 950 struct mlx5_rate_limit *rl); 951 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 952 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 953 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 954 struct mlx5_rate_limit *rl_1); 955 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 956 bool map_wc, bool fast_path); 957 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 958 959 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 960 struct cpumask * 961 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 962 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 963 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 964 u8 roce_version, u8 roce_l3_type, const u8 *gid, 965 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 966 967 static inline int fw_initializing(struct mlx5_core_dev *dev) 968 { 969 return ioread32be(&dev->iseg->initializing) >> 31; 970 } 971 972 static inline u32 mlx5_mkey_to_idx(u32 mkey) 973 { 974 return mkey >> 8; 975 } 976 977 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 978 { 979 return mkey_idx << 8; 980 } 981 982 static inline u8 mlx5_mkey_variant(u32 mkey) 983 { 984 return mkey & 0xff; 985 } 986 987 enum { 988 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 989 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 990 }; 991 992 enum { 993 MR_CACHE_LAST_STD_ENTRY = 20, 994 MLX5_IMR_MTT_CACHE_ENTRY, 995 MLX5_IMR_KSM_CACHE_ENTRY, 996 MAX_MR_CACHE_ENTRIES 997 }; 998 999 enum { 1000 MLX5_INTERFACE_PROTOCOL_IB = 0, 1001 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1002 }; 1003 1004 struct mlx5_interface { 1005 void * (*add)(struct mlx5_core_dev *dev); 1006 void (*remove)(struct mlx5_core_dev *dev, void *context); 1007 int (*attach)(struct mlx5_core_dev *dev, void *context); 1008 void (*detach)(struct mlx5_core_dev *dev, void *context); 1009 int protocol; 1010 struct list_head list; 1011 }; 1012 1013 int mlx5_register_interface(struct mlx5_interface *intf); 1014 void mlx5_unregister_interface(struct mlx5_interface *intf); 1015 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1016 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1017 1018 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1019 1020 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1021 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1022 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1023 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1024 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1025 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1026 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1027 u64 *values, 1028 int num_counters, 1029 size_t *offsets); 1030 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1031 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1032 1033 #ifdef CONFIG_MLX5_CORE_IPOIB 1034 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1035 struct ib_device *ibdev, 1036 const char *name, 1037 void (*setup)(struct net_device *)); 1038 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1039 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1040 struct ib_device *device, 1041 struct rdma_netdev_alloc_params *params); 1042 1043 struct mlx5_profile { 1044 u64 mask; 1045 u8 log_max_qp; 1046 struct { 1047 int size; 1048 int limit; 1049 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1050 }; 1051 1052 enum { 1053 MLX5_PCI_DEV_IS_VF = 1 << 0, 1054 }; 1055 1056 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1057 { 1058 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1059 } 1060 1061 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) 1062 #define MLX5_VPORT_MANAGER(mdev) \ 1063 (MLX5_CAP_GEN(mdev, vport_group_manager) && \ 1064 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ 1065 mlx5_core_is_pf(mdev)) 1066 1067 static inline int mlx5_get_gid_table_len(u16 param) 1068 { 1069 if (param > 4) { 1070 pr_warn("gid table length is zero\n"); 1071 return 0; 1072 } 1073 1074 return 8 * (1 << param); 1075 } 1076 1077 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1078 { 1079 return !!(dev->priv.rl_table.max_size); 1080 } 1081 1082 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1083 { 1084 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1085 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1086 } 1087 1088 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1089 { 1090 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1091 } 1092 1093 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1094 { 1095 return mlx5_core_is_mp_slave(dev) || 1096 mlx5_core_is_mp_master(dev); 1097 } 1098 1099 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1100 { 1101 if (!mlx5_core_mp_enabled(dev)) 1102 return 1; 1103 1104 return MLX5_CAP_GEN(dev, native_port_num); 1105 } 1106 1107 enum { 1108 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1109 }; 1110 1111 #endif /* MLX5_DRIVER_H */ 1112