1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/xarray.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 #include <linux/refcount.h> 51 52 #include <linux/mlx5/device.h> 53 #include <linux/mlx5/doorbell.h> 54 #include <linux/mlx5/eq.h> 55 #include <linux/timecounter.h> 56 #include <linux/ptp_clock_kernel.h> 57 #include <net/devlink.h> 58 59 enum { 60 MLX5_BOARD_ID_LEN = 64, 61 }; 62 63 enum { 64 /* one minute for the sake of bringup. Generally, commands must always 65 * complete and we may need to increase this timeout value 66 */ 67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 68 MLX5_CMD_WQ_MAX_NAME = 32, 69 }; 70 71 enum { 72 CMD_OWNER_SW = 0x0, 73 CMD_OWNER_HW = 0x1, 74 CMD_STATUS_SUCCESS = 0, 75 }; 76 77 enum mlx5_sqp_t { 78 MLX5_SQP_SMI = 0, 79 MLX5_SQP_GSI = 1, 80 MLX5_SQP_IEEE_1588 = 2, 81 MLX5_SQP_SNIFFER = 3, 82 MLX5_SQP_SYNC_UMR = 4, 83 }; 84 85 enum { 86 MLX5_MAX_PORTS = 2, 87 }; 88 89 enum { 90 MLX5_ATOMIC_MODE_OFFSET = 16, 91 MLX5_ATOMIC_MODE_IB_COMP = 1, 92 MLX5_ATOMIC_MODE_CX = 2, 93 MLX5_ATOMIC_MODE_8B = 3, 94 MLX5_ATOMIC_MODE_16B = 4, 95 MLX5_ATOMIC_MODE_32B = 5, 96 MLX5_ATOMIC_MODE_64B = 6, 97 MLX5_ATOMIC_MODE_128B = 7, 98 MLX5_ATOMIC_MODE_256B = 8, 99 }; 100 101 enum { 102 MLX5_REG_QPTS = 0x4002, 103 MLX5_REG_QETCR = 0x4005, 104 MLX5_REG_QTCT = 0x400a, 105 MLX5_REG_QPDPM = 0x4013, 106 MLX5_REG_QCAM = 0x4019, 107 MLX5_REG_DCBX_PARAM = 0x4020, 108 MLX5_REG_DCBX_APP = 0x4021, 109 MLX5_REG_FPGA_CAP = 0x4022, 110 MLX5_REG_FPGA_CTRL = 0x4023, 111 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 112 MLX5_REG_CORE_DUMP = 0x402e, 113 MLX5_REG_PCAP = 0x5001, 114 MLX5_REG_PMTU = 0x5003, 115 MLX5_REG_PTYS = 0x5004, 116 MLX5_REG_PAOS = 0x5006, 117 MLX5_REG_PFCC = 0x5007, 118 MLX5_REG_PPCNT = 0x5008, 119 MLX5_REG_PPTB = 0x500b, 120 MLX5_REG_PBMC = 0x500c, 121 MLX5_REG_PMAOS = 0x5012, 122 MLX5_REG_PUDE = 0x5009, 123 MLX5_REG_PMPE = 0x5010, 124 MLX5_REG_PELC = 0x500e, 125 MLX5_REG_PVLC = 0x500f, 126 MLX5_REG_PCMR = 0x5041, 127 MLX5_REG_PMLP = 0x5002, 128 MLX5_REG_PPLM = 0x5023, 129 MLX5_REG_PCAM = 0x507f, 130 MLX5_REG_NODE_DESC = 0x6001, 131 MLX5_REG_HOST_ENDIANNESS = 0x7004, 132 MLX5_REG_MCIA = 0x9014, 133 MLX5_REG_MFRL = 0x9028, 134 MLX5_REG_MLCR = 0x902b, 135 MLX5_REG_MTRC_CAP = 0x9040, 136 MLX5_REG_MTRC_CONF = 0x9041, 137 MLX5_REG_MTRC_STDB = 0x9042, 138 MLX5_REG_MTRC_CTRL = 0x9043, 139 MLX5_REG_MPEIN = 0x9050, 140 MLX5_REG_MPCNT = 0x9051, 141 MLX5_REG_MTPPS = 0x9053, 142 MLX5_REG_MTPPSE = 0x9054, 143 MLX5_REG_MPEGC = 0x9056, 144 MLX5_REG_MCQS = 0x9060, 145 MLX5_REG_MCQI = 0x9061, 146 MLX5_REG_MCC = 0x9062, 147 MLX5_REG_MCDA = 0x9063, 148 MLX5_REG_MCAM = 0x907f, 149 MLX5_REG_MIRC = 0x9162, 150 MLX5_REG_RESOURCE_DUMP = 0xC000, 151 }; 152 153 enum mlx5_qpts_trust_state { 154 MLX5_QPTS_TRUST_PCP = 1, 155 MLX5_QPTS_TRUST_DSCP = 2, 156 }; 157 158 enum mlx5_dcbx_oper_mode { 159 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 160 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 161 }; 162 163 enum { 164 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 165 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 166 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 167 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 168 }; 169 170 enum mlx5_page_fault_resume_flags { 171 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 172 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 173 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 174 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 175 }; 176 177 enum dbg_rsc_type { 178 MLX5_DBG_RSC_QP, 179 MLX5_DBG_RSC_EQ, 180 MLX5_DBG_RSC_CQ, 181 }; 182 183 enum port_state_policy { 184 MLX5_POLICY_DOWN = 0, 185 MLX5_POLICY_UP = 1, 186 MLX5_POLICY_FOLLOW = 2, 187 MLX5_POLICY_INVALID = 0xffffffff 188 }; 189 190 enum mlx5_coredev_type { 191 MLX5_COREDEV_PF, 192 MLX5_COREDEV_VF 193 }; 194 195 struct mlx5_field_desc { 196 int i; 197 }; 198 199 struct mlx5_rsc_debug { 200 struct mlx5_core_dev *dev; 201 void *object; 202 enum dbg_rsc_type type; 203 struct dentry *root; 204 struct mlx5_field_desc fields[0]; 205 }; 206 207 enum mlx5_dev_event { 208 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 209 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 210 }; 211 212 enum mlx5_port_status { 213 MLX5_PORT_UP = 1, 214 MLX5_PORT_DOWN = 2, 215 }; 216 217 struct mlx5_cmd_first { 218 __be32 data[4]; 219 }; 220 221 struct mlx5_cmd_msg { 222 struct list_head list; 223 struct cmd_msg_cache *parent; 224 u32 len; 225 struct mlx5_cmd_first first; 226 struct mlx5_cmd_mailbox *next; 227 }; 228 229 struct mlx5_cmd_debug { 230 struct dentry *dbg_root; 231 void *in_msg; 232 void *out_msg; 233 u8 status; 234 u16 inlen; 235 u16 outlen; 236 }; 237 238 struct cmd_msg_cache { 239 /* protect block chain allocations 240 */ 241 spinlock_t lock; 242 struct list_head head; 243 unsigned int max_inbox_size; 244 unsigned int num_ent; 245 }; 246 247 enum { 248 MLX5_NUM_COMMAND_CACHES = 5, 249 }; 250 251 struct mlx5_cmd_stats { 252 u64 sum; 253 u64 n; 254 struct dentry *root; 255 /* protect command average calculations */ 256 spinlock_t lock; 257 }; 258 259 struct mlx5_cmd { 260 struct mlx5_nb nb; 261 262 void *cmd_alloc_buf; 263 dma_addr_t alloc_dma; 264 int alloc_size; 265 void *cmd_buf; 266 dma_addr_t dma; 267 u16 cmdif_rev; 268 u8 log_sz; 269 u8 log_stride; 270 int max_reg_cmds; 271 int events; 272 u32 __iomem *vector; 273 274 /* protect command queue allocations 275 */ 276 spinlock_t alloc_lock; 277 278 /* protect token allocations 279 */ 280 spinlock_t token_lock; 281 u8 token; 282 unsigned long bitmask; 283 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 284 struct workqueue_struct *wq; 285 struct semaphore sem; 286 struct semaphore pages_sem; 287 int mode; 288 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 289 struct dma_pool *pool; 290 struct mlx5_cmd_debug dbg; 291 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 292 int checksum_disabled; 293 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 294 }; 295 296 struct mlx5_port_caps { 297 int gid_table_len; 298 int pkey_table_len; 299 u8 ext_port_cap; 300 bool has_smi; 301 }; 302 303 struct mlx5_cmd_mailbox { 304 void *buf; 305 dma_addr_t dma; 306 struct mlx5_cmd_mailbox *next; 307 }; 308 309 struct mlx5_buf_list { 310 void *buf; 311 dma_addr_t map; 312 }; 313 314 struct mlx5_frag_buf { 315 struct mlx5_buf_list *frags; 316 int npages; 317 int size; 318 u8 page_shift; 319 }; 320 321 struct mlx5_frag_buf_ctrl { 322 struct mlx5_buf_list *frags; 323 u32 sz_m1; 324 u16 frag_sz_m1; 325 u16 strides_offset; 326 u8 log_sz; 327 u8 log_stride; 328 u8 log_frag_strides; 329 }; 330 331 struct mlx5_core_psv { 332 u32 psv_idx; 333 struct psv_layout { 334 u32 pd; 335 u16 syndrome; 336 u16 reserved; 337 u16 bg; 338 u16 app_tag; 339 u32 ref_tag; 340 } psv; 341 }; 342 343 struct mlx5_core_sig_ctx { 344 struct mlx5_core_psv psv_memory; 345 struct mlx5_core_psv psv_wire; 346 struct ib_sig_err err_item; 347 bool sig_status_checked; 348 bool sig_err_exists; 349 u32 sigerr_count; 350 }; 351 352 enum { 353 MLX5_MKEY_MR = 1, 354 MLX5_MKEY_MW, 355 MLX5_MKEY_INDIRECT_DEVX, 356 }; 357 358 struct mlx5_core_mkey { 359 u64 iova; 360 u64 size; 361 u32 key; 362 u32 pd; 363 u32 type; 364 }; 365 366 #define MLX5_24BIT_MASK ((1 << 24) - 1) 367 368 enum mlx5_res_type { 369 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 370 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 371 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 372 MLX5_RES_SRQ = 3, 373 MLX5_RES_XSRQ = 4, 374 MLX5_RES_XRQ = 5, 375 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 376 }; 377 378 struct mlx5_core_rsc_common { 379 enum mlx5_res_type res; 380 refcount_t refcount; 381 struct completion free; 382 }; 383 384 struct mlx5_uars_page { 385 void __iomem *map; 386 bool wc; 387 u32 index; 388 struct list_head list; 389 unsigned int bfregs; 390 unsigned long *reg_bitmap; /* for non fast path bf regs */ 391 unsigned long *fp_bitmap; 392 unsigned int reg_avail; 393 unsigned int fp_avail; 394 struct kref ref_count; 395 struct mlx5_core_dev *mdev; 396 }; 397 398 struct mlx5_bfreg_head { 399 /* protect blue flame registers allocations */ 400 struct mutex lock; 401 struct list_head list; 402 }; 403 404 struct mlx5_bfreg_data { 405 struct mlx5_bfreg_head reg_head; 406 struct mlx5_bfreg_head wc_head; 407 }; 408 409 struct mlx5_sq_bfreg { 410 void __iomem *map; 411 struct mlx5_uars_page *up; 412 bool wc; 413 u32 index; 414 unsigned int offset; 415 }; 416 417 struct mlx5_core_health { 418 struct health_buffer __iomem *health; 419 __be32 __iomem *health_counter; 420 struct timer_list timer; 421 u32 prev; 422 int miss_counter; 423 u8 synd; 424 u32 fatal_error; 425 u32 crdump_size; 426 /* wq spinlock to synchronize draining */ 427 spinlock_t wq_lock; 428 struct workqueue_struct *wq; 429 unsigned long flags; 430 struct work_struct fatal_report_work; 431 struct work_struct report_work; 432 struct delayed_work recover_work; 433 struct devlink_health_reporter *fw_reporter; 434 struct devlink_health_reporter *fw_fatal_reporter; 435 }; 436 437 struct mlx5_qp_table { 438 struct notifier_block nb; 439 440 /* protect radix tree 441 */ 442 spinlock_t lock; 443 struct radix_tree_root tree; 444 }; 445 446 struct mlx5_vf_context { 447 int enabled; 448 u64 port_guid; 449 u64 node_guid; 450 /* Valid bits are used to validate administrative guid only. 451 * Enabled after ndo_set_vf_guid 452 */ 453 u8 port_guid_valid:1; 454 u8 node_guid_valid:1; 455 enum port_state_policy policy; 456 }; 457 458 struct mlx5_core_sriov { 459 struct mlx5_vf_context *vfs_ctx; 460 int num_vfs; 461 u16 max_vfs; 462 }; 463 464 struct mlx5_fc_pool { 465 struct mlx5_core_dev *dev; 466 struct mutex pool_lock; /* protects pool lists */ 467 struct list_head fully_used; 468 struct list_head partially_used; 469 struct list_head unused; 470 int available_fcs; 471 int used_fcs; 472 int threshold; 473 }; 474 475 struct mlx5_fc_stats { 476 spinlock_t counters_idr_lock; /* protects counters_idr */ 477 struct idr counters_idr; 478 struct list_head counters; 479 struct llist_head addlist; 480 struct llist_head dellist; 481 482 struct workqueue_struct *wq; 483 struct delayed_work work; 484 unsigned long next_query; 485 unsigned long sampling_interval; /* jiffies */ 486 u32 *bulk_query_out; 487 struct mlx5_fc_pool fc_pool; 488 }; 489 490 struct mlx5_events; 491 struct mlx5_mpfs; 492 struct mlx5_eswitch; 493 struct mlx5_lag; 494 struct mlx5_devcom; 495 struct mlx5_eq_table; 496 struct mlx5_irq_table; 497 498 struct mlx5_rate_limit { 499 u32 rate; 500 u32 max_burst_sz; 501 u16 typical_pkt_sz; 502 }; 503 504 struct mlx5_rl_entry { 505 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; 506 u16 index; 507 u64 refcount; 508 u16 uid; 509 u8 dedicated : 1; 510 }; 511 512 struct mlx5_rl_table { 513 /* protect rate limit table */ 514 struct mutex rl_lock; 515 u16 max_size; 516 u32 max_rate; 517 u32 min_rate; 518 struct mlx5_rl_entry *rl_entry; 519 }; 520 521 struct mlx5_core_roce { 522 struct mlx5_flow_table *ft; 523 struct mlx5_flow_group *fg; 524 struct mlx5_flow_handle *allow_rule; 525 }; 526 527 struct mlx5_priv { 528 /* IRQ table valid only for real pci devices PF or VF */ 529 struct mlx5_irq_table *irq_table; 530 struct mlx5_eq_table *eq_table; 531 532 /* pages stuff */ 533 struct mlx5_nb pg_nb; 534 struct workqueue_struct *pg_wq; 535 struct rb_root page_root; 536 int fw_pages; 537 atomic_t reg_pages; 538 struct list_head free_list; 539 int vfs_pages; 540 int peer_pf_pages; 541 542 struct mlx5_core_health health; 543 544 /* start: qp staff */ 545 struct dentry *qp_debugfs; 546 struct dentry *eq_debugfs; 547 struct dentry *cq_debugfs; 548 struct dentry *cmdif_debugfs; 549 /* end: qp staff */ 550 551 /* start: alloc staff */ 552 /* protect buffer alocation according to numa node */ 553 struct mutex alloc_mutex; 554 int numa_node; 555 556 struct mutex pgdir_mutex; 557 struct list_head pgdir_list; 558 /* end: alloc staff */ 559 struct dentry *dbg_root; 560 561 struct list_head dev_list; 562 struct list_head ctx_list; 563 spinlock_t ctx_lock; 564 struct mlx5_events *events; 565 566 struct mlx5_flow_steering *steering; 567 struct mlx5_mpfs *mpfs; 568 struct mlx5_eswitch *eswitch; 569 struct mlx5_core_sriov sriov; 570 struct mlx5_lag *lag; 571 struct mlx5_devcom *devcom; 572 struct mlx5_core_roce roce; 573 struct mlx5_fc_stats fc_stats; 574 struct mlx5_rl_table rl_table; 575 576 struct mlx5_bfreg_data bfregs; 577 struct mlx5_uars_page *uar; 578 }; 579 580 enum mlx5_device_state { 581 MLX5_DEVICE_STATE_UNINITIALIZED, 582 MLX5_DEVICE_STATE_UP, 583 MLX5_DEVICE_STATE_INTERNAL_ERROR, 584 }; 585 586 enum mlx5_interface_state { 587 MLX5_INTERFACE_STATE_UP = BIT(0), 588 }; 589 590 enum mlx5_pci_status { 591 MLX5_PCI_STATUS_DISABLED, 592 MLX5_PCI_STATUS_ENABLED, 593 }; 594 595 enum mlx5_pagefault_type_flags { 596 MLX5_PFAULT_REQUESTOR = 1 << 0, 597 MLX5_PFAULT_WRITE = 1 << 1, 598 MLX5_PFAULT_RDMA = 1 << 2, 599 }; 600 601 struct mlx5_td { 602 /* protects tirs list changes while tirs refresh */ 603 struct mutex list_lock; 604 struct list_head tirs_list; 605 u32 tdn; 606 }; 607 608 struct mlx5e_resources { 609 u32 pdn; 610 struct mlx5_td td; 611 struct mlx5_core_mkey mkey; 612 struct mlx5_sq_bfreg bfreg; 613 }; 614 615 enum mlx5_sw_icm_type { 616 MLX5_SW_ICM_TYPE_STEERING, 617 MLX5_SW_ICM_TYPE_HEADER_MODIFY, 618 }; 619 620 #define MLX5_MAX_RESERVED_GIDS 8 621 622 struct mlx5_rsvd_gids { 623 unsigned int start; 624 unsigned int count; 625 struct ida ida; 626 }; 627 628 #define MAX_PIN_NUM 8 629 struct mlx5_pps { 630 u8 pin_caps[MAX_PIN_NUM]; 631 struct work_struct out_work; 632 u64 start[MAX_PIN_NUM]; 633 u8 enabled; 634 }; 635 636 struct mlx5_clock { 637 struct mlx5_core_dev *mdev; 638 struct mlx5_nb pps_nb; 639 seqlock_t lock; 640 struct cyclecounter cycles; 641 struct timecounter tc; 642 struct hwtstamp_config hwtstamp_config; 643 u32 nominal_c_mult; 644 unsigned long overflow_period; 645 struct delayed_work overflow_work; 646 struct ptp_clock *ptp; 647 struct ptp_clock_info ptp_info; 648 struct mlx5_pps pps_info; 649 }; 650 651 struct mlx5_dm; 652 struct mlx5_fw_tracer; 653 struct mlx5_vxlan; 654 struct mlx5_geneve; 655 struct mlx5_hv_vhca; 656 657 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 658 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 659 660 struct mlx5_core_dev { 661 struct device *device; 662 enum mlx5_coredev_type coredev_type; 663 struct pci_dev *pdev; 664 /* sync pci state */ 665 struct mutex pci_status_mutex; 666 enum mlx5_pci_status pci_status; 667 u8 rev_id; 668 char board_id[MLX5_BOARD_ID_LEN]; 669 struct mlx5_cmd cmd; 670 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 671 struct { 672 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 673 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 674 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 675 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; 676 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 677 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 678 u8 embedded_cpu; 679 } caps; 680 u64 sys_image_guid; 681 phys_addr_t iseg_base; 682 struct mlx5_init_seg __iomem *iseg; 683 phys_addr_t bar_addr; 684 enum mlx5_device_state state; 685 /* sync interface state */ 686 struct mutex intf_state_mutex; 687 unsigned long intf_state; 688 struct mlx5_priv priv; 689 struct mlx5_profile *profile; 690 u32 issi; 691 struct mlx5e_resources mlx5e_res; 692 struct mlx5_dm *dm; 693 struct mlx5_vxlan *vxlan; 694 struct mlx5_geneve *geneve; 695 struct { 696 struct mlx5_rsvd_gids reserved_gids; 697 u32 roce_en; 698 } roce; 699 #ifdef CONFIG_MLX5_FPGA 700 struct mlx5_fpga_device *fpga; 701 #endif 702 struct mlx5_clock clock; 703 struct mlx5_ib_clock_info *clock_info; 704 struct mlx5_fw_tracer *tracer; 705 struct mlx5_rsc_dump *rsc_dump; 706 u32 vsc_addr; 707 struct mlx5_hv_vhca *hv_vhca; 708 }; 709 710 struct mlx5_db { 711 __be32 *db; 712 union { 713 struct mlx5_db_pgdir *pgdir; 714 struct mlx5_ib_user_db_page *user_page; 715 } u; 716 dma_addr_t dma; 717 int index; 718 }; 719 720 enum { 721 MLX5_COMP_EQ_SIZE = 1024, 722 }; 723 724 enum { 725 MLX5_PTYS_IB = 1 << 0, 726 MLX5_PTYS_EN = 1 << 2, 727 }; 728 729 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 730 731 enum { 732 MLX5_CMD_ENT_STATE_PENDING_COMP, 733 }; 734 735 struct mlx5_cmd_work_ent { 736 unsigned long state; 737 struct mlx5_cmd_msg *in; 738 struct mlx5_cmd_msg *out; 739 void *uout; 740 int uout_size; 741 mlx5_cmd_cbk_t callback; 742 struct delayed_work cb_timeout_work; 743 void *context; 744 int idx; 745 struct completion done; 746 struct mlx5_cmd *cmd; 747 struct work_struct work; 748 struct mlx5_cmd_layout *lay; 749 int ret; 750 int page_queue; 751 u8 status; 752 u8 token; 753 u64 ts1; 754 u64 ts2; 755 u16 op; 756 bool polling; 757 }; 758 759 struct mlx5_pas { 760 u64 pa; 761 u8 log_sz; 762 }; 763 764 enum phy_port_state { 765 MLX5_AAA_111 766 }; 767 768 struct mlx5_hca_vport_context { 769 u32 field_select; 770 bool sm_virt_aware; 771 bool has_smi; 772 bool has_raw; 773 enum port_state_policy policy; 774 enum phy_port_state phys_state; 775 enum ib_port_state vport_state; 776 u8 port_physical_state; 777 u64 sys_image_guid; 778 u64 port_guid; 779 u64 node_guid; 780 u32 cap_mask1; 781 u32 cap_mask1_perm; 782 u16 cap_mask2; 783 u16 cap_mask2_perm; 784 u16 lid; 785 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 786 u8 lmc; 787 u8 subnet_timeout; 788 u16 sm_lid; 789 u8 sm_sl; 790 u16 qkey_violation_counter; 791 u16 pkey_violation_counter; 792 bool grh_required; 793 }; 794 795 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 796 { 797 return buf->frags->buf + offset; 798 } 799 800 #define STRUCT_FIELD(header, field) \ 801 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 802 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 803 804 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 805 { 806 return pci_get_drvdata(pdev); 807 } 808 809 extern struct dentry *mlx5_debugfs_root; 810 811 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 812 { 813 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 814 } 815 816 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 817 { 818 return ioread32be(&dev->iseg->fw_rev) >> 16; 819 } 820 821 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 822 { 823 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 824 } 825 826 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 827 { 828 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 829 } 830 831 static inline u32 mlx5_base_mkey(const u32 key) 832 { 833 return key & 0xffffff00u; 834 } 835 836 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 837 u8 log_stride, u8 log_sz, 838 u16 strides_offset, 839 struct mlx5_frag_buf_ctrl *fbc) 840 { 841 fbc->frags = frags; 842 fbc->log_stride = log_stride; 843 fbc->log_sz = log_sz; 844 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 845 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 846 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 847 fbc->strides_offset = strides_offset; 848 } 849 850 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 851 u8 log_stride, u8 log_sz, 852 struct mlx5_frag_buf_ctrl *fbc) 853 { 854 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 855 } 856 857 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 858 u32 ix) 859 { 860 unsigned int frag; 861 862 ix += fbc->strides_offset; 863 frag = ix >> fbc->log_frag_strides; 864 865 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 866 } 867 868 static inline u32 869 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 870 { 871 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 872 873 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 874 } 875 876 int mlx5_cmd_init(struct mlx5_core_dev *dev); 877 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 878 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 879 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 880 881 struct mlx5_async_ctx { 882 struct mlx5_core_dev *dev; 883 atomic_t num_inflight; 884 struct wait_queue_head wait; 885 }; 886 887 struct mlx5_async_work; 888 889 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 890 891 struct mlx5_async_work { 892 struct mlx5_async_ctx *ctx; 893 mlx5_async_cbk_t user_callback; 894 }; 895 896 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 897 struct mlx5_async_ctx *ctx); 898 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 899 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 900 void *out, int out_size, mlx5_async_cbk_t callback, 901 struct mlx5_async_work *work); 902 903 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 904 int out_size); 905 906 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \ 907 ({ \ 908 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \ 909 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \ 910 }) 911 912 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \ 913 ({ \ 914 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \ 915 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \ 916 }) 917 918 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 919 void *out, int out_size); 920 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 921 922 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 923 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 924 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 925 void mlx5_health_flush(struct mlx5_core_dev *dev); 926 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 927 int mlx5_health_init(struct mlx5_core_dev *dev); 928 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 929 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 930 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 931 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 932 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 933 int size, struct mlx5_frag_buf *buf); 934 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 935 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 936 struct mlx5_frag_buf *buf, int node); 937 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 938 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 939 gfp_t flags, int npages); 940 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 941 struct mlx5_cmd_mailbox *head); 942 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 943 struct mlx5_core_mkey *mkey, 944 u32 *in, int inlen); 945 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 946 struct mlx5_core_mkey *mkey); 947 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 948 u32 *out, int outlen); 949 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 950 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 951 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 952 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 953 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 954 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 955 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 956 s32 npages, bool ec_function); 957 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 958 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 959 void mlx5_register_debugfs(void); 960 void mlx5_unregister_debugfs(void); 961 962 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 963 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 964 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 965 unsigned int *irqn); 966 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 967 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 968 969 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 970 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 971 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 972 int size_in, void *data_out, int size_out, 973 u16 reg_num, int arg, int write); 974 975 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 976 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 977 int node); 978 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 979 980 const char *mlx5_command_str(int command); 981 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 982 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 983 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 984 int npsvs, u32 *sig_index); 985 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 986 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 987 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 988 struct mlx5_odp_caps *odp_caps); 989 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 990 u8 port_num, void *out, size_t sz); 991 992 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 993 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 994 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 995 struct mlx5_rate_limit *rl); 996 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 997 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 998 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, 999 bool dedicated_entry, u16 *index); 1000 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); 1001 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 1002 struct mlx5_rate_limit *rl_1); 1003 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1004 bool map_wc, bool fast_path); 1005 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1006 1007 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 1008 struct cpumask * 1009 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 1010 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1011 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1012 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1013 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 1014 1015 static inline int fw_initializing(struct mlx5_core_dev *dev) 1016 { 1017 return ioread32be(&dev->iseg->initializing) >> 31; 1018 } 1019 1020 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1021 { 1022 return mkey >> 8; 1023 } 1024 1025 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1026 { 1027 return mkey_idx << 8; 1028 } 1029 1030 static inline u8 mlx5_mkey_variant(u32 mkey) 1031 { 1032 return mkey & 0xff; 1033 } 1034 1035 enum { 1036 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1037 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1038 }; 1039 1040 enum { 1041 MR_CACHE_LAST_STD_ENTRY = 20, 1042 MLX5_IMR_MTT_CACHE_ENTRY, 1043 MLX5_IMR_KSM_CACHE_ENTRY, 1044 MAX_MR_CACHE_ENTRIES 1045 }; 1046 1047 enum { 1048 MLX5_INTERFACE_PROTOCOL_IB = 0, 1049 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1050 }; 1051 1052 struct mlx5_interface { 1053 void * (*add)(struct mlx5_core_dev *dev); 1054 void (*remove)(struct mlx5_core_dev *dev, void *context); 1055 int (*attach)(struct mlx5_core_dev *dev, void *context); 1056 void (*detach)(struct mlx5_core_dev *dev, void *context); 1057 int protocol; 1058 struct list_head list; 1059 }; 1060 1061 int mlx5_register_interface(struct mlx5_interface *intf); 1062 void mlx5_unregister_interface(struct mlx5_interface *intf); 1063 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1064 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1065 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1066 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1067 1068 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1069 1070 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1071 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1072 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1073 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1074 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1075 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1076 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1077 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1078 u64 *values, 1079 int num_counters, 1080 size_t *offsets); 1081 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1082 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1083 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1084 u64 length, u32 log_alignment, u16 uid, 1085 phys_addr_t *addr, u32 *obj_id); 1086 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1087 u64 length, u16 uid, phys_addr_t addr, u32 obj_id); 1088 1089 #ifdef CONFIG_MLX5_CORE_IPOIB 1090 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1091 struct ib_device *ibdev, 1092 const char *name, 1093 void (*setup)(struct net_device *)); 1094 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1095 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1096 struct ib_device *device, 1097 struct rdma_netdev_alloc_params *params); 1098 1099 struct mlx5_profile { 1100 u64 mask; 1101 u8 log_max_qp; 1102 struct { 1103 int size; 1104 int limit; 1105 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1106 }; 1107 1108 enum { 1109 MLX5_PCI_DEV_IS_VF = 1 << 0, 1110 }; 1111 1112 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) 1113 { 1114 return dev->coredev_type == MLX5_COREDEV_PF; 1115 } 1116 1117 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) 1118 { 1119 return dev->coredev_type == MLX5_COREDEV_VF; 1120 } 1121 1122 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1123 { 1124 return dev->caps.embedded_cpu; 1125 } 1126 1127 static inline bool 1128 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) 1129 { 1130 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1131 } 1132 1133 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) 1134 { 1135 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1136 } 1137 1138 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) 1139 { 1140 return dev->priv.sriov.max_vfs; 1141 } 1142 1143 static inline int mlx5_get_gid_table_len(u16 param) 1144 { 1145 if (param > 4) { 1146 pr_warn("gid table length is zero\n"); 1147 return 0; 1148 } 1149 1150 return 8 * (1 << param); 1151 } 1152 1153 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1154 { 1155 return !!(dev->priv.rl_table.max_size); 1156 } 1157 1158 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1159 { 1160 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1161 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1162 } 1163 1164 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1165 { 1166 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1167 } 1168 1169 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1170 { 1171 return mlx5_core_is_mp_slave(dev) || 1172 mlx5_core_is_mp_master(dev); 1173 } 1174 1175 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1176 { 1177 if (!mlx5_core_mp_enabled(dev)) 1178 return 1; 1179 1180 return MLX5_CAP_GEN(dev, native_port_num); 1181 } 1182 1183 enum { 1184 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1185 }; 1186 1187 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev) 1188 { 1189 struct devlink *devlink = priv_to_devlink(dev); 1190 union devlink_param_value val; 1191 1192 devlink_param_driverinit_value_get(devlink, 1193 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 1194 &val); 1195 return val.vbool; 1196 } 1197 1198 #endif /* MLX5_DRIVER_H */ 1199