xref: /linux-6.15/include/linux/mlx5/driver.h (revision cd57dc5a) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/mempool.h>
46 #include <linux/interrupt.h>
47 #include <linux/idr.h>
48 
49 #include <linux/mlx5/device.h>
50 #include <linux/mlx5/doorbell.h>
51 #include <linux/mlx5/srq.h>
52 
53 enum {
54 	MLX5_BOARD_ID_LEN = 64,
55 	MLX5_MAX_NAME_LEN = 16,
56 };
57 
58 enum {
59 	/* one minute for the sake of bringup. Generally, commands must always
60 	 * complete and we may need to increase this timeout value
61 	 */
62 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
63 	MLX5_CMD_WQ_MAX_NAME	= 32,
64 };
65 
66 enum {
67 	CMD_OWNER_SW		= 0x0,
68 	CMD_OWNER_HW		= 0x1,
69 	CMD_STATUS_SUCCESS	= 0,
70 };
71 
72 enum mlx5_sqp_t {
73 	MLX5_SQP_SMI		= 0,
74 	MLX5_SQP_GSI		= 1,
75 	MLX5_SQP_IEEE_1588	= 2,
76 	MLX5_SQP_SNIFFER	= 3,
77 	MLX5_SQP_SYNC_UMR	= 4,
78 };
79 
80 enum {
81 	MLX5_MAX_PORTS	= 2,
82 };
83 
84 enum {
85 	MLX5_EQ_VEC_PAGES	 = 0,
86 	MLX5_EQ_VEC_CMD		 = 1,
87 	MLX5_EQ_VEC_ASYNC	 = 2,
88 	MLX5_EQ_VEC_PFAULT	 = 3,
89 	MLX5_EQ_VEC_COMP_BASE,
90 };
91 
92 enum {
93 	MLX5_MAX_IRQ_NAME	= 32
94 };
95 
96 enum {
97 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << 16,
98 	MLX5_ATOMIC_MODE_CX		= 2 << 16,
99 	MLX5_ATOMIC_MODE_8B		= 3 << 16,
100 	MLX5_ATOMIC_MODE_16B		= 4 << 16,
101 	MLX5_ATOMIC_MODE_32B		= 5 << 16,
102 	MLX5_ATOMIC_MODE_64B		= 6 << 16,
103 	MLX5_ATOMIC_MODE_128B		= 7 << 16,
104 	MLX5_ATOMIC_MODE_256B		= 8 << 16,
105 };
106 
107 enum {
108 	MLX5_REG_QETCR		 = 0x4005,
109 	MLX5_REG_QTCT		 = 0x400a,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_PCAP		 = 0x5001,
116 	MLX5_REG_PMTU		 = 0x5003,
117 	MLX5_REG_PTYS		 = 0x5004,
118 	MLX5_REG_PAOS		 = 0x5006,
119 	MLX5_REG_PFCC            = 0x5007,
120 	MLX5_REG_PPCNT		 = 0x5008,
121 	MLX5_REG_PMAOS		 = 0x5012,
122 	MLX5_REG_PUDE		 = 0x5009,
123 	MLX5_REG_PMPE		 = 0x5010,
124 	MLX5_REG_PELC		 = 0x500e,
125 	MLX5_REG_PVLC		 = 0x500f,
126 	MLX5_REG_PCMR		 = 0x5041,
127 	MLX5_REG_PMLP		 = 0x5002,
128 	MLX5_REG_PCAM		 = 0x507f,
129 	MLX5_REG_NODE_DESC	 = 0x6001,
130 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
131 	MLX5_REG_MCIA		 = 0x9014,
132 	MLX5_REG_MLCR		 = 0x902b,
133 	MLX5_REG_MPCNT		 = 0x9051,
134 	MLX5_REG_MTPPS		 = 0x9053,
135 	MLX5_REG_MTPPSE		 = 0x9054,
136 	MLX5_REG_MCQI		 = 0x9061,
137 	MLX5_REG_MCC		 = 0x9062,
138 	MLX5_REG_MCDA		 = 0x9063,
139 	MLX5_REG_MCAM		 = 0x907f,
140 };
141 
142 enum mlx5_dcbx_oper_mode {
143 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
144 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
145 };
146 
147 enum {
148 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
149 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
150 };
151 
152 enum mlx5_page_fault_resume_flags {
153 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
154 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
155 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
156 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
157 };
158 
159 enum dbg_rsc_type {
160 	MLX5_DBG_RSC_QP,
161 	MLX5_DBG_RSC_EQ,
162 	MLX5_DBG_RSC_CQ,
163 };
164 
165 enum port_state_policy {
166 	MLX5_POLICY_DOWN	= 0,
167 	MLX5_POLICY_UP		= 1,
168 	MLX5_POLICY_FOLLOW	= 2,
169 	MLX5_POLICY_INVALID	= 0xffffffff
170 };
171 
172 struct mlx5_field_desc {
173 	struct dentry	       *dent;
174 	int			i;
175 };
176 
177 struct mlx5_rsc_debug {
178 	struct mlx5_core_dev   *dev;
179 	void		       *object;
180 	enum dbg_rsc_type	type;
181 	struct dentry	       *root;
182 	struct mlx5_field_desc	fields[0];
183 };
184 
185 enum mlx5_dev_event {
186 	MLX5_DEV_EVENT_SYS_ERROR,
187 	MLX5_DEV_EVENT_PORT_UP,
188 	MLX5_DEV_EVENT_PORT_DOWN,
189 	MLX5_DEV_EVENT_PORT_INITIALIZED,
190 	MLX5_DEV_EVENT_LID_CHANGE,
191 	MLX5_DEV_EVENT_PKEY_CHANGE,
192 	MLX5_DEV_EVENT_GUID_CHANGE,
193 	MLX5_DEV_EVENT_CLIENT_REREG,
194 	MLX5_DEV_EVENT_PPS,
195 	MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
196 };
197 
198 enum mlx5_port_status {
199 	MLX5_PORT_UP        = 1,
200 	MLX5_PORT_DOWN      = 2,
201 };
202 
203 enum mlx5_eq_type {
204 	MLX5_EQ_TYPE_COMP,
205 	MLX5_EQ_TYPE_ASYNC,
206 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
207 	MLX5_EQ_TYPE_PF,
208 #endif
209 };
210 
211 struct mlx5_bfreg_info {
212 	u32		       *sys_pages;
213 	int			num_low_latency_bfregs;
214 	unsigned int	       *count;
215 
216 	/*
217 	 * protect bfreg allocation data structs
218 	 */
219 	struct mutex		lock;
220 	u32			ver;
221 	bool			lib_uar_4k;
222 	u32			num_sys_pages;
223 };
224 
225 struct mlx5_cmd_first {
226 	__be32		data[4];
227 };
228 
229 struct mlx5_cmd_msg {
230 	struct list_head		list;
231 	struct cmd_msg_cache	       *parent;
232 	u32				len;
233 	struct mlx5_cmd_first		first;
234 	struct mlx5_cmd_mailbox	       *next;
235 };
236 
237 struct mlx5_cmd_debug {
238 	struct dentry	       *dbg_root;
239 	struct dentry	       *dbg_in;
240 	struct dentry	       *dbg_out;
241 	struct dentry	       *dbg_outlen;
242 	struct dentry	       *dbg_status;
243 	struct dentry	       *dbg_run;
244 	void		       *in_msg;
245 	void		       *out_msg;
246 	u8			status;
247 	u16			inlen;
248 	u16			outlen;
249 };
250 
251 struct cmd_msg_cache {
252 	/* protect block chain allocations
253 	 */
254 	spinlock_t		lock;
255 	struct list_head	head;
256 	unsigned int		max_inbox_size;
257 	unsigned int		num_ent;
258 };
259 
260 enum {
261 	MLX5_NUM_COMMAND_CACHES = 5,
262 };
263 
264 struct mlx5_cmd_stats {
265 	u64		sum;
266 	u64		n;
267 	struct dentry  *root;
268 	struct dentry  *avg;
269 	struct dentry  *count;
270 	/* protect command average calculations */
271 	spinlock_t	lock;
272 };
273 
274 struct mlx5_cmd {
275 	void	       *cmd_alloc_buf;
276 	dma_addr_t	alloc_dma;
277 	int		alloc_size;
278 	void	       *cmd_buf;
279 	dma_addr_t	dma;
280 	u16		cmdif_rev;
281 	u8		log_sz;
282 	u8		log_stride;
283 	int		max_reg_cmds;
284 	int		events;
285 	u32 __iomem    *vector;
286 
287 	/* protect command queue allocations
288 	 */
289 	spinlock_t	alloc_lock;
290 
291 	/* protect token allocations
292 	 */
293 	spinlock_t	token_lock;
294 	u8		token;
295 	unsigned long	bitmask;
296 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
297 	struct workqueue_struct *wq;
298 	struct semaphore sem;
299 	struct semaphore pages_sem;
300 	int	mode;
301 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
302 	struct dma_pool *pool;
303 	struct mlx5_cmd_debug dbg;
304 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
305 	int checksum_disabled;
306 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
307 };
308 
309 struct mlx5_port_caps {
310 	int	gid_table_len;
311 	int	pkey_table_len;
312 	u8	ext_port_cap;
313 	bool	has_smi;
314 };
315 
316 struct mlx5_cmd_mailbox {
317 	void	       *buf;
318 	dma_addr_t	dma;
319 	struct mlx5_cmd_mailbox *next;
320 };
321 
322 struct mlx5_buf_list {
323 	void		       *buf;
324 	dma_addr_t		map;
325 };
326 
327 struct mlx5_buf {
328 	struct mlx5_buf_list	direct;
329 	int			npages;
330 	int			size;
331 	u8			page_shift;
332 };
333 
334 struct mlx5_frag_buf {
335 	struct mlx5_buf_list	*frags;
336 	int			npages;
337 	int			size;
338 	u8			page_shift;
339 };
340 
341 struct mlx5_eq_tasklet {
342 	struct list_head list;
343 	struct list_head process_list;
344 	struct tasklet_struct task;
345 	/* lock on completion tasklet list */
346 	spinlock_t lock;
347 };
348 
349 struct mlx5_eq_pagefault {
350 	struct work_struct       work;
351 	/* Pagefaults lock */
352 	spinlock_t		 lock;
353 	struct workqueue_struct *wq;
354 	mempool_t		*pool;
355 };
356 
357 struct mlx5_eq {
358 	struct mlx5_core_dev   *dev;
359 	__be32 __iomem	       *doorbell;
360 	u32			cons_index;
361 	struct mlx5_buf		buf;
362 	int			size;
363 	unsigned int		irqn;
364 	u8			eqn;
365 	int			nent;
366 	u64			mask;
367 	struct list_head	list;
368 	int			index;
369 	struct mlx5_rsc_debug	*dbg;
370 	enum mlx5_eq_type	type;
371 	union {
372 		struct mlx5_eq_tasklet   tasklet_ctx;
373 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
374 		struct mlx5_eq_pagefault pf_ctx;
375 #endif
376 	};
377 };
378 
379 struct mlx5_core_psv {
380 	u32	psv_idx;
381 	struct psv_layout {
382 		u32	pd;
383 		u16	syndrome;
384 		u16	reserved;
385 		u16	bg;
386 		u16	app_tag;
387 		u32	ref_tag;
388 	} psv;
389 };
390 
391 struct mlx5_core_sig_ctx {
392 	struct mlx5_core_psv	psv_memory;
393 	struct mlx5_core_psv	psv_wire;
394 	struct ib_sig_err       err_item;
395 	bool			sig_status_checked;
396 	bool			sig_err_exists;
397 	u32			sigerr_count;
398 };
399 
400 enum {
401 	MLX5_MKEY_MR = 1,
402 	MLX5_MKEY_MW,
403 };
404 
405 struct mlx5_core_mkey {
406 	u64			iova;
407 	u64			size;
408 	u32			key;
409 	u32			pd;
410 	u32			type;
411 };
412 
413 #define MLX5_24BIT_MASK		((1 << 24) - 1)
414 
415 enum mlx5_res_type {
416 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
417 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
418 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
419 	MLX5_RES_SRQ	= 3,
420 	MLX5_RES_XSRQ	= 4,
421 	MLX5_RES_XRQ	= 5,
422 };
423 
424 struct mlx5_core_rsc_common {
425 	enum mlx5_res_type	res;
426 	atomic_t		refcount;
427 	struct completion	free;
428 };
429 
430 struct mlx5_core_srq {
431 	struct mlx5_core_rsc_common	common; /* must be first */
432 	u32		srqn;
433 	int		max;
434 	int		max_gs;
435 	int		max_avail_gather;
436 	int		wqe_shift;
437 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
438 
439 	atomic_t		refcount;
440 	struct completion	free;
441 };
442 
443 struct mlx5_eq_table {
444 	void __iomem	       *update_ci;
445 	void __iomem	       *update_arm_ci;
446 	struct list_head	comp_eqs_list;
447 	struct mlx5_eq		pages_eq;
448 	struct mlx5_eq		async_eq;
449 	struct mlx5_eq		cmd_eq;
450 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
451 	struct mlx5_eq		pfault_eq;
452 #endif
453 	int			num_comp_vectors;
454 	/* protect EQs list
455 	 */
456 	spinlock_t		lock;
457 };
458 
459 struct mlx5_uars_page {
460 	void __iomem	       *map;
461 	bool			wc;
462 	u32			index;
463 	struct list_head	list;
464 	unsigned int		bfregs;
465 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
466 	unsigned long	       *fp_bitmap;
467 	unsigned int		reg_avail;
468 	unsigned int		fp_avail;
469 	struct kref		ref_count;
470 	struct mlx5_core_dev   *mdev;
471 };
472 
473 struct mlx5_bfreg_head {
474 	/* protect blue flame registers allocations */
475 	struct mutex		lock;
476 	struct list_head	list;
477 };
478 
479 struct mlx5_bfreg_data {
480 	struct mlx5_bfreg_head	reg_head;
481 	struct mlx5_bfreg_head	wc_head;
482 };
483 
484 struct mlx5_sq_bfreg {
485 	void __iomem	       *map;
486 	struct mlx5_uars_page  *up;
487 	bool			wc;
488 	u32			index;
489 	unsigned int		offset;
490 };
491 
492 struct mlx5_core_health {
493 	struct health_buffer __iomem   *health;
494 	__be32 __iomem		       *health_counter;
495 	struct timer_list		timer;
496 	u32				prev;
497 	int				miss_counter;
498 	bool				sick;
499 	/* wq spinlock to synchronize draining */
500 	spinlock_t			wq_lock;
501 	struct workqueue_struct	       *wq;
502 	unsigned long			flags;
503 	struct work_struct		work;
504 	struct delayed_work		recover_work;
505 };
506 
507 struct mlx5_cq_table {
508 	/* protect radix tree
509 	 */
510 	spinlock_t		lock;
511 	struct radix_tree_root	tree;
512 };
513 
514 struct mlx5_qp_table {
515 	/* protect radix tree
516 	 */
517 	spinlock_t		lock;
518 	struct radix_tree_root	tree;
519 };
520 
521 struct mlx5_srq_table {
522 	/* protect radix tree
523 	 */
524 	spinlock_t		lock;
525 	struct radix_tree_root	tree;
526 };
527 
528 struct mlx5_mkey_table {
529 	/* protect radix tree
530 	 */
531 	rwlock_t		lock;
532 	struct radix_tree_root	tree;
533 };
534 
535 struct mlx5_vf_context {
536 	int	enabled;
537 	u64	port_guid;
538 	u64	node_guid;
539 	enum port_state_policy	policy;
540 };
541 
542 struct mlx5_core_sriov {
543 	struct mlx5_vf_context	*vfs_ctx;
544 	int			num_vfs;
545 	int			enabled_vfs;
546 };
547 
548 struct mlx5_irq_info {
549 	char name[MLX5_MAX_IRQ_NAME];
550 };
551 
552 struct mlx5_fc_stats {
553 	struct rb_root counters;
554 	struct list_head addlist;
555 	/* protect addlist add/splice operations */
556 	spinlock_t addlist_lock;
557 
558 	struct workqueue_struct *wq;
559 	struct delayed_work work;
560 	unsigned long next_query;
561 	unsigned long sampling_interval; /* jiffies */
562 };
563 
564 struct mlx5_mpfs;
565 struct mlx5_eswitch;
566 struct mlx5_lag;
567 struct mlx5_pagefault;
568 
569 struct mlx5_rl_entry {
570 	u32                     rate;
571 	u16                     index;
572 	u16                     refcount;
573 };
574 
575 struct mlx5_rl_table {
576 	/* protect rate limit table */
577 	struct mutex            rl_lock;
578 	u16                     max_size;
579 	u32                     max_rate;
580 	u32                     min_rate;
581 	struct mlx5_rl_entry   *rl_entry;
582 };
583 
584 enum port_module_event_status_type {
585 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
586 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
587 	MLX5_MODULE_STATUS_ERROR     = 0x3,
588 	MLX5_MODULE_STATUS_NUM       = 0x3,
589 };
590 
591 enum  port_module_event_error_type {
592 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
593 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
594 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
595 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
596 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
597 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
598 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
599 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
600 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
601 	MLX5_MODULE_EVENT_ERROR_NUM,
602 };
603 
604 struct mlx5_port_module_event_stats {
605 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
606 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
607 };
608 
609 struct mlx5_priv {
610 	char			name[MLX5_MAX_NAME_LEN];
611 	struct mlx5_eq_table	eq_table;
612 	struct mlx5_irq_info	*irq_info;
613 
614 	/* pages stuff */
615 	struct workqueue_struct *pg_wq;
616 	struct rb_root		page_root;
617 	int			fw_pages;
618 	atomic_t		reg_pages;
619 	struct list_head	free_list;
620 	int			vfs_pages;
621 
622 	struct mlx5_core_health health;
623 
624 	struct mlx5_srq_table	srq_table;
625 
626 	/* start: qp staff */
627 	struct mlx5_qp_table	qp_table;
628 	struct dentry	       *qp_debugfs;
629 	struct dentry	       *eq_debugfs;
630 	struct dentry	       *cq_debugfs;
631 	struct dentry	       *cmdif_debugfs;
632 	/* end: qp staff */
633 
634 	/* start: cq staff */
635 	struct mlx5_cq_table	cq_table;
636 	/* end: cq staff */
637 
638 	/* start: mkey staff */
639 	struct mlx5_mkey_table	mkey_table;
640 	/* end: mkey staff */
641 
642 	/* start: alloc staff */
643 	/* protect buffer alocation according to numa node */
644 	struct mutex            alloc_mutex;
645 	int                     numa_node;
646 
647 	struct mutex            pgdir_mutex;
648 	struct list_head        pgdir_list;
649 	/* end: alloc staff */
650 	struct dentry	       *dbg_root;
651 
652 	/* protect mkey key part */
653 	spinlock_t		mkey_lock;
654 	u8			mkey_key;
655 
656 	struct list_head        dev_list;
657 	struct list_head        ctx_list;
658 	spinlock_t              ctx_lock;
659 
660 	struct list_head	waiting_events_list;
661 	bool			is_accum_events;
662 
663 	struct mlx5_flow_steering *steering;
664 	struct mlx5_mpfs        *mpfs;
665 	struct mlx5_eswitch     *eswitch;
666 	struct mlx5_core_sriov	sriov;
667 	struct mlx5_lag		*lag;
668 	unsigned long		pci_dev_data;
669 	struct mlx5_fc_stats		fc_stats;
670 	struct mlx5_rl_table            rl_table;
671 
672 	struct mlx5_port_module_event_stats  pme_stats;
673 
674 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
675 	void		      (*pfault)(struct mlx5_core_dev *dev,
676 					void *context,
677 					struct mlx5_pagefault *pfault);
678 	void		       *pfault_ctx;
679 	struct srcu_struct      pfault_srcu;
680 #endif
681 	struct mlx5_bfreg_data		bfregs;
682 	struct mlx5_uars_page	       *uar;
683 };
684 
685 enum mlx5_device_state {
686 	MLX5_DEVICE_STATE_UP,
687 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
688 };
689 
690 enum mlx5_interface_state {
691 	MLX5_INTERFACE_STATE_UP = BIT(0),
692 };
693 
694 enum mlx5_pci_status {
695 	MLX5_PCI_STATUS_DISABLED,
696 	MLX5_PCI_STATUS_ENABLED,
697 };
698 
699 enum mlx5_pagefault_type_flags {
700 	MLX5_PFAULT_REQUESTOR = 1 << 0,
701 	MLX5_PFAULT_WRITE     = 1 << 1,
702 	MLX5_PFAULT_RDMA      = 1 << 2,
703 };
704 
705 /* Contains the details of a pagefault. */
706 struct mlx5_pagefault {
707 	u32			bytes_committed;
708 	u32			token;
709 	u8			event_subtype;
710 	u8			type;
711 	union {
712 		/* Initiator or send message responder pagefault details. */
713 		struct {
714 			/* Received packet size, only valid for responders. */
715 			u32	packet_size;
716 			/*
717 			 * Number of resource holding WQE, depends on type.
718 			 */
719 			u32	wq_num;
720 			/*
721 			 * WQE index. Refers to either the send queue or
722 			 * receive queue, according to event_subtype.
723 			 */
724 			u16	wqe_index;
725 		} wqe;
726 		/* RDMA responder pagefault details */
727 		struct {
728 			u32	r_key;
729 			/*
730 			 * Received packet size, minimal size page fault
731 			 * resolution required for forward progress.
732 			 */
733 			u32	packet_size;
734 			u32	rdma_op_len;
735 			u64	rdma_va;
736 		} rdma;
737 	};
738 
739 	struct mlx5_eq	       *eq;
740 	struct work_struct	work;
741 };
742 
743 struct mlx5_td {
744 	struct list_head tirs_list;
745 	u32              tdn;
746 };
747 
748 struct mlx5e_resources {
749 	u32                        pdn;
750 	struct mlx5_td             td;
751 	struct mlx5_core_mkey      mkey;
752 	struct mlx5_sq_bfreg       bfreg;
753 };
754 
755 #define MLX5_MAX_RESERVED_GIDS 8
756 
757 struct mlx5_rsvd_gids {
758 	unsigned int start;
759 	unsigned int count;
760 	struct ida ida;
761 };
762 
763 struct mlx5_core_dev {
764 	struct pci_dev	       *pdev;
765 	/* sync pci state */
766 	struct mutex		pci_status_mutex;
767 	enum mlx5_pci_status	pci_status;
768 	u8			rev_id;
769 	char			board_id[MLX5_BOARD_ID_LEN];
770 	struct mlx5_cmd		cmd;
771 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
772 	struct {
773 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
774 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
775 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
776 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
777 	} caps;
778 	phys_addr_t		iseg_base;
779 	struct mlx5_init_seg __iomem *iseg;
780 	enum mlx5_device_state	state;
781 	/* sync interface state */
782 	struct mutex		intf_state_mutex;
783 	unsigned long		intf_state;
784 	void			(*event) (struct mlx5_core_dev *dev,
785 					  enum mlx5_dev_event event,
786 					  unsigned long param);
787 	struct mlx5_priv	priv;
788 	struct mlx5_profile	*profile;
789 	atomic_t		num_qps;
790 	u32			issi;
791 	struct mlx5e_resources  mlx5e_res;
792 	struct {
793 		struct mlx5_rsvd_gids	reserved_gids;
794 		atomic_t                roce_en;
795 	} roce;
796 #ifdef CONFIG_MLX5_FPGA
797 	struct mlx5_fpga_device *fpga;
798 #endif
799 #ifdef CONFIG_RFS_ACCEL
800 	struct cpu_rmap         *rmap;
801 #endif
802 };
803 
804 struct mlx5_db {
805 	__be32			*db;
806 	union {
807 		struct mlx5_db_pgdir		*pgdir;
808 		struct mlx5_ib_user_db_page	*user_page;
809 	}			u;
810 	dma_addr_t		dma;
811 	int			index;
812 };
813 
814 enum {
815 	MLX5_COMP_EQ_SIZE = 1024,
816 };
817 
818 enum {
819 	MLX5_PTYS_IB = 1 << 0,
820 	MLX5_PTYS_EN = 1 << 2,
821 };
822 
823 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
824 
825 enum {
826 	MLX5_CMD_ENT_STATE_PENDING_COMP,
827 };
828 
829 struct mlx5_cmd_work_ent {
830 	unsigned long		state;
831 	struct mlx5_cmd_msg    *in;
832 	struct mlx5_cmd_msg    *out;
833 	void		       *uout;
834 	int			uout_size;
835 	mlx5_cmd_cbk_t		callback;
836 	struct delayed_work	cb_timeout_work;
837 	void		       *context;
838 	int			idx;
839 	struct completion	done;
840 	struct mlx5_cmd        *cmd;
841 	struct work_struct	work;
842 	struct mlx5_cmd_layout *lay;
843 	int			ret;
844 	int			page_queue;
845 	u8			status;
846 	u8			token;
847 	u64			ts1;
848 	u64			ts2;
849 	u16			op;
850 	bool			polling;
851 };
852 
853 struct mlx5_pas {
854 	u64	pa;
855 	u8	log_sz;
856 };
857 
858 enum phy_port_state {
859 	MLX5_AAA_111
860 };
861 
862 struct mlx5_hca_vport_context {
863 	u32			field_select;
864 	bool			sm_virt_aware;
865 	bool			has_smi;
866 	bool			has_raw;
867 	enum port_state_policy	policy;
868 	enum phy_port_state	phys_state;
869 	enum ib_port_state	vport_state;
870 	u8			port_physical_state;
871 	u64			sys_image_guid;
872 	u64			port_guid;
873 	u64			node_guid;
874 	u32			cap_mask1;
875 	u32			cap_mask1_perm;
876 	u32			cap_mask2;
877 	u32			cap_mask2_perm;
878 	u16			lid;
879 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
880 	u8			lmc;
881 	u8			subnet_timeout;
882 	u16			sm_lid;
883 	u8			sm_sl;
884 	u16			qkey_violation_counter;
885 	u16			pkey_violation_counter;
886 	bool			grh_required;
887 };
888 
889 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
890 {
891 		return buf->direct.buf + offset;
892 }
893 
894 #define STRUCT_FIELD(header, field) \
895 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
896 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
897 
898 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
899 {
900 	return pci_get_drvdata(pdev);
901 }
902 
903 extern struct dentry *mlx5_debugfs_root;
904 
905 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
906 {
907 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
908 }
909 
910 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
911 {
912 	return ioread32be(&dev->iseg->fw_rev) >> 16;
913 }
914 
915 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
916 {
917 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
918 }
919 
920 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
921 {
922 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
923 }
924 
925 static inline u32 mlx5_base_mkey(const u32 key)
926 {
927 	return key & 0xffffff00u;
928 }
929 
930 int mlx5_cmd_init(struct mlx5_core_dev *dev);
931 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
932 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
933 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
934 
935 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
936 		  int out_size);
937 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
938 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
939 		     void *context);
940 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
941 			  void *out, int out_size);
942 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
943 
944 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
945 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
946 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
947 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
948 int mlx5_health_init(struct mlx5_core_dev *dev);
949 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
950 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
951 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
952 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
953 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
954 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
955 			struct mlx5_buf *buf, int node);
956 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
957 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
958 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
959 			     struct mlx5_frag_buf *buf, int node);
960 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
961 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
962 						      gfp_t flags, int npages);
963 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
964 				 struct mlx5_cmd_mailbox *head);
965 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
966 			 struct mlx5_srq_attr *in);
967 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
968 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
969 			struct mlx5_srq_attr *out);
970 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
971 		      u16 lwm, int is_srq);
972 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
973 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
974 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
975 			     struct mlx5_core_mkey *mkey,
976 			     u32 *in, int inlen,
977 			     u32 *out, int outlen,
978 			     mlx5_cmd_cbk_t callback, void *context);
979 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
980 			  struct mlx5_core_mkey *mkey,
981 			  u32 *in, int inlen);
982 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
983 			   struct mlx5_core_mkey *mkey);
984 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
985 			 u32 *out, int outlen);
986 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
987 			     u32 *mkey);
988 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
989 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
990 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
991 		      u16 opmod, u8 port);
992 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
993 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
994 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
995 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
996 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
997 				 s32 npages);
998 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
999 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1000 void mlx5_register_debugfs(void);
1001 void mlx5_unregister_debugfs(void);
1002 int mlx5_eq_init(struct mlx5_core_dev *dev);
1003 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1004 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1005 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1006 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1007 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1008 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1009 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1010 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1011 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1012 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1013 		       int nent, u64 mask, const char *name,
1014 		       enum mlx5_eq_type type);
1015 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1016 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1017 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1018 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1019 		    unsigned int *irqn);
1020 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1021 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1022 
1023 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1024 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1025 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1026 			 int size_in, void *data_out, int size_out,
1027 			 u16 reg_num, int arg, int write);
1028 
1029 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1030 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1031 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1032 		       u32 *out, int outlen);
1033 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1034 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1035 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1036 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1037 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1038 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1039 		       int node);
1040 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1041 
1042 const char *mlx5_command_str(int command);
1043 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1044 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1045 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1046 			 int npsvs, u32 *sig_index);
1047 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1048 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1049 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1050 			struct mlx5_odp_caps *odp_caps);
1051 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1052 			     u8 port_num, void *out, size_t sz);
1053 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1054 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1055 				u32 wq_num, u8 type, int error);
1056 #endif
1057 
1058 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1059 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1060 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1061 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1062 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1063 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1064 		     bool map_wc, bool fast_path);
1065 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1066 
1067 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1068 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1069 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1070 			   const u8 *mac, bool vlan, u16 vlan_id);
1071 
1072 static inline int fw_initializing(struct mlx5_core_dev *dev)
1073 {
1074 	return ioread32be(&dev->iseg->initializing) >> 31;
1075 }
1076 
1077 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1078 {
1079 	return mkey >> 8;
1080 }
1081 
1082 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1083 {
1084 	return mkey_idx << 8;
1085 }
1086 
1087 static inline u8 mlx5_mkey_variant(u32 mkey)
1088 {
1089 	return mkey & 0xff;
1090 }
1091 
1092 enum {
1093 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1094 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1095 };
1096 
1097 enum {
1098 	MR_CACHE_LAST_STD_ENTRY = 20,
1099 	MLX5_IMR_MTT_CACHE_ENTRY,
1100 	MLX5_IMR_KSM_CACHE_ENTRY,
1101 	MAX_MR_CACHE_ENTRIES
1102 };
1103 
1104 enum {
1105 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1106 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1107 };
1108 
1109 struct mlx5_interface {
1110 	void *			(*add)(struct mlx5_core_dev *dev);
1111 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1112 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1113 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1114 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1115 					 enum mlx5_dev_event event, unsigned long param);
1116 	void			(*pfault)(struct mlx5_core_dev *dev,
1117 					  void *context,
1118 					  struct mlx5_pagefault *pfault);
1119 	void *                  (*get_dev)(void *context);
1120 	int			protocol;
1121 	struct list_head	list;
1122 };
1123 
1124 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1125 int mlx5_register_interface(struct mlx5_interface *intf);
1126 void mlx5_unregister_interface(struct mlx5_interface *intf);
1127 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1128 
1129 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1130 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1131 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1132 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1133 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1134 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1135 
1136 #ifndef CONFIG_MLX5_CORE_IPOIB
1137 static inline
1138 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1139 					  struct ib_device *ibdev,
1140 					  const char *name,
1141 					  void (*setup)(struct net_device *))
1142 {
1143 	return ERR_PTR(-EOPNOTSUPP);
1144 }
1145 
1146 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1147 #else
1148 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1149 					  struct ib_device *ibdev,
1150 					  const char *name,
1151 					  void (*setup)(struct net_device *));
1152 void mlx5_rdma_netdev_free(struct net_device *netdev);
1153 #endif /* CONFIG_MLX5_CORE_IPOIB */
1154 
1155 struct mlx5_profile {
1156 	u64	mask;
1157 	u8	log_max_qp;
1158 	struct {
1159 		int	size;
1160 		int	limit;
1161 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1162 };
1163 
1164 enum {
1165 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1166 };
1167 
1168 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1169 {
1170 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1171 }
1172 
1173 static inline int mlx5_get_gid_table_len(u16 param)
1174 {
1175 	if (param > 4) {
1176 		pr_warn("gid table length is zero\n");
1177 		return 0;
1178 	}
1179 
1180 	return 8 * (1 << param);
1181 }
1182 
1183 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1184 {
1185 	return !!(dev->priv.rl_table.max_size);
1186 }
1187 
1188 enum {
1189 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1190 };
1191 
1192 static inline const struct cpumask *
1193 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
1194 {
1195 	return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
1196 }
1197 
1198 #endif /* MLX5_DRIVER_H */
1199