xref: /linux-6.15/include/linux/mlx5/driver.h (revision cd3bc044) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63 
64 enum {
65 	MLX5_BOARD_ID_LEN = 64,
66 };
67 
68 enum {
69 	MLX5_CMD_WQ_MAX_NAME	= 32,
70 };
71 
72 enum {
73 	CMD_OWNER_SW		= 0x0,
74 	CMD_OWNER_HW		= 0x1,
75 	CMD_STATUS_SUCCESS	= 0,
76 };
77 
78 enum mlx5_sqp_t {
79 	MLX5_SQP_SMI		= 0,
80 	MLX5_SQP_GSI		= 1,
81 	MLX5_SQP_IEEE_1588	= 2,
82 	MLX5_SQP_SNIFFER	= 3,
83 	MLX5_SQP_SYNC_UMR	= 4,
84 };
85 
86 enum {
87 	MLX5_MAX_PORTS	= 2,
88 };
89 
90 enum {
91 	MLX5_ATOMIC_MODE_OFFSET = 16,
92 	MLX5_ATOMIC_MODE_IB_COMP = 1,
93 	MLX5_ATOMIC_MODE_CX = 2,
94 	MLX5_ATOMIC_MODE_8B = 3,
95 	MLX5_ATOMIC_MODE_16B = 4,
96 	MLX5_ATOMIC_MODE_32B = 5,
97 	MLX5_ATOMIC_MODE_64B = 6,
98 	MLX5_ATOMIC_MODE_128B = 7,
99 	MLX5_ATOMIC_MODE_256B = 8,
100 };
101 
102 enum {
103 	MLX5_REG_QPTS            = 0x4002,
104 	MLX5_REG_QETCR		 = 0x4005,
105 	MLX5_REG_QTCT		 = 0x400a,
106 	MLX5_REG_QPDPM           = 0x4013,
107 	MLX5_REG_QCAM            = 0x4019,
108 	MLX5_REG_DCBX_PARAM      = 0x4020,
109 	MLX5_REG_DCBX_APP        = 0x4021,
110 	MLX5_REG_FPGA_CAP	 = 0x4022,
111 	MLX5_REG_FPGA_CTRL	 = 0x4023,
112 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 	MLX5_REG_CORE_DUMP	 = 0x402e,
114 	MLX5_REG_PCAP		 = 0x5001,
115 	MLX5_REG_PMTU		 = 0x5003,
116 	MLX5_REG_PTYS		 = 0x5004,
117 	MLX5_REG_PAOS		 = 0x5006,
118 	MLX5_REG_PFCC            = 0x5007,
119 	MLX5_REG_PPCNT		 = 0x5008,
120 	MLX5_REG_PPTB            = 0x500b,
121 	MLX5_REG_PBMC            = 0x500c,
122 	MLX5_REG_PMAOS		 = 0x5012,
123 	MLX5_REG_PUDE		 = 0x5009,
124 	MLX5_REG_PMPE		 = 0x5010,
125 	MLX5_REG_PELC		 = 0x500e,
126 	MLX5_REG_PVLC		 = 0x500f,
127 	MLX5_REG_PCMR		 = 0x5041,
128 	MLX5_REG_PDDR		 = 0x5031,
129 	MLX5_REG_PMLP		 = 0x5002,
130 	MLX5_REG_PPLM		 = 0x5023,
131 	MLX5_REG_PCAM		 = 0x507f,
132 	MLX5_REG_NODE_DESC	 = 0x6001,
133 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 	MLX5_REG_MCIA		 = 0x9014,
135 	MLX5_REG_MFRL		 = 0x9028,
136 	MLX5_REG_MLCR		 = 0x902b,
137 	MLX5_REG_MRTC		 = 0x902d,
138 	MLX5_REG_MTRC_CAP	 = 0x9040,
139 	MLX5_REG_MTRC_CONF	 = 0x9041,
140 	MLX5_REG_MTRC_STDB	 = 0x9042,
141 	MLX5_REG_MTRC_CTRL	 = 0x9043,
142 	MLX5_REG_MPEIN		 = 0x9050,
143 	MLX5_REG_MPCNT		 = 0x9051,
144 	MLX5_REG_MTPPS		 = 0x9053,
145 	MLX5_REG_MTPPSE		 = 0x9054,
146 	MLX5_REG_MTUTC		 = 0x9055,
147 	MLX5_REG_MPEGC		 = 0x9056,
148 	MLX5_REG_MCQS		 = 0x9060,
149 	MLX5_REG_MCQI		 = 0x9061,
150 	MLX5_REG_MCC		 = 0x9062,
151 	MLX5_REG_MCDA		 = 0x9063,
152 	MLX5_REG_MCAM		 = 0x907f,
153 	MLX5_REG_MIRC		 = 0x9162,
154 	MLX5_REG_SBCAM		 = 0xB01F,
155 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
156 	MLX5_REG_DTOR            = 0xC00E,
157 };
158 
159 enum mlx5_qpts_trust_state {
160 	MLX5_QPTS_TRUST_PCP  = 1,
161 	MLX5_QPTS_TRUST_DSCP = 2,
162 };
163 
164 enum mlx5_dcbx_oper_mode {
165 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
166 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
167 };
168 
169 enum {
170 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
171 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
172 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174 };
175 
176 enum mlx5_page_fault_resume_flags {
177 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
179 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
180 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
181 };
182 
183 enum dbg_rsc_type {
184 	MLX5_DBG_RSC_QP,
185 	MLX5_DBG_RSC_EQ,
186 	MLX5_DBG_RSC_CQ,
187 };
188 
189 enum port_state_policy {
190 	MLX5_POLICY_DOWN	= 0,
191 	MLX5_POLICY_UP		= 1,
192 	MLX5_POLICY_FOLLOW	= 2,
193 	MLX5_POLICY_INVALID	= 0xffffffff
194 };
195 
196 enum mlx5_coredev_type {
197 	MLX5_COREDEV_PF,
198 	MLX5_COREDEV_VF,
199 	MLX5_COREDEV_SF,
200 };
201 
202 struct mlx5_field_desc {
203 	int			i;
204 };
205 
206 struct mlx5_rsc_debug {
207 	struct mlx5_core_dev   *dev;
208 	void		       *object;
209 	enum dbg_rsc_type	type;
210 	struct dentry	       *root;
211 	struct mlx5_field_desc	fields[];
212 };
213 
214 enum mlx5_dev_event {
215 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217 };
218 
219 enum mlx5_port_status {
220 	MLX5_PORT_UP        = 1,
221 	MLX5_PORT_DOWN      = 2,
222 };
223 
224 enum mlx5_cmdif_state {
225 	MLX5_CMDIF_STATE_UNINITIALIZED,
226 	MLX5_CMDIF_STATE_UP,
227 	MLX5_CMDIF_STATE_DOWN,
228 };
229 
230 struct mlx5_cmd_first {
231 	__be32		data[4];
232 };
233 
234 struct mlx5_cmd_msg {
235 	struct list_head		list;
236 	struct cmd_msg_cache	       *parent;
237 	u32				len;
238 	struct mlx5_cmd_first		first;
239 	struct mlx5_cmd_mailbox	       *next;
240 };
241 
242 struct mlx5_cmd_debug {
243 	struct dentry	       *dbg_root;
244 	void		       *in_msg;
245 	void		       *out_msg;
246 	u8			status;
247 	u16			inlen;
248 	u16			outlen;
249 };
250 
251 struct cmd_msg_cache {
252 	/* protect block chain allocations
253 	 */
254 	spinlock_t		lock;
255 	struct list_head	head;
256 	unsigned int		max_inbox_size;
257 	unsigned int		num_ent;
258 };
259 
260 enum {
261 	MLX5_NUM_COMMAND_CACHES = 5,
262 };
263 
264 struct mlx5_cmd_stats {
265 	u64		sum;
266 	u64		n;
267 	struct dentry  *root;
268 	/* protect command average calculations */
269 	spinlock_t	lock;
270 };
271 
272 struct mlx5_cmd {
273 	struct mlx5_nb    nb;
274 
275 	enum mlx5_cmdif_state	state;
276 	void	       *cmd_alloc_buf;
277 	dma_addr_t	alloc_dma;
278 	int		alloc_size;
279 	void	       *cmd_buf;
280 	dma_addr_t	dma;
281 	u16		cmdif_rev;
282 	u8		log_sz;
283 	u8		log_stride;
284 	int		max_reg_cmds;
285 	int		events;
286 	u32 __iomem    *vector;
287 
288 	/* protect command queue allocations
289 	 */
290 	spinlock_t	alloc_lock;
291 
292 	/* protect token allocations
293 	 */
294 	spinlock_t	token_lock;
295 	u8		token;
296 	unsigned long	bitmask;
297 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
298 	struct workqueue_struct *wq;
299 	struct semaphore sem;
300 	struct semaphore pages_sem;
301 	int	mode;
302 	u16     allowed_opcode;
303 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
304 	struct dma_pool *pool;
305 	struct mlx5_cmd_debug dbg;
306 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
307 	int checksum_disabled;
308 	struct mlx5_cmd_stats *stats;
309 };
310 
311 struct mlx5_cmd_mailbox {
312 	void	       *buf;
313 	dma_addr_t	dma;
314 	struct mlx5_cmd_mailbox *next;
315 };
316 
317 struct mlx5_buf_list {
318 	void		       *buf;
319 	dma_addr_t		map;
320 };
321 
322 struct mlx5_frag_buf {
323 	struct mlx5_buf_list	*frags;
324 	int			npages;
325 	int			size;
326 	u8			page_shift;
327 };
328 
329 struct mlx5_frag_buf_ctrl {
330 	struct mlx5_buf_list   *frags;
331 	u32			sz_m1;
332 	u16			frag_sz_m1;
333 	u16			strides_offset;
334 	u8			log_sz;
335 	u8			log_stride;
336 	u8			log_frag_strides;
337 };
338 
339 struct mlx5_core_psv {
340 	u32	psv_idx;
341 	struct psv_layout {
342 		u32	pd;
343 		u16	syndrome;
344 		u16	reserved;
345 		u16	bg;
346 		u16	app_tag;
347 		u32	ref_tag;
348 	} psv;
349 };
350 
351 struct mlx5_core_sig_ctx {
352 	struct mlx5_core_psv	psv_memory;
353 	struct mlx5_core_psv	psv_wire;
354 	struct ib_sig_err       err_item;
355 	bool			sig_status_checked;
356 	bool			sig_err_exists;
357 	u32			sigerr_count;
358 };
359 
360 #define MLX5_24BIT_MASK		((1 << 24) - 1)
361 
362 enum mlx5_res_type {
363 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
364 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
365 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
366 	MLX5_RES_SRQ	= 3,
367 	MLX5_RES_XSRQ	= 4,
368 	MLX5_RES_XRQ	= 5,
369 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
370 };
371 
372 struct mlx5_core_rsc_common {
373 	enum mlx5_res_type	res;
374 	refcount_t		refcount;
375 	struct completion	free;
376 };
377 
378 struct mlx5_uars_page {
379 	void __iomem	       *map;
380 	bool			wc;
381 	u32			index;
382 	struct list_head	list;
383 	unsigned int		bfregs;
384 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
385 	unsigned long	       *fp_bitmap;
386 	unsigned int		reg_avail;
387 	unsigned int		fp_avail;
388 	struct kref		ref_count;
389 	struct mlx5_core_dev   *mdev;
390 };
391 
392 struct mlx5_bfreg_head {
393 	/* protect blue flame registers allocations */
394 	struct mutex		lock;
395 	struct list_head	list;
396 };
397 
398 struct mlx5_bfreg_data {
399 	struct mlx5_bfreg_head	reg_head;
400 	struct mlx5_bfreg_head	wc_head;
401 };
402 
403 struct mlx5_sq_bfreg {
404 	void __iomem	       *map;
405 	struct mlx5_uars_page  *up;
406 	bool			wc;
407 	u32			index;
408 	unsigned int		offset;
409 };
410 
411 struct mlx5_core_health {
412 	struct health_buffer __iomem   *health;
413 	__be32 __iomem		       *health_counter;
414 	struct timer_list		timer;
415 	u32				prev;
416 	int				miss_counter;
417 	u8				synd;
418 	u32				fatal_error;
419 	u32				crdump_size;
420 	/* wq spinlock to synchronize draining */
421 	spinlock_t			wq_lock;
422 	struct workqueue_struct	       *wq;
423 	unsigned long			flags;
424 	struct work_struct		fatal_report_work;
425 	struct work_struct		report_work;
426 	struct devlink_health_reporter *fw_reporter;
427 	struct devlink_health_reporter *fw_fatal_reporter;
428 	struct delayed_work		update_fw_log_ts_work;
429 };
430 
431 struct mlx5_qp_table {
432 	struct notifier_block   nb;
433 
434 	/* protect radix tree
435 	 */
436 	spinlock_t		lock;
437 	struct radix_tree_root	tree;
438 };
439 
440 struct mlx5_vf_context {
441 	int	enabled;
442 	u64	port_guid;
443 	u64	node_guid;
444 	/* Valid bits are used to validate administrative guid only.
445 	 * Enabled after ndo_set_vf_guid
446 	 */
447 	u8	port_guid_valid:1;
448 	u8	node_guid_valid:1;
449 	enum port_state_policy	policy;
450 };
451 
452 struct mlx5_core_sriov {
453 	struct mlx5_vf_context	*vfs_ctx;
454 	int			num_vfs;
455 	u16			max_vfs;
456 };
457 
458 struct mlx5_fc_pool {
459 	struct mlx5_core_dev *dev;
460 	struct mutex pool_lock; /* protects pool lists */
461 	struct list_head fully_used;
462 	struct list_head partially_used;
463 	struct list_head unused;
464 	int available_fcs;
465 	int used_fcs;
466 	int threshold;
467 };
468 
469 struct mlx5_fc_stats {
470 	spinlock_t counters_idr_lock; /* protects counters_idr */
471 	struct idr counters_idr;
472 	struct list_head counters;
473 	struct llist_head addlist;
474 	struct llist_head dellist;
475 
476 	struct workqueue_struct *wq;
477 	struct delayed_work work;
478 	unsigned long next_query;
479 	unsigned long sampling_interval; /* jiffies */
480 	u32 *bulk_query_out;
481 	int bulk_query_len;
482 	size_t num_counters;
483 	bool bulk_query_alloc_failed;
484 	unsigned long next_bulk_query_alloc;
485 	struct mlx5_fc_pool fc_pool;
486 };
487 
488 struct mlx5_events;
489 struct mlx5_mpfs;
490 struct mlx5_eswitch;
491 struct mlx5_lag;
492 struct mlx5_devcom;
493 struct mlx5_fw_reset;
494 struct mlx5_eq_table;
495 struct mlx5_irq_table;
496 struct mlx5_vhca_state_notifier;
497 struct mlx5_sf_dev_table;
498 struct mlx5_sf_hw_table;
499 struct mlx5_sf_table;
500 
501 struct mlx5_rate_limit {
502 	u32			rate;
503 	u32			max_burst_sz;
504 	u16			typical_pkt_sz;
505 };
506 
507 struct mlx5_rl_entry {
508 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
509 	u64 refcount;
510 	u16 index;
511 	u16 uid;
512 	u8 dedicated : 1;
513 };
514 
515 struct mlx5_rl_table {
516 	/* protect rate limit table */
517 	struct mutex            rl_lock;
518 	u16                     max_size;
519 	u32                     max_rate;
520 	u32                     min_rate;
521 	struct mlx5_rl_entry   *rl_entry;
522 	u64 refcount;
523 };
524 
525 struct mlx5_core_roce {
526 	struct mlx5_flow_table *ft;
527 	struct mlx5_flow_group *fg;
528 	struct mlx5_flow_handle *allow_rule;
529 };
530 
531 enum {
532 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
533 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
534 	/* Set during device detach to block any further devices
535 	 * creation/deletion on drivers rescan. Unset during device attach.
536 	 */
537 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
538 };
539 
540 struct mlx5_adev {
541 	struct auxiliary_device adev;
542 	struct mlx5_core_dev *mdev;
543 	int idx;
544 };
545 
546 struct mlx5_ft_pool;
547 struct mlx5_priv {
548 	/* IRQ table valid only for real pci devices PF or VF */
549 	struct mlx5_irq_table   *irq_table;
550 	struct mlx5_eq_table	*eq_table;
551 
552 	/* pages stuff */
553 	struct mlx5_nb          pg_nb;
554 	struct workqueue_struct *pg_wq;
555 	struct xarray           page_root_xa;
556 	int			fw_pages;
557 	atomic_t		reg_pages;
558 	struct list_head	free_list;
559 	int			vfs_pages;
560 	int			host_pf_pages;
561 
562 	struct mlx5_core_health health;
563 	struct list_head	traps;
564 
565 	/* start: qp staff */
566 	struct dentry	       *qp_debugfs;
567 	struct dentry	       *eq_debugfs;
568 	struct dentry	       *cq_debugfs;
569 	struct dentry	       *cmdif_debugfs;
570 	/* end: qp staff */
571 
572 	/* start: alloc staff */
573 	/* protect buffer allocation according to numa node */
574 	struct mutex            alloc_mutex;
575 	int                     numa_node;
576 
577 	struct mutex            pgdir_mutex;
578 	struct list_head        pgdir_list;
579 	/* end: alloc staff */
580 	struct dentry	       *dbg_root;
581 
582 	struct list_head        ctx_list;
583 	spinlock_t              ctx_lock;
584 	struct mlx5_adev       **adev;
585 	int			adev_idx;
586 	struct mlx5_events      *events;
587 
588 	struct mlx5_flow_steering *steering;
589 	struct mlx5_mpfs        *mpfs;
590 	struct mlx5_eswitch     *eswitch;
591 	struct mlx5_core_sriov	sriov;
592 	struct mlx5_lag		*lag;
593 	u32			flags;
594 	struct mlx5_devcom	*devcom;
595 	struct mlx5_fw_reset	*fw_reset;
596 	struct mlx5_core_roce	roce;
597 	struct mlx5_fc_stats		fc_stats;
598 	struct mlx5_rl_table            rl_table;
599 	struct mlx5_ft_pool		*ft_pool;
600 
601 	struct mlx5_bfreg_data		bfregs;
602 	struct mlx5_uars_page	       *uar;
603 #ifdef CONFIG_MLX5_SF
604 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
605 	struct mlx5_sf_dev_table *sf_dev_table;
606 	struct mlx5_core_dev *parent_mdev;
607 #endif
608 #ifdef CONFIG_MLX5_SF_MANAGER
609 	struct mlx5_sf_hw_table *sf_hw_table;
610 	struct mlx5_sf_table *sf_table;
611 #endif
612 };
613 
614 enum mlx5_device_state {
615 	MLX5_DEVICE_STATE_UP = 1,
616 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
617 };
618 
619 enum mlx5_interface_state {
620 	MLX5_INTERFACE_STATE_UP = BIT(0),
621 };
622 
623 enum mlx5_pci_status {
624 	MLX5_PCI_STATUS_DISABLED,
625 	MLX5_PCI_STATUS_ENABLED,
626 };
627 
628 enum mlx5_pagefault_type_flags {
629 	MLX5_PFAULT_REQUESTOR = 1 << 0,
630 	MLX5_PFAULT_WRITE     = 1 << 1,
631 	MLX5_PFAULT_RDMA      = 1 << 2,
632 };
633 
634 struct mlx5_td {
635 	/* protects tirs list changes while tirs refresh */
636 	struct mutex     list_lock;
637 	struct list_head tirs_list;
638 	u32              tdn;
639 };
640 
641 struct mlx5e_resources {
642 	struct mlx5e_hw_objs {
643 		u32                        pdn;
644 		struct mlx5_td             td;
645 		u32			   mkey;
646 		struct mlx5_sq_bfreg       bfreg;
647 	} hw_objs;
648 	struct devlink_port dl_port;
649 	struct net_device *uplink_netdev;
650 };
651 
652 enum mlx5_sw_icm_type {
653 	MLX5_SW_ICM_TYPE_STEERING,
654 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
655 };
656 
657 #define MLX5_MAX_RESERVED_GIDS 8
658 
659 struct mlx5_rsvd_gids {
660 	unsigned int start;
661 	unsigned int count;
662 	struct ida ida;
663 };
664 
665 #define MAX_PIN_NUM	8
666 struct mlx5_pps {
667 	u8                         pin_caps[MAX_PIN_NUM];
668 	struct work_struct         out_work;
669 	u64                        start[MAX_PIN_NUM];
670 	u8                         enabled;
671 };
672 
673 struct mlx5_timer {
674 	struct cyclecounter        cycles;
675 	struct timecounter         tc;
676 	u32                        nominal_c_mult;
677 	unsigned long              overflow_period;
678 	struct delayed_work        overflow_work;
679 };
680 
681 struct mlx5_clock {
682 	struct mlx5_nb             pps_nb;
683 	seqlock_t                  lock;
684 	struct hwtstamp_config     hwtstamp_config;
685 	struct ptp_clock          *ptp;
686 	struct ptp_clock_info      ptp_info;
687 	struct mlx5_pps            pps_info;
688 	struct mlx5_timer          timer;
689 };
690 
691 struct mlx5_dm;
692 struct mlx5_fw_tracer;
693 struct mlx5_vxlan;
694 struct mlx5_geneve;
695 struct mlx5_hv_vhca;
696 
697 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
698 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
699 
700 enum {
701 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
702 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
703 };
704 
705 enum {
706 	MR_CACHE_LAST_STD_ENTRY = 20,
707 	MLX5_IMR_MTT_CACHE_ENTRY,
708 	MLX5_IMR_KSM_CACHE_ENTRY,
709 	MAX_MR_CACHE_ENTRIES
710 };
711 
712 struct mlx5_profile {
713 	u64	mask;
714 	u8	log_max_qp;
715 	struct {
716 		int	size;
717 		int	limit;
718 	} mr_cache[MAX_MR_CACHE_ENTRIES];
719 };
720 
721 struct mlx5_hca_cap {
722 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
723 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
724 };
725 
726 struct mlx5_core_dev {
727 	struct device *device;
728 	enum mlx5_coredev_type coredev_type;
729 	struct pci_dev	       *pdev;
730 	/* sync pci state */
731 	struct mutex		pci_status_mutex;
732 	enum mlx5_pci_status	pci_status;
733 	u8			rev_id;
734 	char			board_id[MLX5_BOARD_ID_LEN];
735 	struct mlx5_cmd		cmd;
736 	struct {
737 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
738 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
739 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
740 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
741 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
742 		u8  embedded_cpu;
743 	} caps;
744 	struct mlx5_timeouts	*timeouts;
745 	u64			sys_image_guid;
746 	phys_addr_t		iseg_base;
747 	struct mlx5_init_seg __iomem *iseg;
748 	phys_addr_t             bar_addr;
749 	enum mlx5_device_state	state;
750 	/* sync interface state */
751 	struct mutex		intf_state_mutex;
752 	unsigned long		intf_state;
753 	struct mlx5_priv	priv;
754 	struct mlx5_profile	profile;
755 	u32			issi;
756 	struct mlx5e_resources  mlx5e_res;
757 	struct mlx5_dm          *dm;
758 	struct mlx5_vxlan       *vxlan;
759 	struct mlx5_geneve      *geneve;
760 	struct {
761 		struct mlx5_rsvd_gids	reserved_gids;
762 		u32			roce_en;
763 	} roce;
764 #ifdef CONFIG_MLX5_FPGA
765 	struct mlx5_fpga_device *fpga;
766 #endif
767 #ifdef CONFIG_MLX5_ACCEL
768 	const struct mlx5_accel_ipsec_ops *ipsec_ops;
769 #endif
770 	struct mlx5_clock        clock;
771 	struct mlx5_ib_clock_info  *clock_info;
772 	struct mlx5_fw_tracer   *tracer;
773 	struct mlx5_rsc_dump    *rsc_dump;
774 	u32                      vsc_addr;
775 	struct mlx5_hv_vhca	*hv_vhca;
776 };
777 
778 struct mlx5_db {
779 	__be32			*db;
780 	union {
781 		struct mlx5_db_pgdir		*pgdir;
782 		struct mlx5_ib_user_db_page	*user_page;
783 	}			u;
784 	dma_addr_t		dma;
785 	int			index;
786 };
787 
788 enum {
789 	MLX5_COMP_EQ_SIZE = 1024,
790 };
791 
792 enum {
793 	MLX5_PTYS_IB = 1 << 0,
794 	MLX5_PTYS_EN = 1 << 2,
795 };
796 
797 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
798 
799 enum {
800 	MLX5_CMD_ENT_STATE_PENDING_COMP,
801 };
802 
803 struct mlx5_cmd_work_ent {
804 	unsigned long		state;
805 	struct mlx5_cmd_msg    *in;
806 	struct mlx5_cmd_msg    *out;
807 	void		       *uout;
808 	int			uout_size;
809 	mlx5_cmd_cbk_t		callback;
810 	struct delayed_work	cb_timeout_work;
811 	void		       *context;
812 	int			idx;
813 	struct completion	handling;
814 	struct completion	done;
815 	struct mlx5_cmd        *cmd;
816 	struct work_struct	work;
817 	struct mlx5_cmd_layout *lay;
818 	int			ret;
819 	int			page_queue;
820 	u8			status;
821 	u8			token;
822 	u64			ts1;
823 	u64			ts2;
824 	u16			op;
825 	bool			polling;
826 	/* Track the max comp handlers */
827 	refcount_t              refcnt;
828 };
829 
830 struct mlx5_pas {
831 	u64	pa;
832 	u8	log_sz;
833 };
834 
835 enum phy_port_state {
836 	MLX5_AAA_111
837 };
838 
839 struct mlx5_hca_vport_context {
840 	u32			field_select;
841 	bool			sm_virt_aware;
842 	bool			has_smi;
843 	bool			has_raw;
844 	enum port_state_policy	policy;
845 	enum phy_port_state	phys_state;
846 	enum ib_port_state	vport_state;
847 	u8			port_physical_state;
848 	u64			sys_image_guid;
849 	u64			port_guid;
850 	u64			node_guid;
851 	u32			cap_mask1;
852 	u32			cap_mask1_perm;
853 	u16			cap_mask2;
854 	u16			cap_mask2_perm;
855 	u16			lid;
856 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
857 	u8			lmc;
858 	u8			subnet_timeout;
859 	u16			sm_lid;
860 	u8			sm_sl;
861 	u16			qkey_violation_counter;
862 	u16			pkey_violation_counter;
863 	bool			grh_required;
864 };
865 
866 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
867 {
868 		return buf->frags->buf + offset;
869 }
870 
871 #define STRUCT_FIELD(header, field) \
872 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
873 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
874 
875 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
876 {
877 	return pci_get_drvdata(pdev);
878 }
879 
880 extern struct dentry *mlx5_debugfs_root;
881 
882 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
883 {
884 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
885 }
886 
887 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
888 {
889 	return ioread32be(&dev->iseg->fw_rev) >> 16;
890 }
891 
892 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
893 {
894 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
895 }
896 
897 static inline u32 mlx5_base_mkey(const u32 key)
898 {
899 	return key & 0xffffff00u;
900 }
901 
902 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
903 {
904 	return ((u32)1 << log_sz) << log_stride;
905 }
906 
907 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
908 					u8 log_stride, u8 log_sz,
909 					u16 strides_offset,
910 					struct mlx5_frag_buf_ctrl *fbc)
911 {
912 	fbc->frags      = frags;
913 	fbc->log_stride = log_stride;
914 	fbc->log_sz     = log_sz;
915 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
916 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
917 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
918 	fbc->strides_offset = strides_offset;
919 }
920 
921 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
922 				 u8 log_stride, u8 log_sz,
923 				 struct mlx5_frag_buf_ctrl *fbc)
924 {
925 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
926 }
927 
928 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
929 					  u32 ix)
930 {
931 	unsigned int frag;
932 
933 	ix  += fbc->strides_offset;
934 	frag = ix >> fbc->log_frag_strides;
935 
936 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
937 }
938 
939 static inline u32
940 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
941 {
942 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
943 
944 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
945 }
946 
947 enum {
948 	CMD_ALLOWED_OPCODE_ALL,
949 };
950 
951 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
952 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
953 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
954 
955 struct mlx5_async_ctx {
956 	struct mlx5_core_dev *dev;
957 	atomic_t num_inflight;
958 	struct wait_queue_head wait;
959 };
960 
961 struct mlx5_async_work;
962 
963 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
964 
965 struct mlx5_async_work {
966 	struct mlx5_async_ctx *ctx;
967 	mlx5_async_cbk_t user_callback;
968 };
969 
970 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
971 			     struct mlx5_async_ctx *ctx);
972 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
973 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
974 		     void *out, int out_size, mlx5_async_cbk_t callback,
975 		     struct mlx5_async_work *work);
976 
977 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
978 		  int out_size);
979 
980 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
981 	({                                                                     \
982 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
983 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
984 	})
985 
986 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
987 	({                                                                     \
988 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
989 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
990 	})
991 
992 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
993 			  void *out, int out_size);
994 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
995 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
996 
997 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
998 void mlx5_health_flush(struct mlx5_core_dev *dev);
999 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1000 int mlx5_health_init(struct mlx5_core_dev *dev);
1001 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1002 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1003 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1004 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1005 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1006 		   int size, struct mlx5_frag_buf *buf);
1007 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1008 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1009 			     struct mlx5_frag_buf *buf, int node);
1010 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1011 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1012 						      gfp_t flags, int npages);
1013 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1014 				 struct mlx5_cmd_mailbox *head);
1015 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1016 			  int inlen);
1017 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1018 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1019 			 int outlen);
1020 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1021 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1022 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1023 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1024 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1025 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1026 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1027 				 s32 npages, bool ec_function);
1028 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1029 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1030 void mlx5_register_debugfs(void);
1031 void mlx5_unregister_debugfs(void);
1032 
1033 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1034 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1035 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1036 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1037 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1038 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1039 
1040 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1041 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1042 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1043 			 int size_in, void *data_out, int size_out,
1044 			 u16 reg_num, int arg, int write);
1045 
1046 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1047 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1048 		       int node);
1049 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1050 
1051 const char *mlx5_command_str(int command);
1052 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1053 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1054 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1055 			 int npsvs, u32 *sig_index);
1056 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1057 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1058 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1059 			struct mlx5_odp_caps *odp_caps);
1060 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1061 			     u8 port_num, void *out, size_t sz);
1062 
1063 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1064 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1065 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1066 		     struct mlx5_rate_limit *rl);
1067 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1068 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1069 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1070 			 bool dedicated_entry, u16 *index);
1071 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1072 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1073 		       struct mlx5_rate_limit *rl_1);
1074 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1075 		     bool map_wc, bool fast_path);
1076 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1077 
1078 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1079 struct cpumask *
1080 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1081 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1082 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1083 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1084 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1085 
1086 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1087 {
1088 	return mkey >> 8;
1089 }
1090 
1091 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1092 {
1093 	return mkey_idx << 8;
1094 }
1095 
1096 static inline u8 mlx5_mkey_variant(u32 mkey)
1097 {
1098 	return mkey & 0xff;
1099 }
1100 
1101 /* Async-atomic event notifier used by mlx5 core to forward FW
1102  * evetns received from event queue to mlx5 consumers.
1103  * Optimise event queue dipatching.
1104  */
1105 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1106 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1107 
1108 /* Async-atomic event notifier used for forwarding
1109  * evetns from the event queue into the to mlx5 events dispatcher,
1110  * eswitch, clock and others.
1111  */
1112 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1113 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1114 
1115 /* Blocking event notifier used to forward SW events, used for slow path */
1116 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1117 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1118 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1119 				      void *data);
1120 
1121 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1122 
1123 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1124 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1125 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1126 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1127 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1128 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1129 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1130 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1131 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1132 			   struct net_device *slave);
1133 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1134 				 u64 *values,
1135 				 int num_counters,
1136 				 size_t *offsets);
1137 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1138 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1139 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1140 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1141 			 u64 length, u32 log_alignment, u16 uid,
1142 			 phys_addr_t *addr, u32 *obj_id);
1143 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1144 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1145 
1146 #ifdef CONFIG_MLX5_CORE_IPOIB
1147 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1148 					  struct ib_device *ibdev,
1149 					  const char *name,
1150 					  void (*setup)(struct net_device *));
1151 #endif /* CONFIG_MLX5_CORE_IPOIB */
1152 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1153 			    struct ib_device *device,
1154 			    struct rdma_netdev_alloc_params *params);
1155 
1156 enum {
1157 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1158 };
1159 
1160 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1161 {
1162 	return dev->coredev_type == MLX5_COREDEV_PF;
1163 }
1164 
1165 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1166 {
1167 	return dev->coredev_type == MLX5_COREDEV_VF;
1168 }
1169 
1170 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1171 {
1172 	return dev->caps.embedded_cpu;
1173 }
1174 
1175 static inline bool
1176 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1177 {
1178 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1179 }
1180 
1181 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1182 {
1183 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1184 }
1185 
1186 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1187 {
1188 	return dev->priv.sriov.max_vfs;
1189 }
1190 
1191 static inline int mlx5_get_gid_table_len(u16 param)
1192 {
1193 	if (param > 4) {
1194 		pr_warn("gid table length is zero\n");
1195 		return 0;
1196 	}
1197 
1198 	return 8 * (1 << param);
1199 }
1200 
1201 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1202 {
1203 	return !!(dev->priv.rl_table.max_size);
1204 }
1205 
1206 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1207 {
1208 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1209 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1210 }
1211 
1212 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1213 {
1214 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1215 }
1216 
1217 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1218 {
1219 	return mlx5_core_is_mp_slave(dev) ||
1220 	       mlx5_core_is_mp_master(dev);
1221 }
1222 
1223 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1224 {
1225 	if (!mlx5_core_mp_enabled(dev))
1226 		return 1;
1227 
1228 	return MLX5_CAP_GEN(dev, native_port_num);
1229 }
1230 
1231 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1232 {
1233 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1234 
1235 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1236 		return idx - 1;
1237 	else
1238 		return PCI_FUNC(dev->pdev->devfn);
1239 }
1240 
1241 enum {
1242 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1243 };
1244 
1245 static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1246 {
1247 	struct devlink *devlink = priv_to_devlink(dev);
1248 	union devlink_param_value val;
1249 	int err;
1250 
1251 	err = devlink_param_driverinit_value_get(devlink,
1252 						 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1253 						 &val);
1254 	return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1255 }
1256 
1257 #endif /* MLX5_DRIVER_H */
1258