xref: /linux-6.15/include/linux/mlx5/driver.h (revision caecb05c) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 
52 #include <linux/mlx5/device.h>
53 #include <linux/mlx5/doorbell.h>
54 #include <linux/mlx5/eq.h>
55 #include <linux/timecounter.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/devlink.h>
58 
59 enum {
60 	MLX5_BOARD_ID_LEN = 64,
61 };
62 
63 enum {
64 	/* one minute for the sake of bringup. Generally, commands must always
65 	 * complete and we may need to increase this timeout value
66 	 */
67 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
68 	MLX5_CMD_WQ_MAX_NAME	= 32,
69 };
70 
71 enum {
72 	CMD_OWNER_SW		= 0x0,
73 	CMD_OWNER_HW		= 0x1,
74 	CMD_STATUS_SUCCESS	= 0,
75 };
76 
77 enum mlx5_sqp_t {
78 	MLX5_SQP_SMI		= 0,
79 	MLX5_SQP_GSI		= 1,
80 	MLX5_SQP_IEEE_1588	= 2,
81 	MLX5_SQP_SNIFFER	= 3,
82 	MLX5_SQP_SYNC_UMR	= 4,
83 };
84 
85 enum {
86 	MLX5_MAX_PORTS	= 2,
87 };
88 
89 enum {
90 	MLX5_ATOMIC_MODE_OFFSET = 16,
91 	MLX5_ATOMIC_MODE_IB_COMP = 1,
92 	MLX5_ATOMIC_MODE_CX = 2,
93 	MLX5_ATOMIC_MODE_8B = 3,
94 	MLX5_ATOMIC_MODE_16B = 4,
95 	MLX5_ATOMIC_MODE_32B = 5,
96 	MLX5_ATOMIC_MODE_64B = 6,
97 	MLX5_ATOMIC_MODE_128B = 7,
98 	MLX5_ATOMIC_MODE_256B = 8,
99 };
100 
101 enum {
102 	MLX5_REG_QPTS            = 0x4002,
103 	MLX5_REG_QETCR		 = 0x4005,
104 	MLX5_REG_QTCT		 = 0x400a,
105 	MLX5_REG_QPDPM           = 0x4013,
106 	MLX5_REG_QCAM            = 0x4019,
107 	MLX5_REG_DCBX_PARAM      = 0x4020,
108 	MLX5_REG_DCBX_APP        = 0x4021,
109 	MLX5_REG_FPGA_CAP	 = 0x4022,
110 	MLX5_REG_FPGA_CTRL	 = 0x4023,
111 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
112 	MLX5_REG_CORE_DUMP	 = 0x402e,
113 	MLX5_REG_PCAP		 = 0x5001,
114 	MLX5_REG_PMTU		 = 0x5003,
115 	MLX5_REG_PTYS		 = 0x5004,
116 	MLX5_REG_PAOS		 = 0x5006,
117 	MLX5_REG_PFCC            = 0x5007,
118 	MLX5_REG_PPCNT		 = 0x5008,
119 	MLX5_REG_PPTB            = 0x500b,
120 	MLX5_REG_PBMC            = 0x500c,
121 	MLX5_REG_PMAOS		 = 0x5012,
122 	MLX5_REG_PUDE		 = 0x5009,
123 	MLX5_REG_PMPE		 = 0x5010,
124 	MLX5_REG_PELC		 = 0x500e,
125 	MLX5_REG_PVLC		 = 0x500f,
126 	MLX5_REG_PCMR		 = 0x5041,
127 	MLX5_REG_PMLP		 = 0x5002,
128 	MLX5_REG_PPLM		 = 0x5023,
129 	MLX5_REG_PCAM		 = 0x507f,
130 	MLX5_REG_NODE_DESC	 = 0x6001,
131 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 	MLX5_REG_MCIA		 = 0x9014,
133 	MLX5_REG_MFRL		 = 0x9028,
134 	MLX5_REG_MLCR		 = 0x902b,
135 	MLX5_REG_MTRC_CAP	 = 0x9040,
136 	MLX5_REG_MTRC_CONF	 = 0x9041,
137 	MLX5_REG_MTRC_STDB	 = 0x9042,
138 	MLX5_REG_MTRC_CTRL	 = 0x9043,
139 	MLX5_REG_MPEIN		 = 0x9050,
140 	MLX5_REG_MPCNT		 = 0x9051,
141 	MLX5_REG_MTPPS		 = 0x9053,
142 	MLX5_REG_MTPPSE		 = 0x9054,
143 	MLX5_REG_MPEGC		 = 0x9056,
144 	MLX5_REG_MCQS		 = 0x9060,
145 	MLX5_REG_MCQI		 = 0x9061,
146 	MLX5_REG_MCC		 = 0x9062,
147 	MLX5_REG_MCDA		 = 0x9063,
148 	MLX5_REG_MCAM		 = 0x907f,
149 	MLX5_REG_MIRC		 = 0x9162,
150 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
151 };
152 
153 enum mlx5_qpts_trust_state {
154 	MLX5_QPTS_TRUST_PCP  = 1,
155 	MLX5_QPTS_TRUST_DSCP = 2,
156 };
157 
158 enum mlx5_dcbx_oper_mode {
159 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
160 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
161 };
162 
163 enum {
164 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
165 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
166 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
167 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
168 };
169 
170 enum mlx5_page_fault_resume_flags {
171 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
172 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
173 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
174 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
175 };
176 
177 enum dbg_rsc_type {
178 	MLX5_DBG_RSC_QP,
179 	MLX5_DBG_RSC_EQ,
180 	MLX5_DBG_RSC_CQ,
181 };
182 
183 enum port_state_policy {
184 	MLX5_POLICY_DOWN	= 0,
185 	MLX5_POLICY_UP		= 1,
186 	MLX5_POLICY_FOLLOW	= 2,
187 	MLX5_POLICY_INVALID	= 0xffffffff
188 };
189 
190 enum mlx5_coredev_type {
191 	MLX5_COREDEV_PF,
192 	MLX5_COREDEV_VF
193 };
194 
195 struct mlx5_field_desc {
196 	int			i;
197 };
198 
199 struct mlx5_rsc_debug {
200 	struct mlx5_core_dev   *dev;
201 	void		       *object;
202 	enum dbg_rsc_type	type;
203 	struct dentry	       *root;
204 	struct mlx5_field_desc	fields[];
205 };
206 
207 enum mlx5_dev_event {
208 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
209 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
210 };
211 
212 enum mlx5_port_status {
213 	MLX5_PORT_UP        = 1,
214 	MLX5_PORT_DOWN      = 2,
215 };
216 
217 enum mlx5_cmdif_state {
218 	MLX5_CMDIF_STATE_UNINITIALIZED,
219 	MLX5_CMDIF_STATE_UP,
220 	MLX5_CMDIF_STATE_DOWN,
221 };
222 
223 struct mlx5_cmd_first {
224 	__be32		data[4];
225 };
226 
227 struct mlx5_cmd_msg {
228 	struct list_head		list;
229 	struct cmd_msg_cache	       *parent;
230 	u32				len;
231 	struct mlx5_cmd_first		first;
232 	struct mlx5_cmd_mailbox	       *next;
233 };
234 
235 struct mlx5_cmd_debug {
236 	struct dentry	       *dbg_root;
237 	void		       *in_msg;
238 	void		       *out_msg;
239 	u8			status;
240 	u16			inlen;
241 	u16			outlen;
242 };
243 
244 struct cmd_msg_cache {
245 	/* protect block chain allocations
246 	 */
247 	spinlock_t		lock;
248 	struct list_head	head;
249 	unsigned int		max_inbox_size;
250 	unsigned int		num_ent;
251 };
252 
253 enum {
254 	MLX5_NUM_COMMAND_CACHES = 5,
255 };
256 
257 struct mlx5_cmd_stats {
258 	u64		sum;
259 	u64		n;
260 	struct dentry  *root;
261 	/* protect command average calculations */
262 	spinlock_t	lock;
263 };
264 
265 struct mlx5_cmd {
266 	struct mlx5_nb    nb;
267 
268 	enum mlx5_cmdif_state	state;
269 	void	       *cmd_alloc_buf;
270 	dma_addr_t	alloc_dma;
271 	int		alloc_size;
272 	void	       *cmd_buf;
273 	dma_addr_t	dma;
274 	u16		cmdif_rev;
275 	u8		log_sz;
276 	u8		log_stride;
277 	int		max_reg_cmds;
278 	int		events;
279 	u32 __iomem    *vector;
280 
281 	/* protect command queue allocations
282 	 */
283 	spinlock_t	alloc_lock;
284 
285 	/* protect token allocations
286 	 */
287 	spinlock_t	token_lock;
288 	u8		token;
289 	unsigned long	bitmask;
290 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
291 	struct workqueue_struct *wq;
292 	struct semaphore sem;
293 	struct semaphore pages_sem;
294 	int	mode;
295 	u16     allowed_opcode;
296 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
297 	struct dma_pool *pool;
298 	struct mlx5_cmd_debug dbg;
299 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
300 	int checksum_disabled;
301 	struct mlx5_cmd_stats *stats;
302 };
303 
304 struct mlx5_port_caps {
305 	int	gid_table_len;
306 	int	pkey_table_len;
307 	u8	ext_port_cap;
308 	bool	has_smi;
309 };
310 
311 struct mlx5_cmd_mailbox {
312 	void	       *buf;
313 	dma_addr_t	dma;
314 	struct mlx5_cmd_mailbox *next;
315 };
316 
317 struct mlx5_buf_list {
318 	void		       *buf;
319 	dma_addr_t		map;
320 };
321 
322 struct mlx5_frag_buf {
323 	struct mlx5_buf_list	*frags;
324 	int			npages;
325 	int			size;
326 	u8			page_shift;
327 };
328 
329 struct mlx5_frag_buf_ctrl {
330 	struct mlx5_buf_list   *frags;
331 	u32			sz_m1;
332 	u16			frag_sz_m1;
333 	u16			strides_offset;
334 	u8			log_sz;
335 	u8			log_stride;
336 	u8			log_frag_strides;
337 };
338 
339 struct mlx5_core_psv {
340 	u32	psv_idx;
341 	struct psv_layout {
342 		u32	pd;
343 		u16	syndrome;
344 		u16	reserved;
345 		u16	bg;
346 		u16	app_tag;
347 		u32	ref_tag;
348 	} psv;
349 };
350 
351 struct mlx5_core_sig_ctx {
352 	struct mlx5_core_psv	psv_memory;
353 	struct mlx5_core_psv	psv_wire;
354 	struct ib_sig_err       err_item;
355 	bool			sig_status_checked;
356 	bool			sig_err_exists;
357 	u32			sigerr_count;
358 };
359 
360 enum {
361 	MLX5_MKEY_MR = 1,
362 	MLX5_MKEY_MW,
363 	MLX5_MKEY_INDIRECT_DEVX,
364 };
365 
366 struct mlx5_core_mkey {
367 	u64			iova;
368 	u64			size;
369 	u32			key;
370 	u32			pd;
371 	u32			type;
372 };
373 
374 #define MLX5_24BIT_MASK		((1 << 24) - 1)
375 
376 enum mlx5_res_type {
377 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
378 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
379 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
380 	MLX5_RES_SRQ	= 3,
381 	MLX5_RES_XSRQ	= 4,
382 	MLX5_RES_XRQ	= 5,
383 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
384 };
385 
386 struct mlx5_core_rsc_common {
387 	enum mlx5_res_type	res;
388 	refcount_t		refcount;
389 	struct completion	free;
390 };
391 
392 struct mlx5_uars_page {
393 	void __iomem	       *map;
394 	bool			wc;
395 	u32			index;
396 	struct list_head	list;
397 	unsigned int		bfregs;
398 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
399 	unsigned long	       *fp_bitmap;
400 	unsigned int		reg_avail;
401 	unsigned int		fp_avail;
402 	struct kref		ref_count;
403 	struct mlx5_core_dev   *mdev;
404 };
405 
406 struct mlx5_bfreg_head {
407 	/* protect blue flame registers allocations */
408 	struct mutex		lock;
409 	struct list_head	list;
410 };
411 
412 struct mlx5_bfreg_data {
413 	struct mlx5_bfreg_head	reg_head;
414 	struct mlx5_bfreg_head	wc_head;
415 };
416 
417 struct mlx5_sq_bfreg {
418 	void __iomem	       *map;
419 	struct mlx5_uars_page  *up;
420 	bool			wc;
421 	u32			index;
422 	unsigned int		offset;
423 };
424 
425 struct mlx5_core_health {
426 	struct health_buffer __iomem   *health;
427 	__be32 __iomem		       *health_counter;
428 	struct timer_list		timer;
429 	u32				prev;
430 	int				miss_counter;
431 	u8				synd;
432 	u32				fatal_error;
433 	u32				crdump_size;
434 	/* wq spinlock to synchronize draining */
435 	spinlock_t			wq_lock;
436 	struct workqueue_struct	       *wq;
437 	unsigned long			flags;
438 	struct work_struct		fatal_report_work;
439 	struct work_struct		report_work;
440 	struct delayed_work		recover_work;
441 	struct devlink_health_reporter *fw_reporter;
442 	struct devlink_health_reporter *fw_fatal_reporter;
443 };
444 
445 struct mlx5_qp_table {
446 	struct notifier_block   nb;
447 
448 	/* protect radix tree
449 	 */
450 	spinlock_t		lock;
451 	struct radix_tree_root	tree;
452 };
453 
454 struct mlx5_vf_context {
455 	int	enabled;
456 	u64	port_guid;
457 	u64	node_guid;
458 	/* Valid bits are used to validate administrative guid only.
459 	 * Enabled after ndo_set_vf_guid
460 	 */
461 	u8	port_guid_valid:1;
462 	u8	node_guid_valid:1;
463 	enum port_state_policy	policy;
464 };
465 
466 struct mlx5_core_sriov {
467 	struct mlx5_vf_context	*vfs_ctx;
468 	int			num_vfs;
469 	u16			max_vfs;
470 };
471 
472 struct mlx5_fc_pool {
473 	struct mlx5_core_dev *dev;
474 	struct mutex pool_lock; /* protects pool lists */
475 	struct list_head fully_used;
476 	struct list_head partially_used;
477 	struct list_head unused;
478 	int available_fcs;
479 	int used_fcs;
480 	int threshold;
481 };
482 
483 struct mlx5_fc_stats {
484 	spinlock_t counters_idr_lock; /* protects counters_idr */
485 	struct idr counters_idr;
486 	struct list_head counters;
487 	struct llist_head addlist;
488 	struct llist_head dellist;
489 
490 	struct workqueue_struct *wq;
491 	struct delayed_work work;
492 	unsigned long next_query;
493 	unsigned long sampling_interval; /* jiffies */
494 	u32 *bulk_query_out;
495 	struct mlx5_fc_pool fc_pool;
496 };
497 
498 struct mlx5_events;
499 struct mlx5_mpfs;
500 struct mlx5_eswitch;
501 struct mlx5_lag;
502 struct mlx5_devcom;
503 struct mlx5_eq_table;
504 struct mlx5_irq_table;
505 
506 struct mlx5_rate_limit {
507 	u32			rate;
508 	u32			max_burst_sz;
509 	u16			typical_pkt_sz;
510 };
511 
512 struct mlx5_rl_entry {
513 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
514 	u16 index;
515 	u64 refcount;
516 	u16 uid;
517 	u8 dedicated : 1;
518 };
519 
520 struct mlx5_rl_table {
521 	/* protect rate limit table */
522 	struct mutex            rl_lock;
523 	u16                     max_size;
524 	u32                     max_rate;
525 	u32                     min_rate;
526 	struct mlx5_rl_entry   *rl_entry;
527 };
528 
529 struct mlx5_core_roce {
530 	struct mlx5_flow_table *ft;
531 	struct mlx5_flow_group *fg;
532 	struct mlx5_flow_handle *allow_rule;
533 };
534 
535 struct mlx5_priv {
536 	/* IRQ table valid only for real pci devices PF or VF */
537 	struct mlx5_irq_table   *irq_table;
538 	struct mlx5_eq_table	*eq_table;
539 
540 	/* pages stuff */
541 	struct mlx5_nb          pg_nb;
542 	struct workqueue_struct *pg_wq;
543 	struct rb_root		page_root;
544 	int			fw_pages;
545 	atomic_t		reg_pages;
546 	struct list_head	free_list;
547 	int			vfs_pages;
548 	int			peer_pf_pages;
549 
550 	struct mlx5_core_health health;
551 
552 	/* start: qp staff */
553 	struct dentry	       *qp_debugfs;
554 	struct dentry	       *eq_debugfs;
555 	struct dentry	       *cq_debugfs;
556 	struct dentry	       *cmdif_debugfs;
557 	/* end: qp staff */
558 
559 	/* start: alloc staff */
560 	/* protect buffer alocation according to numa node */
561 	struct mutex            alloc_mutex;
562 	int                     numa_node;
563 
564 	struct mutex            pgdir_mutex;
565 	struct list_head        pgdir_list;
566 	/* end: alloc staff */
567 	struct dentry	       *dbg_root;
568 
569 	struct list_head        dev_list;
570 	struct list_head        ctx_list;
571 	spinlock_t              ctx_lock;
572 	struct mlx5_events      *events;
573 
574 	struct mlx5_flow_steering *steering;
575 	struct mlx5_mpfs        *mpfs;
576 	struct mlx5_eswitch     *eswitch;
577 	struct mlx5_core_sriov	sriov;
578 	struct mlx5_lag		*lag;
579 	struct mlx5_devcom	*devcom;
580 	struct mlx5_core_roce	roce;
581 	struct mlx5_fc_stats		fc_stats;
582 	struct mlx5_rl_table            rl_table;
583 
584 	struct mlx5_bfreg_data		bfregs;
585 	struct mlx5_uars_page	       *uar;
586 };
587 
588 enum mlx5_device_state {
589 	MLX5_DEVICE_STATE_UNINITIALIZED,
590 	MLX5_DEVICE_STATE_UP,
591 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
592 };
593 
594 enum mlx5_interface_state {
595 	MLX5_INTERFACE_STATE_UP = BIT(0),
596 };
597 
598 enum mlx5_pci_status {
599 	MLX5_PCI_STATUS_DISABLED,
600 	MLX5_PCI_STATUS_ENABLED,
601 };
602 
603 enum mlx5_pagefault_type_flags {
604 	MLX5_PFAULT_REQUESTOR = 1 << 0,
605 	MLX5_PFAULT_WRITE     = 1 << 1,
606 	MLX5_PFAULT_RDMA      = 1 << 2,
607 };
608 
609 struct mlx5_td {
610 	/* protects tirs list changes while tirs refresh */
611 	struct mutex     list_lock;
612 	struct list_head tirs_list;
613 	u32              tdn;
614 };
615 
616 struct mlx5e_resources {
617 	u32                        pdn;
618 	struct mlx5_td             td;
619 	struct mlx5_core_mkey      mkey;
620 	struct mlx5_sq_bfreg       bfreg;
621 };
622 
623 enum mlx5_sw_icm_type {
624 	MLX5_SW_ICM_TYPE_STEERING,
625 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
626 };
627 
628 #define MLX5_MAX_RESERVED_GIDS 8
629 
630 struct mlx5_rsvd_gids {
631 	unsigned int start;
632 	unsigned int count;
633 	struct ida ida;
634 };
635 
636 #define MAX_PIN_NUM	8
637 struct mlx5_pps {
638 	u8                         pin_caps[MAX_PIN_NUM];
639 	struct work_struct         out_work;
640 	u64                        start[MAX_PIN_NUM];
641 	u8                         enabled;
642 };
643 
644 struct mlx5_clock {
645 	struct mlx5_core_dev      *mdev;
646 	struct mlx5_nb             pps_nb;
647 	seqlock_t                  lock;
648 	struct cyclecounter        cycles;
649 	struct timecounter         tc;
650 	struct hwtstamp_config     hwtstamp_config;
651 	u32                        nominal_c_mult;
652 	unsigned long              overflow_period;
653 	struct delayed_work        overflow_work;
654 	struct ptp_clock          *ptp;
655 	struct ptp_clock_info      ptp_info;
656 	struct mlx5_pps            pps_info;
657 };
658 
659 struct mlx5_dm;
660 struct mlx5_fw_tracer;
661 struct mlx5_vxlan;
662 struct mlx5_geneve;
663 struct mlx5_hv_vhca;
664 
665 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
666 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
667 
668 struct mlx5_core_dev {
669 	struct device *device;
670 	enum mlx5_coredev_type coredev_type;
671 	struct pci_dev	       *pdev;
672 	/* sync pci state */
673 	struct mutex		pci_status_mutex;
674 	enum mlx5_pci_status	pci_status;
675 	u8			rev_id;
676 	char			board_id[MLX5_BOARD_ID_LEN];
677 	struct mlx5_cmd		cmd;
678 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
679 	struct {
680 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
681 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
682 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
683 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
684 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
685 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
686 		u8  embedded_cpu;
687 	} caps;
688 	u64			sys_image_guid;
689 	phys_addr_t		iseg_base;
690 	struct mlx5_init_seg __iomem *iseg;
691 	phys_addr_t             bar_addr;
692 	enum mlx5_device_state	state;
693 	/* sync interface state */
694 	struct mutex		intf_state_mutex;
695 	unsigned long		intf_state;
696 	struct mlx5_priv	priv;
697 	struct mlx5_profile	*profile;
698 	u32			issi;
699 	struct mlx5e_resources  mlx5e_res;
700 	struct mlx5_dm          *dm;
701 	struct mlx5_vxlan       *vxlan;
702 	struct mlx5_geneve      *geneve;
703 	struct {
704 		struct mlx5_rsvd_gids	reserved_gids;
705 		u32			roce_en;
706 	} roce;
707 #ifdef CONFIG_MLX5_FPGA
708 	struct mlx5_fpga_device *fpga;
709 #endif
710 	struct mlx5_clock        clock;
711 	struct mlx5_ib_clock_info  *clock_info;
712 	struct mlx5_fw_tracer   *tracer;
713 	struct mlx5_rsc_dump    *rsc_dump;
714 	u32                      vsc_addr;
715 	struct mlx5_hv_vhca	*hv_vhca;
716 };
717 
718 struct mlx5_db {
719 	__be32			*db;
720 	union {
721 		struct mlx5_db_pgdir		*pgdir;
722 		struct mlx5_ib_user_db_page	*user_page;
723 	}			u;
724 	dma_addr_t		dma;
725 	int			index;
726 };
727 
728 enum {
729 	MLX5_COMP_EQ_SIZE = 1024,
730 };
731 
732 enum {
733 	MLX5_PTYS_IB = 1 << 0,
734 	MLX5_PTYS_EN = 1 << 2,
735 };
736 
737 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
738 
739 enum {
740 	MLX5_CMD_ENT_STATE_PENDING_COMP,
741 };
742 
743 struct mlx5_cmd_work_ent {
744 	unsigned long		state;
745 	struct mlx5_cmd_msg    *in;
746 	struct mlx5_cmd_msg    *out;
747 	void		       *uout;
748 	int			uout_size;
749 	mlx5_cmd_cbk_t		callback;
750 	struct delayed_work	cb_timeout_work;
751 	void		       *context;
752 	int			idx;
753 	struct completion	handling;
754 	struct completion	done;
755 	struct mlx5_cmd        *cmd;
756 	struct work_struct	work;
757 	struct mlx5_cmd_layout *lay;
758 	int			ret;
759 	int			page_queue;
760 	u8			status;
761 	u8			token;
762 	u64			ts1;
763 	u64			ts2;
764 	u16			op;
765 	bool			polling;
766 };
767 
768 struct mlx5_pas {
769 	u64	pa;
770 	u8	log_sz;
771 };
772 
773 enum phy_port_state {
774 	MLX5_AAA_111
775 };
776 
777 struct mlx5_hca_vport_context {
778 	u32			field_select;
779 	bool			sm_virt_aware;
780 	bool			has_smi;
781 	bool			has_raw;
782 	enum port_state_policy	policy;
783 	enum phy_port_state	phys_state;
784 	enum ib_port_state	vport_state;
785 	u8			port_physical_state;
786 	u64			sys_image_guid;
787 	u64			port_guid;
788 	u64			node_guid;
789 	u32			cap_mask1;
790 	u32			cap_mask1_perm;
791 	u16			cap_mask2;
792 	u16			cap_mask2_perm;
793 	u16			lid;
794 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
795 	u8			lmc;
796 	u8			subnet_timeout;
797 	u16			sm_lid;
798 	u8			sm_sl;
799 	u16			qkey_violation_counter;
800 	u16			pkey_violation_counter;
801 	bool			grh_required;
802 };
803 
804 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
805 {
806 		return buf->frags->buf + offset;
807 }
808 
809 #define STRUCT_FIELD(header, field) \
810 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
811 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
812 
813 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
814 {
815 	return pci_get_drvdata(pdev);
816 }
817 
818 extern struct dentry *mlx5_debugfs_root;
819 
820 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
821 {
822 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
823 }
824 
825 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
826 {
827 	return ioread32be(&dev->iseg->fw_rev) >> 16;
828 }
829 
830 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
831 {
832 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
833 }
834 
835 static inline u32 mlx5_base_mkey(const u32 key)
836 {
837 	return key & 0xffffff00u;
838 }
839 
840 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
841 					u8 log_stride, u8 log_sz,
842 					u16 strides_offset,
843 					struct mlx5_frag_buf_ctrl *fbc)
844 {
845 	fbc->frags      = frags;
846 	fbc->log_stride = log_stride;
847 	fbc->log_sz     = log_sz;
848 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
849 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
850 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
851 	fbc->strides_offset = strides_offset;
852 }
853 
854 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
855 				 u8 log_stride, u8 log_sz,
856 				 struct mlx5_frag_buf_ctrl *fbc)
857 {
858 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
859 }
860 
861 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
862 					  u32 ix)
863 {
864 	unsigned int frag;
865 
866 	ix  += fbc->strides_offset;
867 	frag = ix >> fbc->log_frag_strides;
868 
869 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
870 }
871 
872 static inline u32
873 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
874 {
875 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
876 
877 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
878 }
879 
880 enum {
881 	CMD_ALLOWED_OPCODE_ALL,
882 };
883 
884 int mlx5_cmd_init(struct mlx5_core_dev *dev);
885 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
886 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
887 			enum mlx5_cmdif_state cmdif_state);
888 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
889 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
890 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
891 
892 struct mlx5_async_ctx {
893 	struct mlx5_core_dev *dev;
894 	atomic_t num_inflight;
895 	struct wait_queue_head wait;
896 };
897 
898 struct mlx5_async_work;
899 
900 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
901 
902 struct mlx5_async_work {
903 	struct mlx5_async_ctx *ctx;
904 	mlx5_async_cbk_t user_callback;
905 };
906 
907 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
908 			     struct mlx5_async_ctx *ctx);
909 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
910 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
911 		     void *out, int out_size, mlx5_async_cbk_t callback,
912 		     struct mlx5_async_work *work);
913 
914 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
915 		  int out_size);
916 
917 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
918 	({                                                                     \
919 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
920 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
921 	})
922 
923 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
924 	({                                                                     \
925 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
926 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
927 	})
928 
929 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
930 			  void *out, int out_size);
931 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
932 
933 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
934 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
935 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
936 void mlx5_health_flush(struct mlx5_core_dev *dev);
937 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
938 int mlx5_health_init(struct mlx5_core_dev *dev);
939 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
940 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
941 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
942 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
943 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
944 		   int size, struct mlx5_frag_buf *buf);
945 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
946 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
947 			     struct mlx5_frag_buf *buf, int node);
948 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
949 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
950 						      gfp_t flags, int npages);
951 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
952 				 struct mlx5_cmd_mailbox *head);
953 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
954 			  struct mlx5_core_mkey *mkey,
955 			  u32 *in, int inlen);
956 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
957 			   struct mlx5_core_mkey *mkey);
958 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
959 			 u32 *out, int outlen);
960 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
961 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
962 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
963 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
964 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
965 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
966 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
967 				 s32 npages, bool ec_function);
968 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
969 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
970 void mlx5_register_debugfs(void);
971 void mlx5_unregister_debugfs(void);
972 
973 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
974 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
975 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
976 		    unsigned int *irqn);
977 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
978 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
979 
980 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
981 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
982 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
983 			 int size_in, void *data_out, int size_out,
984 			 u16 reg_num, int arg, int write);
985 
986 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
987 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
988 		       int node);
989 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
990 
991 const char *mlx5_command_str(int command);
992 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
993 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
994 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
995 			 int npsvs, u32 *sig_index);
996 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
997 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
998 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
999 			struct mlx5_odp_caps *odp_caps);
1000 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1001 			     u8 port_num, void *out, size_t sz);
1002 
1003 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1004 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1005 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1006 		     struct mlx5_rate_limit *rl);
1007 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1008 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1009 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1010 			 bool dedicated_entry, u16 *index);
1011 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1012 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1013 		       struct mlx5_rate_limit *rl_1);
1014 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1015 		     bool map_wc, bool fast_path);
1016 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1017 
1018 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1019 struct cpumask *
1020 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1021 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1022 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1023 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1024 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1025 
1026 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1027 {
1028 	return mkey >> 8;
1029 }
1030 
1031 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1032 {
1033 	return mkey_idx << 8;
1034 }
1035 
1036 static inline u8 mlx5_mkey_variant(u32 mkey)
1037 {
1038 	return mkey & 0xff;
1039 }
1040 
1041 enum {
1042 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1043 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1044 };
1045 
1046 enum {
1047 	MR_CACHE_LAST_STD_ENTRY = 20,
1048 	MLX5_IMR_MTT_CACHE_ENTRY,
1049 	MLX5_IMR_KSM_CACHE_ENTRY,
1050 	MAX_MR_CACHE_ENTRIES
1051 };
1052 
1053 enum {
1054 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1055 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1056 };
1057 
1058 struct mlx5_interface {
1059 	void *			(*add)(struct mlx5_core_dev *dev);
1060 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1061 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1062 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1063 	int			protocol;
1064 	struct list_head	list;
1065 };
1066 
1067 int mlx5_register_interface(struct mlx5_interface *intf);
1068 void mlx5_unregister_interface(struct mlx5_interface *intf);
1069 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1070 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1071 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1072 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1073 
1074 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1075 
1076 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1077 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1078 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1079 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1080 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1081 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1082 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1083 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1084 			   struct net_device *slave);
1085 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1086 				 u64 *values,
1087 				 int num_counters,
1088 				 size_t *offsets);
1089 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1090 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1091 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1092 			 u64 length, u32 log_alignment, u16 uid,
1093 			 phys_addr_t *addr, u32 *obj_id);
1094 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1095 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1096 
1097 #ifdef CONFIG_MLX5_CORE_IPOIB
1098 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1099 					  struct ib_device *ibdev,
1100 					  const char *name,
1101 					  void (*setup)(struct net_device *));
1102 #endif /* CONFIG_MLX5_CORE_IPOIB */
1103 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1104 			    struct ib_device *device,
1105 			    struct rdma_netdev_alloc_params *params);
1106 
1107 struct mlx5_profile {
1108 	u64	mask;
1109 	u8	log_max_qp;
1110 	struct {
1111 		int	size;
1112 		int	limit;
1113 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1114 };
1115 
1116 enum {
1117 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1118 };
1119 
1120 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1121 {
1122 	return dev->coredev_type == MLX5_COREDEV_PF;
1123 }
1124 
1125 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1126 {
1127 	return dev->coredev_type == MLX5_COREDEV_VF;
1128 }
1129 
1130 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1131 {
1132 	return dev->caps.embedded_cpu;
1133 }
1134 
1135 static inline bool
1136 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1137 {
1138 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1139 }
1140 
1141 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1142 {
1143 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1144 }
1145 
1146 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1147 {
1148 	return dev->priv.sriov.max_vfs;
1149 }
1150 
1151 static inline int mlx5_get_gid_table_len(u16 param)
1152 {
1153 	if (param > 4) {
1154 		pr_warn("gid table length is zero\n");
1155 		return 0;
1156 	}
1157 
1158 	return 8 * (1 << param);
1159 }
1160 
1161 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1162 {
1163 	return !!(dev->priv.rl_table.max_size);
1164 }
1165 
1166 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1167 {
1168 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1169 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1170 }
1171 
1172 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1173 {
1174 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1175 }
1176 
1177 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1178 {
1179 	return mlx5_core_is_mp_slave(dev) ||
1180 	       mlx5_core_is_mp_master(dev);
1181 }
1182 
1183 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1184 {
1185 	if (!mlx5_core_mp_enabled(dev))
1186 		return 1;
1187 
1188 	return MLX5_CAP_GEN(dev, native_port_num);
1189 }
1190 
1191 enum {
1192 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1193 };
1194 
1195 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1196 {
1197 	struct devlink *devlink = priv_to_devlink(dev);
1198 	union devlink_param_value val;
1199 
1200 	devlink_param_driverinit_value_get(devlink,
1201 					   DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1202 					   &val);
1203 	return val.vbool;
1204 }
1205 
1206 #endif /* MLX5_DRIVER_H */
1207