xref: /linux-6.15/include/linux/mlx5/driver.h (revision c411ed85) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/mempool.h>
46 #include <linux/interrupt.h>
47 #include <linux/idr.h>
48 
49 #include <linux/mlx5/device.h>
50 #include <linux/mlx5/doorbell.h>
51 #include <linux/mlx5/srq.h>
52 
53 enum {
54 	MLX5_BOARD_ID_LEN = 64,
55 	MLX5_MAX_NAME_LEN = 16,
56 };
57 
58 enum {
59 	/* one minute for the sake of bringup. Generally, commands must always
60 	 * complete and we may need to increase this timeout value
61 	 */
62 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
63 	MLX5_CMD_WQ_MAX_NAME	= 32,
64 };
65 
66 enum {
67 	CMD_OWNER_SW		= 0x0,
68 	CMD_OWNER_HW		= 0x1,
69 	CMD_STATUS_SUCCESS	= 0,
70 };
71 
72 enum mlx5_sqp_t {
73 	MLX5_SQP_SMI		= 0,
74 	MLX5_SQP_GSI		= 1,
75 	MLX5_SQP_IEEE_1588	= 2,
76 	MLX5_SQP_SNIFFER	= 3,
77 	MLX5_SQP_SYNC_UMR	= 4,
78 };
79 
80 enum {
81 	MLX5_MAX_PORTS	= 2,
82 };
83 
84 enum {
85 	MLX5_EQ_VEC_PAGES	 = 0,
86 	MLX5_EQ_VEC_CMD		 = 1,
87 	MLX5_EQ_VEC_ASYNC	 = 2,
88 	MLX5_EQ_VEC_PFAULT	 = 3,
89 	MLX5_EQ_VEC_COMP_BASE,
90 };
91 
92 enum {
93 	MLX5_MAX_IRQ_NAME	= 32
94 };
95 
96 enum {
97 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << 16,
98 	MLX5_ATOMIC_MODE_CX		= 2 << 16,
99 	MLX5_ATOMIC_MODE_8B		= 3 << 16,
100 	MLX5_ATOMIC_MODE_16B		= 4 << 16,
101 	MLX5_ATOMIC_MODE_32B		= 5 << 16,
102 	MLX5_ATOMIC_MODE_64B		= 6 << 16,
103 	MLX5_ATOMIC_MODE_128B		= 7 << 16,
104 	MLX5_ATOMIC_MODE_256B		= 8 << 16,
105 };
106 
107 enum {
108 	MLX5_REG_QETCR		 = 0x4005,
109 	MLX5_REG_QTCT		 = 0x400a,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_PCAP		 = 0x5001,
116 	MLX5_REG_PMTU		 = 0x5003,
117 	MLX5_REG_PTYS		 = 0x5004,
118 	MLX5_REG_PAOS		 = 0x5006,
119 	MLX5_REG_PFCC            = 0x5007,
120 	MLX5_REG_PPCNT		 = 0x5008,
121 	MLX5_REG_PMAOS		 = 0x5012,
122 	MLX5_REG_PUDE		 = 0x5009,
123 	MLX5_REG_PMPE		 = 0x5010,
124 	MLX5_REG_PELC		 = 0x500e,
125 	MLX5_REG_PVLC		 = 0x500f,
126 	MLX5_REG_PCMR		 = 0x5041,
127 	MLX5_REG_PMLP		 = 0x5002,
128 	MLX5_REG_PCAM		 = 0x507f,
129 	MLX5_REG_NODE_DESC	 = 0x6001,
130 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
131 	MLX5_REG_MCIA		 = 0x9014,
132 	MLX5_REG_MLCR		 = 0x902b,
133 	MLX5_REG_MPCNT		 = 0x9051,
134 	MLX5_REG_MTPPS		 = 0x9053,
135 	MLX5_REG_MTPPSE		 = 0x9054,
136 	MLX5_REG_MCQI		 = 0x9061,
137 	MLX5_REG_MCC		 = 0x9062,
138 	MLX5_REG_MCDA		 = 0x9063,
139 	MLX5_REG_MCAM		 = 0x907f,
140 };
141 
142 enum mlx5_dcbx_oper_mode {
143 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
144 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
145 };
146 
147 enum {
148 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
149 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
150 };
151 
152 enum mlx5_page_fault_resume_flags {
153 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
154 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
155 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
156 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
157 };
158 
159 enum dbg_rsc_type {
160 	MLX5_DBG_RSC_QP,
161 	MLX5_DBG_RSC_EQ,
162 	MLX5_DBG_RSC_CQ,
163 };
164 
165 struct mlx5_field_desc {
166 	struct dentry	       *dent;
167 	int			i;
168 };
169 
170 struct mlx5_rsc_debug {
171 	struct mlx5_core_dev   *dev;
172 	void		       *object;
173 	enum dbg_rsc_type	type;
174 	struct dentry	       *root;
175 	struct mlx5_field_desc	fields[0];
176 };
177 
178 enum mlx5_dev_event {
179 	MLX5_DEV_EVENT_SYS_ERROR,
180 	MLX5_DEV_EVENT_PORT_UP,
181 	MLX5_DEV_EVENT_PORT_DOWN,
182 	MLX5_DEV_EVENT_PORT_INITIALIZED,
183 	MLX5_DEV_EVENT_LID_CHANGE,
184 	MLX5_DEV_EVENT_PKEY_CHANGE,
185 	MLX5_DEV_EVENT_GUID_CHANGE,
186 	MLX5_DEV_EVENT_CLIENT_REREG,
187 	MLX5_DEV_EVENT_PPS,
188 };
189 
190 enum mlx5_port_status {
191 	MLX5_PORT_UP        = 1,
192 	MLX5_PORT_DOWN      = 2,
193 };
194 
195 enum mlx5_eq_type {
196 	MLX5_EQ_TYPE_COMP,
197 	MLX5_EQ_TYPE_ASYNC,
198 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
199 	MLX5_EQ_TYPE_PF,
200 #endif
201 };
202 
203 struct mlx5_bfreg_info {
204 	u32		       *sys_pages;
205 	int			num_low_latency_bfregs;
206 	unsigned int	       *count;
207 
208 	/*
209 	 * protect bfreg allocation data structs
210 	 */
211 	struct mutex		lock;
212 	u32			ver;
213 	bool			lib_uar_4k;
214 	u32			num_sys_pages;
215 };
216 
217 struct mlx5_cmd_first {
218 	__be32		data[4];
219 };
220 
221 struct mlx5_cmd_msg {
222 	struct list_head		list;
223 	struct cmd_msg_cache	       *parent;
224 	u32				len;
225 	struct mlx5_cmd_first		first;
226 	struct mlx5_cmd_mailbox	       *next;
227 };
228 
229 struct mlx5_cmd_debug {
230 	struct dentry	       *dbg_root;
231 	struct dentry	       *dbg_in;
232 	struct dentry	       *dbg_out;
233 	struct dentry	       *dbg_outlen;
234 	struct dentry	       *dbg_status;
235 	struct dentry	       *dbg_run;
236 	void		       *in_msg;
237 	void		       *out_msg;
238 	u8			status;
239 	u16			inlen;
240 	u16			outlen;
241 };
242 
243 struct cmd_msg_cache {
244 	/* protect block chain allocations
245 	 */
246 	spinlock_t		lock;
247 	struct list_head	head;
248 	unsigned int		max_inbox_size;
249 	unsigned int		num_ent;
250 };
251 
252 enum {
253 	MLX5_NUM_COMMAND_CACHES = 5,
254 };
255 
256 struct mlx5_cmd_stats {
257 	u64		sum;
258 	u64		n;
259 	struct dentry  *root;
260 	struct dentry  *avg;
261 	struct dentry  *count;
262 	/* protect command average calculations */
263 	spinlock_t	lock;
264 };
265 
266 struct mlx5_cmd {
267 	void	       *cmd_alloc_buf;
268 	dma_addr_t	alloc_dma;
269 	int		alloc_size;
270 	void	       *cmd_buf;
271 	dma_addr_t	dma;
272 	u16		cmdif_rev;
273 	u8		log_sz;
274 	u8		log_stride;
275 	int		max_reg_cmds;
276 	int		events;
277 	u32 __iomem    *vector;
278 
279 	/* protect command queue allocations
280 	 */
281 	spinlock_t	alloc_lock;
282 
283 	/* protect token allocations
284 	 */
285 	spinlock_t	token_lock;
286 	u8		token;
287 	unsigned long	bitmask;
288 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
289 	struct workqueue_struct *wq;
290 	struct semaphore sem;
291 	struct semaphore pages_sem;
292 	int	mode;
293 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
294 	struct pci_pool *pool;
295 	struct mlx5_cmd_debug dbg;
296 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
297 	int checksum_disabled;
298 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
299 };
300 
301 struct mlx5_port_caps {
302 	int	gid_table_len;
303 	int	pkey_table_len;
304 	u8	ext_port_cap;
305 	bool	has_smi;
306 };
307 
308 struct mlx5_cmd_mailbox {
309 	void	       *buf;
310 	dma_addr_t	dma;
311 	struct mlx5_cmd_mailbox *next;
312 };
313 
314 struct mlx5_buf_list {
315 	void		       *buf;
316 	dma_addr_t		map;
317 };
318 
319 struct mlx5_buf {
320 	struct mlx5_buf_list	direct;
321 	int			npages;
322 	int			size;
323 	u8			page_shift;
324 };
325 
326 struct mlx5_frag_buf {
327 	struct mlx5_buf_list	*frags;
328 	int			npages;
329 	int			size;
330 	u8			page_shift;
331 };
332 
333 struct mlx5_eq_tasklet {
334 	struct list_head list;
335 	struct list_head process_list;
336 	struct tasklet_struct task;
337 	/* lock on completion tasklet list */
338 	spinlock_t lock;
339 };
340 
341 struct mlx5_eq_pagefault {
342 	struct work_struct       work;
343 	/* Pagefaults lock */
344 	spinlock_t		 lock;
345 	struct workqueue_struct *wq;
346 	mempool_t		*pool;
347 };
348 
349 struct mlx5_eq {
350 	struct mlx5_core_dev   *dev;
351 	__be32 __iomem	       *doorbell;
352 	u32			cons_index;
353 	struct mlx5_buf		buf;
354 	int			size;
355 	unsigned int		irqn;
356 	u8			eqn;
357 	int			nent;
358 	u64			mask;
359 	struct list_head	list;
360 	int			index;
361 	struct mlx5_rsc_debug	*dbg;
362 	enum mlx5_eq_type	type;
363 	union {
364 		struct mlx5_eq_tasklet   tasklet_ctx;
365 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
366 		struct mlx5_eq_pagefault pf_ctx;
367 #endif
368 	};
369 };
370 
371 struct mlx5_core_psv {
372 	u32	psv_idx;
373 	struct psv_layout {
374 		u32	pd;
375 		u16	syndrome;
376 		u16	reserved;
377 		u16	bg;
378 		u16	app_tag;
379 		u32	ref_tag;
380 	} psv;
381 };
382 
383 struct mlx5_core_sig_ctx {
384 	struct mlx5_core_psv	psv_memory;
385 	struct mlx5_core_psv	psv_wire;
386 	struct ib_sig_err       err_item;
387 	bool			sig_status_checked;
388 	bool			sig_err_exists;
389 	u32			sigerr_count;
390 };
391 
392 enum {
393 	MLX5_MKEY_MR = 1,
394 	MLX5_MKEY_MW,
395 };
396 
397 struct mlx5_core_mkey {
398 	u64			iova;
399 	u64			size;
400 	u32			key;
401 	u32			pd;
402 	u32			type;
403 };
404 
405 #define MLX5_24BIT_MASK		((1 << 24) - 1)
406 
407 enum mlx5_res_type {
408 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
409 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
410 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
411 	MLX5_RES_SRQ	= 3,
412 	MLX5_RES_XSRQ	= 4,
413 };
414 
415 struct mlx5_core_rsc_common {
416 	enum mlx5_res_type	res;
417 	atomic_t		refcount;
418 	struct completion	free;
419 };
420 
421 struct mlx5_core_srq {
422 	struct mlx5_core_rsc_common	common; /* must be first */
423 	u32		srqn;
424 	int		max;
425 	int		max_gs;
426 	int		max_avail_gather;
427 	int		wqe_shift;
428 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
429 
430 	atomic_t		refcount;
431 	struct completion	free;
432 };
433 
434 struct mlx5_eq_table {
435 	void __iomem	       *update_ci;
436 	void __iomem	       *update_arm_ci;
437 	struct list_head	comp_eqs_list;
438 	struct mlx5_eq		pages_eq;
439 	struct mlx5_eq		async_eq;
440 	struct mlx5_eq		cmd_eq;
441 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
442 	struct mlx5_eq		pfault_eq;
443 #endif
444 	int			num_comp_vectors;
445 	/* protect EQs list
446 	 */
447 	spinlock_t		lock;
448 };
449 
450 struct mlx5_uars_page {
451 	void __iomem	       *map;
452 	bool			wc;
453 	u32			index;
454 	struct list_head	list;
455 	unsigned int		bfregs;
456 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
457 	unsigned long	       *fp_bitmap;
458 	unsigned int		reg_avail;
459 	unsigned int		fp_avail;
460 	struct kref		ref_count;
461 	struct mlx5_core_dev   *mdev;
462 };
463 
464 struct mlx5_bfreg_head {
465 	/* protect blue flame registers allocations */
466 	struct mutex		lock;
467 	struct list_head	list;
468 };
469 
470 struct mlx5_bfreg_data {
471 	struct mlx5_bfreg_head	reg_head;
472 	struct mlx5_bfreg_head	wc_head;
473 };
474 
475 struct mlx5_sq_bfreg {
476 	void __iomem	       *map;
477 	struct mlx5_uars_page  *up;
478 	bool			wc;
479 	u32			index;
480 	unsigned int		offset;
481 };
482 
483 struct mlx5_core_health {
484 	struct health_buffer __iomem   *health;
485 	__be32 __iomem		       *health_counter;
486 	struct timer_list		timer;
487 	u32				prev;
488 	int				miss_counter;
489 	bool				sick;
490 	/* wq spinlock to synchronize draining */
491 	spinlock_t			wq_lock;
492 	struct workqueue_struct	       *wq;
493 	unsigned long			flags;
494 	struct work_struct		work;
495 	struct delayed_work		recover_work;
496 };
497 
498 struct mlx5_cq_table {
499 	/* protect radix tree
500 	 */
501 	spinlock_t		lock;
502 	struct radix_tree_root	tree;
503 };
504 
505 struct mlx5_qp_table {
506 	/* protect radix tree
507 	 */
508 	spinlock_t		lock;
509 	struct radix_tree_root	tree;
510 };
511 
512 struct mlx5_srq_table {
513 	/* protect radix tree
514 	 */
515 	spinlock_t		lock;
516 	struct radix_tree_root	tree;
517 };
518 
519 struct mlx5_mkey_table {
520 	/* protect radix tree
521 	 */
522 	rwlock_t		lock;
523 	struct radix_tree_root	tree;
524 };
525 
526 struct mlx5_vf_context {
527 	int	enabled;
528 };
529 
530 struct mlx5_core_sriov {
531 	struct mlx5_vf_context	*vfs_ctx;
532 	int			num_vfs;
533 	int			enabled_vfs;
534 };
535 
536 struct mlx5_irq_info {
537 	cpumask_var_t mask;
538 	char name[MLX5_MAX_IRQ_NAME];
539 };
540 
541 struct mlx5_fc_stats {
542 	struct rb_root counters;
543 	struct list_head addlist;
544 	/* protect addlist add/splice operations */
545 	spinlock_t addlist_lock;
546 
547 	struct workqueue_struct *wq;
548 	struct delayed_work work;
549 	unsigned long next_query;
550 	unsigned long sampling_interval; /* jiffies */
551 };
552 
553 struct mlx5_mpfs;
554 struct mlx5_eswitch;
555 struct mlx5_lag;
556 struct mlx5_pagefault;
557 
558 struct mlx5_rl_entry {
559 	u32                     rate;
560 	u16                     index;
561 	u16                     refcount;
562 };
563 
564 struct mlx5_rl_table {
565 	/* protect rate limit table */
566 	struct mutex            rl_lock;
567 	u16                     max_size;
568 	u32                     max_rate;
569 	u32                     min_rate;
570 	struct mlx5_rl_entry   *rl_entry;
571 };
572 
573 enum port_module_event_status_type {
574 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
575 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
576 	MLX5_MODULE_STATUS_ERROR     = 0x3,
577 	MLX5_MODULE_STATUS_NUM       = 0x3,
578 };
579 
580 enum  port_module_event_error_type {
581 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
582 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
583 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
584 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
585 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
586 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
587 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
588 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
589 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
590 	MLX5_MODULE_EVENT_ERROR_NUM,
591 };
592 
593 struct mlx5_port_module_event_stats {
594 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
595 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
596 };
597 
598 struct mlx5_priv {
599 	char			name[MLX5_MAX_NAME_LEN];
600 	struct mlx5_eq_table	eq_table;
601 	struct msix_entry	*msix_arr;
602 	struct mlx5_irq_info	*irq_info;
603 
604 	/* pages stuff */
605 	struct workqueue_struct *pg_wq;
606 	struct rb_root		page_root;
607 	int			fw_pages;
608 	atomic_t		reg_pages;
609 	struct list_head	free_list;
610 	int			vfs_pages;
611 
612 	struct mlx5_core_health health;
613 
614 	struct mlx5_srq_table	srq_table;
615 
616 	/* start: qp staff */
617 	struct mlx5_qp_table	qp_table;
618 	struct dentry	       *qp_debugfs;
619 	struct dentry	       *eq_debugfs;
620 	struct dentry	       *cq_debugfs;
621 	struct dentry	       *cmdif_debugfs;
622 	/* end: qp staff */
623 
624 	/* start: cq staff */
625 	struct mlx5_cq_table	cq_table;
626 	/* end: cq staff */
627 
628 	/* start: mkey staff */
629 	struct mlx5_mkey_table	mkey_table;
630 	/* end: mkey staff */
631 
632 	/* start: alloc staff */
633 	/* protect buffer alocation according to numa node */
634 	struct mutex            alloc_mutex;
635 	int                     numa_node;
636 
637 	struct mutex            pgdir_mutex;
638 	struct list_head        pgdir_list;
639 	/* end: alloc staff */
640 	struct dentry	       *dbg_root;
641 
642 	/* protect mkey key part */
643 	spinlock_t		mkey_lock;
644 	u8			mkey_key;
645 
646 	struct list_head        dev_list;
647 	struct list_head        ctx_list;
648 	spinlock_t              ctx_lock;
649 
650 	struct list_head	waiting_events_list;
651 	bool			is_accum_events;
652 
653 	struct mlx5_flow_steering *steering;
654 	struct mlx5_mpfs        *mpfs;
655 	struct mlx5_eswitch     *eswitch;
656 	struct mlx5_core_sriov	sriov;
657 	struct mlx5_lag		*lag;
658 	unsigned long		pci_dev_data;
659 	struct mlx5_fc_stats		fc_stats;
660 	struct mlx5_rl_table            rl_table;
661 
662 	struct mlx5_port_module_event_stats  pme_stats;
663 
664 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
665 	void		      (*pfault)(struct mlx5_core_dev *dev,
666 					void *context,
667 					struct mlx5_pagefault *pfault);
668 	void		       *pfault_ctx;
669 	struct srcu_struct      pfault_srcu;
670 #endif
671 	struct mlx5_bfreg_data		bfregs;
672 	struct mlx5_uars_page	       *uar;
673 };
674 
675 enum mlx5_device_state {
676 	MLX5_DEVICE_STATE_UP,
677 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
678 };
679 
680 enum mlx5_interface_state {
681 	MLX5_INTERFACE_STATE_DOWN = BIT(0),
682 	MLX5_INTERFACE_STATE_UP = BIT(1),
683 	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
684 };
685 
686 enum mlx5_pci_status {
687 	MLX5_PCI_STATUS_DISABLED,
688 	MLX5_PCI_STATUS_ENABLED,
689 };
690 
691 enum mlx5_pagefault_type_flags {
692 	MLX5_PFAULT_REQUESTOR = 1 << 0,
693 	MLX5_PFAULT_WRITE     = 1 << 1,
694 	MLX5_PFAULT_RDMA      = 1 << 2,
695 };
696 
697 /* Contains the details of a pagefault. */
698 struct mlx5_pagefault {
699 	u32			bytes_committed;
700 	u32			token;
701 	u8			event_subtype;
702 	u8			type;
703 	union {
704 		/* Initiator or send message responder pagefault details. */
705 		struct {
706 			/* Received packet size, only valid for responders. */
707 			u32	packet_size;
708 			/*
709 			 * Number of resource holding WQE, depends on type.
710 			 */
711 			u32	wq_num;
712 			/*
713 			 * WQE index. Refers to either the send queue or
714 			 * receive queue, according to event_subtype.
715 			 */
716 			u16	wqe_index;
717 		} wqe;
718 		/* RDMA responder pagefault details */
719 		struct {
720 			u32	r_key;
721 			/*
722 			 * Received packet size, minimal size page fault
723 			 * resolution required for forward progress.
724 			 */
725 			u32	packet_size;
726 			u32	rdma_op_len;
727 			u64	rdma_va;
728 		} rdma;
729 	};
730 
731 	struct mlx5_eq	       *eq;
732 	struct work_struct	work;
733 };
734 
735 struct mlx5_td {
736 	struct list_head tirs_list;
737 	u32              tdn;
738 };
739 
740 struct mlx5e_resources {
741 	u32                        pdn;
742 	struct mlx5_td             td;
743 	struct mlx5_core_mkey      mkey;
744 	struct mlx5_sq_bfreg       bfreg;
745 };
746 
747 #define MLX5_MAX_RESERVED_GIDS 8
748 
749 struct mlx5_rsvd_gids {
750 	unsigned int start;
751 	unsigned int count;
752 	struct ida ida;
753 };
754 
755 struct mlx5_core_dev {
756 	struct pci_dev	       *pdev;
757 	/* sync pci state */
758 	struct mutex		pci_status_mutex;
759 	enum mlx5_pci_status	pci_status;
760 	u8			rev_id;
761 	char			board_id[MLX5_BOARD_ID_LEN];
762 	struct mlx5_cmd		cmd;
763 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
764 	struct {
765 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
766 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
767 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
768 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
769 	} caps;
770 	phys_addr_t		iseg_base;
771 	struct mlx5_init_seg __iomem *iseg;
772 	enum mlx5_device_state	state;
773 	/* sync interface state */
774 	struct mutex		intf_state_mutex;
775 	unsigned long		intf_state;
776 	void			(*event) (struct mlx5_core_dev *dev,
777 					  enum mlx5_dev_event event,
778 					  unsigned long param);
779 	struct mlx5_priv	priv;
780 	struct mlx5_profile	*profile;
781 	atomic_t		num_qps;
782 	u32			issi;
783 	struct mlx5e_resources  mlx5e_res;
784 	struct {
785 		struct mlx5_rsvd_gids	reserved_gids;
786 		atomic_t                roce_en;
787 	} roce;
788 #ifdef CONFIG_MLX5_FPGA
789 	struct mlx5_fpga_device *fpga;
790 #endif
791 #ifdef CONFIG_RFS_ACCEL
792 	struct cpu_rmap         *rmap;
793 #endif
794 };
795 
796 struct mlx5_db {
797 	__be32			*db;
798 	union {
799 		struct mlx5_db_pgdir		*pgdir;
800 		struct mlx5_ib_user_db_page	*user_page;
801 	}			u;
802 	dma_addr_t		dma;
803 	int			index;
804 };
805 
806 enum {
807 	MLX5_COMP_EQ_SIZE = 1024,
808 };
809 
810 enum {
811 	MLX5_PTYS_IB = 1 << 0,
812 	MLX5_PTYS_EN = 1 << 2,
813 };
814 
815 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
816 
817 enum {
818 	MLX5_CMD_ENT_STATE_PENDING_COMP,
819 };
820 
821 struct mlx5_cmd_work_ent {
822 	unsigned long		state;
823 	struct mlx5_cmd_msg    *in;
824 	struct mlx5_cmd_msg    *out;
825 	void		       *uout;
826 	int			uout_size;
827 	mlx5_cmd_cbk_t		callback;
828 	struct delayed_work	cb_timeout_work;
829 	void		       *context;
830 	int			idx;
831 	struct completion	done;
832 	struct mlx5_cmd        *cmd;
833 	struct work_struct	work;
834 	struct mlx5_cmd_layout *lay;
835 	int			ret;
836 	int			page_queue;
837 	u8			status;
838 	u8			token;
839 	u64			ts1;
840 	u64			ts2;
841 	u16			op;
842 	bool			polling;
843 };
844 
845 struct mlx5_pas {
846 	u64	pa;
847 	u8	log_sz;
848 };
849 
850 enum port_state_policy {
851 	MLX5_POLICY_DOWN	= 0,
852 	MLX5_POLICY_UP		= 1,
853 	MLX5_POLICY_FOLLOW	= 2,
854 	MLX5_POLICY_INVALID	= 0xffffffff
855 };
856 
857 enum phy_port_state {
858 	MLX5_AAA_111
859 };
860 
861 struct mlx5_hca_vport_context {
862 	u32			field_select;
863 	bool			sm_virt_aware;
864 	bool			has_smi;
865 	bool			has_raw;
866 	enum port_state_policy	policy;
867 	enum phy_port_state	phys_state;
868 	enum ib_port_state	vport_state;
869 	u8			port_physical_state;
870 	u64			sys_image_guid;
871 	u64			port_guid;
872 	u64			node_guid;
873 	u32			cap_mask1;
874 	u32			cap_mask1_perm;
875 	u32			cap_mask2;
876 	u32			cap_mask2_perm;
877 	u16			lid;
878 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
879 	u8			lmc;
880 	u8			subnet_timeout;
881 	u16			sm_lid;
882 	u8			sm_sl;
883 	u16			qkey_violation_counter;
884 	u16			pkey_violation_counter;
885 	bool			grh_required;
886 };
887 
888 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
889 {
890 		return buf->direct.buf + offset;
891 }
892 
893 #define STRUCT_FIELD(header, field) \
894 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
895 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
896 
897 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
898 {
899 	return pci_get_drvdata(pdev);
900 }
901 
902 extern struct dentry *mlx5_debugfs_root;
903 
904 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
905 {
906 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
907 }
908 
909 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
910 {
911 	return ioread32be(&dev->iseg->fw_rev) >> 16;
912 }
913 
914 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
915 {
916 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
917 }
918 
919 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
920 {
921 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
922 }
923 
924 static inline u32 mlx5_base_mkey(const u32 key)
925 {
926 	return key & 0xffffff00u;
927 }
928 
929 int mlx5_cmd_init(struct mlx5_core_dev *dev);
930 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
931 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
932 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
933 
934 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
935 		  int out_size);
936 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
937 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
938 		     void *context);
939 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
940 			  void *out, int out_size);
941 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
942 
943 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
944 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
945 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
946 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
947 int mlx5_health_init(struct mlx5_core_dev *dev);
948 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
949 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
950 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
951 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
952 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
953 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
954 			struct mlx5_buf *buf, int node);
955 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
956 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
957 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
958 			     struct mlx5_frag_buf *buf, int node);
959 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
960 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
961 						      gfp_t flags, int npages);
962 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
963 				 struct mlx5_cmd_mailbox *head);
964 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
965 			 struct mlx5_srq_attr *in);
966 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
967 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
968 			struct mlx5_srq_attr *out);
969 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
970 		      u16 lwm, int is_srq);
971 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
972 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
973 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
974 			     struct mlx5_core_mkey *mkey,
975 			     u32 *in, int inlen,
976 			     u32 *out, int outlen,
977 			     mlx5_cmd_cbk_t callback, void *context);
978 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
979 			  struct mlx5_core_mkey *mkey,
980 			  u32 *in, int inlen);
981 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
982 			   struct mlx5_core_mkey *mkey);
983 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
984 			 u32 *out, int outlen);
985 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
986 			     u32 *mkey);
987 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
988 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
989 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
990 		      u16 opmod, u8 port);
991 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
992 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
993 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
994 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
995 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
996 				 s32 npages);
997 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
998 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
999 void mlx5_register_debugfs(void);
1000 void mlx5_unregister_debugfs(void);
1001 int mlx5_eq_init(struct mlx5_core_dev *dev);
1002 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1003 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1004 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1005 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1006 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1007 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1008 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1009 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1010 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1011 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1012 		       int nent, u64 mask, const char *name,
1013 		       enum mlx5_eq_type type);
1014 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1015 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1016 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1017 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1018 		    unsigned int *irqn);
1019 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1020 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1021 
1022 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1023 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1024 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1025 			 int size_in, void *data_out, int size_out,
1026 			 u16 reg_num, int arg, int write);
1027 
1028 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1029 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1030 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1031 		       u32 *out, int outlen);
1032 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1033 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1034 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1035 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1036 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1037 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1038 		       int node);
1039 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1040 
1041 const char *mlx5_command_str(int command);
1042 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1043 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1044 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1045 			 int npsvs, u32 *sig_index);
1046 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1047 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1048 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1049 			struct mlx5_odp_caps *odp_caps);
1050 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1051 			     u8 port_num, void *out, size_t sz);
1052 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1053 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1054 				u32 wq_num, u8 type, int error);
1055 #endif
1056 
1057 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1058 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1059 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1060 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1061 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1062 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1063 		     bool map_wc, bool fast_path);
1064 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1065 
1066 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1067 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1068 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1069 			   const u8 *mac, bool vlan, u16 vlan_id);
1070 
1071 static inline int fw_initializing(struct mlx5_core_dev *dev)
1072 {
1073 	return ioread32be(&dev->iseg->initializing) >> 31;
1074 }
1075 
1076 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1077 {
1078 	return mkey >> 8;
1079 }
1080 
1081 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1082 {
1083 	return mkey_idx << 8;
1084 }
1085 
1086 static inline u8 mlx5_mkey_variant(u32 mkey)
1087 {
1088 	return mkey & 0xff;
1089 }
1090 
1091 enum {
1092 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1093 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1094 };
1095 
1096 enum {
1097 	MAX_UMR_CACHE_ENTRY = 20,
1098 	MLX5_IMR_MTT_CACHE_ENTRY,
1099 	MLX5_IMR_KSM_CACHE_ENTRY,
1100 	MAX_MR_CACHE_ENTRIES
1101 };
1102 
1103 enum {
1104 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1105 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1106 };
1107 
1108 struct mlx5_interface {
1109 	void *			(*add)(struct mlx5_core_dev *dev);
1110 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1111 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1112 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1113 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1114 					 enum mlx5_dev_event event, unsigned long param);
1115 	void			(*pfault)(struct mlx5_core_dev *dev,
1116 					  void *context,
1117 					  struct mlx5_pagefault *pfault);
1118 	void *                  (*get_dev)(void *context);
1119 	int			protocol;
1120 	struct list_head	list;
1121 };
1122 
1123 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1124 int mlx5_register_interface(struct mlx5_interface *intf);
1125 void mlx5_unregister_interface(struct mlx5_interface *intf);
1126 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1127 
1128 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1129 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1130 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1131 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1132 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1133 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1134 
1135 #ifndef CONFIG_MLX5_CORE_IPOIB
1136 static inline
1137 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1138 					  struct ib_device *ibdev,
1139 					  const char *name,
1140 					  void (*setup)(struct net_device *))
1141 {
1142 	return ERR_PTR(-EOPNOTSUPP);
1143 }
1144 
1145 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1146 #else
1147 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1148 					  struct ib_device *ibdev,
1149 					  const char *name,
1150 					  void (*setup)(struct net_device *));
1151 void mlx5_rdma_netdev_free(struct net_device *netdev);
1152 #endif /* CONFIG_MLX5_CORE_IPOIB */
1153 
1154 struct mlx5_profile {
1155 	u64	mask;
1156 	u8	log_max_qp;
1157 	struct {
1158 		int	size;
1159 		int	limit;
1160 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1161 };
1162 
1163 enum {
1164 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1165 };
1166 
1167 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1168 {
1169 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1170 }
1171 
1172 static inline int mlx5_get_gid_table_len(u16 param)
1173 {
1174 	if (param > 4) {
1175 		pr_warn("gid table length is zero\n");
1176 		return 0;
1177 	}
1178 
1179 	return 8 * (1 << param);
1180 }
1181 
1182 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1183 {
1184 	return !!(dev->priv.rl_table.max_size);
1185 }
1186 
1187 enum {
1188 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1189 };
1190 
1191 #endif /* MLX5_DRIVER_H */
1192