xref: /linux-6.15/include/linux/mlx5/driver.h (revision bfca85fa) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63 
64 enum {
65 	MLX5_BOARD_ID_LEN = 64,
66 };
67 
68 enum {
69 	MLX5_CMD_WQ_MAX_NAME	= 32,
70 };
71 
72 enum {
73 	CMD_OWNER_SW		= 0x0,
74 	CMD_OWNER_HW		= 0x1,
75 	CMD_STATUS_SUCCESS	= 0,
76 };
77 
78 enum mlx5_sqp_t {
79 	MLX5_SQP_SMI		= 0,
80 	MLX5_SQP_GSI		= 1,
81 	MLX5_SQP_IEEE_1588	= 2,
82 	MLX5_SQP_SNIFFER	= 3,
83 	MLX5_SQP_SYNC_UMR	= 4,
84 };
85 
86 enum {
87 	MLX5_MAX_PORTS	= 8,
88 };
89 
90 enum {
91 	MLX5_ATOMIC_MODE_OFFSET = 16,
92 	MLX5_ATOMIC_MODE_IB_COMP = 1,
93 	MLX5_ATOMIC_MODE_CX = 2,
94 	MLX5_ATOMIC_MODE_8B = 3,
95 	MLX5_ATOMIC_MODE_16B = 4,
96 	MLX5_ATOMIC_MODE_32B = 5,
97 	MLX5_ATOMIC_MODE_64B = 6,
98 	MLX5_ATOMIC_MODE_128B = 7,
99 	MLX5_ATOMIC_MODE_256B = 8,
100 };
101 
102 enum {
103 	MLX5_REG_SBPR            = 0xb001,
104 	MLX5_REG_SBCM            = 0xb002,
105 	MLX5_REG_QPTS            = 0x4002,
106 	MLX5_REG_QETCR		 = 0x4005,
107 	MLX5_REG_QTCT		 = 0x400a,
108 	MLX5_REG_QPDPM           = 0x4013,
109 	MLX5_REG_QCAM            = 0x4019,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_CORE_DUMP	 = 0x402e,
116 	MLX5_REG_PCAP		 = 0x5001,
117 	MLX5_REG_PMTU		 = 0x5003,
118 	MLX5_REG_PTYS		 = 0x5004,
119 	MLX5_REG_PAOS		 = 0x5006,
120 	MLX5_REG_PFCC            = 0x5007,
121 	MLX5_REG_PPCNT		 = 0x5008,
122 	MLX5_REG_PPTB            = 0x500b,
123 	MLX5_REG_PBMC            = 0x500c,
124 	MLX5_REG_PMAOS		 = 0x5012,
125 	MLX5_REG_PUDE		 = 0x5009,
126 	MLX5_REG_PMPE		 = 0x5010,
127 	MLX5_REG_PELC		 = 0x500e,
128 	MLX5_REG_PVLC		 = 0x500f,
129 	MLX5_REG_PCMR		 = 0x5041,
130 	MLX5_REG_PDDR		 = 0x5031,
131 	MLX5_REG_PMLP		 = 0x5002,
132 	MLX5_REG_PPLM		 = 0x5023,
133 	MLX5_REG_PCAM		 = 0x507f,
134 	MLX5_REG_NODE_DESC	 = 0x6001,
135 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 	MLX5_REG_MTCAP		 = 0x9009,
137 	MLX5_REG_MTMP		 = 0x900A,
138 	MLX5_REG_MCIA		 = 0x9014,
139 	MLX5_REG_MFRL		 = 0x9028,
140 	MLX5_REG_MLCR		 = 0x902b,
141 	MLX5_REG_MRTC		 = 0x902d,
142 	MLX5_REG_MTRC_CAP	 = 0x9040,
143 	MLX5_REG_MTRC_CONF	 = 0x9041,
144 	MLX5_REG_MTRC_STDB	 = 0x9042,
145 	MLX5_REG_MTRC_CTRL	 = 0x9043,
146 	MLX5_REG_MPEIN		 = 0x9050,
147 	MLX5_REG_MPCNT		 = 0x9051,
148 	MLX5_REG_MTPPS		 = 0x9053,
149 	MLX5_REG_MTPPSE		 = 0x9054,
150 	MLX5_REG_MTUTC		 = 0x9055,
151 	MLX5_REG_MPEGC		 = 0x9056,
152 	MLX5_REG_MPIR		 = 0x9059,
153 	MLX5_REG_MCQS		 = 0x9060,
154 	MLX5_REG_MCQI		 = 0x9061,
155 	MLX5_REG_MCC		 = 0x9062,
156 	MLX5_REG_MCDA		 = 0x9063,
157 	MLX5_REG_MCAM		 = 0x907f,
158 	MLX5_REG_MSECQ		 = 0x9155,
159 	MLX5_REG_MSEES		 = 0x9156,
160 	MLX5_REG_MIRC		 = 0x9162,
161 	MLX5_REG_MTPTM		 = 0x9180,
162 	MLX5_REG_MTCTR		 = 0x9181,
163 	MLX5_REG_SBCAM		 = 0xB01F,
164 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
165 	MLX5_REG_DTOR            = 0xC00E,
166 };
167 
168 enum mlx5_qpts_trust_state {
169 	MLX5_QPTS_TRUST_PCP  = 1,
170 	MLX5_QPTS_TRUST_DSCP = 2,
171 };
172 
173 enum mlx5_dcbx_oper_mode {
174 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
175 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
176 };
177 
178 enum {
179 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
180 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
181 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
182 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
183 };
184 
185 enum mlx5_page_fault_resume_flags {
186 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
187 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
188 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
189 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
190 };
191 
192 enum dbg_rsc_type {
193 	MLX5_DBG_RSC_QP,
194 	MLX5_DBG_RSC_EQ,
195 	MLX5_DBG_RSC_CQ,
196 };
197 
198 enum port_state_policy {
199 	MLX5_POLICY_DOWN	= 0,
200 	MLX5_POLICY_UP		= 1,
201 	MLX5_POLICY_FOLLOW	= 2,
202 	MLX5_POLICY_INVALID	= 0xffffffff
203 };
204 
205 enum mlx5_coredev_type {
206 	MLX5_COREDEV_PF,
207 	MLX5_COREDEV_VF,
208 	MLX5_COREDEV_SF,
209 };
210 
211 struct mlx5_field_desc {
212 	int			i;
213 };
214 
215 struct mlx5_rsc_debug {
216 	struct mlx5_core_dev   *dev;
217 	void		       *object;
218 	enum dbg_rsc_type	type;
219 	struct dentry	       *root;
220 	struct mlx5_field_desc	fields[];
221 };
222 
223 enum mlx5_dev_event {
224 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
225 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
226 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
227 };
228 
229 enum mlx5_port_status {
230 	MLX5_PORT_UP        = 1,
231 	MLX5_PORT_DOWN      = 2,
232 };
233 
234 enum mlx5_cmdif_state {
235 	MLX5_CMDIF_STATE_UNINITIALIZED,
236 	MLX5_CMDIF_STATE_UP,
237 	MLX5_CMDIF_STATE_DOWN,
238 };
239 
240 struct mlx5_cmd_first {
241 	__be32		data[4];
242 };
243 
244 struct mlx5_cmd_msg {
245 	struct list_head		list;
246 	struct cmd_msg_cache	       *parent;
247 	u32				len;
248 	struct mlx5_cmd_first		first;
249 	struct mlx5_cmd_mailbox	       *next;
250 };
251 
252 struct mlx5_cmd_debug {
253 	struct dentry	       *dbg_root;
254 	void		       *in_msg;
255 	void		       *out_msg;
256 	u8			status;
257 	u16			inlen;
258 	u16			outlen;
259 };
260 
261 struct cmd_msg_cache {
262 	/* protect block chain allocations
263 	 */
264 	spinlock_t		lock;
265 	struct list_head	head;
266 	unsigned int		max_inbox_size;
267 	unsigned int		num_ent;
268 };
269 
270 enum {
271 	MLX5_NUM_COMMAND_CACHES = 5,
272 };
273 
274 struct mlx5_cmd_stats {
275 	u64		sum;
276 	u64		n;
277 	/* number of times command failed */
278 	u64		failed;
279 	/* number of times command failed on bad status returned by FW */
280 	u64		failed_mbox_status;
281 	/* last command failed returned errno */
282 	u32		last_failed_errno;
283 	/* last bad status returned by FW */
284 	u8		last_failed_mbox_status;
285 	/* last command failed syndrome returned by FW */
286 	u32		last_failed_syndrome;
287 	struct dentry  *root;
288 	/* protect command average calculations */
289 	spinlock_t	lock;
290 };
291 
292 struct mlx5_cmd {
293 	struct mlx5_nb    nb;
294 
295 	/* members which needs to be queried or reinitialized each reload */
296 	struct {
297 		u16		cmdif_rev;
298 		u8		log_sz;
299 		u8		log_stride;
300 		int		max_reg_cmds;
301 		unsigned long	bitmask;
302 		struct semaphore sem;
303 		struct semaphore pages_sem;
304 		struct semaphore throttle_sem;
305 	} vars;
306 	enum mlx5_cmdif_state	state;
307 	void	       *cmd_alloc_buf;
308 	dma_addr_t	alloc_dma;
309 	int		alloc_size;
310 	void	       *cmd_buf;
311 	dma_addr_t	dma;
312 
313 	/* protect command queue allocations
314 	 */
315 	spinlock_t	alloc_lock;
316 
317 	/* protect token allocations
318 	 */
319 	spinlock_t	token_lock;
320 	u8		token;
321 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
322 	struct workqueue_struct *wq;
323 	int	mode;
324 	u16     allowed_opcode;
325 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
326 	struct dma_pool *pool;
327 	struct mlx5_cmd_debug dbg;
328 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
329 	int checksum_disabled;
330 	struct xarray stats;
331 };
332 
333 struct mlx5_cmd_mailbox {
334 	void	       *buf;
335 	dma_addr_t	dma;
336 	struct mlx5_cmd_mailbox *next;
337 };
338 
339 struct mlx5_buf_list {
340 	void		       *buf;
341 	dma_addr_t		map;
342 };
343 
344 struct mlx5_frag_buf {
345 	struct mlx5_buf_list	*frags;
346 	int			npages;
347 	int			size;
348 	u8			page_shift;
349 };
350 
351 struct mlx5_frag_buf_ctrl {
352 	struct mlx5_buf_list   *frags;
353 	u32			sz_m1;
354 	u16			frag_sz_m1;
355 	u16			strides_offset;
356 	u8			log_sz;
357 	u8			log_stride;
358 	u8			log_frag_strides;
359 };
360 
361 struct mlx5_core_psv {
362 	u32	psv_idx;
363 	struct psv_layout {
364 		u32	pd;
365 		u16	syndrome;
366 		u16	reserved;
367 		u16	bg;
368 		u16	app_tag;
369 		u32	ref_tag;
370 	} psv;
371 };
372 
373 struct mlx5_core_sig_ctx {
374 	struct mlx5_core_psv	psv_memory;
375 	struct mlx5_core_psv	psv_wire;
376 	struct ib_sig_err       err_item;
377 	bool			sig_status_checked;
378 	bool			sig_err_exists;
379 	u32			sigerr_count;
380 };
381 
382 #define MLX5_24BIT_MASK		((1 << 24) - 1)
383 
384 enum mlx5_res_type {
385 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
386 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
387 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
388 	MLX5_RES_SRQ	= 3,
389 	MLX5_RES_XSRQ	= 4,
390 	MLX5_RES_XRQ	= 5,
391 };
392 
393 struct mlx5_core_rsc_common {
394 	enum mlx5_res_type	res;
395 	refcount_t		refcount;
396 	struct completion	free;
397 };
398 
399 struct mlx5_uars_page {
400 	void __iomem	       *map;
401 	bool			wc;
402 	u32			index;
403 	struct list_head	list;
404 	unsigned int		bfregs;
405 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
406 	unsigned long	       *fp_bitmap;
407 	unsigned int		reg_avail;
408 	unsigned int		fp_avail;
409 	struct kref		ref_count;
410 	struct mlx5_core_dev   *mdev;
411 };
412 
413 struct mlx5_bfreg_head {
414 	/* protect blue flame registers allocations */
415 	struct mutex		lock;
416 	struct list_head	list;
417 };
418 
419 struct mlx5_bfreg_data {
420 	struct mlx5_bfreg_head	reg_head;
421 	struct mlx5_bfreg_head	wc_head;
422 };
423 
424 struct mlx5_sq_bfreg {
425 	void __iomem	       *map;
426 	struct mlx5_uars_page  *up;
427 	bool			wc;
428 	u32			index;
429 	unsigned int		offset;
430 };
431 
432 struct mlx5_core_health {
433 	struct health_buffer __iomem   *health;
434 	__be32 __iomem		       *health_counter;
435 	struct timer_list		timer;
436 	u32				prev;
437 	int				miss_counter;
438 	u8				synd;
439 	u32				fatal_error;
440 	u32				crdump_size;
441 	struct workqueue_struct	       *wq;
442 	unsigned long			flags;
443 	struct work_struct		fatal_report_work;
444 	struct work_struct		report_work;
445 	struct devlink_health_reporter *fw_reporter;
446 	struct devlink_health_reporter *fw_fatal_reporter;
447 	struct devlink_health_reporter *vnic_reporter;
448 	struct delayed_work		update_fw_log_ts_work;
449 };
450 
451 enum {
452 	MLX5_PF_NOTIFY_DISABLE_VF,
453 	MLX5_PF_NOTIFY_ENABLE_VF,
454 };
455 
456 struct mlx5_vf_context {
457 	int	enabled;
458 	u64	port_guid;
459 	u64	node_guid;
460 	/* Valid bits are used to validate administrative guid only.
461 	 * Enabled after ndo_set_vf_guid
462 	 */
463 	u8	port_guid_valid:1;
464 	u8	node_guid_valid:1;
465 	enum port_state_policy	policy;
466 	struct blocking_notifier_head notifier;
467 };
468 
469 struct mlx5_core_sriov {
470 	struct mlx5_vf_context	*vfs_ctx;
471 	int			num_vfs;
472 	u16			max_vfs;
473 	u16			max_ec_vfs;
474 };
475 
476 struct mlx5_events;
477 struct mlx5_mpfs;
478 struct mlx5_eswitch;
479 struct mlx5_lag;
480 struct mlx5_devcom_dev;
481 struct mlx5_fw_reset;
482 struct mlx5_eq_table;
483 struct mlx5_irq_table;
484 struct mlx5_vhca_state_notifier;
485 struct mlx5_sf_dev_table;
486 struct mlx5_sf_hw_table;
487 struct mlx5_sf_table;
488 struct mlx5_crypto_dek_priv;
489 
490 struct mlx5_rate_limit {
491 	u32			rate;
492 	u32			max_burst_sz;
493 	u16			typical_pkt_sz;
494 };
495 
496 struct mlx5_rl_entry {
497 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
498 	u64 refcount;
499 	u16 index;
500 	u16 uid;
501 	u8 dedicated : 1;
502 };
503 
504 struct mlx5_rl_table {
505 	/* protect rate limit table */
506 	struct mutex            rl_lock;
507 	u16                     max_size;
508 	u32                     max_rate;
509 	u32                     min_rate;
510 	struct mlx5_rl_entry   *rl_entry;
511 	u64 refcount;
512 };
513 
514 struct mlx5_core_roce {
515 	struct mlx5_flow_table *ft;
516 	struct mlx5_flow_group *fg;
517 	struct mlx5_flow_handle *allow_rule;
518 };
519 
520 enum {
521 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
522 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
523 	/* Set during device detach to block any further devices
524 	 * creation/deletion on drivers rescan. Unset during device attach.
525 	 */
526 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
527 };
528 
529 struct mlx5_adev {
530 	struct auxiliary_device adev;
531 	struct mlx5_core_dev *mdev;
532 	int idx;
533 };
534 
535 struct mlx5_debugfs_entries {
536 	struct dentry *dbg_root;
537 	struct dentry *qp_debugfs;
538 	struct dentry *eq_debugfs;
539 	struct dentry *cq_debugfs;
540 	struct dentry *cmdif_debugfs;
541 	struct dentry *pages_debugfs;
542 	struct dentry *lag_debugfs;
543 };
544 
545 enum mlx5_func_type {
546 	MLX5_PF,
547 	MLX5_VF,
548 	MLX5_SF,
549 	MLX5_HOST_PF,
550 	MLX5_EC_VF,
551 	MLX5_FUNC_TYPE_NUM,
552 };
553 
554 struct mlx5_ft_pool;
555 struct mlx5_priv {
556 	/* IRQ table valid only for real pci devices PF or VF */
557 	struct mlx5_irq_table   *irq_table;
558 	struct mlx5_eq_table	*eq_table;
559 
560 	/* pages stuff */
561 	struct mlx5_nb          pg_nb;
562 	struct workqueue_struct *pg_wq;
563 	struct xarray           page_root_xa;
564 	atomic_t		reg_pages;
565 	struct list_head	free_list;
566 	u32			fw_pages;
567 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
568 	u32			fw_pages_alloc_failed;
569 	u32			give_pages_dropped;
570 	u32			reclaim_pages_discard;
571 
572 	struct mlx5_core_health health;
573 	struct list_head	traps;
574 
575 	struct mlx5_debugfs_entries dbg;
576 
577 	/* start: alloc staff */
578 	/* protect buffer allocation according to numa node */
579 	struct mutex            alloc_mutex;
580 	int                     numa_node;
581 
582 	struct mutex            pgdir_mutex;
583 	struct list_head        pgdir_list;
584 	/* end: alloc staff */
585 
586 	struct mlx5_adev       **adev;
587 	int			adev_idx;
588 	int			sw_vhca_id;
589 	struct mlx5_events      *events;
590 	struct mlx5_vhca_events *vhca_events;
591 
592 	struct mlx5_flow_steering *steering;
593 	struct mlx5_mpfs        *mpfs;
594 	struct mlx5_eswitch     *eswitch;
595 	struct mlx5_core_sriov	sriov;
596 	struct mlx5_lag		*lag;
597 	u32			flags;
598 	struct mlx5_devcom_dev	*devc;
599 	struct mlx5_devcom_comp_dev *hca_devcom_comp;
600 	struct mlx5_fw_reset	*fw_reset;
601 	struct mlx5_core_roce	roce;
602 	struct mlx5_fc_stats		*fc_stats;
603 	struct mlx5_rl_table            rl_table;
604 	struct mlx5_ft_pool		*ft_pool;
605 
606 	struct mlx5_bfreg_data		bfregs;
607 	struct mlx5_uars_page	       *uar;
608 #ifdef CONFIG_MLX5_SF
609 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
610 	struct mlx5_sf_dev_table *sf_dev_table;
611 	struct mlx5_core_dev *parent_mdev;
612 #endif
613 #ifdef CONFIG_MLX5_SF_MANAGER
614 	struct mlx5_sf_hw_table *sf_hw_table;
615 	struct mlx5_sf_table *sf_table;
616 #endif
617 	struct blocking_notifier_head lag_nh;
618 };
619 
620 enum mlx5_device_state {
621 	MLX5_DEVICE_STATE_UP = 1,
622 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
623 };
624 
625 enum mlx5_interface_state {
626 	MLX5_INTERFACE_STATE_UP = BIT(0),
627 	MLX5_BREAK_FW_WAIT = BIT(1),
628 };
629 
630 enum mlx5_pci_status {
631 	MLX5_PCI_STATUS_DISABLED,
632 	MLX5_PCI_STATUS_ENABLED,
633 };
634 
635 enum mlx5_pagefault_type_flags {
636 	MLX5_PFAULT_REQUESTOR = 1 << 0,
637 	MLX5_PFAULT_WRITE     = 1 << 1,
638 	MLX5_PFAULT_RDMA      = 1 << 2,
639 };
640 
641 struct mlx5_td {
642 	/* protects tirs list changes while tirs refresh */
643 	struct mutex     list_lock;
644 	struct list_head tirs_list;
645 	u32              tdn;
646 };
647 
648 struct mlx5e_resources {
649 	struct mlx5e_hw_objs {
650 		u32                        pdn;
651 		struct mlx5_td             td;
652 		u32			   mkey;
653 		struct mlx5_sq_bfreg       bfreg;
654 #define MLX5_MAX_NUM_TC 8
655 		u32                        tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
656 		bool			   tisn_valid;
657 	} hw_objs;
658 	struct net_device *uplink_netdev;
659 	struct mutex uplink_netdev_lock;
660 	struct mlx5_crypto_dek_priv *dek_priv;
661 };
662 
663 enum mlx5_sw_icm_type {
664 	MLX5_SW_ICM_TYPE_STEERING,
665 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
666 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
667 	MLX5_SW_ICM_TYPE_SW_ENCAP,
668 };
669 
670 #define MLX5_MAX_RESERVED_GIDS 8
671 
672 struct mlx5_rsvd_gids {
673 	unsigned int start;
674 	unsigned int count;
675 	struct ida ida;
676 };
677 
678 #define MAX_PIN_NUM	8
679 struct mlx5_pps {
680 	u8                         pin_caps[MAX_PIN_NUM];
681 	struct work_struct         out_work;
682 	u64                        start[MAX_PIN_NUM];
683 	u8                         enabled;
684 	u64                        min_npps_period;
685 	u64                        min_out_pulse_duration_ns;
686 };
687 
688 struct mlx5_timer {
689 	struct cyclecounter        cycles;
690 	struct timecounter         tc;
691 	u32                        nominal_c_mult;
692 	unsigned long              overflow_period;
693 	struct delayed_work        overflow_work;
694 };
695 
696 struct mlx5_clock {
697 	struct mlx5_nb             pps_nb;
698 	seqlock_t                  lock;
699 	struct hwtstamp_config     hwtstamp_config;
700 	struct ptp_clock          *ptp;
701 	struct ptp_clock_info      ptp_info;
702 	struct mlx5_pps            pps_info;
703 	struct mlx5_timer          timer;
704 };
705 
706 struct mlx5_dm;
707 struct mlx5_fw_tracer;
708 struct mlx5_vxlan;
709 struct mlx5_geneve;
710 struct mlx5_hv_vhca;
711 
712 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
713 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
714 
715 enum {
716 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
717 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
718 };
719 
720 enum {
721 	MKEY_CACHE_LAST_STD_ENTRY = 20,
722 	MLX5_IMR_KSM_CACHE_ENTRY,
723 	MAX_MKEY_CACHE_ENTRIES
724 };
725 
726 struct mlx5_profile {
727 	u64	mask;
728 	u8	log_max_qp;
729 	u8	num_cmd_caches;
730 	struct {
731 		int	size;
732 		int	limit;
733 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
734 };
735 
736 struct mlx5_hca_cap {
737 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
738 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
739 };
740 
741 enum mlx5_wc_state {
742 	MLX5_WC_STATE_UNINITIALIZED,
743 	MLX5_WC_STATE_UNSUPPORTED,
744 	MLX5_WC_STATE_SUPPORTED,
745 };
746 
747 struct mlx5_core_dev {
748 	struct device *device;
749 	enum mlx5_coredev_type coredev_type;
750 	struct pci_dev	       *pdev;
751 	/* sync pci state */
752 	struct mutex		pci_status_mutex;
753 	enum mlx5_pci_status	pci_status;
754 	u8			rev_id;
755 	char			board_id[MLX5_BOARD_ID_LEN];
756 	struct mlx5_cmd		cmd;
757 	struct {
758 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
759 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
760 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
761 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
762 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
763 		u8  embedded_cpu;
764 	} caps;
765 	struct mlx5_timeouts	*timeouts;
766 	u64			sys_image_guid;
767 	phys_addr_t		iseg_base;
768 	struct mlx5_init_seg __iomem *iseg;
769 	phys_addr_t             bar_addr;
770 	enum mlx5_device_state	state;
771 	/* sync interface state */
772 	struct mutex		intf_state_mutex;
773 	struct lock_class_key	lock_key;
774 	unsigned long		intf_state;
775 	struct mlx5_priv	priv;
776 	struct mlx5_profile	profile;
777 	u32			issi;
778 	struct mlx5e_resources  mlx5e_res;
779 	struct mlx5_dm          *dm;
780 	struct mlx5_vxlan       *vxlan;
781 	struct mlx5_geneve      *geneve;
782 	struct {
783 		struct mlx5_rsvd_gids	reserved_gids;
784 		u32			roce_en;
785 	} roce;
786 #ifdef CONFIG_MLX5_FPGA
787 	struct mlx5_fpga_device *fpga;
788 #endif
789 	struct mlx5_clock        clock;
790 	struct mlx5_ib_clock_info  *clock_info;
791 	struct mlx5_fw_tracer   *tracer;
792 	struct mlx5_rsc_dump    *rsc_dump;
793 	u32                      vsc_addr;
794 	struct mlx5_hv_vhca	*hv_vhca;
795 	struct mlx5_hwmon	*hwmon;
796 	u64			num_block_tc;
797 	u64			num_block_ipsec;
798 #ifdef CONFIG_MLX5_MACSEC
799 	struct mlx5_macsec_fs *macsec_fs;
800 	/* MACsec notifier chain to sync MACsec core and IB database */
801 	struct blocking_notifier_head macsec_nh;
802 #endif
803 	u64 num_ipsec_offloads;
804 	struct mlx5_sd          *sd;
805 	enum mlx5_wc_state wc_state;
806 	/* sync write combining state */
807 	struct mutex wc_state_lock;
808 };
809 
810 struct mlx5_db {
811 	__be32			*db;
812 	union {
813 		struct mlx5_db_pgdir		*pgdir;
814 		struct mlx5_ib_user_db_page	*user_page;
815 	}			u;
816 	dma_addr_t		dma;
817 	int			index;
818 };
819 
820 enum {
821 	MLX5_COMP_EQ_SIZE = 1024,
822 };
823 
824 enum {
825 	MLX5_PTYS_IB = 1 << 0,
826 	MLX5_PTYS_EN = 1 << 2,
827 };
828 
829 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
830 
831 enum {
832 	MLX5_CMD_ENT_STATE_PENDING_COMP,
833 };
834 
835 struct mlx5_cmd_work_ent {
836 	unsigned long		state;
837 	struct mlx5_cmd_msg    *in;
838 	struct mlx5_cmd_msg    *out;
839 	void		       *uout;
840 	int			uout_size;
841 	mlx5_cmd_cbk_t		callback;
842 	struct delayed_work	cb_timeout_work;
843 	void		       *context;
844 	int			idx;
845 	struct completion	handling;
846 	struct completion	slotted;
847 	struct completion	done;
848 	struct mlx5_cmd        *cmd;
849 	struct work_struct	work;
850 	struct mlx5_cmd_layout *lay;
851 	int			ret;
852 	int			page_queue;
853 	u8			status;
854 	u8			token;
855 	u64			ts1;
856 	u64			ts2;
857 	u16			op;
858 	bool			polling;
859 	/* Track the max comp handlers */
860 	refcount_t              refcnt;
861 };
862 
863 enum phy_port_state {
864 	MLX5_AAA_111
865 };
866 
867 struct mlx5_hca_vport_context {
868 	u32			field_select;
869 	bool			sm_virt_aware;
870 	bool			has_smi;
871 	bool			has_raw;
872 	enum port_state_policy	policy;
873 	enum phy_port_state	phys_state;
874 	enum ib_port_state	vport_state;
875 	u8			port_physical_state;
876 	u64			sys_image_guid;
877 	u64			port_guid;
878 	u64			node_guid;
879 	u32			cap_mask1;
880 	u32			cap_mask1_perm;
881 	u16			cap_mask2;
882 	u16			cap_mask2_perm;
883 	u16			lid;
884 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
885 	u8			lmc;
886 	u8			subnet_timeout;
887 	u16			sm_lid;
888 	u8			sm_sl;
889 	u16			qkey_violation_counter;
890 	u16			pkey_violation_counter;
891 	bool			grh_required;
892 	u8			num_plane;
893 };
894 
895 #define STRUCT_FIELD(header, field) \
896 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
897 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
898 
899 extern struct dentry *mlx5_debugfs_root;
900 
901 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
902 {
903 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
904 }
905 
906 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
907 {
908 	return ioread32be(&dev->iseg->fw_rev) >> 16;
909 }
910 
911 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
912 {
913 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
914 }
915 
916 static inline u32 mlx5_base_mkey(const u32 key)
917 {
918 	return key & 0xffffff00u;
919 }
920 
921 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
922 {
923 	return ((u32)1 << log_sz) << log_stride;
924 }
925 
926 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
927 					u8 log_stride, u8 log_sz,
928 					u16 strides_offset,
929 					struct mlx5_frag_buf_ctrl *fbc)
930 {
931 	fbc->frags      = frags;
932 	fbc->log_stride = log_stride;
933 	fbc->log_sz     = log_sz;
934 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
935 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
936 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
937 	fbc->strides_offset = strides_offset;
938 }
939 
940 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
941 				 u8 log_stride, u8 log_sz,
942 				 struct mlx5_frag_buf_ctrl *fbc)
943 {
944 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
945 }
946 
947 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
948 					  u32 ix)
949 {
950 	unsigned int frag;
951 
952 	ix  += fbc->strides_offset;
953 	frag = ix >> fbc->log_frag_strides;
954 
955 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
956 }
957 
958 static inline u32
959 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
960 {
961 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
962 
963 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
964 }
965 
966 enum {
967 	CMD_ALLOWED_OPCODE_ALL,
968 };
969 
970 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
971 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
972 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
973 
974 struct mlx5_async_ctx {
975 	struct mlx5_core_dev *dev;
976 	atomic_t num_inflight;
977 	struct completion inflight_done;
978 };
979 
980 struct mlx5_async_work;
981 
982 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
983 
984 struct mlx5_async_work {
985 	struct mlx5_async_ctx *ctx;
986 	mlx5_async_cbk_t user_callback;
987 	u16 opcode; /* cmd opcode */
988 	u16 op_mod; /* cmd op_mod */
989 	void *out; /* pointer to the cmd output buffer */
990 };
991 
992 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
993 			     struct mlx5_async_ctx *ctx);
994 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
995 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
996 		     void *out, int out_size, mlx5_async_cbk_t callback,
997 		     struct mlx5_async_work *work);
998 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
999 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1000 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1001 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1002 		  int out_size);
1003 
1004 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1005 	({                                                                     \
1006 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1007 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1008 	})
1009 
1010 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1011 	({                                                                     \
1012 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1013 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1014 	})
1015 
1016 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1017 			  void *out, int out_size);
1018 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1019 
1020 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1021 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1022 
1023 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1024 
1025 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1026 int mlx5_health_init(struct mlx5_core_dev *dev);
1027 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1028 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1029 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1030 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1031 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1032 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1033 			     struct mlx5_frag_buf *buf, int node);
1034 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1035 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1036 			  int inlen);
1037 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1038 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1039 			 int outlen);
1040 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1041 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1042 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1043 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1044 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1045 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1046 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1047 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1048 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1049 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1050 void mlx5_register_debugfs(void);
1051 void mlx5_unregister_debugfs(void);
1052 
1053 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1054 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1055 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1056 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1057 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1058 
1059 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1060 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1061 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1062 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1063 		    void *data_out, int size_out, u16 reg_id, int arg,
1064 		    int write, bool verbose);
1065 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1066 			 int size_in, void *data_out, int size_out,
1067 			 u16 reg_num, int arg, int write);
1068 
1069 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1070 		       int node);
1071 
1072 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1073 {
1074 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1075 }
1076 
1077 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1078 
1079 const char *mlx5_command_str(int command);
1080 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1081 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1082 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1083 			 int npsvs, u32 *sig_index);
1084 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1085 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1086 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1087 
1088 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1089 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1090 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1091 		     struct mlx5_rate_limit *rl);
1092 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1093 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1094 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1095 			 bool dedicated_entry, u16 *index);
1096 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1097 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1098 		       struct mlx5_rate_limit *rl_1);
1099 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1100 		     bool map_wc, bool fast_path);
1101 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1102 
1103 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1104 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1105 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1106 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1107 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1108 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1109 
1110 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1111 {
1112 	return mkey >> 8;
1113 }
1114 
1115 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1116 {
1117 	return mkey_idx << 8;
1118 }
1119 
1120 static inline u8 mlx5_mkey_variant(u32 mkey)
1121 {
1122 	return mkey & 0xff;
1123 }
1124 
1125 /* Async-atomic event notifier used by mlx5 core to forward FW
1126  * evetns received from event queue to mlx5 consumers.
1127  * Optimise event queue dipatching.
1128  */
1129 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1130 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131 
1132 /* Async-atomic event notifier used for forwarding
1133  * evetns from the event queue into the to mlx5 events dispatcher,
1134  * eswitch, clock and others.
1135  */
1136 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1137 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1138 
1139 /* Blocking event notifier used to forward SW events, used for slow path */
1140 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1141 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1143 				      void *data);
1144 
1145 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1146 
1147 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1148 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1149 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1150 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1151 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1155 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1156 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1157 			   struct net_device *slave);
1158 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1159 				 u64 *values,
1160 				 int num_counters,
1161 				 size_t *offsets);
1162 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1163 
1164 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1165 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1166 	     peer;								\
1167 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1168 
1169 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1170 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1171 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1172 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1173 			 u64 length, u32 log_alignment, u16 uid,
1174 			 phys_addr_t *addr, u32 *obj_id);
1175 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1176 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1177 
1178 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1179 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1180 
1181 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1182 					  int vf_id,
1183 					  struct notifier_block *nb);
1184 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1185 					     int vf_id,
1186 					     struct notifier_block *nb);
1187 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1188 			    struct ib_device *device,
1189 			    struct rdma_netdev_alloc_params *params);
1190 
1191 enum {
1192 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1193 };
1194 
1195 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1196 {
1197 	return dev->coredev_type == MLX5_COREDEV_PF;
1198 }
1199 
1200 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1201 {
1202 	return dev->coredev_type == MLX5_COREDEV_VF;
1203 }
1204 
1205 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1206 {
1207 	return dev->caps.embedded_cpu;
1208 }
1209 
1210 static inline bool
1211 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1212 {
1213 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1214 }
1215 
1216 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1217 {
1218 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1219 }
1220 
1221 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1222 {
1223 	return dev->priv.sriov.max_vfs;
1224 }
1225 
1226 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1227 {
1228 	/* LACP owner conditions:
1229 	 * 1) Function is physical.
1230 	 * 2) LAG is supported by FW.
1231 	 * 3) LAG is managed by driver (currently the only option).
1232 	 */
1233 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1234 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1235 		    MLX5_CAP_GEN(dev, lag_master);
1236 }
1237 
1238 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1239 {
1240 	return dev->priv.sriov.max_ec_vfs;
1241 }
1242 
1243 static inline int mlx5_get_gid_table_len(u16 param)
1244 {
1245 	if (param > 4) {
1246 		pr_warn("gid table length is zero\n");
1247 		return 0;
1248 	}
1249 
1250 	return 8 * (1 << param);
1251 }
1252 
1253 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1254 {
1255 	return !!(dev->priv.rl_table.max_size);
1256 }
1257 
1258 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1259 {
1260 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1261 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1262 }
1263 
1264 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1265 {
1266 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1267 }
1268 
1269 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1270 {
1271 	return mlx5_core_is_mp_slave(dev) ||
1272 	       mlx5_core_is_mp_master(dev);
1273 }
1274 
1275 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1276 {
1277 	if (!mlx5_core_mp_enabled(dev))
1278 		return 1;
1279 
1280 	return MLX5_CAP_GEN(dev, native_port_num);
1281 }
1282 
1283 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1284 {
1285 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1286 
1287 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1288 		return idx - 1;
1289 	else
1290 		return PCI_FUNC(dev->pdev->devfn);
1291 }
1292 
1293 enum {
1294 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1295 };
1296 
1297 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1298 
1299 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1300 {
1301 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1302 		return MLX5_CAP_GEN(dev, roce);
1303 
1304 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1305 	 * in order to support RoCE enable/disable feature
1306 	 */
1307 	return mlx5_is_roce_on(dev);
1308 }
1309 
1310 #ifdef CONFIG_MLX5_MACSEC
1311 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1312 {
1313 	if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1314 	    MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1315 		return false;
1316 
1317 	if (!MLX5_CAP_GEN(mdev, log_max_dek))
1318 		return false;
1319 
1320 	if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1321 		return false;
1322 
1323 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1324 	    !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1325 		return false;
1326 
1327 	if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1328 	    !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1329 		return false;
1330 
1331 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1332 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1333 		return false;
1334 
1335 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1336 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1337 		return false;
1338 
1339 	return true;
1340 }
1341 
1342 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1343 
1344 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1345 {
1346 	if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1347 	     NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1348 	     !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1349 	     !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1350 		return false;
1351 
1352 	return true;
1353 }
1354 #endif
1355 
1356 enum {
1357 	MLX5_OCTWORD = 16,
1358 };
1359 
1360 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1361 #endif /* MLX5_DRIVER_H */
1362