1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 51 #include <linux/mlx5/device.h> 52 #include <linux/mlx5/doorbell.h> 53 #include <linux/mlx5/eq.h> 54 #include <linux/timecounter.h> 55 #include <linux/ptp_clock_kernel.h> 56 57 enum { 58 MLX5_BOARD_ID_LEN = 64, 59 MLX5_MAX_NAME_LEN = 16, 60 }; 61 62 enum { 63 /* one minute for the sake of bringup. Generally, commands must always 64 * complete and we may need to increase this timeout value 65 */ 66 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 67 MLX5_CMD_WQ_MAX_NAME = 32, 68 }; 69 70 enum { 71 CMD_OWNER_SW = 0x0, 72 CMD_OWNER_HW = 0x1, 73 CMD_STATUS_SUCCESS = 0, 74 }; 75 76 enum mlx5_sqp_t { 77 MLX5_SQP_SMI = 0, 78 MLX5_SQP_GSI = 1, 79 MLX5_SQP_IEEE_1588 = 2, 80 MLX5_SQP_SNIFFER = 3, 81 MLX5_SQP_SYNC_UMR = 4, 82 }; 83 84 enum { 85 MLX5_MAX_PORTS = 2, 86 }; 87 88 enum { 89 MLX5_ATOMIC_MODE_OFFSET = 16, 90 MLX5_ATOMIC_MODE_IB_COMP = 1, 91 MLX5_ATOMIC_MODE_CX = 2, 92 MLX5_ATOMIC_MODE_8B = 3, 93 MLX5_ATOMIC_MODE_16B = 4, 94 MLX5_ATOMIC_MODE_32B = 5, 95 MLX5_ATOMIC_MODE_64B = 6, 96 MLX5_ATOMIC_MODE_128B = 7, 97 MLX5_ATOMIC_MODE_256B = 8, 98 }; 99 100 enum { 101 MLX5_REG_QPTS = 0x4002, 102 MLX5_REG_QETCR = 0x4005, 103 MLX5_REG_QTCT = 0x400a, 104 MLX5_REG_QPDPM = 0x4013, 105 MLX5_REG_QCAM = 0x4019, 106 MLX5_REG_DCBX_PARAM = 0x4020, 107 MLX5_REG_DCBX_APP = 0x4021, 108 MLX5_REG_FPGA_CAP = 0x4022, 109 MLX5_REG_FPGA_CTRL = 0x4023, 110 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 111 MLX5_REG_PCAP = 0x5001, 112 MLX5_REG_PMTU = 0x5003, 113 MLX5_REG_PTYS = 0x5004, 114 MLX5_REG_PAOS = 0x5006, 115 MLX5_REG_PFCC = 0x5007, 116 MLX5_REG_PPCNT = 0x5008, 117 MLX5_REG_PPTB = 0x500b, 118 MLX5_REG_PBMC = 0x500c, 119 MLX5_REG_PMAOS = 0x5012, 120 MLX5_REG_PUDE = 0x5009, 121 MLX5_REG_PMPE = 0x5010, 122 MLX5_REG_PELC = 0x500e, 123 MLX5_REG_PVLC = 0x500f, 124 MLX5_REG_PCMR = 0x5041, 125 MLX5_REG_PMLP = 0x5002, 126 MLX5_REG_PPLM = 0x5023, 127 MLX5_REG_PCAM = 0x507f, 128 MLX5_REG_NODE_DESC = 0x6001, 129 MLX5_REG_HOST_ENDIANNESS = 0x7004, 130 MLX5_REG_MCIA = 0x9014, 131 MLX5_REG_MLCR = 0x902b, 132 MLX5_REG_MTRC_CAP = 0x9040, 133 MLX5_REG_MTRC_CONF = 0x9041, 134 MLX5_REG_MTRC_STDB = 0x9042, 135 MLX5_REG_MTRC_CTRL = 0x9043, 136 MLX5_REG_MPCNT = 0x9051, 137 MLX5_REG_MTPPS = 0x9053, 138 MLX5_REG_MTPPSE = 0x9054, 139 MLX5_REG_MPEGC = 0x9056, 140 MLX5_REG_MCQI = 0x9061, 141 MLX5_REG_MCC = 0x9062, 142 MLX5_REG_MCDA = 0x9063, 143 MLX5_REG_MCAM = 0x907f, 144 }; 145 146 enum mlx5_qpts_trust_state { 147 MLX5_QPTS_TRUST_PCP = 1, 148 MLX5_QPTS_TRUST_DSCP = 2, 149 }; 150 151 enum mlx5_dcbx_oper_mode { 152 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 153 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 154 }; 155 156 enum { 157 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 158 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 159 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 160 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 161 }; 162 163 enum mlx5_page_fault_resume_flags { 164 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 165 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 166 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 167 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 168 }; 169 170 enum dbg_rsc_type { 171 MLX5_DBG_RSC_QP, 172 MLX5_DBG_RSC_EQ, 173 MLX5_DBG_RSC_CQ, 174 }; 175 176 enum port_state_policy { 177 MLX5_POLICY_DOWN = 0, 178 MLX5_POLICY_UP = 1, 179 MLX5_POLICY_FOLLOW = 2, 180 MLX5_POLICY_INVALID = 0xffffffff 181 }; 182 183 struct mlx5_field_desc { 184 struct dentry *dent; 185 int i; 186 }; 187 188 struct mlx5_rsc_debug { 189 struct mlx5_core_dev *dev; 190 void *object; 191 enum dbg_rsc_type type; 192 struct dentry *root; 193 struct mlx5_field_desc fields[0]; 194 }; 195 196 enum mlx5_dev_event { 197 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 198 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 199 }; 200 201 enum mlx5_port_status { 202 MLX5_PORT_UP = 1, 203 MLX5_PORT_DOWN = 2, 204 }; 205 206 struct mlx5_bfreg_info { 207 u32 *sys_pages; 208 int num_low_latency_bfregs; 209 unsigned int *count; 210 211 /* 212 * protect bfreg allocation data structs 213 */ 214 struct mutex lock; 215 u32 ver; 216 bool lib_uar_4k; 217 u32 num_sys_pages; 218 u32 num_static_sys_pages; 219 u32 total_num_bfregs; 220 u32 num_dyn_bfregs; 221 }; 222 223 struct mlx5_cmd_first { 224 __be32 data[4]; 225 }; 226 227 struct mlx5_cmd_msg { 228 struct list_head list; 229 struct cmd_msg_cache *parent; 230 u32 len; 231 struct mlx5_cmd_first first; 232 struct mlx5_cmd_mailbox *next; 233 }; 234 235 struct mlx5_cmd_debug { 236 struct dentry *dbg_root; 237 struct dentry *dbg_in; 238 struct dentry *dbg_out; 239 struct dentry *dbg_outlen; 240 struct dentry *dbg_status; 241 struct dentry *dbg_run; 242 void *in_msg; 243 void *out_msg; 244 u8 status; 245 u16 inlen; 246 u16 outlen; 247 }; 248 249 struct cmd_msg_cache { 250 /* protect block chain allocations 251 */ 252 spinlock_t lock; 253 struct list_head head; 254 unsigned int max_inbox_size; 255 unsigned int num_ent; 256 }; 257 258 enum { 259 MLX5_NUM_COMMAND_CACHES = 5, 260 }; 261 262 struct mlx5_cmd_stats { 263 u64 sum; 264 u64 n; 265 struct dentry *root; 266 struct dentry *avg; 267 struct dentry *count; 268 /* protect command average calculations */ 269 spinlock_t lock; 270 }; 271 272 struct mlx5_cmd { 273 struct mlx5_nb nb; 274 275 void *cmd_alloc_buf; 276 dma_addr_t alloc_dma; 277 int alloc_size; 278 void *cmd_buf; 279 dma_addr_t dma; 280 u16 cmdif_rev; 281 u8 log_sz; 282 u8 log_stride; 283 int max_reg_cmds; 284 int events; 285 u32 __iomem *vector; 286 287 /* protect command queue allocations 288 */ 289 spinlock_t alloc_lock; 290 291 /* protect token allocations 292 */ 293 spinlock_t token_lock; 294 u8 token; 295 unsigned long bitmask; 296 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 297 struct workqueue_struct *wq; 298 struct semaphore sem; 299 struct semaphore pages_sem; 300 int mode; 301 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 302 struct dma_pool *pool; 303 struct mlx5_cmd_debug dbg; 304 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 305 int checksum_disabled; 306 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 307 }; 308 309 struct mlx5_port_caps { 310 int gid_table_len; 311 int pkey_table_len; 312 u8 ext_port_cap; 313 bool has_smi; 314 }; 315 316 struct mlx5_cmd_mailbox { 317 void *buf; 318 dma_addr_t dma; 319 struct mlx5_cmd_mailbox *next; 320 }; 321 322 struct mlx5_buf_list { 323 void *buf; 324 dma_addr_t map; 325 }; 326 327 struct mlx5_frag_buf { 328 struct mlx5_buf_list *frags; 329 int npages; 330 int size; 331 u8 page_shift; 332 }; 333 334 struct mlx5_frag_buf_ctrl { 335 struct mlx5_buf_list *frags; 336 u32 sz_m1; 337 u16 frag_sz_m1; 338 u16 strides_offset; 339 u8 log_sz; 340 u8 log_stride; 341 u8 log_frag_strides; 342 }; 343 344 struct mlx5_core_psv { 345 u32 psv_idx; 346 struct psv_layout { 347 u32 pd; 348 u16 syndrome; 349 u16 reserved; 350 u16 bg; 351 u16 app_tag; 352 u32 ref_tag; 353 } psv; 354 }; 355 356 struct mlx5_core_sig_ctx { 357 struct mlx5_core_psv psv_memory; 358 struct mlx5_core_psv psv_wire; 359 struct ib_sig_err err_item; 360 bool sig_status_checked; 361 bool sig_err_exists; 362 u32 sigerr_count; 363 }; 364 365 enum { 366 MLX5_MKEY_MR = 1, 367 MLX5_MKEY_MW, 368 }; 369 370 struct mlx5_core_mkey { 371 u64 iova; 372 u64 size; 373 u32 key; 374 u32 pd; 375 u32 type; 376 }; 377 378 #define MLX5_24BIT_MASK ((1 << 24) - 1) 379 380 enum mlx5_res_type { 381 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 382 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 383 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 384 MLX5_RES_SRQ = 3, 385 MLX5_RES_XSRQ = 4, 386 MLX5_RES_XRQ = 5, 387 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 388 }; 389 390 struct mlx5_core_rsc_common { 391 enum mlx5_res_type res; 392 atomic_t refcount; 393 struct completion free; 394 }; 395 396 struct mlx5_uars_page { 397 void __iomem *map; 398 bool wc; 399 u32 index; 400 struct list_head list; 401 unsigned int bfregs; 402 unsigned long *reg_bitmap; /* for non fast path bf regs */ 403 unsigned long *fp_bitmap; 404 unsigned int reg_avail; 405 unsigned int fp_avail; 406 struct kref ref_count; 407 struct mlx5_core_dev *mdev; 408 }; 409 410 struct mlx5_bfreg_head { 411 /* protect blue flame registers allocations */ 412 struct mutex lock; 413 struct list_head list; 414 }; 415 416 struct mlx5_bfreg_data { 417 struct mlx5_bfreg_head reg_head; 418 struct mlx5_bfreg_head wc_head; 419 }; 420 421 struct mlx5_sq_bfreg { 422 void __iomem *map; 423 struct mlx5_uars_page *up; 424 bool wc; 425 u32 index; 426 unsigned int offset; 427 }; 428 429 struct mlx5_core_health { 430 struct health_buffer __iomem *health; 431 __be32 __iomem *health_counter; 432 struct timer_list timer; 433 u32 prev; 434 int miss_counter; 435 bool sick; 436 /* wq spinlock to synchronize draining */ 437 spinlock_t wq_lock; 438 struct workqueue_struct *wq; 439 unsigned long flags; 440 struct work_struct work; 441 struct delayed_work recover_work; 442 }; 443 444 struct mlx5_qp_table { 445 struct notifier_block nb; 446 447 /* protect radix tree 448 */ 449 spinlock_t lock; 450 struct radix_tree_root tree; 451 }; 452 453 struct mlx5_mkey_table { 454 /* protect radix tree 455 */ 456 rwlock_t lock; 457 struct radix_tree_root tree; 458 }; 459 460 struct mlx5_vf_context { 461 int enabled; 462 u64 port_guid; 463 u64 node_guid; 464 enum port_state_policy policy; 465 }; 466 467 struct mlx5_core_sriov { 468 struct mlx5_vf_context *vfs_ctx; 469 int num_vfs; 470 int enabled_vfs; 471 }; 472 473 struct mlx5_fc_stats { 474 spinlock_t counters_idr_lock; /* protects counters_idr */ 475 struct idr counters_idr; 476 struct list_head counters; 477 struct llist_head addlist; 478 struct llist_head dellist; 479 480 struct workqueue_struct *wq; 481 struct delayed_work work; 482 unsigned long next_query; 483 unsigned long sampling_interval; /* jiffies */ 484 }; 485 486 struct mlx5_events; 487 struct mlx5_mpfs; 488 struct mlx5_eswitch; 489 struct mlx5_lag; 490 struct mlx5_devcom; 491 struct mlx5_eq_table; 492 493 struct mlx5_rate_limit { 494 u32 rate; 495 u32 max_burst_sz; 496 u16 typical_pkt_sz; 497 }; 498 499 struct mlx5_rl_entry { 500 struct mlx5_rate_limit rl; 501 u16 index; 502 u16 refcount; 503 }; 504 505 struct mlx5_rl_table { 506 /* protect rate limit table */ 507 struct mutex rl_lock; 508 u16 max_size; 509 u32 max_rate; 510 u32 min_rate; 511 struct mlx5_rl_entry *rl_entry; 512 }; 513 514 struct mlx5_priv { 515 char name[MLX5_MAX_NAME_LEN]; 516 struct mlx5_eq_table *eq_table; 517 518 /* pages stuff */ 519 struct mlx5_nb pg_nb; 520 struct workqueue_struct *pg_wq; 521 struct rb_root page_root; 522 int fw_pages; 523 atomic_t reg_pages; 524 struct list_head free_list; 525 int vfs_pages; 526 int peer_pf_pages; 527 528 struct mlx5_core_health health; 529 530 /* start: qp staff */ 531 struct mlx5_qp_table qp_table; 532 struct dentry *qp_debugfs; 533 struct dentry *eq_debugfs; 534 struct dentry *cq_debugfs; 535 struct dentry *cmdif_debugfs; 536 /* end: qp staff */ 537 538 /* start: mkey staff */ 539 struct mlx5_mkey_table mkey_table; 540 /* end: mkey staff */ 541 542 /* start: alloc staff */ 543 /* protect buffer alocation according to numa node */ 544 struct mutex alloc_mutex; 545 int numa_node; 546 547 struct mutex pgdir_mutex; 548 struct list_head pgdir_list; 549 /* end: alloc staff */ 550 struct dentry *dbg_root; 551 552 /* protect mkey key part */ 553 spinlock_t mkey_lock; 554 u8 mkey_key; 555 556 struct list_head dev_list; 557 struct list_head ctx_list; 558 spinlock_t ctx_lock; 559 struct mlx5_events *events; 560 561 struct mlx5_flow_steering *steering; 562 struct mlx5_mpfs *mpfs; 563 struct mlx5_eswitch *eswitch; 564 struct mlx5_core_sriov sriov; 565 struct mlx5_lag *lag; 566 struct mlx5_devcom *devcom; 567 unsigned long pci_dev_data; 568 struct mlx5_fc_stats fc_stats; 569 struct mlx5_rl_table rl_table; 570 571 struct mlx5_bfreg_data bfregs; 572 struct mlx5_uars_page *uar; 573 }; 574 575 enum mlx5_device_state { 576 MLX5_DEVICE_STATE_UP, 577 MLX5_DEVICE_STATE_INTERNAL_ERROR, 578 }; 579 580 enum mlx5_interface_state { 581 MLX5_INTERFACE_STATE_UP = BIT(0), 582 }; 583 584 enum mlx5_pci_status { 585 MLX5_PCI_STATUS_DISABLED, 586 MLX5_PCI_STATUS_ENABLED, 587 }; 588 589 enum mlx5_pagefault_type_flags { 590 MLX5_PFAULT_REQUESTOR = 1 << 0, 591 MLX5_PFAULT_WRITE = 1 << 1, 592 MLX5_PFAULT_RDMA = 1 << 2, 593 }; 594 595 struct mlx5_td { 596 struct list_head tirs_list; 597 u32 tdn; 598 }; 599 600 struct mlx5e_resources { 601 u32 pdn; 602 struct mlx5_td td; 603 struct mlx5_core_mkey mkey; 604 struct mlx5_sq_bfreg bfreg; 605 }; 606 607 #define MLX5_MAX_RESERVED_GIDS 8 608 609 struct mlx5_rsvd_gids { 610 unsigned int start; 611 unsigned int count; 612 struct ida ida; 613 }; 614 615 #define MAX_PIN_NUM 8 616 struct mlx5_pps { 617 u8 pin_caps[MAX_PIN_NUM]; 618 struct work_struct out_work; 619 u64 start[MAX_PIN_NUM]; 620 u8 enabled; 621 }; 622 623 struct mlx5_clock { 624 struct mlx5_core_dev *mdev; 625 struct mlx5_nb pps_nb; 626 seqlock_t lock; 627 struct cyclecounter cycles; 628 struct timecounter tc; 629 struct hwtstamp_config hwtstamp_config; 630 u32 nominal_c_mult; 631 unsigned long overflow_period; 632 struct delayed_work overflow_work; 633 struct ptp_clock *ptp; 634 struct ptp_clock_info ptp_info; 635 struct mlx5_pps pps_info; 636 }; 637 638 struct mlx5_fw_tracer; 639 struct mlx5_vxlan; 640 641 struct mlx5_core_dev { 642 struct pci_dev *pdev; 643 /* sync pci state */ 644 struct mutex pci_status_mutex; 645 enum mlx5_pci_status pci_status; 646 u8 rev_id; 647 char board_id[MLX5_BOARD_ID_LEN]; 648 struct mlx5_cmd cmd; 649 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 650 struct { 651 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 652 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 653 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 654 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 655 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 656 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 657 u8 embedded_cpu; 658 } caps; 659 u64 sys_image_guid; 660 phys_addr_t iseg_base; 661 struct mlx5_init_seg __iomem *iseg; 662 enum mlx5_device_state state; 663 /* sync interface state */ 664 struct mutex intf_state_mutex; 665 unsigned long intf_state; 666 struct mlx5_priv priv; 667 struct mlx5_profile *profile; 668 atomic_t num_qps; 669 u32 issi; 670 struct mlx5e_resources mlx5e_res; 671 struct mlx5_vxlan *vxlan; 672 struct { 673 struct mlx5_rsvd_gids reserved_gids; 674 u32 roce_en; 675 } roce; 676 #ifdef CONFIG_MLX5_FPGA 677 struct mlx5_fpga_device *fpga; 678 #endif 679 struct mlx5_clock clock; 680 struct mlx5_ib_clock_info *clock_info; 681 struct page *clock_info_page; 682 struct mlx5_fw_tracer *tracer; 683 }; 684 685 struct mlx5_db { 686 __be32 *db; 687 union { 688 struct mlx5_db_pgdir *pgdir; 689 struct mlx5_ib_user_db_page *user_page; 690 } u; 691 dma_addr_t dma; 692 int index; 693 }; 694 695 enum { 696 MLX5_COMP_EQ_SIZE = 1024, 697 }; 698 699 enum { 700 MLX5_PTYS_IB = 1 << 0, 701 MLX5_PTYS_EN = 1 << 2, 702 }; 703 704 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 705 706 enum { 707 MLX5_CMD_ENT_STATE_PENDING_COMP, 708 }; 709 710 struct mlx5_cmd_work_ent { 711 unsigned long state; 712 struct mlx5_cmd_msg *in; 713 struct mlx5_cmd_msg *out; 714 void *uout; 715 int uout_size; 716 mlx5_cmd_cbk_t callback; 717 struct delayed_work cb_timeout_work; 718 void *context; 719 int idx; 720 struct completion done; 721 struct mlx5_cmd *cmd; 722 struct work_struct work; 723 struct mlx5_cmd_layout *lay; 724 int ret; 725 int page_queue; 726 u8 status; 727 u8 token; 728 u64 ts1; 729 u64 ts2; 730 u16 op; 731 bool polling; 732 }; 733 734 struct mlx5_pas { 735 u64 pa; 736 u8 log_sz; 737 }; 738 739 enum phy_port_state { 740 MLX5_AAA_111 741 }; 742 743 struct mlx5_hca_vport_context { 744 u32 field_select; 745 bool sm_virt_aware; 746 bool has_smi; 747 bool has_raw; 748 enum port_state_policy policy; 749 enum phy_port_state phys_state; 750 enum ib_port_state vport_state; 751 u8 port_physical_state; 752 u64 sys_image_guid; 753 u64 port_guid; 754 u64 node_guid; 755 u32 cap_mask1; 756 u32 cap_mask1_perm; 757 u16 cap_mask2; 758 u16 cap_mask2_perm; 759 u16 lid; 760 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 761 u8 lmc; 762 u8 subnet_timeout; 763 u16 sm_lid; 764 u8 sm_sl; 765 u16 qkey_violation_counter; 766 u16 pkey_violation_counter; 767 bool grh_required; 768 }; 769 770 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 771 { 772 return buf->frags->buf + offset; 773 } 774 775 #define STRUCT_FIELD(header, field) \ 776 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 777 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 778 779 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 780 { 781 return pci_get_drvdata(pdev); 782 } 783 784 extern struct dentry *mlx5_debugfs_root; 785 786 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 787 { 788 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 789 } 790 791 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 792 { 793 return ioread32be(&dev->iseg->fw_rev) >> 16; 794 } 795 796 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 797 { 798 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 799 } 800 801 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 802 { 803 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 804 } 805 806 static inline u32 mlx5_base_mkey(const u32 key) 807 { 808 return key & 0xffffff00u; 809 } 810 811 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 812 u8 log_stride, u8 log_sz, 813 u16 strides_offset, 814 struct mlx5_frag_buf_ctrl *fbc) 815 { 816 fbc->frags = frags; 817 fbc->log_stride = log_stride; 818 fbc->log_sz = log_sz; 819 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 820 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 821 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 822 fbc->strides_offset = strides_offset; 823 } 824 825 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 826 u8 log_stride, u8 log_sz, 827 struct mlx5_frag_buf_ctrl *fbc) 828 { 829 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 830 } 831 832 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 833 u32 ix) 834 { 835 unsigned int frag; 836 837 ix += fbc->strides_offset; 838 frag = ix >> fbc->log_frag_strides; 839 840 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 841 } 842 843 static inline u32 844 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 845 { 846 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 847 848 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 849 } 850 851 int mlx5_cmd_init(struct mlx5_core_dev *dev); 852 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 853 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 854 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 855 856 struct mlx5_async_ctx { 857 struct mlx5_core_dev *dev; 858 atomic_t num_inflight; 859 struct wait_queue_head wait; 860 }; 861 862 struct mlx5_async_work; 863 864 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 865 866 struct mlx5_async_work { 867 struct mlx5_async_ctx *ctx; 868 mlx5_async_cbk_t user_callback; 869 }; 870 871 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 872 struct mlx5_async_ctx *ctx); 873 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 874 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 875 void *out, int out_size, mlx5_async_cbk_t callback, 876 struct mlx5_async_work *work); 877 878 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 879 int out_size); 880 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 881 void *out, int out_size); 882 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 883 884 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 885 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 886 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 887 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 888 int mlx5_health_init(struct mlx5_core_dev *dev); 889 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 890 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 891 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 892 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 893 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 894 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 895 struct mlx5_frag_buf *buf, int node); 896 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 897 int size, struct mlx5_frag_buf *buf); 898 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 899 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 900 struct mlx5_frag_buf *buf, int node); 901 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 902 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 903 gfp_t flags, int npages); 904 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 905 struct mlx5_cmd_mailbox *head); 906 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 907 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 908 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 909 struct mlx5_core_mkey *mkey, 910 struct mlx5_async_ctx *async_ctx, u32 *in, 911 int inlen, u32 *out, int outlen, 912 mlx5_async_cbk_t callback, 913 struct mlx5_async_work *context); 914 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 915 struct mlx5_core_mkey *mkey, 916 u32 *in, int inlen); 917 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 918 struct mlx5_core_mkey *mkey); 919 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 920 u32 *out, int outlen); 921 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 922 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 923 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 924 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 925 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 926 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 927 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 928 s32 npages, bool ec_function); 929 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 930 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 931 void mlx5_register_debugfs(void); 932 void mlx5_unregister_debugfs(void); 933 934 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 935 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 936 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 937 unsigned int *irqn); 938 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 939 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 940 941 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 942 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 943 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 944 int size_in, void *data_out, int size_out, 945 u16 reg_num, int arg, int write); 946 947 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 948 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 949 int node); 950 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 951 952 const char *mlx5_command_str(int command); 953 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 954 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 955 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 956 int npsvs, u32 *sig_index); 957 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 958 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 959 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 960 struct mlx5_odp_caps *odp_caps); 961 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 962 u8 port_num, void *out, size_t sz); 963 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 964 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 965 u32 wq_num, u8 type, int error); 966 #endif 967 968 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 969 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 970 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 971 struct mlx5_rate_limit *rl); 972 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 973 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 974 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 975 struct mlx5_rate_limit *rl_1); 976 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 977 bool map_wc, bool fast_path); 978 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 979 980 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 981 struct cpumask * 982 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 983 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 984 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 985 u8 roce_version, u8 roce_l3_type, const u8 *gid, 986 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 987 988 static inline int fw_initializing(struct mlx5_core_dev *dev) 989 { 990 return ioread32be(&dev->iseg->initializing) >> 31; 991 } 992 993 static inline u32 mlx5_mkey_to_idx(u32 mkey) 994 { 995 return mkey >> 8; 996 } 997 998 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 999 { 1000 return mkey_idx << 8; 1001 } 1002 1003 static inline u8 mlx5_mkey_variant(u32 mkey) 1004 { 1005 return mkey & 0xff; 1006 } 1007 1008 enum { 1009 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1010 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1011 }; 1012 1013 enum { 1014 MR_CACHE_LAST_STD_ENTRY = 20, 1015 MLX5_IMR_MTT_CACHE_ENTRY, 1016 MLX5_IMR_KSM_CACHE_ENTRY, 1017 MAX_MR_CACHE_ENTRIES 1018 }; 1019 1020 enum { 1021 MLX5_INTERFACE_PROTOCOL_IB = 0, 1022 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1023 }; 1024 1025 struct mlx5_interface { 1026 void * (*add)(struct mlx5_core_dev *dev); 1027 void (*remove)(struct mlx5_core_dev *dev, void *context); 1028 int (*attach)(struct mlx5_core_dev *dev, void *context); 1029 void (*detach)(struct mlx5_core_dev *dev, void *context); 1030 int protocol; 1031 struct list_head list; 1032 }; 1033 1034 int mlx5_register_interface(struct mlx5_interface *intf); 1035 void mlx5_unregister_interface(struct mlx5_interface *intf); 1036 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1037 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1038 1039 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1040 1041 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1042 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1043 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1044 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1045 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1046 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1047 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1048 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1049 u64 *values, 1050 int num_counters, 1051 size_t *offsets); 1052 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1053 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1054 1055 #ifdef CONFIG_MLX5_CORE_IPOIB 1056 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1057 struct ib_device *ibdev, 1058 const char *name, 1059 void (*setup)(struct net_device *)); 1060 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1061 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1062 struct ib_device *device, 1063 struct rdma_netdev_alloc_params *params); 1064 1065 struct mlx5_profile { 1066 u64 mask; 1067 u8 log_max_qp; 1068 struct { 1069 int size; 1070 int limit; 1071 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1072 }; 1073 1074 enum { 1075 MLX5_PCI_DEV_IS_VF = 1 << 0, 1076 }; 1077 1078 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1079 { 1080 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1081 } 1082 1083 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1084 { 1085 return dev->caps.embedded_cpu; 1086 } 1087 1088 static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev) 1089 { 1090 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1091 } 1092 1093 static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev) 1094 { 1095 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1096 } 1097 1098 #define MLX5_HOST_PF_MAX_VFS (127u) 1099 static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev) 1100 { 1101 if (mlx5_core_is_ecpf_esw_manager(dev)) 1102 return MLX5_HOST_PF_MAX_VFS; 1103 else 1104 return pci_sriov_get_totalvfs(dev->pdev); 1105 } 1106 1107 static inline int mlx5_get_gid_table_len(u16 param) 1108 { 1109 if (param > 4) { 1110 pr_warn("gid table length is zero\n"); 1111 return 0; 1112 } 1113 1114 return 8 * (1 << param); 1115 } 1116 1117 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1118 { 1119 return !!(dev->priv.rl_table.max_size); 1120 } 1121 1122 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1123 { 1124 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1125 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1126 } 1127 1128 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1129 { 1130 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1131 } 1132 1133 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1134 { 1135 return mlx5_core_is_mp_slave(dev) || 1136 mlx5_core_is_mp_master(dev); 1137 } 1138 1139 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1140 { 1141 if (!mlx5_core_mp_enabled(dev)) 1142 return 1; 1143 1144 return MLX5_CAP_GEN(dev, native_port_num); 1145 } 1146 1147 enum { 1148 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1149 }; 1150 1151 #endif /* MLX5_DRIVER_H */ 1152