xref: /linux-6.15/include/linux/mlx5/driver.h (revision bbaf1ff0) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53 
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <linux/ptp_clock_kernel.h>
59 #include <net/devlink.h>
60 
61 #define MLX5_ADEV_NAME "mlx5_core"
62 
63 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
64 
65 enum {
66 	MLX5_BOARD_ID_LEN = 64,
67 };
68 
69 enum {
70 	MLX5_CMD_WQ_MAX_NAME	= 32,
71 };
72 
73 enum {
74 	CMD_OWNER_SW		= 0x0,
75 	CMD_OWNER_HW		= 0x1,
76 	CMD_STATUS_SUCCESS	= 0,
77 };
78 
79 enum mlx5_sqp_t {
80 	MLX5_SQP_SMI		= 0,
81 	MLX5_SQP_GSI		= 1,
82 	MLX5_SQP_IEEE_1588	= 2,
83 	MLX5_SQP_SNIFFER	= 3,
84 	MLX5_SQP_SYNC_UMR	= 4,
85 };
86 
87 enum {
88 	MLX5_MAX_PORTS	= 4,
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFFSET = 16,
93 	MLX5_ATOMIC_MODE_IB_COMP = 1,
94 	MLX5_ATOMIC_MODE_CX = 2,
95 	MLX5_ATOMIC_MODE_8B = 3,
96 	MLX5_ATOMIC_MODE_16B = 4,
97 	MLX5_ATOMIC_MODE_32B = 5,
98 	MLX5_ATOMIC_MODE_64B = 6,
99 	MLX5_ATOMIC_MODE_128B = 7,
100 	MLX5_ATOMIC_MODE_256B = 8,
101 };
102 
103 enum {
104 	MLX5_REG_SBPR            = 0xb001,
105 	MLX5_REG_SBCM            = 0xb002,
106 	MLX5_REG_QPTS            = 0x4002,
107 	MLX5_REG_QETCR		 = 0x4005,
108 	MLX5_REG_QTCT		 = 0x400a,
109 	MLX5_REG_QPDPM           = 0x4013,
110 	MLX5_REG_QCAM            = 0x4019,
111 	MLX5_REG_DCBX_PARAM      = 0x4020,
112 	MLX5_REG_DCBX_APP        = 0x4021,
113 	MLX5_REG_FPGA_CAP	 = 0x4022,
114 	MLX5_REG_FPGA_CTRL	 = 0x4023,
115 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 	MLX5_REG_CORE_DUMP	 = 0x402e,
117 	MLX5_REG_PCAP		 = 0x5001,
118 	MLX5_REG_PMTU		 = 0x5003,
119 	MLX5_REG_PTYS		 = 0x5004,
120 	MLX5_REG_PAOS		 = 0x5006,
121 	MLX5_REG_PFCC            = 0x5007,
122 	MLX5_REG_PPCNT		 = 0x5008,
123 	MLX5_REG_PPTB            = 0x500b,
124 	MLX5_REG_PBMC            = 0x500c,
125 	MLX5_REG_PMAOS		 = 0x5012,
126 	MLX5_REG_PUDE		 = 0x5009,
127 	MLX5_REG_PMPE		 = 0x5010,
128 	MLX5_REG_PELC		 = 0x500e,
129 	MLX5_REG_PVLC		 = 0x500f,
130 	MLX5_REG_PCMR		 = 0x5041,
131 	MLX5_REG_PDDR		 = 0x5031,
132 	MLX5_REG_PMLP		 = 0x5002,
133 	MLX5_REG_PPLM		 = 0x5023,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MTMP		 = 0x900A,
138 	MLX5_REG_MCIA		 = 0x9014,
139 	MLX5_REG_MFRL		 = 0x9028,
140 	MLX5_REG_MLCR		 = 0x902b,
141 	MLX5_REG_MRTC		 = 0x902d,
142 	MLX5_REG_MTRC_CAP	 = 0x9040,
143 	MLX5_REG_MTRC_CONF	 = 0x9041,
144 	MLX5_REG_MTRC_STDB	 = 0x9042,
145 	MLX5_REG_MTRC_CTRL	 = 0x9043,
146 	MLX5_REG_MPEIN		 = 0x9050,
147 	MLX5_REG_MPCNT		 = 0x9051,
148 	MLX5_REG_MTPPS		 = 0x9053,
149 	MLX5_REG_MTPPSE		 = 0x9054,
150 	MLX5_REG_MTUTC		 = 0x9055,
151 	MLX5_REG_MPEGC		 = 0x9056,
152 	MLX5_REG_MCQS		 = 0x9060,
153 	MLX5_REG_MCQI		 = 0x9061,
154 	MLX5_REG_MCC		 = 0x9062,
155 	MLX5_REG_MCDA		 = 0x9063,
156 	MLX5_REG_MCAM		 = 0x907f,
157 	MLX5_REG_MIRC		 = 0x9162,
158 	MLX5_REG_SBCAM		 = 0xB01F,
159 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
160 	MLX5_REG_DTOR            = 0xC00E,
161 };
162 
163 enum mlx5_qpts_trust_state {
164 	MLX5_QPTS_TRUST_PCP  = 1,
165 	MLX5_QPTS_TRUST_DSCP = 2,
166 };
167 
168 enum mlx5_dcbx_oper_mode {
169 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
170 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
171 };
172 
173 enum {
174 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
175 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
176 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
177 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
178 };
179 
180 enum mlx5_page_fault_resume_flags {
181 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
182 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
183 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
184 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
185 };
186 
187 enum dbg_rsc_type {
188 	MLX5_DBG_RSC_QP,
189 	MLX5_DBG_RSC_EQ,
190 	MLX5_DBG_RSC_CQ,
191 };
192 
193 enum port_state_policy {
194 	MLX5_POLICY_DOWN	= 0,
195 	MLX5_POLICY_UP		= 1,
196 	MLX5_POLICY_FOLLOW	= 2,
197 	MLX5_POLICY_INVALID	= 0xffffffff
198 };
199 
200 enum mlx5_coredev_type {
201 	MLX5_COREDEV_PF,
202 	MLX5_COREDEV_VF,
203 	MLX5_COREDEV_SF,
204 };
205 
206 struct mlx5_field_desc {
207 	int			i;
208 };
209 
210 struct mlx5_rsc_debug {
211 	struct mlx5_core_dev   *dev;
212 	void		       *object;
213 	enum dbg_rsc_type	type;
214 	struct dentry	       *root;
215 	struct mlx5_field_desc	fields[];
216 };
217 
218 enum mlx5_dev_event {
219 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
220 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
221 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
222 };
223 
224 enum mlx5_port_status {
225 	MLX5_PORT_UP        = 1,
226 	MLX5_PORT_DOWN      = 2,
227 };
228 
229 enum mlx5_cmdif_state {
230 	MLX5_CMDIF_STATE_UNINITIALIZED,
231 	MLX5_CMDIF_STATE_UP,
232 	MLX5_CMDIF_STATE_DOWN,
233 };
234 
235 struct mlx5_cmd_first {
236 	__be32		data[4];
237 };
238 
239 struct mlx5_cmd_msg {
240 	struct list_head		list;
241 	struct cmd_msg_cache	       *parent;
242 	u32				len;
243 	struct mlx5_cmd_first		first;
244 	struct mlx5_cmd_mailbox	       *next;
245 };
246 
247 struct mlx5_cmd_debug {
248 	struct dentry	       *dbg_root;
249 	void		       *in_msg;
250 	void		       *out_msg;
251 	u8			status;
252 	u16			inlen;
253 	u16			outlen;
254 };
255 
256 struct cmd_msg_cache {
257 	/* protect block chain allocations
258 	 */
259 	spinlock_t		lock;
260 	struct list_head	head;
261 	unsigned int		max_inbox_size;
262 	unsigned int		num_ent;
263 };
264 
265 enum {
266 	MLX5_NUM_COMMAND_CACHES = 5,
267 };
268 
269 struct mlx5_cmd_stats {
270 	u64		sum;
271 	u64		n;
272 	/* number of times command failed */
273 	u64		failed;
274 	/* number of times command failed on bad status returned by FW */
275 	u64		failed_mbox_status;
276 	/* last command failed returned errno */
277 	u32		last_failed_errno;
278 	/* last bad status returned by FW */
279 	u8		last_failed_mbox_status;
280 	/* last command failed syndrome returned by FW */
281 	u32		last_failed_syndrome;
282 	struct dentry  *root;
283 	/* protect command average calculations */
284 	spinlock_t	lock;
285 };
286 
287 struct mlx5_cmd {
288 	struct mlx5_nb    nb;
289 
290 	enum mlx5_cmdif_state	state;
291 	void	       *cmd_alloc_buf;
292 	dma_addr_t	alloc_dma;
293 	int		alloc_size;
294 	void	       *cmd_buf;
295 	dma_addr_t	dma;
296 	u16		cmdif_rev;
297 	u8		log_sz;
298 	u8		log_stride;
299 	int		max_reg_cmds;
300 	int		events;
301 	u32 __iomem    *vector;
302 
303 	/* protect command queue allocations
304 	 */
305 	spinlock_t	alloc_lock;
306 
307 	/* protect token allocations
308 	 */
309 	spinlock_t	token_lock;
310 	u8		token;
311 	unsigned long	bitmask;
312 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
313 	struct workqueue_struct *wq;
314 	struct semaphore sem;
315 	struct semaphore pages_sem;
316 	struct semaphore throttle_sem;
317 	int	mode;
318 	u16     allowed_opcode;
319 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
320 	struct dma_pool *pool;
321 	struct mlx5_cmd_debug dbg;
322 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
323 	int checksum_disabled;
324 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
325 };
326 
327 struct mlx5_cmd_mailbox {
328 	void	       *buf;
329 	dma_addr_t	dma;
330 	struct mlx5_cmd_mailbox *next;
331 };
332 
333 struct mlx5_buf_list {
334 	void		       *buf;
335 	dma_addr_t		map;
336 };
337 
338 struct mlx5_frag_buf {
339 	struct mlx5_buf_list	*frags;
340 	int			npages;
341 	int			size;
342 	u8			page_shift;
343 };
344 
345 struct mlx5_frag_buf_ctrl {
346 	struct mlx5_buf_list   *frags;
347 	u32			sz_m1;
348 	u16			frag_sz_m1;
349 	u16			strides_offset;
350 	u8			log_sz;
351 	u8			log_stride;
352 	u8			log_frag_strides;
353 };
354 
355 struct mlx5_core_psv {
356 	u32	psv_idx;
357 	struct psv_layout {
358 		u32	pd;
359 		u16	syndrome;
360 		u16	reserved;
361 		u16	bg;
362 		u16	app_tag;
363 		u32	ref_tag;
364 	} psv;
365 };
366 
367 struct mlx5_core_sig_ctx {
368 	struct mlx5_core_psv	psv_memory;
369 	struct mlx5_core_psv	psv_wire;
370 	struct ib_sig_err       err_item;
371 	bool			sig_status_checked;
372 	bool			sig_err_exists;
373 	u32			sigerr_count;
374 };
375 
376 #define MLX5_24BIT_MASK		((1 << 24) - 1)
377 
378 enum mlx5_res_type {
379 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
380 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
381 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
382 	MLX5_RES_SRQ	= 3,
383 	MLX5_RES_XSRQ	= 4,
384 	MLX5_RES_XRQ	= 5,
385 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
386 };
387 
388 struct mlx5_core_rsc_common {
389 	enum mlx5_res_type	res;
390 	refcount_t		refcount;
391 	struct completion	free;
392 };
393 
394 struct mlx5_uars_page {
395 	void __iomem	       *map;
396 	bool			wc;
397 	u32			index;
398 	struct list_head	list;
399 	unsigned int		bfregs;
400 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
401 	unsigned long	       *fp_bitmap;
402 	unsigned int		reg_avail;
403 	unsigned int		fp_avail;
404 	struct kref		ref_count;
405 	struct mlx5_core_dev   *mdev;
406 };
407 
408 struct mlx5_bfreg_head {
409 	/* protect blue flame registers allocations */
410 	struct mutex		lock;
411 	struct list_head	list;
412 };
413 
414 struct mlx5_bfreg_data {
415 	struct mlx5_bfreg_head	reg_head;
416 	struct mlx5_bfreg_head	wc_head;
417 };
418 
419 struct mlx5_sq_bfreg {
420 	void __iomem	       *map;
421 	struct mlx5_uars_page  *up;
422 	bool			wc;
423 	u32			index;
424 	unsigned int		offset;
425 };
426 
427 struct mlx5_core_health {
428 	struct health_buffer __iomem   *health;
429 	__be32 __iomem		       *health_counter;
430 	struct timer_list		timer;
431 	u32				prev;
432 	int				miss_counter;
433 	u8				synd;
434 	u32				fatal_error;
435 	u32				crdump_size;
436 	struct workqueue_struct	       *wq;
437 	unsigned long			flags;
438 	struct work_struct		fatal_report_work;
439 	struct work_struct		report_work;
440 	struct devlink_health_reporter *fw_reporter;
441 	struct devlink_health_reporter *fw_fatal_reporter;
442 	struct devlink_health_reporter *vnic_reporter;
443 	struct delayed_work		update_fw_log_ts_work;
444 };
445 
446 struct mlx5_qp_table {
447 	struct notifier_block   nb;
448 
449 	/* protect radix tree
450 	 */
451 	spinlock_t		lock;
452 	struct radix_tree_root	tree;
453 };
454 
455 enum {
456 	MLX5_PF_NOTIFY_DISABLE_VF,
457 	MLX5_PF_NOTIFY_ENABLE_VF,
458 };
459 
460 struct mlx5_vf_context {
461 	int	enabled;
462 	u64	port_guid;
463 	u64	node_guid;
464 	/* Valid bits are used to validate administrative guid only.
465 	 * Enabled after ndo_set_vf_guid
466 	 */
467 	u8	port_guid_valid:1;
468 	u8	node_guid_valid:1;
469 	enum port_state_policy	policy;
470 	struct blocking_notifier_head notifier;
471 };
472 
473 struct mlx5_core_sriov {
474 	struct mlx5_vf_context	*vfs_ctx;
475 	int			num_vfs;
476 	u16			max_vfs;
477 	u16			max_ec_vfs;
478 };
479 
480 struct mlx5_fc_pool {
481 	struct mlx5_core_dev *dev;
482 	struct mutex pool_lock; /* protects pool lists */
483 	struct list_head fully_used;
484 	struct list_head partially_used;
485 	struct list_head unused;
486 	int available_fcs;
487 	int used_fcs;
488 	int threshold;
489 };
490 
491 struct mlx5_fc_stats {
492 	spinlock_t counters_idr_lock; /* protects counters_idr */
493 	struct idr counters_idr;
494 	struct list_head counters;
495 	struct llist_head addlist;
496 	struct llist_head dellist;
497 
498 	struct workqueue_struct *wq;
499 	struct delayed_work work;
500 	unsigned long next_query;
501 	unsigned long sampling_interval; /* jiffies */
502 	u32 *bulk_query_out;
503 	int bulk_query_len;
504 	size_t num_counters;
505 	bool bulk_query_alloc_failed;
506 	unsigned long next_bulk_query_alloc;
507 	struct mlx5_fc_pool fc_pool;
508 };
509 
510 struct mlx5_events;
511 struct mlx5_mpfs;
512 struct mlx5_eswitch;
513 struct mlx5_lag;
514 struct mlx5_devcom;
515 struct mlx5_fw_reset;
516 struct mlx5_eq_table;
517 struct mlx5_irq_table;
518 struct mlx5_vhca_state_notifier;
519 struct mlx5_sf_dev_table;
520 struct mlx5_sf_hw_table;
521 struct mlx5_sf_table;
522 struct mlx5_crypto_dek_priv;
523 
524 struct mlx5_rate_limit {
525 	u32			rate;
526 	u32			max_burst_sz;
527 	u16			typical_pkt_sz;
528 };
529 
530 struct mlx5_rl_entry {
531 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
532 	u64 refcount;
533 	u16 index;
534 	u16 uid;
535 	u8 dedicated : 1;
536 };
537 
538 struct mlx5_rl_table {
539 	/* protect rate limit table */
540 	struct mutex            rl_lock;
541 	u16                     max_size;
542 	u32                     max_rate;
543 	u32                     min_rate;
544 	struct mlx5_rl_entry   *rl_entry;
545 	u64 refcount;
546 };
547 
548 struct mlx5_core_roce {
549 	struct mlx5_flow_table *ft;
550 	struct mlx5_flow_group *fg;
551 	struct mlx5_flow_handle *allow_rule;
552 };
553 
554 enum {
555 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
556 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
557 	/* Set during device detach to block any further devices
558 	 * creation/deletion on drivers rescan. Unset during device attach.
559 	 */
560 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
561 };
562 
563 struct mlx5_adev {
564 	struct auxiliary_device adev;
565 	struct mlx5_core_dev *mdev;
566 	int idx;
567 };
568 
569 struct mlx5_debugfs_entries {
570 	struct dentry *dbg_root;
571 	struct dentry *qp_debugfs;
572 	struct dentry *eq_debugfs;
573 	struct dentry *cq_debugfs;
574 	struct dentry *cmdif_debugfs;
575 	struct dentry *pages_debugfs;
576 	struct dentry *lag_debugfs;
577 };
578 
579 enum mlx5_func_type {
580 	MLX5_PF,
581 	MLX5_VF,
582 	MLX5_SF,
583 	MLX5_HOST_PF,
584 	MLX5_EC_VF,
585 	MLX5_FUNC_TYPE_NUM,
586 };
587 
588 struct mlx5_ft_pool;
589 struct mlx5_priv {
590 	/* IRQ table valid only for real pci devices PF or VF */
591 	struct mlx5_irq_table   *irq_table;
592 	struct mlx5_eq_table	*eq_table;
593 
594 	/* pages stuff */
595 	struct mlx5_nb          pg_nb;
596 	struct workqueue_struct *pg_wq;
597 	struct xarray           page_root_xa;
598 	atomic_t		reg_pages;
599 	struct list_head	free_list;
600 	u32			fw_pages;
601 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
602 	u32			fw_pages_alloc_failed;
603 	u32			give_pages_dropped;
604 	u32			reclaim_pages_discard;
605 
606 	struct mlx5_core_health health;
607 	struct list_head	traps;
608 
609 	struct mlx5_debugfs_entries dbg;
610 
611 	/* start: alloc staff */
612 	/* protect buffer allocation according to numa node */
613 	struct mutex            alloc_mutex;
614 	int                     numa_node;
615 
616 	struct mutex            pgdir_mutex;
617 	struct list_head        pgdir_list;
618 	/* end: alloc staff */
619 
620 	struct mlx5_adev       **adev;
621 	int			adev_idx;
622 	int			sw_vhca_id;
623 	struct mlx5_events      *events;
624 
625 	struct mlx5_flow_steering *steering;
626 	struct mlx5_mpfs        *mpfs;
627 	struct mlx5_eswitch     *eswitch;
628 	struct mlx5_core_sriov	sriov;
629 	struct mlx5_lag		*lag;
630 	u32			flags;
631 	struct mlx5_devcom	*devcom;
632 	struct mlx5_fw_reset	*fw_reset;
633 	struct mlx5_core_roce	roce;
634 	struct mlx5_fc_stats		fc_stats;
635 	struct mlx5_rl_table            rl_table;
636 	struct mlx5_ft_pool		*ft_pool;
637 
638 	struct mlx5_bfreg_data		bfregs;
639 	struct mlx5_uars_page	       *uar;
640 #ifdef CONFIG_MLX5_SF
641 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
642 	struct mlx5_sf_dev_table *sf_dev_table;
643 	struct mlx5_core_dev *parent_mdev;
644 #endif
645 #ifdef CONFIG_MLX5_SF_MANAGER
646 	struct mlx5_sf_hw_table *sf_hw_table;
647 	struct mlx5_sf_table *sf_table;
648 #endif
649 };
650 
651 enum mlx5_device_state {
652 	MLX5_DEVICE_STATE_UP = 1,
653 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
654 };
655 
656 enum mlx5_interface_state {
657 	MLX5_INTERFACE_STATE_UP = BIT(0),
658 	MLX5_BREAK_FW_WAIT = BIT(1),
659 };
660 
661 enum mlx5_pci_status {
662 	MLX5_PCI_STATUS_DISABLED,
663 	MLX5_PCI_STATUS_ENABLED,
664 };
665 
666 enum mlx5_pagefault_type_flags {
667 	MLX5_PFAULT_REQUESTOR = 1 << 0,
668 	MLX5_PFAULT_WRITE     = 1 << 1,
669 	MLX5_PFAULT_RDMA      = 1 << 2,
670 };
671 
672 struct mlx5_td {
673 	/* protects tirs list changes while tirs refresh */
674 	struct mutex     list_lock;
675 	struct list_head tirs_list;
676 	u32              tdn;
677 };
678 
679 struct mlx5e_resources {
680 	struct mlx5e_hw_objs {
681 		u32                        pdn;
682 		struct mlx5_td             td;
683 		u32			   mkey;
684 		struct mlx5_sq_bfreg       bfreg;
685 	} hw_objs;
686 	struct net_device *uplink_netdev;
687 	struct mutex uplink_netdev_lock;
688 	struct mlx5_crypto_dek_priv *dek_priv;
689 };
690 
691 enum mlx5_sw_icm_type {
692 	MLX5_SW_ICM_TYPE_STEERING,
693 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
694 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
695 };
696 
697 #define MLX5_MAX_RESERVED_GIDS 8
698 
699 struct mlx5_rsvd_gids {
700 	unsigned int start;
701 	unsigned int count;
702 	struct ida ida;
703 };
704 
705 #define MAX_PIN_NUM	8
706 struct mlx5_pps {
707 	u8                         pin_caps[MAX_PIN_NUM];
708 	struct work_struct         out_work;
709 	u64                        start[MAX_PIN_NUM];
710 	u8                         enabled;
711 	u64                        min_npps_period;
712 	u64                        min_out_pulse_duration_ns;
713 };
714 
715 struct mlx5_timer {
716 	struct cyclecounter        cycles;
717 	struct timecounter         tc;
718 	u32                        nominal_c_mult;
719 	unsigned long              overflow_period;
720 	struct delayed_work        overflow_work;
721 };
722 
723 struct mlx5_clock {
724 	struct mlx5_nb             pps_nb;
725 	seqlock_t                  lock;
726 	struct hwtstamp_config     hwtstamp_config;
727 	struct ptp_clock          *ptp;
728 	struct ptp_clock_info      ptp_info;
729 	struct mlx5_pps            pps_info;
730 	struct mlx5_timer          timer;
731 };
732 
733 struct mlx5_dm;
734 struct mlx5_fw_tracer;
735 struct mlx5_vxlan;
736 struct mlx5_geneve;
737 struct mlx5_hv_vhca;
738 struct mlx5_thermal;
739 
740 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
741 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
742 
743 enum {
744 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
745 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
746 };
747 
748 enum {
749 	MKEY_CACHE_LAST_STD_ENTRY = 20,
750 	MLX5_IMR_KSM_CACHE_ENTRY,
751 	MAX_MKEY_CACHE_ENTRIES
752 };
753 
754 struct mlx5_profile {
755 	u64	mask;
756 	u8	log_max_qp;
757 	u8	num_cmd_caches;
758 	struct {
759 		int	size;
760 		int	limit;
761 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
762 };
763 
764 struct mlx5_hca_cap {
765 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
766 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
767 };
768 
769 struct mlx5_core_dev {
770 	struct device *device;
771 	enum mlx5_coredev_type coredev_type;
772 	struct pci_dev	       *pdev;
773 	/* sync pci state */
774 	struct mutex		pci_status_mutex;
775 	enum mlx5_pci_status	pci_status;
776 	u8			rev_id;
777 	char			board_id[MLX5_BOARD_ID_LEN];
778 	struct mlx5_cmd		cmd;
779 	struct {
780 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
781 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
782 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
783 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
784 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
785 		u8  embedded_cpu;
786 	} caps;
787 	struct mlx5_timeouts	*timeouts;
788 	u64			sys_image_guid;
789 	phys_addr_t		iseg_base;
790 	struct mlx5_init_seg __iomem *iseg;
791 	phys_addr_t             bar_addr;
792 	enum mlx5_device_state	state;
793 	/* sync interface state */
794 	struct mutex		intf_state_mutex;
795 	struct lock_class_key	lock_key;
796 	unsigned long		intf_state;
797 	struct mlx5_priv	priv;
798 	struct mlx5_profile	profile;
799 	u32			issi;
800 	struct mlx5e_resources  mlx5e_res;
801 	struct mlx5_dm          *dm;
802 	struct mlx5_vxlan       *vxlan;
803 	struct mlx5_geneve      *geneve;
804 	struct {
805 		struct mlx5_rsvd_gids	reserved_gids;
806 		u32			roce_en;
807 	} roce;
808 #ifdef CONFIG_MLX5_FPGA
809 	struct mlx5_fpga_device *fpga;
810 #endif
811 	struct mlx5_clock        clock;
812 	struct mlx5_ib_clock_info  *clock_info;
813 	struct mlx5_fw_tracer   *tracer;
814 	struct mlx5_rsc_dump    *rsc_dump;
815 	u32                      vsc_addr;
816 	struct mlx5_hv_vhca	*hv_vhca;
817 	struct mlx5_thermal	*thermal;
818 };
819 
820 struct mlx5_db {
821 	__be32			*db;
822 	union {
823 		struct mlx5_db_pgdir		*pgdir;
824 		struct mlx5_ib_user_db_page	*user_page;
825 	}			u;
826 	dma_addr_t		dma;
827 	int			index;
828 };
829 
830 enum {
831 	MLX5_COMP_EQ_SIZE = 1024,
832 };
833 
834 enum {
835 	MLX5_PTYS_IB = 1 << 0,
836 	MLX5_PTYS_EN = 1 << 2,
837 };
838 
839 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
840 
841 enum {
842 	MLX5_CMD_ENT_STATE_PENDING_COMP,
843 };
844 
845 struct mlx5_cmd_work_ent {
846 	unsigned long		state;
847 	struct mlx5_cmd_msg    *in;
848 	struct mlx5_cmd_msg    *out;
849 	void		       *uout;
850 	int			uout_size;
851 	mlx5_cmd_cbk_t		callback;
852 	struct delayed_work	cb_timeout_work;
853 	void		       *context;
854 	int			idx;
855 	struct completion	handling;
856 	struct completion	done;
857 	struct mlx5_cmd        *cmd;
858 	struct work_struct	work;
859 	struct mlx5_cmd_layout *lay;
860 	int			ret;
861 	int			page_queue;
862 	u8			status;
863 	u8			token;
864 	u64			ts1;
865 	u64			ts2;
866 	u16			op;
867 	bool			polling;
868 	/* Track the max comp handlers */
869 	refcount_t              refcnt;
870 };
871 
872 enum phy_port_state {
873 	MLX5_AAA_111
874 };
875 
876 struct mlx5_hca_vport_context {
877 	u32			field_select;
878 	bool			sm_virt_aware;
879 	bool			has_smi;
880 	bool			has_raw;
881 	enum port_state_policy	policy;
882 	enum phy_port_state	phys_state;
883 	enum ib_port_state	vport_state;
884 	u8			port_physical_state;
885 	u64			sys_image_guid;
886 	u64			port_guid;
887 	u64			node_guid;
888 	u32			cap_mask1;
889 	u32			cap_mask1_perm;
890 	u16			cap_mask2;
891 	u16			cap_mask2_perm;
892 	u16			lid;
893 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
894 	u8			lmc;
895 	u8			subnet_timeout;
896 	u16			sm_lid;
897 	u8			sm_sl;
898 	u16			qkey_violation_counter;
899 	u16			pkey_violation_counter;
900 	bool			grh_required;
901 };
902 
903 #define STRUCT_FIELD(header, field) \
904 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
905 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
906 
907 extern struct dentry *mlx5_debugfs_root;
908 
909 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
910 {
911 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
912 }
913 
914 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
915 {
916 	return ioread32be(&dev->iseg->fw_rev) >> 16;
917 }
918 
919 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
920 {
921 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
922 }
923 
924 static inline u32 mlx5_base_mkey(const u32 key)
925 {
926 	return key & 0xffffff00u;
927 }
928 
929 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
930 {
931 	return ((u32)1 << log_sz) << log_stride;
932 }
933 
934 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
935 					u8 log_stride, u8 log_sz,
936 					u16 strides_offset,
937 					struct mlx5_frag_buf_ctrl *fbc)
938 {
939 	fbc->frags      = frags;
940 	fbc->log_stride = log_stride;
941 	fbc->log_sz     = log_sz;
942 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
943 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
944 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
945 	fbc->strides_offset = strides_offset;
946 }
947 
948 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
949 				 u8 log_stride, u8 log_sz,
950 				 struct mlx5_frag_buf_ctrl *fbc)
951 {
952 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
953 }
954 
955 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
956 					  u32 ix)
957 {
958 	unsigned int frag;
959 
960 	ix  += fbc->strides_offset;
961 	frag = ix >> fbc->log_frag_strides;
962 
963 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
964 }
965 
966 static inline u32
967 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
968 {
969 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
970 
971 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
972 }
973 
974 enum {
975 	CMD_ALLOWED_OPCODE_ALL,
976 };
977 
978 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
979 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
980 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
981 
982 struct mlx5_async_ctx {
983 	struct mlx5_core_dev *dev;
984 	atomic_t num_inflight;
985 	struct completion inflight_done;
986 };
987 
988 struct mlx5_async_work;
989 
990 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
991 
992 struct mlx5_async_work {
993 	struct mlx5_async_ctx *ctx;
994 	mlx5_async_cbk_t user_callback;
995 	u16 opcode; /* cmd opcode */
996 	u16 op_mod; /* cmd op_mod */
997 	void *out; /* pointer to the cmd output buffer */
998 };
999 
1000 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1001 			     struct mlx5_async_ctx *ctx);
1002 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1003 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1004 		     void *out, int out_size, mlx5_async_cbk_t callback,
1005 		     struct mlx5_async_work *work);
1006 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1007 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1008 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1009 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1010 		  int out_size);
1011 
1012 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1013 	({                                                                     \
1014 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1015 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1016 	})
1017 
1018 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1019 	({                                                                     \
1020 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1021 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1022 	})
1023 
1024 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1025 			  void *out, int out_size);
1026 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1027 
1028 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1029 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1030 
1031 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1032 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1033 int mlx5_health_init(struct mlx5_core_dev *dev);
1034 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1035 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1036 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1037 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1038 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1039 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1040 			     struct mlx5_frag_buf *buf, int node);
1041 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1042 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1043 						      gfp_t flags, int npages);
1044 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1045 				 struct mlx5_cmd_mailbox *head);
1046 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1047 			  int inlen);
1048 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1049 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1050 			 int outlen);
1051 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1052 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1053 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1054 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1055 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1056 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1057 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1058 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1059 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1060 				 s32 npages, bool ec_function);
1061 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1062 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1063 void mlx5_register_debugfs(void);
1064 void mlx5_unregister_debugfs(void);
1065 
1066 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1067 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1068 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1069 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1070 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1071 
1072 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1073 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1074 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1075 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1076 		    void *data_out, int size_out, u16 reg_id, int arg,
1077 		    int write, bool verbose);
1078 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1079 			 int size_in, void *data_out, int size_out,
1080 			 u16 reg_num, int arg, int write);
1081 
1082 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1083 		       int node);
1084 
1085 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1086 {
1087 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1088 }
1089 
1090 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1091 
1092 const char *mlx5_command_str(int command);
1093 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1094 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1095 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1096 			 int npsvs, u32 *sig_index);
1097 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1098 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1099 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1100 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1101 			struct mlx5_odp_caps *odp_caps);
1102 
1103 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1104 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1105 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1106 		     struct mlx5_rate_limit *rl);
1107 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1108 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1109 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1110 			 bool dedicated_entry, u16 *index);
1111 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1112 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1113 		       struct mlx5_rate_limit *rl_1);
1114 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1115 		     bool map_wc, bool fast_path);
1116 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1117 
1118 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1119 struct cpumask *
1120 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1121 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1122 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1123 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1124 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1125 
1126 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1127 {
1128 	return mkey >> 8;
1129 }
1130 
1131 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1132 {
1133 	return mkey_idx << 8;
1134 }
1135 
1136 static inline u8 mlx5_mkey_variant(u32 mkey)
1137 {
1138 	return mkey & 0xff;
1139 }
1140 
1141 /* Async-atomic event notifier used by mlx5 core to forward FW
1142  * evetns received from event queue to mlx5 consumers.
1143  * Optimise event queue dipatching.
1144  */
1145 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1146 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1147 
1148 /* Async-atomic event notifier used for forwarding
1149  * evetns from the event queue into the to mlx5 events dispatcher,
1150  * eswitch, clock and others.
1151  */
1152 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1153 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1154 
1155 /* Blocking event notifier used to forward SW events, used for slow path */
1156 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1157 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1158 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1159 				      void *data);
1160 
1161 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1162 
1163 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1164 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1165 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1166 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1167 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1168 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1169 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1170 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1171 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1172 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1173 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1174 			   struct net_device *slave);
1175 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1176 				 u64 *values,
1177 				 int num_counters,
1178 				 size_t *offsets);
1179 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1180 
1181 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1182 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1183 	     peer;								\
1184 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1185 
1186 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1187 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1188 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1189 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1190 			 u64 length, u32 log_alignment, u16 uid,
1191 			 phys_addr_t *addr, u32 *obj_id);
1192 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1193 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1194 
1195 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1196 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1197 
1198 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1199 					  int vf_id,
1200 					  struct notifier_block *nb);
1201 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1202 					     int vf_id,
1203 					     struct notifier_block *nb);
1204 #ifdef CONFIG_MLX5_CORE_IPOIB
1205 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1206 					  struct ib_device *ibdev,
1207 					  const char *name,
1208 					  void (*setup)(struct net_device *));
1209 #endif /* CONFIG_MLX5_CORE_IPOIB */
1210 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1211 			    struct ib_device *device,
1212 			    struct rdma_netdev_alloc_params *params);
1213 
1214 enum {
1215 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1216 };
1217 
1218 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1219 {
1220 	return dev->coredev_type == MLX5_COREDEV_PF;
1221 }
1222 
1223 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1224 {
1225 	return dev->coredev_type == MLX5_COREDEV_VF;
1226 }
1227 
1228 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1229 {
1230 	return dev->caps.embedded_cpu;
1231 }
1232 
1233 static inline bool
1234 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1235 {
1236 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1237 }
1238 
1239 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1240 {
1241 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1242 }
1243 
1244 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1245 {
1246 	return dev->priv.sriov.max_vfs;
1247 }
1248 
1249 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1250 {
1251 	/* LACP owner conditions:
1252 	 * 1) Function is physical.
1253 	 * 2) LAG is supported by FW.
1254 	 * 3) LAG is managed by driver (currently the only option).
1255 	 */
1256 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1257 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1258 		    MLX5_CAP_GEN(dev, lag_master);
1259 }
1260 
1261 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1262 {
1263 	return dev->priv.sriov.max_ec_vfs;
1264 }
1265 
1266 static inline int mlx5_get_gid_table_len(u16 param)
1267 {
1268 	if (param > 4) {
1269 		pr_warn("gid table length is zero\n");
1270 		return 0;
1271 	}
1272 
1273 	return 8 * (1 << param);
1274 }
1275 
1276 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1277 {
1278 	return !!(dev->priv.rl_table.max_size);
1279 }
1280 
1281 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1282 {
1283 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1284 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1285 }
1286 
1287 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1288 {
1289 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1290 }
1291 
1292 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1293 {
1294 	return mlx5_core_is_mp_slave(dev) ||
1295 	       mlx5_core_is_mp_master(dev);
1296 }
1297 
1298 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1299 {
1300 	if (!mlx5_core_mp_enabled(dev))
1301 		return 1;
1302 
1303 	return MLX5_CAP_GEN(dev, native_port_num);
1304 }
1305 
1306 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1307 {
1308 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1309 
1310 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1311 		return idx - 1;
1312 	else
1313 		return PCI_FUNC(dev->pdev->devfn);
1314 }
1315 
1316 enum {
1317 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1318 };
1319 
1320 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1321 
1322 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1323 {
1324 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1325 		return MLX5_CAP_GEN(dev, roce);
1326 
1327 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1328 	 * in order to support RoCE enable/disable feature
1329 	 */
1330 	return mlx5_is_roce_on(dev);
1331 }
1332 
1333 enum {
1334 	MLX5_OCTWORD = 16,
1335 };
1336 
1337 struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev,
1338 			       irqreturn_t (*handler)(int, void *),
1339 			       const struct irq_affinity_desc *affdesc,
1340 			       const char *name);
1341 void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map);
1342 
1343 #endif /* MLX5_DRIVER_H */
1344