1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/spinlock_types.h> 40 #include <linux/semaphore.h> 41 #include <linux/slab.h> 42 #include <linux/vmalloc.h> 43 #include <linux/radix-tree.h> 44 #include <linux/workqueue.h> 45 #include <linux/interrupt.h> 46 47 #include <linux/mlx5/device.h> 48 #include <linux/mlx5/doorbell.h> 49 50 enum { 51 MLX5_RQ_BITMASK_VSD = 1 << 1, 52 }; 53 54 enum { 55 MLX5_BOARD_ID_LEN = 64, 56 MLX5_MAX_NAME_LEN = 16, 57 }; 58 59 enum { 60 /* one minute for the sake of bringup. Generally, commands must always 61 * complete and we may need to increase this timeout value 62 */ 63 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 64 MLX5_CMD_WQ_MAX_NAME = 32, 65 }; 66 67 enum { 68 CMD_OWNER_SW = 0x0, 69 CMD_OWNER_HW = 0x1, 70 CMD_STATUS_SUCCESS = 0, 71 }; 72 73 enum mlx5_sqp_t { 74 MLX5_SQP_SMI = 0, 75 MLX5_SQP_GSI = 1, 76 MLX5_SQP_IEEE_1588 = 2, 77 MLX5_SQP_SNIFFER = 3, 78 MLX5_SQP_SYNC_UMR = 4, 79 }; 80 81 enum { 82 MLX5_MAX_PORTS = 2, 83 }; 84 85 enum { 86 MLX5_EQ_VEC_PAGES = 0, 87 MLX5_EQ_VEC_CMD = 1, 88 MLX5_EQ_VEC_ASYNC = 2, 89 MLX5_EQ_VEC_COMP_BASE, 90 }; 91 92 enum { 93 MLX5_MAX_IRQ_NAME = 32 94 }; 95 96 enum { 97 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 98 MLX5_ATOMIC_MODE_CX = 2 << 16, 99 MLX5_ATOMIC_MODE_8B = 3 << 16, 100 MLX5_ATOMIC_MODE_16B = 4 << 16, 101 MLX5_ATOMIC_MODE_32B = 5 << 16, 102 MLX5_ATOMIC_MODE_64B = 6 << 16, 103 MLX5_ATOMIC_MODE_128B = 7 << 16, 104 MLX5_ATOMIC_MODE_256B = 8 << 16, 105 }; 106 107 enum { 108 MLX5_REG_QETCR = 0x4005, 109 MLX5_REG_QTCT = 0x400a, 110 MLX5_REG_PCAP = 0x5001, 111 MLX5_REG_PMTU = 0x5003, 112 MLX5_REG_PTYS = 0x5004, 113 MLX5_REG_PAOS = 0x5006, 114 MLX5_REG_PFCC = 0x5007, 115 MLX5_REG_PPCNT = 0x5008, 116 MLX5_REG_PMAOS = 0x5012, 117 MLX5_REG_PUDE = 0x5009, 118 MLX5_REG_PMPE = 0x5010, 119 MLX5_REG_PELC = 0x500e, 120 MLX5_REG_PVLC = 0x500f, 121 MLX5_REG_PCMR = 0x5041, 122 MLX5_REG_PMLP = 0x5002, 123 MLX5_REG_NODE_DESC = 0x6001, 124 MLX5_REG_HOST_ENDIANNESS = 0x7004, 125 MLX5_REG_MCIA = 0x9014, 126 MLX5_REG_MLCR = 0x902b, 127 }; 128 129 enum { 130 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 131 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 132 }; 133 134 enum mlx5_page_fault_resume_flags { 135 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 136 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 137 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 138 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 139 }; 140 141 enum dbg_rsc_type { 142 MLX5_DBG_RSC_QP, 143 MLX5_DBG_RSC_EQ, 144 MLX5_DBG_RSC_CQ, 145 }; 146 147 struct mlx5_field_desc { 148 struct dentry *dent; 149 int i; 150 }; 151 152 struct mlx5_rsc_debug { 153 struct mlx5_core_dev *dev; 154 void *object; 155 enum dbg_rsc_type type; 156 struct dentry *root; 157 struct mlx5_field_desc fields[0]; 158 }; 159 160 enum mlx5_dev_event { 161 MLX5_DEV_EVENT_SYS_ERROR, 162 MLX5_DEV_EVENT_PORT_UP, 163 MLX5_DEV_EVENT_PORT_DOWN, 164 MLX5_DEV_EVENT_PORT_INITIALIZED, 165 MLX5_DEV_EVENT_LID_CHANGE, 166 MLX5_DEV_EVENT_PKEY_CHANGE, 167 MLX5_DEV_EVENT_GUID_CHANGE, 168 MLX5_DEV_EVENT_CLIENT_REREG, 169 }; 170 171 enum mlx5_port_status { 172 MLX5_PORT_UP = 1, 173 MLX5_PORT_DOWN = 2, 174 }; 175 176 struct mlx5_uuar_info { 177 struct mlx5_uar *uars; 178 int num_uars; 179 int num_low_latency_uuars; 180 unsigned long *bitmap; 181 unsigned int *count; 182 struct mlx5_bf *bfs; 183 184 /* 185 * protect uuar allocation data structs 186 */ 187 struct mutex lock; 188 u32 ver; 189 }; 190 191 struct mlx5_bf { 192 void __iomem *reg; 193 void __iomem *regreg; 194 int buf_size; 195 struct mlx5_uar *uar; 196 unsigned long offset; 197 int need_lock; 198 /* protect blue flame buffer selection when needed 199 */ 200 spinlock_t lock; 201 202 /* serialize 64 bit writes when done as two 32 bit accesses 203 */ 204 spinlock_t lock32; 205 int uuarn; 206 }; 207 208 struct mlx5_cmd_first { 209 __be32 data[4]; 210 }; 211 212 struct mlx5_cmd_msg { 213 struct list_head list; 214 struct cache_ent *cache; 215 u32 len; 216 struct mlx5_cmd_first first; 217 struct mlx5_cmd_mailbox *next; 218 }; 219 220 struct mlx5_cmd_debug { 221 struct dentry *dbg_root; 222 struct dentry *dbg_in; 223 struct dentry *dbg_out; 224 struct dentry *dbg_outlen; 225 struct dentry *dbg_status; 226 struct dentry *dbg_run; 227 void *in_msg; 228 void *out_msg; 229 u8 status; 230 u16 inlen; 231 u16 outlen; 232 }; 233 234 struct cache_ent { 235 /* protect block chain allocations 236 */ 237 spinlock_t lock; 238 struct list_head head; 239 }; 240 241 struct cmd_msg_cache { 242 struct cache_ent large; 243 struct cache_ent med; 244 245 }; 246 247 struct mlx5_cmd_stats { 248 u64 sum; 249 u64 n; 250 struct dentry *root; 251 struct dentry *avg; 252 struct dentry *count; 253 /* protect command average calculations */ 254 spinlock_t lock; 255 }; 256 257 struct mlx5_cmd { 258 void *cmd_alloc_buf; 259 dma_addr_t alloc_dma; 260 int alloc_size; 261 void *cmd_buf; 262 dma_addr_t dma; 263 u16 cmdif_rev; 264 u8 log_sz; 265 u8 log_stride; 266 int max_reg_cmds; 267 int events; 268 u32 __iomem *vector; 269 270 /* protect command queue allocations 271 */ 272 spinlock_t alloc_lock; 273 274 /* protect token allocations 275 */ 276 spinlock_t token_lock; 277 u8 token; 278 unsigned long bitmask; 279 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 280 struct workqueue_struct *wq; 281 struct semaphore sem; 282 struct semaphore pages_sem; 283 int mode; 284 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 285 struct pci_pool *pool; 286 struct mlx5_cmd_debug dbg; 287 struct cmd_msg_cache cache; 288 int checksum_disabled; 289 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 290 }; 291 292 struct mlx5_port_caps { 293 int gid_table_len; 294 int pkey_table_len; 295 u8 ext_port_cap; 296 }; 297 298 struct mlx5_cmd_mailbox { 299 void *buf; 300 dma_addr_t dma; 301 struct mlx5_cmd_mailbox *next; 302 }; 303 304 struct mlx5_buf_list { 305 void *buf; 306 dma_addr_t map; 307 }; 308 309 struct mlx5_buf { 310 struct mlx5_buf_list direct; 311 int npages; 312 int size; 313 u8 page_shift; 314 }; 315 316 struct mlx5_eq_tasklet { 317 struct list_head list; 318 struct list_head process_list; 319 struct tasklet_struct task; 320 /* lock on completion tasklet list */ 321 spinlock_t lock; 322 }; 323 324 struct mlx5_eq { 325 struct mlx5_core_dev *dev; 326 __be32 __iomem *doorbell; 327 u32 cons_index; 328 struct mlx5_buf buf; 329 int size; 330 unsigned int irqn; 331 u8 eqn; 332 int nent; 333 u64 mask; 334 struct list_head list; 335 int index; 336 struct mlx5_rsc_debug *dbg; 337 struct mlx5_eq_tasklet tasklet_ctx; 338 }; 339 340 struct mlx5_core_psv { 341 u32 psv_idx; 342 struct psv_layout { 343 u32 pd; 344 u16 syndrome; 345 u16 reserved; 346 u16 bg; 347 u16 app_tag; 348 u32 ref_tag; 349 } psv; 350 }; 351 352 struct mlx5_core_sig_ctx { 353 struct mlx5_core_psv psv_memory; 354 struct mlx5_core_psv psv_wire; 355 struct ib_sig_err err_item; 356 bool sig_status_checked; 357 bool sig_err_exists; 358 u32 sigerr_count; 359 }; 360 361 struct mlx5_core_mkey { 362 u64 iova; 363 u64 size; 364 u32 key; 365 u32 pd; 366 }; 367 368 enum mlx5_res_type { 369 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 370 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 371 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 372 MLX5_RES_SRQ = 3, 373 MLX5_RES_XSRQ = 4, 374 }; 375 376 struct mlx5_core_rsc_common { 377 enum mlx5_res_type res; 378 atomic_t refcount; 379 struct completion free; 380 }; 381 382 struct mlx5_core_srq { 383 struct mlx5_core_rsc_common common; /* must be first */ 384 u32 srqn; 385 int max; 386 int max_gs; 387 int max_avail_gather; 388 int wqe_shift; 389 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 390 391 atomic_t refcount; 392 struct completion free; 393 }; 394 395 struct mlx5_eq_table { 396 void __iomem *update_ci; 397 void __iomem *update_arm_ci; 398 struct list_head comp_eqs_list; 399 struct mlx5_eq pages_eq; 400 struct mlx5_eq async_eq; 401 struct mlx5_eq cmd_eq; 402 int num_comp_vectors; 403 /* protect EQs list 404 */ 405 spinlock_t lock; 406 }; 407 408 struct mlx5_uar { 409 u32 index; 410 struct list_head bf_list; 411 unsigned free_bf_bmap; 412 void __iomem *bf_map; 413 void __iomem *map; 414 }; 415 416 417 struct mlx5_core_health { 418 struct health_buffer __iomem *health; 419 __be32 __iomem *health_counter; 420 struct timer_list timer; 421 u32 prev; 422 int miss_counter; 423 bool sick; 424 struct workqueue_struct *wq; 425 struct work_struct work; 426 }; 427 428 struct mlx5_cq_table { 429 /* protect radix tree 430 */ 431 spinlock_t lock; 432 struct radix_tree_root tree; 433 }; 434 435 struct mlx5_qp_table { 436 /* protect radix tree 437 */ 438 spinlock_t lock; 439 struct radix_tree_root tree; 440 }; 441 442 struct mlx5_srq_table { 443 /* protect radix tree 444 */ 445 spinlock_t lock; 446 struct radix_tree_root tree; 447 }; 448 449 struct mlx5_mkey_table { 450 /* protect radix tree 451 */ 452 rwlock_t lock; 453 struct radix_tree_root tree; 454 }; 455 456 struct mlx5_vf_context { 457 int enabled; 458 }; 459 460 struct mlx5_core_sriov { 461 struct mlx5_vf_context *vfs_ctx; 462 int num_vfs; 463 int enabled_vfs; 464 }; 465 466 struct mlx5_irq_info { 467 cpumask_var_t mask; 468 char name[MLX5_MAX_IRQ_NAME]; 469 }; 470 471 struct mlx5_fc_stats { 472 struct list_head list; 473 struct list_head addlist; 474 /* protect addlist add/splice operations */ 475 spinlock_t addlist_lock; 476 477 struct workqueue_struct *wq; 478 struct delayed_work work; 479 unsigned long next_query; 480 }; 481 482 struct mlx5_eswitch; 483 484 struct mlx5_priv { 485 char name[MLX5_MAX_NAME_LEN]; 486 struct mlx5_eq_table eq_table; 487 struct msix_entry *msix_arr; 488 struct mlx5_irq_info *irq_info; 489 struct mlx5_uuar_info uuari; 490 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 491 492 /* pages stuff */ 493 struct workqueue_struct *pg_wq; 494 struct rb_root page_root; 495 int fw_pages; 496 atomic_t reg_pages; 497 struct list_head free_list; 498 int vfs_pages; 499 500 struct mlx5_core_health health; 501 502 struct mlx5_srq_table srq_table; 503 504 /* start: qp staff */ 505 struct mlx5_qp_table qp_table; 506 struct dentry *qp_debugfs; 507 struct dentry *eq_debugfs; 508 struct dentry *cq_debugfs; 509 struct dentry *cmdif_debugfs; 510 /* end: qp staff */ 511 512 /* start: cq staff */ 513 struct mlx5_cq_table cq_table; 514 /* end: cq staff */ 515 516 /* start: mkey staff */ 517 struct mlx5_mkey_table mkey_table; 518 /* end: mkey staff */ 519 520 /* start: alloc staff */ 521 /* protect buffer alocation according to numa node */ 522 struct mutex alloc_mutex; 523 int numa_node; 524 525 struct mutex pgdir_mutex; 526 struct list_head pgdir_list; 527 /* end: alloc staff */ 528 struct dentry *dbg_root; 529 530 /* protect mkey key part */ 531 spinlock_t mkey_lock; 532 u8 mkey_key; 533 534 struct list_head dev_list; 535 struct list_head ctx_list; 536 spinlock_t ctx_lock; 537 538 struct mlx5_eswitch *eswitch; 539 struct mlx5_core_sriov sriov; 540 unsigned long pci_dev_data; 541 struct mlx5_flow_root_namespace *root_ns; 542 struct mlx5_flow_root_namespace *fdb_root_ns; 543 struct mlx5_flow_root_namespace *esw_egress_root_ns; 544 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 545 546 struct mlx5_fc_stats fc_stats; 547 }; 548 549 enum mlx5_device_state { 550 MLX5_DEVICE_STATE_UP, 551 MLX5_DEVICE_STATE_INTERNAL_ERROR, 552 }; 553 554 enum mlx5_interface_state { 555 MLX5_INTERFACE_STATE_DOWN = BIT(0), 556 MLX5_INTERFACE_STATE_UP = BIT(1), 557 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 558 }; 559 560 enum mlx5_pci_status { 561 MLX5_PCI_STATUS_DISABLED, 562 MLX5_PCI_STATUS_ENABLED, 563 }; 564 565 struct mlx5_core_dev { 566 struct pci_dev *pdev; 567 /* sync pci state */ 568 struct mutex pci_status_mutex; 569 enum mlx5_pci_status pci_status; 570 u8 rev_id; 571 char board_id[MLX5_BOARD_ID_LEN]; 572 struct mlx5_cmd cmd; 573 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 574 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 575 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 576 phys_addr_t iseg_base; 577 struct mlx5_init_seg __iomem *iseg; 578 enum mlx5_device_state state; 579 /* sync interface state */ 580 struct mutex intf_state_mutex; 581 unsigned long intf_state; 582 void (*event) (struct mlx5_core_dev *dev, 583 enum mlx5_dev_event event, 584 unsigned long param); 585 struct mlx5_priv priv; 586 struct mlx5_profile *profile; 587 atomic_t num_qps; 588 u32 issi; 589 #ifdef CONFIG_RFS_ACCEL 590 struct cpu_rmap *rmap; 591 #endif 592 }; 593 594 struct mlx5_db { 595 __be32 *db; 596 union { 597 struct mlx5_db_pgdir *pgdir; 598 struct mlx5_ib_user_db_page *user_page; 599 } u; 600 dma_addr_t dma; 601 int index; 602 }; 603 604 enum { 605 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 606 }; 607 608 enum { 609 MLX5_COMP_EQ_SIZE = 1024, 610 }; 611 612 enum { 613 MLX5_PTYS_IB = 1 << 0, 614 MLX5_PTYS_EN = 1 << 2, 615 }; 616 617 struct mlx5_db_pgdir { 618 struct list_head list; 619 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 620 __be32 *db_page; 621 dma_addr_t db_dma; 622 }; 623 624 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 625 626 struct mlx5_cmd_work_ent { 627 struct mlx5_cmd_msg *in; 628 struct mlx5_cmd_msg *out; 629 void *uout; 630 int uout_size; 631 mlx5_cmd_cbk_t callback; 632 void *context; 633 int idx; 634 struct completion done; 635 struct mlx5_cmd *cmd; 636 struct work_struct work; 637 struct mlx5_cmd_layout *lay; 638 int ret; 639 int page_queue; 640 u8 status; 641 u8 token; 642 u64 ts1; 643 u64 ts2; 644 u16 op; 645 }; 646 647 struct mlx5_pas { 648 u64 pa; 649 u8 log_sz; 650 }; 651 652 enum port_state_policy { 653 MLX5_POLICY_DOWN = 0, 654 MLX5_POLICY_UP = 1, 655 MLX5_POLICY_FOLLOW = 2, 656 MLX5_POLICY_INVALID = 0xffffffff 657 }; 658 659 enum phy_port_state { 660 MLX5_AAA_111 661 }; 662 663 struct mlx5_hca_vport_context { 664 u32 field_select; 665 bool sm_virt_aware; 666 bool has_smi; 667 bool has_raw; 668 enum port_state_policy policy; 669 enum phy_port_state phys_state; 670 enum ib_port_state vport_state; 671 u8 port_physical_state; 672 u64 sys_image_guid; 673 u64 port_guid; 674 u64 node_guid; 675 u32 cap_mask1; 676 u32 cap_mask1_perm; 677 u32 cap_mask2; 678 u32 cap_mask2_perm; 679 u16 lid; 680 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 681 u8 lmc; 682 u8 subnet_timeout; 683 u16 sm_lid; 684 u8 sm_sl; 685 u16 qkey_violation_counter; 686 u16 pkey_violation_counter; 687 bool grh_required; 688 }; 689 690 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 691 { 692 return buf->direct.buf + offset; 693 } 694 695 extern struct workqueue_struct *mlx5_core_wq; 696 697 #define STRUCT_FIELD(header, field) \ 698 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 699 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 700 701 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 702 { 703 return pci_get_drvdata(pdev); 704 } 705 706 extern struct dentry *mlx5_debugfs_root; 707 708 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 709 { 710 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 711 } 712 713 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 714 { 715 return ioread32be(&dev->iseg->fw_rev) >> 16; 716 } 717 718 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 719 { 720 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 721 } 722 723 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 724 { 725 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 726 } 727 728 static inline void *mlx5_vzalloc(unsigned long size) 729 { 730 void *rtn; 731 732 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 733 if (!rtn) 734 rtn = vzalloc(size); 735 return rtn; 736 } 737 738 static inline u32 mlx5_base_mkey(const u32 key) 739 { 740 return key & 0xffffff00u; 741 } 742 743 int mlx5_cmd_init(struct mlx5_core_dev *dev); 744 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 745 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 746 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 747 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 748 int mlx5_cmd_status_to_err_v2(void *ptr); 749 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 750 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 751 int out_size); 752 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 753 void *out, int out_size, mlx5_cmd_cbk_t callback, 754 void *context); 755 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 756 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 757 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 758 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 759 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar, 760 bool map_wc); 761 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 762 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 763 int mlx5_health_init(struct mlx5_core_dev *dev); 764 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 765 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 766 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 767 struct mlx5_buf *buf, int node); 768 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); 769 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 770 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 771 gfp_t flags, int npages); 772 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 773 struct mlx5_cmd_mailbox *head); 774 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 775 struct mlx5_create_srq_mbox_in *in, int inlen, 776 int is_xrc); 777 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 778 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 779 struct mlx5_query_srq_mbox_out *out); 780 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 781 u16 lwm, int is_srq); 782 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 783 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 784 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 785 struct mlx5_core_mkey *mkey, 786 struct mlx5_create_mkey_mbox_in *in, int inlen, 787 mlx5_cmd_cbk_t callback, void *context, 788 struct mlx5_create_mkey_mbox_out *out); 789 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 790 struct mlx5_core_mkey *mkey); 791 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 792 struct mlx5_query_mkey_mbox_out *out, int outlen); 793 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, 794 u32 *mkey); 795 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 796 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 797 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 798 u16 opmod, u8 port); 799 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 800 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 801 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 802 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 803 int mlx5_sriov_init(struct mlx5_core_dev *dev); 804 int mlx5_sriov_cleanup(struct mlx5_core_dev *dev); 805 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 806 s32 npages); 807 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 808 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 809 void mlx5_register_debugfs(void); 810 void mlx5_unregister_debugfs(void); 811 int mlx5_eq_init(struct mlx5_core_dev *dev); 812 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 813 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 814 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 815 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 816 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 817 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); 818 #endif 819 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 820 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 821 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); 822 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 823 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 824 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 825 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 826 int mlx5_start_eqs(struct mlx5_core_dev *dev); 827 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 828 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 829 unsigned int *irqn); 830 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 831 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 832 833 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 834 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 835 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 836 int size_in, void *data_out, int size_out, 837 u16 reg_num, int arg, int write); 838 839 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 840 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 841 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 842 struct mlx5_query_eq_mbox_out *out, int outlen); 843 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 844 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 845 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 846 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 847 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 848 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 849 int node); 850 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 851 852 const char *mlx5_command_str(int command); 853 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 854 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 855 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 856 int npsvs, u32 *sig_index); 857 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 858 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 859 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 860 struct mlx5_odp_caps *odp_caps); 861 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 862 u8 port_num, void *out, size_t sz); 863 864 static inline int fw_initializing(struct mlx5_core_dev *dev) 865 { 866 return ioread32be(&dev->iseg->initializing) >> 31; 867 } 868 869 static inline u32 mlx5_mkey_to_idx(u32 mkey) 870 { 871 return mkey >> 8; 872 } 873 874 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 875 { 876 return mkey_idx << 8; 877 } 878 879 static inline u8 mlx5_mkey_variant(u32 mkey) 880 { 881 return mkey & 0xff; 882 } 883 884 enum { 885 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 886 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 887 }; 888 889 enum { 890 MAX_MR_CACHE_ENTRIES = 16, 891 }; 892 893 enum { 894 MLX5_INTERFACE_PROTOCOL_IB = 0, 895 MLX5_INTERFACE_PROTOCOL_ETH = 1, 896 }; 897 898 struct mlx5_interface { 899 void * (*add)(struct mlx5_core_dev *dev); 900 void (*remove)(struct mlx5_core_dev *dev, void *context); 901 void (*event)(struct mlx5_core_dev *dev, void *context, 902 enum mlx5_dev_event event, unsigned long param); 903 void * (*get_dev)(void *context); 904 int protocol; 905 struct list_head list; 906 }; 907 908 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 909 int mlx5_register_interface(struct mlx5_interface *intf); 910 void mlx5_unregister_interface(struct mlx5_interface *intf); 911 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 912 913 struct mlx5_profile { 914 u64 mask; 915 u8 log_max_qp; 916 struct { 917 int size; 918 int limit; 919 } mr_cache[MAX_MR_CACHE_ENTRIES]; 920 }; 921 922 enum { 923 MLX5_PCI_DEV_IS_VF = 1 << 0, 924 }; 925 926 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 927 { 928 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 929 } 930 931 static inline int mlx5_get_gid_table_len(u16 param) 932 { 933 if (param > 4) { 934 pr_warn("gid table length is zero\n"); 935 return 0; 936 } 937 938 return 8 * (1 << param); 939 } 940 941 enum { 942 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 943 }; 944 945 #endif /* MLX5_DRIVER_H */ 946